1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4 #ifndef _I40E_H_
5 #define _I40E_H_
6
7 #include <net/tcp.h>
8 #include <net/udp.h>
9 #include <linux/types.h>
10 #include <linux/errno.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/aer.h>
14 #include <linux/netdevice.h>
15 #include <linux/ioport.h>
16 #include <linux/iommu.h>
17 #include <linux/slab.h>
18 #include <linux/list.h>
19 #include <linux/hashtable.h>
20 #include <linux/string.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/sctp.h>
24 #include <linux/pkt_sched.h>
25 #include <linux/ipv6.h>
26 #include <net/checksum.h>
27 #include <net/ip6_checksum.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/if_macvlan.h>
31 #include <linux/if_bridge.h>
32 #include <linux/clocksource.h>
33 #include <linux/net_tstamp.h>
34 #include <linux/ptp_clock_kernel.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_mirred.h>
38 #include <net/udp_tunnel.h>
39 #include <net/xdp_sock.h>
40 #include "i40e_type.h"
41 #include "i40e_prototype.h"
42 #include <linux/net/intel/i40e_client.h>
43 #include <linux/avf/virtchnl.h>
44 #include "i40e_virtchnl_pf.h"
45 #include "i40e_txrx.h"
46 #include "i40e_dcb.h"
47
48 /* Useful i40e defaults */
49 #define I40E_MAX_VEB 16
50
51 #define I40E_MAX_NUM_DESCRIPTORS 4096
52 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
53 #define I40E_DEFAULT_NUM_DESCRIPTORS 512
54 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32
55 #define I40E_MIN_NUM_DESCRIPTORS 64
56 #define I40E_MIN_MSIX 2
57 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
58 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
59 /* max 16 qps */
60 #define i40e_default_queues_per_vmdq(pf) \
61 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
62 #define I40E_DEFAULT_QUEUES_PER_VF 4
63 #define I40E_MAX_VF_QUEUES 16
64 #define i40e_pf_get_max_q_per_tc(pf) \
65 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
66 #define I40E_FDIR_RING_COUNT 32
67 #define I40E_MAX_AQ_BUF_SIZE 4096
68 #define I40E_AQ_LEN 256
69 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
70 #define I40E_MAX_USER_PRIORITY 8
71 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
72 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
73 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
74
75 #define I40E_NVM_VERSION_LO_SHIFT 0
76 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
77 #define I40E_NVM_VERSION_HI_SHIFT 12
78 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
79 #define I40E_OEM_VER_BUILD_MASK 0xffff
80 #define I40E_OEM_VER_PATCH_MASK 0xff
81 #define I40E_OEM_VER_BUILD_SHIFT 8
82 #define I40E_OEM_VER_SHIFT 24
83 #define I40E_PHY_DEBUG_ALL \
84 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
85 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
86
87 #define I40E_OEM_EETRACK_ID 0xffffffff
88 #define I40E_OEM_GEN_SHIFT 24
89 #define I40E_OEM_SNAP_MASK 0x00ff0000
90 #define I40E_OEM_SNAP_SHIFT 16
91 #define I40E_OEM_RELEASE_MASK 0x0000ffff
92
93 #define I40E_RX_DESC(R, i) \
94 (&(((union i40e_rx_desc *)((R)->desc))[i]))
95 #define I40E_TX_DESC(R, i) \
96 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
97 #define I40E_TX_CTXTDESC(R, i) \
98 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
99 #define I40E_TX_FDIRDESC(R, i) \
100 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
101
102 /* BW rate limiting */
103 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
104 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
105 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
106
107 /* driver state flags */
108 enum i40e_state_t {
109 __I40E_TESTING,
110 __I40E_CONFIG_BUSY,
111 __I40E_CONFIG_DONE,
112 __I40E_DOWN,
113 __I40E_SERVICE_SCHED,
114 __I40E_ADMINQ_EVENT_PENDING,
115 __I40E_MDD_EVENT_PENDING,
116 __I40E_VFLR_EVENT_PENDING,
117 __I40E_RESET_RECOVERY_PENDING,
118 __I40E_TIMEOUT_RECOVERY_PENDING,
119 __I40E_MISC_IRQ_REQUESTED,
120 __I40E_RESET_INTR_RECEIVED,
121 __I40E_REINIT_REQUESTED,
122 __I40E_PF_RESET_REQUESTED,
123 __I40E_PF_RESET_AND_REBUILD_REQUESTED,
124 __I40E_CORE_RESET_REQUESTED,
125 __I40E_GLOBAL_RESET_REQUESTED,
126 __I40E_EMP_RESET_INTR_RECEIVED,
127 __I40E_SUSPENDED,
128 __I40E_PTP_TX_IN_PROGRESS,
129 __I40E_BAD_EEPROM,
130 __I40E_DOWN_REQUESTED,
131 __I40E_FD_FLUSH_REQUESTED,
132 __I40E_FD_ATR_AUTO_DISABLED,
133 __I40E_FD_SB_AUTO_DISABLED,
134 __I40E_RESET_FAILED,
135 __I40E_PORT_SUSPENDED,
136 __I40E_VF_DISABLE,
137 __I40E_MACVLAN_SYNC_PENDING,
138 __I40E_TEMP_LINK_POLLING,
139 __I40E_CLIENT_SERVICE_REQUESTED,
140 __I40E_CLIENT_L2_CHANGE,
141 __I40E_CLIENT_RESET,
142 __I40E_VIRTCHNL_OP_PENDING,
143 __I40E_RECOVERY_MODE,
144 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */
145 __I40E_VFS_RELEASING,
146 /* This must be last as it determines the size of the BITMAP */
147 __I40E_STATE_SIZE__,
148 };
149
150 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
151 #define I40E_PF_RESET_AND_REBUILD_FLAG \
152 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
153
154 /* VSI state flags */
155 enum i40e_vsi_state_t {
156 __I40E_VSI_DOWN,
157 __I40E_VSI_NEEDS_RESTART,
158 __I40E_VSI_SYNCING_FILTERS,
159 __I40E_VSI_OVERFLOW_PROMISC,
160 __I40E_VSI_REINIT_REQUESTED,
161 __I40E_VSI_DOWN_REQUESTED,
162 __I40E_VSI_RELEASING,
163 /* This must be last as it determines the size of the BITMAP */
164 __I40E_VSI_STATE_SIZE__,
165 };
166
167 enum i40e_interrupt_policy {
168 I40E_INTERRUPT_BEST_CASE,
169 I40E_INTERRUPT_MEDIUM,
170 I40E_INTERRUPT_LOWEST
171 };
172
173 struct i40e_lump_tracking {
174 u16 num_entries;
175 u16 list[0];
176 #define I40E_PILE_VALID_BIT 0x8000
177 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
178 };
179
180 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20
181 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
182 #define I40E_FDIR_BUFFER_FULL_MARGIN 10
183 #define I40E_FDIR_BUFFER_HEAD_ROOM 32
184 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
185
186 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
187 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
188 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
189
190 enum i40e_fd_stat_idx {
191 I40E_FD_STAT_ATR,
192 I40E_FD_STAT_SB,
193 I40E_FD_STAT_ATR_TUNNEL,
194 I40E_FD_STAT_PF_COUNT
195 };
196 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
197 #define I40E_FD_ATR_STAT_IDX(pf_id) \
198 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
199 #define I40E_FD_SB_STAT_IDX(pf_id) \
200 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
201 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
203
204 /* The following structure contains the data parsed from the user-defined
205 * field of the ethtool_rx_flow_spec structure.
206 */
207 struct i40e_rx_flow_userdef {
208 bool flex_filter;
209 u16 flex_word;
210 u16 flex_offset;
211 };
212
213 struct i40e_fdir_filter {
214 struct hlist_node fdir_node;
215 /* filter ipnut set */
216 u8 flow_type;
217 u8 ip4_proto;
218 /* TX packet view of src and dst */
219 __be32 dst_ip;
220 __be32 src_ip;
221 __be16 src_port;
222 __be16 dst_port;
223 __be32 sctp_v_tag;
224
225 /* Flexible data to match within the packet payload */
226 __be16 flex_word;
227 u16 flex_offset;
228 bool flex_filter;
229
230 /* filter control */
231 u16 q_index;
232 u8 flex_off;
233 u8 pctype;
234 u16 dest_vsi;
235 u8 dest_ctl;
236 u8 fd_status;
237 u16 cnt_index;
238 u32 fd_id;
239 };
240
241 #define I40E_CLOUD_FIELD_OMAC BIT(0)
242 #define I40E_CLOUD_FIELD_IMAC BIT(1)
243 #define I40E_CLOUD_FIELD_IVLAN BIT(2)
244 #define I40E_CLOUD_FIELD_TEN_ID BIT(3)
245 #define I40E_CLOUD_FIELD_IIP BIT(4)
246
247 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
248 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
249 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
250 I40E_CLOUD_FIELD_IVLAN)
251 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
252 I40E_CLOUD_FIELD_TEN_ID)
253 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
254 I40E_CLOUD_FIELD_IMAC | \
255 I40E_CLOUD_FIELD_TEN_ID)
256 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
257 I40E_CLOUD_FIELD_IVLAN | \
258 I40E_CLOUD_FIELD_TEN_ID)
259 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
260
261 struct i40e_cloud_filter {
262 struct hlist_node cloud_node;
263 unsigned long cookie;
264 /* cloud filter input set follows */
265 u8 dst_mac[ETH_ALEN];
266 u8 src_mac[ETH_ALEN];
267 __be16 vlan_id;
268 u16 seid; /* filter control */
269 __be16 dst_port;
270 __be16 src_port;
271 u32 tenant_id;
272 union {
273 struct {
274 struct in_addr dst_ip;
275 struct in_addr src_ip;
276 } v4;
277 struct {
278 struct in6_addr dst_ip6;
279 struct in6_addr src_ip6;
280 } v6;
281 } ip;
282 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32
283 #define src_ipv6 ip.v6.src_ip6.s6_addr32
284 #define dst_ipv4 ip.v4.dst_ip.s_addr
285 #define src_ipv4 ip.v4.src_ip.s_addr
286 u16 n_proto; /* Ethernet Protocol */
287 u8 ip_proto; /* IPPROTO value */
288 u8 flags;
289 #define I40E_CLOUD_TNL_TYPE_NONE 0xff
290 u8 tunnel_type;
291 };
292
293 /* DCB per TC information data structure */
294 struct i40e_tc_info {
295 u16 qoffset; /* Queue offset from base queue */
296 u16 qcount; /* Total Queues */
297 u8 netdev_tc; /* Netdev TC index if netdev associated */
298 };
299
300 /* TC configuration data structure */
301 struct i40e_tc_configuration {
302 u8 numtc; /* Total number of enabled TCs */
303 u8 enabled_tc; /* TC map */
304 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
305 };
306
307 #define I40E_UDP_PORT_INDEX_UNUSED 255
308 struct i40e_udp_port_config {
309 /* AdminQ command interface expects port number in Host byte order */
310 u16 port;
311 u8 type;
312 u8 filter_index;
313 };
314
315 #define I40_DDP_FLASH_REGION 100
316 #define I40E_PROFILE_INFO_SIZE 48
317 #define I40E_MAX_PROFILE_NUM 16
318 #define I40E_PROFILE_LIST_SIZE \
319 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4)
320 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/"
321 #define I40E_DDP_PROFILE_NAME_MAX 64
322
323 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
324 bool is_add);
325 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);
326
327 struct i40e_ddp_profile_list {
328 u32 p_count;
329 struct i40e_profile_info p_info[];
330 };
331
332 struct i40e_ddp_old_profile_list {
333 struct list_head list;
334 size_t old_ddp_size;
335 u8 old_ddp_buf[];
336 };
337
338 /* macros related to FLX_PIT */
339 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
340 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
341 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
342 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
343 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
344 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
345 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
346 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
347 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
348 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
349 I40E_FLEX_SET_FSIZE(fsize) | \
350 I40E_FLEX_SET_SRC_WORD(src))
351
352
353 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
354
355 /* macros related to GLQF_ORT */
356 #define I40E_ORT_SET_IDX(idx) (((idx) << \
357 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
358 I40E_GLQF_ORT_PIT_INDX_MASK)
359
360 #define I40E_ORT_SET_COUNT(count) (((count) << \
361 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
362 I40E_GLQF_ORT_FIELD_CNT_MASK)
363
364 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
365 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
366 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
367
368 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
369 I40E_ORT_SET_COUNT(count) | \
370 I40E_ORT_SET_PAYLOAD(payload))
371
372 #define I40E_L3_GLQF_ORT_IDX 34
373 #define I40E_L4_GLQF_ORT_IDX 35
374
375 /* Flex PIT register index */
376 #define I40E_FLEX_PIT_IDX_START_L3 3
377 #define I40E_FLEX_PIT_IDX_START_L4 6
378
379 #define I40E_FLEX_PIT_TABLE_SIZE 3
380
381 #define I40E_FLEX_DEST_UNUSED 63
382
383 #define I40E_FLEX_INDEX_ENTRIES 8
384
385 /* Flex MASK to disable all flexible entries */
386 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
387 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
388 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
389 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
390
391 struct i40e_flex_pit {
392 struct list_head list;
393 u16 src_offset;
394 u8 pit_index;
395 };
396
397 struct i40e_fwd_adapter {
398 struct net_device *netdev;
399 int bit_no;
400 };
401
402 struct i40e_channel {
403 struct list_head list;
404 bool initialized;
405 u8 type;
406 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
407 u16 stat_counter_idx;
408 u16 base_queue;
409 u16 num_queue_pairs; /* Requested by user */
410 u16 seid;
411
412 u8 enabled_tc;
413 struct i40e_aqc_vsi_properties_data info;
414
415 u64 max_tx_rate;
416 struct i40e_fwd_adapter *fwd;
417
418 /* track this channel belongs to which VSI */
419 struct i40e_vsi *parent_vsi;
420 };
421
i40e_is_channel_macvlan(struct i40e_channel * ch)422 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
423 {
424 return !!ch->fwd;
425 }
426
i40e_channel_mac(struct i40e_channel * ch)427 static inline u8 *i40e_channel_mac(struct i40e_channel *ch)
428 {
429 if (i40e_is_channel_macvlan(ch))
430 return ch->fwd->netdev->dev_addr;
431 else
432 return NULL;
433 }
434
435 /* struct that defines the Ethernet device */
436 struct i40e_pf {
437 struct pci_dev *pdev;
438 struct i40e_hw hw;
439 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
440 struct msix_entry *msix_entries;
441 bool fc_autoneg_status;
442
443 u16 eeprom_version;
444 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
445 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
446 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
447 u16 num_req_vfs; /* num VFs requested for this PF */
448 u16 num_vf_qps; /* num queue pairs per VF */
449 u16 num_lan_qps; /* num lan queues this PF has set up */
450 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
451 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
452 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
453 int iwarp_base_vector;
454 int queues_left; /* queues left unclaimed */
455 u16 alloc_rss_size; /* allocated RSS queues */
456 u16 rss_size_max; /* HW defined max RSS queues */
457 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
458 u16 num_alloc_vsi; /* num VSIs this driver supports */
459 u8 atr_sample_rate;
460 bool wol_en;
461
462 struct hlist_head fdir_filter_list;
463 u16 fdir_pf_active_filters;
464 unsigned long fd_flush_timestamp;
465 u32 fd_flush_cnt;
466 u32 fd_add_err;
467 u32 fd_atr_cnt;
468
469 /* Book-keeping of side-band filter count per flow-type.
470 * This is used to detect and handle input set changes for
471 * respective flow-type.
472 */
473 u16 fd_tcp4_filter_cnt;
474 u16 fd_udp4_filter_cnt;
475 u16 fd_sctp4_filter_cnt;
476 u16 fd_ip4_filter_cnt;
477
478 /* Flexible filter table values that need to be programmed into
479 * hardware, which expects L3 and L4 to be programmed separately. We
480 * need to ensure that the values are in ascended order and don't have
481 * duplicates, so we track each L3 and L4 values in separate lists.
482 */
483 struct list_head l3_flex_pit_list;
484 struct list_head l4_flex_pit_list;
485
486 struct udp_tunnel_nic_shared udp_tunnel_shared;
487 struct udp_tunnel_nic_info udp_tunnel_nic;
488
489 struct hlist_head cloud_filter_list;
490 u16 num_cloud_filters;
491
492 enum i40e_interrupt_policy int_policy;
493 u16 rx_itr_default;
494 u16 tx_itr_default;
495 u32 msg_enable;
496 char int_name[I40E_INT_NAME_STR_LEN];
497 u16 adminq_work_limit; /* num of admin receive queue desc to process */
498 unsigned long service_timer_period;
499 unsigned long service_timer_previous;
500 struct timer_list service_timer;
501 struct work_struct service_task;
502
503 u32 hw_features;
504 #define I40E_HW_RSS_AQ_CAPABLE BIT(0)
505 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
506 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
507 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
508 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
509 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
510 #define I40E_HW_100M_SGMII_CAPABLE BIT(6)
511 #define I40E_HW_NO_DCB_SUPPORT BIT(7)
512 #define I40E_HW_USE_SET_LLDP_MIB BIT(8)
513 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
514 #define I40E_HW_PTP_L4_CAPABLE BIT(10)
515 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
516 #define I40E_HW_HAVE_CRT_RETIMER BIT(13)
517 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
518 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
519 #define I40E_HW_STOP_FW_LLDP BIT(16)
520 #define I40E_HW_PORT_ID_VALID BIT(17)
521 #define I40E_HW_RESTART_AUTONEG BIT(18)
522
523 u32 flags;
524 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
525 #define I40E_FLAG_MSI_ENABLED BIT(1)
526 #define I40E_FLAG_MSIX_ENABLED BIT(2)
527 #define I40E_FLAG_RSS_ENABLED BIT(3)
528 #define I40E_FLAG_VMDQ_ENABLED BIT(4)
529 #define I40E_FLAG_SRIOV_ENABLED BIT(5)
530 #define I40E_FLAG_DCB_CAPABLE BIT(6)
531 #define I40E_FLAG_DCB_ENABLED BIT(7)
532 #define I40E_FLAG_FD_SB_ENABLED BIT(8)
533 #define I40E_FLAG_FD_ATR_ENABLED BIT(9)
534 #define I40E_FLAG_MFP_ENABLED BIT(10)
535 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11)
536 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12)
537 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13)
538 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14)
539 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15)
540 #define I40E_FLAG_LEGACY_RX BIT(16)
541 #define I40E_FLAG_PTP BIT(17)
542 #define I40E_FLAG_IWARP_ENABLED BIT(18)
543 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19)
544 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20)
545 #define I40E_FLAG_TC_MQPRIO BIT(21)
546 #define I40E_FLAG_FD_SB_INACTIVE BIT(22)
547 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23)
548 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24)
549 #define I40E_FLAG_RS_FEC BIT(25)
550 #define I40E_FLAG_BASE_R_FEC BIT(26)
551 /* TOTAL_PORT_SHUTDOWN
552 * Allows to physically disable the link on the NIC's port.
553 * If enabled, (after link down request from the OS)
554 * no link, traffic or led activity is possible on that port.
555 *
556 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the
557 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true
558 * and cannot be disabled by system admin at that time.
559 * The functionalities are exclusive in terms of configuration, but they also
560 * have similar behavior (allowing to disable physical link of the port),
561 * with following differences:
562 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is
563 * supported by whole family of 7xx Intel Ethernet Controllers
564 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS)
565 * only if motherboard's BIOS and NIC's FW has support of it
566 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down
567 * by sending phy_type=0 to NIC's FW
568 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead
569 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK)
570 * in abilities field of i40e_aq_set_phy_config structure
571 */
572 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27)
573
574 struct i40e_client_instance *cinst;
575 bool stat_offsets_loaded;
576 struct i40e_hw_port_stats stats;
577 struct i40e_hw_port_stats stats_offsets;
578 u32 tx_timeout_count;
579 u32 tx_timeout_recovery_level;
580 unsigned long tx_timeout_last_recovery;
581 u32 tx_sluggish_count;
582 u32 hw_csum_rx_error;
583 u32 led_status;
584 u16 corer_count; /* Core reset count */
585 u16 globr_count; /* Global reset count */
586 u16 empr_count; /* EMP reset count */
587 u16 pfr_count; /* PF reset count */
588 u16 sw_int_count; /* SW interrupt count */
589
590 struct mutex switch_mutex;
591 u16 lan_vsi; /* our default LAN VSI */
592 u16 lan_veb; /* initial relay, if exists */
593 #define I40E_NO_VEB 0xffff
594 #define I40E_NO_VSI 0xffff
595 u16 next_vsi; /* Next unallocated VSI - 0-based! */
596 struct i40e_vsi **vsi;
597 struct i40e_veb *veb[I40E_MAX_VEB];
598
599 struct i40e_lump_tracking *qp_pile;
600 struct i40e_lump_tracking *irq_pile;
601
602 /* switch config info */
603 u16 pf_seid;
604 u16 main_vsi_seid;
605 u16 mac_seid;
606 struct kobject *switch_kobj;
607 #ifdef CONFIG_DEBUG_FS
608 struct dentry *i40e_dbg_pf;
609 #endif /* CONFIG_DEBUG_FS */
610 bool cur_promisc;
611
612 u16 instance; /* A unique number per i40e_pf instance in the system */
613
614 /* sr-iov config info */
615 struct i40e_vf *vf;
616 int num_alloc_vfs; /* actual number of VFs allocated */
617 u32 vf_aq_requests;
618 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
619
620 /* DCBx/DCBNL capability for PF that indicates
621 * whether DCBx is managed by firmware or host
622 * based agent (LLDPAD). Also, indicates what
623 * flavor of DCBx protocol (IEEE/CEE) is supported
624 * by the device. For now we're supporting IEEE
625 * mode only.
626 */
627 u16 dcbx_cap;
628
629 struct i40e_filter_control_settings filter_settings;
630
631 struct ptp_clock *ptp_clock;
632 struct ptp_clock_info ptp_caps;
633 struct sk_buff *ptp_tx_skb;
634 unsigned long ptp_tx_start;
635 struct hwtstamp_config tstamp_config;
636 struct timespec64 ptp_prev_hw_time;
637 ktime_t ptp_reset_start;
638 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
639 u32 ptp_adj_mult;
640 u32 tx_hwtstamp_timeouts;
641 u32 tx_hwtstamp_skipped;
642 u32 rx_hwtstamp_cleared;
643 u32 latch_event_flags;
644 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
645 unsigned long latch_events[4];
646 bool ptp_tx;
647 bool ptp_rx;
648 u16 rss_table_size; /* HW RSS table size */
649 u32 max_bw;
650 u32 min_bw;
651
652 u32 ioremap_len;
653 u32 fd_inv;
654 u16 phy_led_val;
655
656 u16 override_q_count;
657 u16 last_sw_conf_flags;
658 u16 last_sw_conf_valid_flags;
659 /* List to keep previous DDP profiles to be rolled back in the future */
660 struct list_head ddp_old_prof;
661 };
662
663 /**
664 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
665 * @macaddr: the MAC Address as the base key
666 *
667 * Simply copies the address and returns it as a u64 for hashing
668 **/
i40e_addr_to_hkey(const u8 * macaddr)669 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
670 {
671 u64 key = 0;
672
673 ether_addr_copy((u8 *)&key, macaddr);
674 return key;
675 }
676
677 enum i40e_filter_state {
678 I40E_FILTER_INVALID = 0, /* Invalid state */
679 I40E_FILTER_NEW, /* New, not sent to FW yet */
680 I40E_FILTER_ACTIVE, /* Added to switch by FW */
681 I40E_FILTER_FAILED, /* Rejected by FW */
682 I40E_FILTER_REMOVE, /* To be removed */
683 /* There is no 'removed' state; the filter struct is freed */
684 };
685 struct i40e_mac_filter {
686 struct hlist_node hlist;
687 u8 macaddr[ETH_ALEN];
688 #define I40E_VLAN_ANY -1
689 s16 vlan;
690 enum i40e_filter_state state;
691 };
692
693 /* Wrapper structure to keep track of filters while we are preparing to send
694 * firmware commands. We cannot send firmware commands while holding a
695 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
696 * a separate structure, which will track the state change and update the real
697 * filter while under lock. We can't simply hold the filters in a separate
698 * list, as this opens a window for a race condition when adding new MAC
699 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
700 */
701 struct i40e_new_mac_filter {
702 struct hlist_node hlist;
703 struct i40e_mac_filter *f;
704
705 /* Track future changes to state separately */
706 enum i40e_filter_state state;
707 };
708
709 struct i40e_veb {
710 struct i40e_pf *pf;
711 u16 idx;
712 u16 veb_idx; /* index of VEB parent */
713 u16 seid;
714 u16 uplink_seid;
715 u16 stats_idx; /* index of VEB parent */
716 u8 enabled_tc;
717 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
718 u16 flags;
719 u16 bw_limit;
720 u8 bw_max_quanta;
721 bool is_abs_credits;
722 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
723 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
724 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
725 struct kobject *kobj;
726 bool stat_offsets_loaded;
727 struct i40e_eth_stats stats;
728 struct i40e_eth_stats stats_offsets;
729 struct i40e_veb_tc_stats tc_stats;
730 struct i40e_veb_tc_stats tc_stats_offsets;
731 };
732
733 /* struct that defines a VSI, associated with a dev */
734 struct i40e_vsi {
735 struct net_device *netdev;
736 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
737 bool netdev_registered;
738 bool stat_offsets_loaded;
739
740 u32 current_netdev_flags;
741 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
742 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
743 #define I40E_VSI_FLAG_VEB_OWNER BIT(1)
744 unsigned long flags;
745
746 /* Per VSI lock to protect elements/hash (MAC filter) */
747 spinlock_t mac_filter_hash_lock;
748 /* Fixed size hash table with 2^8 buckets for MAC filters */
749 DECLARE_HASHTABLE(mac_filter_hash, 8);
750 bool has_vlan_filter;
751
752 /* VSI stats */
753 struct rtnl_link_stats64 net_stats;
754 struct rtnl_link_stats64 net_stats_offsets;
755 struct i40e_eth_stats eth_stats;
756 struct i40e_eth_stats eth_stats_offsets;
757 u64 tx_restart;
758 u64 tx_busy;
759 u64 tx_linearize;
760 u64 tx_force_wb;
761 u64 rx_buf_failed;
762 u64 rx_page_failed;
763
764 /* These are containers of ring pointers, allocated at run-time */
765 struct i40e_ring **rx_rings;
766 struct i40e_ring **tx_rings;
767 struct i40e_ring **xdp_rings; /* XDP Tx rings */
768
769 u32 active_filters;
770 u32 promisc_threshold;
771
772 u16 work_limit;
773 u16 int_rate_limit; /* value in usecs */
774
775 u16 rss_table_size; /* HW RSS table size */
776 u16 rss_size; /* Allocated RSS queues */
777 u8 *rss_hkey_user; /* User configured hash keys */
778 u8 *rss_lut_user; /* User configured lookup table entries */
779
780
781 u16 max_frame;
782 u16 rx_buf_len;
783
784 struct bpf_prog *xdp_prog;
785
786 /* List of q_vectors allocated to this VSI */
787 struct i40e_q_vector **q_vectors;
788 int num_q_vectors;
789 int base_vector;
790 bool irqs_ready;
791
792 u16 seid; /* HW index of this VSI (absolute index) */
793 u16 id; /* VSI number */
794 u16 uplink_seid;
795
796 u16 base_queue; /* vsi's first queue in hw array */
797 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
798 u16 req_queue_pairs; /* User requested queue pairs */
799 u16 num_queue_pairs; /* Used tx and rx pairs */
800 u16 num_tx_desc;
801 u16 num_rx_desc;
802 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
803 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
804
805 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
806 struct i40e_tc_configuration tc_config;
807 struct i40e_aqc_vsi_properties_data info;
808
809 /* VSI BW limit (absolute across all TCs) */
810 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
811 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
812
813 /* Relative TC credits across VSIs */
814 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
815 /* TC BW limit credits within VSI */
816 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
817 /* TC BW limit max quanta within VSI */
818 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
819
820 struct i40e_pf *back; /* Backreference to associated PF */
821 u16 idx; /* index in pf->vsi[] */
822 u16 veb_idx; /* index of VEB parent */
823 struct kobject *kobj; /* sysfs object */
824 bool current_isup; /* Sync 'link up' logging */
825 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
826
827 /* channel specific fields */
828 u16 cnt_q_avail; /* num of queues available for channel usage */
829 u16 orig_rss_size;
830 u16 current_rss_size;
831 bool reconfig_rss;
832
833 u16 next_base_queue; /* next queue to be used for channel setup */
834
835 struct list_head ch_list;
836 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
837
838 /* macvlan fields */
839 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */
840 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */
841 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
842 struct list_head macvlan_list;
843 int macvlan_cnt;
844
845 void *priv; /* client driver data reference. */
846
847 /* VSI specific handlers */
848 irqreturn_t (*irq_handler)(int irq, void *data);
849
850 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
851 } ____cacheline_internodealigned_in_smp;
852
853 struct i40e_netdev_priv {
854 struct i40e_vsi *vsi;
855 };
856
857 /* struct that defines an interrupt vector */
858 struct i40e_q_vector {
859 struct i40e_vsi *vsi;
860
861 u16 v_idx; /* index in the vsi->q_vector array. */
862 u16 reg_idx; /* register index of the interrupt */
863
864 struct napi_struct napi;
865
866 struct i40e_ring_container rx;
867 struct i40e_ring_container tx;
868
869 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
870 u8 num_ringpairs; /* total number of ring pairs in vector */
871
872 cpumask_t affinity_mask;
873 struct irq_affinity_notify affinity_notify;
874
875 struct rcu_head rcu; /* to avoid race with update stats on free */
876 char name[I40E_INT_NAME_STR_LEN];
877 bool arm_wb_state;
878 } ____cacheline_internodealigned_in_smp;
879
880 /* lan device */
881 struct i40e_device {
882 struct list_head list;
883 struct i40e_pf *pf;
884 };
885
886 /**
887 * i40e_nvm_version_str - format the NVM version strings
888 * @hw: ptr to the hardware info
889 **/
i40e_nvm_version_str(struct i40e_hw * hw)890 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
891 {
892 static char buf[32];
893 u32 full_ver;
894
895 full_ver = hw->nvm.oem_ver;
896
897 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
898 u8 gen, snap;
899 u16 release;
900
901 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
902 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
903 I40E_OEM_SNAP_SHIFT);
904 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
905
906 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
907 } else {
908 u8 ver, patch;
909 u16 build;
910
911 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
912 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
913 I40E_OEM_VER_BUILD_MASK);
914 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
915
916 snprintf(buf, sizeof(buf),
917 "%x.%02x 0x%x %d.%d.%d",
918 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
919 I40E_NVM_VERSION_HI_SHIFT,
920 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
921 I40E_NVM_VERSION_LO_SHIFT,
922 hw->nvm.eetrack, ver, build, patch);
923 }
924
925 return buf;
926 }
927
928 /**
929 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
930 * @netdev: the corresponding netdev
931 *
932 * Return the PF struct for the given netdev
933 **/
i40e_netdev_to_pf(struct net_device * netdev)934 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
935 {
936 struct i40e_netdev_priv *np = netdev_priv(netdev);
937 struct i40e_vsi *vsi = np->vsi;
938
939 return vsi->back;
940 }
941
i40e_vsi_setup_irqhandler(struct i40e_vsi * vsi,irqreturn_t (* irq_handler)(int,void *))942 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
943 irqreturn_t (*irq_handler)(int, void *))
944 {
945 vsi->irq_handler = irq_handler;
946 }
947
948 /**
949 * i40e_get_fd_cnt_all - get the total FD filter space available
950 * @pf: pointer to the PF struct
951 **/
i40e_get_fd_cnt_all(struct i40e_pf * pf)952 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
953 {
954 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
955 }
956
957 /**
958 * i40e_read_fd_input_set - reads value of flow director input set register
959 * @pf: pointer to the PF struct
960 * @addr: register addr
961 *
962 * This function reads value of flow director input set register
963 * specified by 'addr' (which is specific to flow-type)
964 **/
i40e_read_fd_input_set(struct i40e_pf * pf,u16 addr)965 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
966 {
967 u64 val;
968
969 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
970 val <<= 32;
971 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
972
973 return val;
974 }
975
976 /**
977 * i40e_write_fd_input_set - writes value into flow director input set register
978 * @pf: pointer to the PF struct
979 * @addr: register addr
980 * @val: value to be written
981 *
982 * This function writes specified value to the register specified by 'addr'.
983 * This register is input set register based on flow-type.
984 **/
i40e_write_fd_input_set(struct i40e_pf * pf,u16 addr,u64 val)985 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
986 u16 addr, u64 val)
987 {
988 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
989 (u32)(val >> 32));
990 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
991 (u32)(val & 0xFFFFFFFFULL));
992 }
993
994 /* needed by i40e_ethtool.c */
995 int i40e_up(struct i40e_vsi *vsi);
996 void i40e_down(struct i40e_vsi *vsi);
997 extern const char i40e_driver_name[];
998 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
999 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1000 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1001 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1002 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1003 u16 rss_table_size, u16 rss_size);
1004 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1005 /**
1006 * i40e_find_vsi_by_type - Find and return Flow Director VSI
1007 * @pf: PF to search for VSI
1008 * @type: Value indicating type of VSI we are looking for
1009 **/
1010 static inline struct i40e_vsi *
i40e_find_vsi_by_type(struct i40e_pf * pf,u16 type)1011 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1012 {
1013 int i;
1014
1015 for (i = 0; i < pf->num_alloc_vsi; i++) {
1016 struct i40e_vsi *vsi = pf->vsi[i];
1017
1018 if (vsi && vsi->type == type)
1019 return vsi;
1020 }
1021
1022 return NULL;
1023 }
1024 void i40e_update_stats(struct i40e_vsi *vsi);
1025 void i40e_update_veb_stats(struct i40e_veb *veb);
1026 void i40e_update_eth_stats(struct i40e_vsi *vsi);
1027 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1028 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1029 bool printconfig);
1030
1031 int i40e_add_del_fdir(struct i40e_vsi *vsi,
1032 struct i40e_fdir_filter *input, bool add);
1033 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1034 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1035 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1036 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1037 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1038 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1039 void i40e_set_ethtool_ops(struct net_device *netdev);
1040 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1041 const u8 *macaddr, s16 vlan);
1042 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1043 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1044 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1045 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1046 u16 uplink, u32 param1);
1047 int i40e_vsi_release(struct i40e_vsi *vsi);
1048 void i40e_service_event_schedule(struct i40e_pf *pf);
1049 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1050 u8 *msg, u16 len);
1051
1052 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1053 bool enable);
1054 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1055 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1056 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1057 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1058 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1059 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1060 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1061 u16 downlink_seid, u8 enabled_tc);
1062 void i40e_veb_release(struct i40e_veb *veb);
1063
1064 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1065 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1066 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1067 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1068 void i40e_pf_reset_stats(struct i40e_pf *pf);
1069 #ifdef CONFIG_DEBUG_FS
1070 void i40e_dbg_pf_init(struct i40e_pf *pf);
1071 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1072 void i40e_dbg_init(void);
1073 void i40e_dbg_exit(void);
1074 #else
i40e_dbg_pf_init(struct i40e_pf * pf)1075 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
i40e_dbg_pf_exit(struct i40e_pf * pf)1076 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
i40e_dbg_init(void)1077 static inline void i40e_dbg_init(void) {}
i40e_dbg_exit(void)1078 static inline void i40e_dbg_exit(void) {}
1079 #endif /* CONFIG_DEBUG_FS*/
1080 /* needed by client drivers */
1081 int i40e_lan_add_device(struct i40e_pf *pf);
1082 int i40e_lan_del_device(struct i40e_pf *pf);
1083 void i40e_client_subtask(struct i40e_pf *pf);
1084 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1085 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1086 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1087 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1088 void i40e_client_update_msix_info(struct i40e_pf *pf);
1089 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1090 /**
1091 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1092 * @vsi: pointer to a vsi
1093 * @vector: enable a particular Hw Interrupt vector, without base_vector
1094 **/
i40e_irq_dynamic_enable(struct i40e_vsi * vsi,int vector)1095 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1096 {
1097 struct i40e_pf *pf = vsi->back;
1098 struct i40e_hw *hw = &pf->hw;
1099 u32 val;
1100
1101 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1102 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1103 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1104 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1105 /* skip the flush */
1106 }
1107
1108 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1109 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1110 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1111 int i40e_open(struct net_device *netdev);
1112 int i40e_close(struct net_device *netdev);
1113 int i40e_vsi_open(struct i40e_vsi *vsi);
1114 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1115 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1116 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1117 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1118 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1119 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1120 const u8 *macaddr);
1121 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1122 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1123 int i40e_count_filters(struct i40e_vsi *vsi);
1124 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1125 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1126 #ifdef CONFIG_I40E_DCB
1127 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1128 struct i40e_dcbx_config *old_cfg,
1129 struct i40e_dcbx_config *new_cfg);
1130 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1131 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1132 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1133 struct i40e_dcbx_config *old_cfg,
1134 struct i40e_dcbx_config *new_cfg);
1135 #endif /* CONFIG_I40E_DCB */
1136 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1137 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1138 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1139 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1140 void i40e_ptp_set_increment(struct i40e_pf *pf);
1141 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1142 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1143 void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1144 void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1145 void i40e_ptp_init(struct i40e_pf *pf);
1146 void i40e_ptp_stop(struct i40e_pf *pf);
1147 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
1148 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1149 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1150 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1151 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1152 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1153
1154 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
1155
i40e_enabled_xdp_vsi(struct i40e_vsi * vsi)1156 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1157 {
1158 return !!READ_ONCE(vsi->xdp_prog);
1159 }
1160
1161 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1162 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1163 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1164 struct i40e_cloud_filter *filter,
1165 bool add);
1166 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1167 struct i40e_cloud_filter *filter,
1168 bool add);
1169 #endif /* _I40E_H_ */
1170