1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "c99_compat.h"
46 #include "util/compiler.h"
47 #include "util/macros.h"
48 #include "util/format/u_format.h"
49
50 #ifdef __cplusplus
51 extern "C" {
52 #endif
53
54 struct intel_device_info;
55 struct brw_image_param;
56
57 #ifndef ISL_GFX_VER
58 /**
59 * @brief Get the hardware generation of isl_device.
60 *
61 * You can define this as a compile-time constant in the CFLAGS. For example,
62 * `gcc -DISL_GFX_VER(dev)=9 ...`.
63 */
64 #define ISL_GFX_VER(__dev) ((__dev)->info->ver)
65 #define ISL_GFX_VERX10(__dev) ((__dev)->info->verx10)
66 #define ISL_GFX_VER_SANITIZE(__dev)
67 #else
68 #define ISL_GFX_VER_SANITIZE(__dev) \
69 (assert(ISL_GFX_VER(__dev) == (__dev)->info->ver) && \
70 ISL_GFX_VERX10(__dev) == (__dev)->info->verx10))
71 #endif
72
73 #ifndef ISL_DEV_IS_G4X
74 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
75 #endif
76
77 #ifndef ISL_DEV_IS_HASWELL
78 /**
79 * @brief Get the hardware generation of isl_device.
80 *
81 * You can define this as a compile-time constant in the CFLAGS. For example,
82 * `gcc -DISL_GFX_VER(dev)=9 ...`.
83 */
84 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
85 #endif
86
87 #ifndef ISL_DEV_IS_BAYTRAIL
88 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
89 #endif
90
91 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
92 /**
93 * You can define this as a compile-time constant in the CFLAGS. For example,
94 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
95 */
96 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
97 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
98 #else
99 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
100 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
101 #endif
102
103 /**
104 * Hardware enumeration SURFACE_FORMAT.
105 *
106 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
107 * Enumerations: SURFACE_FORMAT.
108 */
109 enum isl_format {
110 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
111 ISL_FORMAT_R32G32B32A32_SINT = 1,
112 ISL_FORMAT_R32G32B32A32_UINT = 2,
113 ISL_FORMAT_R32G32B32A32_UNORM = 3,
114 ISL_FORMAT_R32G32B32A32_SNORM = 4,
115 ISL_FORMAT_R64G64_FLOAT = 5,
116 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
117 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
118 ISL_FORMAT_R32G32B32A32_USCALED = 8,
119 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
120 ISL_FORMAT_R64G64_PASSTHRU = 33,
121 ISL_FORMAT_R32G32B32_FLOAT = 64,
122 ISL_FORMAT_R32G32B32_SINT = 65,
123 ISL_FORMAT_R32G32B32_UINT = 66,
124 ISL_FORMAT_R32G32B32_UNORM = 67,
125 ISL_FORMAT_R32G32B32_SNORM = 68,
126 ISL_FORMAT_R32G32B32_SSCALED = 69,
127 ISL_FORMAT_R32G32B32_USCALED = 70,
128 ISL_FORMAT_R32G32B32_SFIXED = 80,
129 ISL_FORMAT_R16G16B16A16_UNORM = 128,
130 ISL_FORMAT_R16G16B16A16_SNORM = 129,
131 ISL_FORMAT_R16G16B16A16_SINT = 130,
132 ISL_FORMAT_R16G16B16A16_UINT = 131,
133 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
134 ISL_FORMAT_R32G32_FLOAT = 133,
135 ISL_FORMAT_R32G32_SINT = 134,
136 ISL_FORMAT_R32G32_UINT = 135,
137 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
138 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
139 ISL_FORMAT_L32A32_FLOAT = 138,
140 ISL_FORMAT_R32G32_UNORM = 139,
141 ISL_FORMAT_R32G32_SNORM = 140,
142 ISL_FORMAT_R64_FLOAT = 141,
143 ISL_FORMAT_R16G16B16X16_UNORM = 142,
144 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
145 ISL_FORMAT_A32X32_FLOAT = 144,
146 ISL_FORMAT_L32X32_FLOAT = 145,
147 ISL_FORMAT_I32X32_FLOAT = 146,
148 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
149 ISL_FORMAT_R16G16B16A16_USCALED = 148,
150 ISL_FORMAT_R32G32_SSCALED = 149,
151 ISL_FORMAT_R32G32_USCALED = 150,
152 ISL_FORMAT_R32G32_FLOAT_LD = 151,
153 ISL_FORMAT_R32G32_SFIXED = 160,
154 ISL_FORMAT_R64_PASSTHRU = 161,
155 ISL_FORMAT_B8G8R8A8_UNORM = 192,
156 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
157 ISL_FORMAT_R10G10B10A2_UNORM = 194,
158 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
159 ISL_FORMAT_R10G10B10A2_UINT = 196,
160 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
161 ISL_FORMAT_R8G8B8A8_UNORM = 199,
162 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
163 ISL_FORMAT_R8G8B8A8_SNORM = 201,
164 ISL_FORMAT_R8G8B8A8_SINT = 202,
165 ISL_FORMAT_R8G8B8A8_UINT = 203,
166 ISL_FORMAT_R16G16_UNORM = 204,
167 ISL_FORMAT_R16G16_SNORM = 205,
168 ISL_FORMAT_R16G16_SINT = 206,
169 ISL_FORMAT_R16G16_UINT = 207,
170 ISL_FORMAT_R16G16_FLOAT = 208,
171 ISL_FORMAT_B10G10R10A2_UNORM = 209,
172 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
173 ISL_FORMAT_R11G11B10_FLOAT = 211,
174 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM = 213,
175 ISL_FORMAT_R32_SINT = 214,
176 ISL_FORMAT_R32_UINT = 215,
177 ISL_FORMAT_R32_FLOAT = 216,
178 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
179 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
180 ISL_FORMAT_L32_UNORM = 221,
181 ISL_FORMAT_A32_UNORM = 222,
182 ISL_FORMAT_L16A16_UNORM = 223,
183 ISL_FORMAT_I24X8_UNORM = 224,
184 ISL_FORMAT_L24X8_UNORM = 225,
185 ISL_FORMAT_A24X8_UNORM = 226,
186 ISL_FORMAT_I32_FLOAT = 227,
187 ISL_FORMAT_L32_FLOAT = 228,
188 ISL_FORMAT_A32_FLOAT = 229,
189 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
190 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
191 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
192 ISL_FORMAT_B8G8R8X8_UNORM = 233,
193 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
194 ISL_FORMAT_R8G8B8X8_UNORM = 235,
195 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
196 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
197 ISL_FORMAT_B10G10R10X2_UNORM = 238,
198 ISL_FORMAT_L16A16_FLOAT = 240,
199 ISL_FORMAT_R32_UNORM = 241,
200 ISL_FORMAT_R32_SNORM = 242,
201 ISL_FORMAT_R10G10B10X2_USCALED = 243,
202 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
203 ISL_FORMAT_R8G8B8A8_USCALED = 245,
204 ISL_FORMAT_R16G16_SSCALED = 246,
205 ISL_FORMAT_R16G16_USCALED = 247,
206 ISL_FORMAT_R32_SSCALED = 248,
207 ISL_FORMAT_R32_USCALED = 249,
208 ISL_FORMAT_B5G6R5_UNORM = 256,
209 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
210 ISL_FORMAT_B5G5R5A1_UNORM = 258,
211 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
212 ISL_FORMAT_B4G4R4A4_UNORM = 260,
213 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
214 ISL_FORMAT_R8G8_UNORM = 262,
215 ISL_FORMAT_R8G8_SNORM = 263,
216 ISL_FORMAT_R8G8_SINT = 264,
217 ISL_FORMAT_R8G8_UINT = 265,
218 ISL_FORMAT_R16_UNORM = 266,
219 ISL_FORMAT_R16_SNORM = 267,
220 ISL_FORMAT_R16_SINT = 268,
221 ISL_FORMAT_R16_UINT = 269,
222 ISL_FORMAT_R16_FLOAT = 270,
223 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
224 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
225 ISL_FORMAT_I16_UNORM = 273,
226 ISL_FORMAT_L16_UNORM = 274,
227 ISL_FORMAT_A16_UNORM = 275,
228 ISL_FORMAT_L8A8_UNORM = 276,
229 ISL_FORMAT_I16_FLOAT = 277,
230 ISL_FORMAT_L16_FLOAT = 278,
231 ISL_FORMAT_A16_FLOAT = 279,
232 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
233 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
234 ISL_FORMAT_B5G5R5X1_UNORM = 282,
235 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
236 ISL_FORMAT_R8G8_SSCALED = 284,
237 ISL_FORMAT_R8G8_USCALED = 285,
238 ISL_FORMAT_R16_SSCALED = 286,
239 ISL_FORMAT_R16_USCALED = 287,
240 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
241 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
242 ISL_FORMAT_A1B5G5R5_UNORM = 292,
243 ISL_FORMAT_A4B4G4R4_UNORM = 293,
244 ISL_FORMAT_L8A8_UINT = 294,
245 ISL_FORMAT_L8A8_SINT = 295,
246 ISL_FORMAT_R8_UNORM = 320,
247 ISL_FORMAT_R8_SNORM = 321,
248 ISL_FORMAT_R8_SINT = 322,
249 ISL_FORMAT_R8_UINT = 323,
250 ISL_FORMAT_A8_UNORM = 324,
251 ISL_FORMAT_I8_UNORM = 325,
252 ISL_FORMAT_L8_UNORM = 326,
253 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
254 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
255 ISL_FORMAT_R8_SSCALED = 329,
256 ISL_FORMAT_R8_USCALED = 330,
257 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
258 ISL_FORMAT_L8_UNORM_SRGB = 332,
259 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
260 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
261 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
262 ISL_FORMAT_Y8_UNORM = 336,
263 ISL_FORMAT_L8_UINT = 338,
264 ISL_FORMAT_L8_SINT = 339,
265 ISL_FORMAT_I8_UINT = 340,
266 ISL_FORMAT_I8_SINT = 341,
267 ISL_FORMAT_DXT1_RGB_SRGB = 384,
268 ISL_FORMAT_R1_UNORM = 385,
269 ISL_FORMAT_YCRCB_NORMAL = 386,
270 ISL_FORMAT_YCRCB_SWAPUVY = 387,
271 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
272 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
273 ISL_FORMAT_BC1_UNORM = 390,
274 ISL_FORMAT_BC2_UNORM = 391,
275 ISL_FORMAT_BC3_UNORM = 392,
276 ISL_FORMAT_BC4_UNORM = 393,
277 ISL_FORMAT_BC5_UNORM = 394,
278 ISL_FORMAT_BC1_UNORM_SRGB = 395,
279 ISL_FORMAT_BC2_UNORM_SRGB = 396,
280 ISL_FORMAT_BC3_UNORM_SRGB = 397,
281 ISL_FORMAT_MONO8 = 398,
282 ISL_FORMAT_YCRCB_SWAPUV = 399,
283 ISL_FORMAT_YCRCB_SWAPY = 400,
284 ISL_FORMAT_DXT1_RGB = 401,
285 ISL_FORMAT_FXT1 = 402,
286 ISL_FORMAT_R8G8B8_UNORM = 403,
287 ISL_FORMAT_R8G8B8_SNORM = 404,
288 ISL_FORMAT_R8G8B8_SSCALED = 405,
289 ISL_FORMAT_R8G8B8_USCALED = 406,
290 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
291 ISL_FORMAT_R64G64B64_FLOAT = 408,
292 ISL_FORMAT_BC4_SNORM = 409,
293 ISL_FORMAT_BC5_SNORM = 410,
294 ISL_FORMAT_R16G16B16_FLOAT = 411,
295 ISL_FORMAT_R16G16B16_UNORM = 412,
296 ISL_FORMAT_R16G16B16_SNORM = 413,
297 ISL_FORMAT_R16G16B16_SSCALED = 414,
298 ISL_FORMAT_R16G16B16_USCALED = 415,
299 ISL_FORMAT_BC6H_SF16 = 417,
300 ISL_FORMAT_BC7_UNORM = 418,
301 ISL_FORMAT_BC7_UNORM_SRGB = 419,
302 ISL_FORMAT_BC6H_UF16 = 420,
303 ISL_FORMAT_PLANAR_420_8 = 421,
304 ISL_FORMAT_PLANAR_420_16 = 422,
305 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
306 ISL_FORMAT_ETC1_RGB8 = 425,
307 ISL_FORMAT_ETC2_RGB8 = 426,
308 ISL_FORMAT_EAC_R11 = 427,
309 ISL_FORMAT_EAC_RG11 = 428,
310 ISL_FORMAT_EAC_SIGNED_R11 = 429,
311 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
312 ISL_FORMAT_ETC2_SRGB8 = 431,
313 ISL_FORMAT_R16G16B16_UINT = 432,
314 ISL_FORMAT_R16G16B16_SINT = 433,
315 ISL_FORMAT_R32_SFIXED = 434,
316 ISL_FORMAT_R10G10B10A2_SNORM = 435,
317 ISL_FORMAT_R10G10B10A2_USCALED = 436,
318 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
319 ISL_FORMAT_R10G10B10A2_SINT = 438,
320 ISL_FORMAT_B10G10R10A2_SNORM = 439,
321 ISL_FORMAT_B10G10R10A2_USCALED = 440,
322 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
323 ISL_FORMAT_B10G10R10A2_UINT = 442,
324 ISL_FORMAT_B10G10R10A2_SINT = 443,
325 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
326 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
327 ISL_FORMAT_ETC2_RGB8_PTA = 448,
328 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
329 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
330 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
331 ISL_FORMAT_R8G8B8_UINT = 456,
332 ISL_FORMAT_R8G8B8_SINT = 457,
333 ISL_FORMAT_RAW = 511,
334 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
335 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
336 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
337 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
338 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
339 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
340 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
341 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
342 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
343 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
344 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
345 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
346 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
347 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
348 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
349 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
350 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
351 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
352 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
353 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
354 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
355 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
356 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
357 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
358 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
359 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
360 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
361 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
362 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
363 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
364 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
365 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
366 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
367 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
368 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
369 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
370 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
371 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
372 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
373 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
374 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
375 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
376
377 /* The formats that follow are internal to ISL and as such don't have an
378 * explicit number. We'll just let the C compiler assign it for us. Any
379 * actual hardware formats *must* come before these in the list.
380 */
381
382 /* Formats for the aux-map */
383 ISL_FORMAT_PLANAR_420_10,
384 ISL_FORMAT_PLANAR_420_12,
385
386 /* Formats for auxiliary surfaces */
387 ISL_FORMAT_HIZ,
388 ISL_FORMAT_MCS_2X,
389 ISL_FORMAT_MCS_4X,
390 ISL_FORMAT_MCS_8X,
391 ISL_FORMAT_MCS_16X,
392 ISL_FORMAT_GFX7_CCS_32BPP_X,
393 ISL_FORMAT_GFX7_CCS_64BPP_X,
394 ISL_FORMAT_GFX7_CCS_128BPP_X,
395 ISL_FORMAT_GFX7_CCS_32BPP_Y,
396 ISL_FORMAT_GFX7_CCS_64BPP_Y,
397 ISL_FORMAT_GFX7_CCS_128BPP_Y,
398 ISL_FORMAT_GFX9_CCS_32BPP,
399 ISL_FORMAT_GFX9_CCS_64BPP,
400 ISL_FORMAT_GFX9_CCS_128BPP,
401 ISL_FORMAT_GFX12_CCS_8BPP_Y0,
402 ISL_FORMAT_GFX12_CCS_16BPP_Y0,
403 ISL_FORMAT_GFX12_CCS_32BPP_Y0,
404 ISL_FORMAT_GFX12_CCS_64BPP_Y0,
405 ISL_FORMAT_GFX12_CCS_128BPP_Y0,
406
407 /* An upper bound on the supported format enumerations */
408 ISL_NUM_FORMATS,
409
410 /* Hardware doesn't understand this out-of-band value */
411 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
412 };
413
414 /**
415 * Numerical base type for channels of isl_format.
416 */
417 enum PACKED isl_base_type {
418 /** Data which takes up space but is ignored */
419 ISL_VOID,
420
421 /** Data in a "raw" form and cannot be easily interpreted */
422 ISL_RAW,
423
424 /**
425 * Unsigned normalized data
426 *
427 * Though stored as an integer, the data is interpreted as a floating-point
428 * number in the range [0, 1] where the conversion from the in-memory
429 * representation to float is given by \f$\frac{x}{2^{bits} - 1}\f$.
430 */
431 ISL_UNORM,
432
433 /**
434 * Signed normalized data
435 *
436 * Though stored as an integer, the data is interpreted as a floating-point
437 * number in the range [-1, 1] where the conversion from the in-memory
438 * representation to float is given by
439 * \f$max\left(\frac{x}{2^{bits - 1} - 1}, -1\right)\f$.
440 */
441 ISL_SNORM,
442
443 /**
444 * Unsigned floating-point data
445 *
446 * Unlike the standard IEEE floating-point representation, unsigned
447 * floating-point data has no sign bit. This saves a bit of space which is
448 * important if more than one float is required to represent a color value.
449 * As with IEEE floats, the high bits are the exponent and the low bits are
450 * the mantissa. The available bit sizes for unsigned floats are as
451 * follows:
452 *
453 * \rst
454 * ===== ========= =========
455 * Bits Mantissa Exponent
456 * ===== ========= =========
457 * 11 6 5
458 * 10 5 5
459 * ===== ========= =========
460 * \endrst
461 *
462 * In particular, both unsigned floating-point formats are identical to
463 * IEEE float16 except that the sign bit and the bottom mantissa bits are
464 * removed.
465 */
466 ISL_UFLOAT,
467
468 /** Signed floating-point data
469 *
470 * Signed floating-point data is represented as standard IEEE floats with
471 * the usual number of mantissa and exponent bits
472 *
473 * \rst
474 * ===== ========= =========
475 * Bits Mantissa Exponent
476 * ===== ========= =========
477 * 64 52 11
478 * 32 23 8
479 * 16 10 5
480 * ===== ========= =========
481 * \endrst
482 */
483 ISL_SFLOAT,
484
485 /**
486 * Unsigned fixed-point data
487 *
488 * This is a 32-bit unsigned integer that is interpreted as a 16.16
489 * fixed-point value.
490 */
491 ISL_UFIXED,
492
493 /**
494 * Signed fixed-point data
495 *
496 * This is a 32-bit signed integer that is interpreted as a 16.16
497 * fixed-point value.
498 */
499 ISL_SFIXED,
500
501 /** Unsigned integer data */
502 ISL_UINT,
503
504 /** Signed integer data */
505 ISL_SINT,
506
507 /**
508 * Unsigned scaled data
509 *
510 * This is data which is stored as an unsigned integer but interpreted as a
511 * floating-point value by the hardware. The re-interpretation is done via
512 * a simple unsigned integer to float cast. This is typically used as a
513 * vertex format.
514 */
515 ISL_USCALED,
516
517 /**
518 * Signed scaled data
519 *
520 * This is data which is stored as a signed integer but interpreted as a
521 * floating-point value by the hardware. The re-interpretation is done via
522 * a simple signed integer to float cast. This is typically used as a
523 * vertex format.
524 */
525 ISL_SSCALED,
526 };
527
528 /**
529 * Colorspace of isl_format.
530 */
531 enum isl_colorspace {
532 ISL_COLORSPACE_NONE = 0,
533 ISL_COLORSPACE_LINEAR,
534 ISL_COLORSPACE_SRGB,
535 ISL_COLORSPACE_YUV,
536 };
537
538 /**
539 * Texture compression mode of isl_format.
540 */
541 enum isl_txc {
542 ISL_TXC_NONE = 0,
543 ISL_TXC_DXT1,
544 ISL_TXC_DXT3,
545 ISL_TXC_DXT5,
546 ISL_TXC_FXT1,
547 ISL_TXC_RGTC1,
548 ISL_TXC_RGTC2,
549 ISL_TXC_BPTC,
550 ISL_TXC_ETC1,
551 ISL_TXC_ETC2,
552 ISL_TXC_ASTC,
553
554 /* Used for auxiliary surface formats */
555 ISL_TXC_HIZ,
556 ISL_TXC_MCS,
557 ISL_TXC_CCS,
558 };
559
560 /**
561 * Describes the memory tiling of a surface
562 *
563 * This differs from the HW enum values used to represent tiling. The bits
564 * used by hardware have varried significantly over the years from the
565 * "Tile Walk" bit on old pre-Broadwell parts to the "Tile Mode" enum on
566 * Broadwell to the combination of "Tile Mode" and "Tiled Resource Mode" on
567 * Skylake. This enum represents them all in a consistent manner and in one
568 * place.
569 *
570 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
571 * clearly distinguish it from Yf and Ys.
572 */
573 enum isl_tiling {
574 ISL_TILING_LINEAR = 0, /**< Linear, or no tiling */
575 ISL_TILING_W, /**< W tiling */
576 ISL_TILING_X, /**< X tiling */
577 ISL_TILING_Y0, /**< Legacy Y tiling */
578 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
579 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
580 ISL_TILING_4, /**< 4K tiling. */
581 ISL_TILING_64, /**< 64K tiling.*/
582 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
583 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
584 ISL_TILING_GFX12_CCS, /**< Tiling format for Gfx12 CCS surfaces */
585 };
586
587 /**
588 * @defgroup Tiling Flags
589 * @{
590 */
591 typedef uint32_t isl_tiling_flags_t;
592 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
593 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
594 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
595 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
596 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
597 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
598 #define ISL_TILING_4_BIT (1u << ISL_TILING_4)
599 #define ISL_TILING_64_BIT (1u << ISL_TILING_64)
600 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
601 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
602 #define ISL_TILING_GFX12_CCS_BIT (1u << ISL_TILING_GFX12_CCS)
603 #define ISL_TILING_ANY_MASK (~0u)
604 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
605
606 /** Any Y tiling, including legacy Y tiling. */
607 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
608 ISL_TILING_Yf_BIT | \
609 ISL_TILING_Ys_BIT)
610
611 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
612 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
613 ISL_TILING_Ys_BIT)
614 /** @} */
615
616 /**
617 * @brief Logical dimension of surface.
618 *
619 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
620 * as 2D array surfaces.
621 */
622 enum isl_surf_dim {
623 ISL_SURF_DIM_1D,
624 ISL_SURF_DIM_2D,
625 ISL_SURF_DIM_3D,
626 };
627
628 /**
629 * @brief Physical layout of the surface's dimensions.
630 */
631 enum isl_dim_layout {
632 /**
633 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
634 * 6.17.3: 2D Surfaces.
635 *
636 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
637 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
638 *
639 * One-dimensional surfaces are identical to 2D surfaces with height of
640 * one.
641 *
642 * @invariant isl_surf::phys_level0_sa::depth == 1
643 */
644 ISL_DIM_LAYOUT_GFX4_2D,
645
646 /**
647 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
648 * 6.17.5: 3D Surfaces.
649 *
650 * @invariant isl_surf::phys_level0_sa::array_len == 1
651 */
652 ISL_DIM_LAYOUT_GFX4_3D,
653
654 /**
655 * Special layout used for HiZ and stencil on Sandy Bridge to work around
656 * the hardware's lack of mipmap support. On gfx6, HiZ and stencil buffers
657 * work the same as on gfx7+ except that they don't technically support
658 * mipmapping. That does not, however, stop us from doing it. As far as
659 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
660 * single miplevel 2D (possibly array) image. The dimensions of that image
661 * are NOT minified.
662 *
663 * In order to implement HiZ and stencil on Sandy Bridge, we create one
664 * full-sized 2D (possibly array) image for every LOD with every image
665 * aligned to a page boundary. When the surface is used with the stencil
666 * or HiZ hardware, we manually offset to the image for the given LOD.
667 *
668 * As a memory saving measure, we pretend that the width of each miplevel
669 * is minified and we place LOD1 and above below LOD0 but horizontally
670 * adjacent to each other. When considered as full-sized images, LOD1 and
671 * above technically overlap. However, since we only write to part of that
672 * image, the hardware will never notice the overlap.
673 *
674 * This layout looks something like this:
675 *
676 * +---------+
677 * | |
678 * | |
679 * +---------+
680 * | |
681 * | |
682 * +---------+
683 *
684 * +----+ +-+ .
685 * | | +-+
686 * +----+
687 *
688 * +----+ +-+ .
689 * | | +-+
690 * +----+
691 */
692 ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ,
693
694 /**
695 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
696 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
697 */
698 ISL_DIM_LAYOUT_GFX9_1D,
699 };
700
701 /**
702 * Enumerates the different forms of auxiliary surface compression
703 */
704 enum isl_aux_usage {
705 /** No Auxiliary surface is used */
706 ISL_AUX_USAGE_NONE,
707
708 /** Hierarchical depth compression
709 *
710 * First introduced on Iron Lake, this compression scheme compresses depth
711 * surfaces by storing alternate forms of the depth value in a HiZ surface.
712 * Possible (not all) compressed forms include:
713 *
714 * - An uncompressed "look at the main surface" value
715 *
716 * - A special value indicating that the main surface data should be
717 * ignored and considered to contain the clear value.
718 *
719 * - The depth for the entire main-surface block as a plane equation
720 *
721 * - The minimum/maximum depth for the main-surface block
722 *
723 * This second one isn't helpful for getting exact depth values but can
724 * still substantially accelerate depth testing if the specified range is
725 * sufficiently small.
726 */
727 ISL_AUX_USAGE_HIZ,
728
729 /** Multisampled color compression
730 *
731 * Introduced on Ivy Bridge, this compression scheme compresses
732 * multisampled color surfaces by storing a mapping from samples to planes
733 * in the MCS surface, allowing for de-duplication of identical samples.
734 * The MCS value of all 1's is reserved to indicate that the pixel contains
735 * the clear color. Exact details about the data stored in the MCS and how
736 * it maps samples to slices is documented in the PRMs.
737 *
738 * @invariant isl_surf::samples > 1
739 */
740 ISL_AUX_USAGE_MCS,
741
742 /** Single-sampled fast-clear-only color compression
743 *
744 * Introduced on Ivy Bridge, this compression scheme compresses
745 * single-sampled color surfaces by storing a bit for each cache line pair
746 * in the main surface in the CCS which indicates that the corresponding
747 * pair of cache lines in the main surface only contains the clear color.
748 * On Skylake, this is increased to two bits per cache line pair with 0x0
749 * meaning resolved and 0x3 meaning clear.
750 *
751 * @invariant The surface is a color surface
752 * @invariant isl_surf::samples == 1
753 */
754 ISL_AUX_USAGE_CCS_D,
755
756 /** Single-sample lossless color compression
757 *
758 * Introduced on Skylake, this compression scheme compresses single-sampled
759 * color surfaces by storing a 2-bit value for each cache line pair in the
760 * main surface which says how the corresponding pair of cache lines in the
761 * main surface are to be interpreted. Valid CCS values include:
762 *
763 * - `0x0`: Indicates that the corresponding pair of cache lines in the
764 * main surface contain valid color data
765 *
766 * - `0x1`: Indicates that the corresponding pair of cache lines in the
767 * main surface contain compressed color data. Typically, the
768 * compressed data fits in one of the two cache lines.
769 *
770 * - `0x3`: Indicates that the corresponding pair of cache lines in the
771 * main surface should be ignored. Those cache lines should be
772 * considered to contain the clear color.
773 *
774 * Starting with Tigerlake, each CCS value is 4 bits per cache line pair in
775 * the main surface.
776 *
777 * @invariant The surface is a color surface
778 * @invariant isl_surf::samples == 1
779 */
780 ISL_AUX_USAGE_CCS_E,
781
782 /** Single-sample lossless color compression on Tigerlake
783 *
784 * This is identical to ISL_AUX_USAGE_CCS_E except it also encodes the
785 * Tigerlake quirk about regular render writes possibly fast-clearing
786 * blocks in the surface.
787 *
788 * @invariant The surface is a color surface
789 * @invariant isl_surf::samples == 1
790 */
791 ISL_AUX_USAGE_GFX12_CCS_E,
792
793 /** Media color compression
794 *
795 * Used by the media engine on Tigerlake and above. This compression form
796 * is typically not produced by 3D drivers but they need to be able to
797 * consume it in order to get end-to-end compression when the image comes
798 * from media decode.
799 *
800 * @invariant The surface is a color surface
801 * @invariant isl_surf::samples == 1
802 */
803 ISL_AUX_USAGE_MC,
804
805 /** Combined HiZ+CCS in write-through mode
806 *
807 * In this mode, introduced on Tigerlake, the HiZ and CCS surfaces act as a
808 * single fused compression surface where resolves (but not ambiguates)
809 * operate on both surfaces at the same time. In this mode, the HiZ
810 * surface operates in write-through mode where it is only used for
811 * accelerating depth testing and not for actual compression. The
812 * CCS-compressed surface contains valid data at all times.
813 *
814 * @invariant The surface is a color surface
815 * @invariant isl_surf::samples == 1
816 */
817 ISL_AUX_USAGE_HIZ_CCS_WT,
818
819 /** Combined HiZ+CCS without write-through
820 *
821 * In this mode, introduced on Tigerlake, the HiZ and CCS surfaces act as a
822 * single fused compression surface where resolves (but not ambiguates)
823 * operate on both surfaces at the same time. In this mode, full HiZ
824 * compression is enabled and the CCS-compressed main surface may not
825 * contain valid data. The only way to read the surface outside of the
826 * depth hardware is to do a full resolve which resolves both HiZ and CCS
827 * so the surface is in the pass-through state.
828 *
829 * @invariant The surface is a depth surface
830 */
831 ISL_AUX_USAGE_HIZ_CCS,
832
833 /** Combined MCS+CCS without write-through
834 *
835 * In this mode, introduced on Tigerlake, we have fused MCS+CCS compression
836 * where the MCS is used for fast-clears and "identical samples"
837 * compression just like on Gfx7-11 but each plane is then CCS compressed.
838 *
839 * @invariant The surface is a depth surface
840 * @invariant isl_surf::samples > 1
841 */
842 ISL_AUX_USAGE_MCS_CCS,
843
844 /** Stencil compression
845 *
846 * Introduced on Tigerlake, this is similar to CCS_E only used to compress
847 * stencil surfaces.
848 *
849 * @invariant The surface is a stencil surface
850 * @invariant isl_surf::samples == 1
851 */
852 ISL_AUX_USAGE_STC_CCS,
853 };
854
855 /**
856 * Enum for keeping track of the state an auxiliary compressed surface.
857 *
858 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
859 * given slice (lod + array layer) can be in one of the seven states described
860 * by this enum. Drawing with or without aux enabled may implicitly cause the
861 * surface to transition between these states. There are also four types of
862 * auxiliary compression operations which cause an explicit transition which
863 * are described by the isl_aux_op enum below.
864 *
865 * Not all operations are valid or useful in all states. The diagram below
866 * contains a complete description of the states and all valid and useful
867 * transitions except clear.
868 *
869 * Draw w/ Aux
870 * +----------+
871 * | |
872 * | +-------------+ Draw w/ Aux +-------------+
873 * +------>| Compressed |<-------------------| Clear |
874 * | w/ Clear |----->----+ | |
875 * +-------------+ | +-------------+
876 * | /|\ | | |
877 * | | | | |
878 * | | +------<-----+ | Draw w/
879 * | | | | Clear Only
880 * | | Full | | +----------+
881 * Partial | | Resolve | \|/ | |
882 * Resolve | | | +-------------+ |
883 * | | | | Partial |<------+
884 * | | | | Clear |<----------+
885 * | | | +-------------+ |
886 * | | | | |
887 * | | +------>---------+ Full |
888 * | | | Resolve |
889 * Draw w/ aux | | Partial Fast Clear | |
890 * +----------+ | +--------------------------+ | |
891 * | | \|/ | \|/ |
892 * | +-------------+ Full Resolve +-------------+ |
893 * +------>| Compressed |------------------->| Resolved | |
894 * | w/o Clear |<-------------------| | |
895 * +-------------+ Draw w/ Aux +-------------+ |
896 * /|\ | | |
897 * | Draw | | Draw |
898 * | w/ Aux | | w/o Aux |
899 * | Ambiguate | | |
900 * | +--------------------------+ | |
901 * Draw w/o Aux | | | Draw w/o Aux |
902 * +----------+ | | | +----------+ |
903 * | | | \|/ \|/ | | |
904 * | +-------------+ Ambiguate +-------------+ | |
905 * +------>| Pass- |<-------------------| Aux |<------+ |
906 * +------>| through | | Invalid | |
907 * | +-------------+ +-------------+ |
908 * | | | |
909 * +----------+ +-----------------------------------------------------+
910 * Draw w/ Partial Fast Clear
911 * Clear Only
912 *
913 *
914 * While the above general theory applies to all forms of auxiliary
915 * compression on Intel hardware, not all states and operations are available
916 * on all compression types. However, each of the auxiliary states and
917 * operations can be fairly easily mapped onto the above diagram:
918 *
919 * **HiZ:** Hierarchical depth compression is capable of being in any of
920 * the states above. Hardware provides three HiZ operations: "Depth
921 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast Clear",
922 * "Full Resolve", and "Ambiguate" respectively. The hardware provides no
923 * HiZ partial resolve operation so the only way to get into the
924 * "Compressed w/o Clear" state is to render with HiZ when the surface is
925 * in the resolved or pass-through states.
926 *
927 * **MCS:** Multisample compression is technically capable of being in any of
928 * the states above except that most of them aren't useful. Both the render
929 * engine and the sampler support MCS compression and, apart from clear color,
930 * MCS is format-unaware so we leave the surface compressed 100% of the time.
931 * The hardware provides no MCS operations.
932 *
933 * **CCS_D:** Single-sample fast-clears (also called CCS_D in ISL) are one of
934 * the simplest forms of compression since they don't do anything beyond clear
935 * color tracking. They really only support three of the six states: Clear,
936 * Partial Clear, and Pass-through. The only CCS_D operation is "Resolve"
937 * which maps to a full resolve followed by an ambiguate.
938 *
939 * **CCS_E:** Single-sample render target compression (also called CCS_E in
940 * ISL) is capable of being in almost all of the above states. THe only
941 * exception is that it does not have separate resolved and pass- through
942 * states. Instead, the CCS_E full resolve operation does both a resolve and
943 * an ambiguate so it goes directly into the pass-through state. CCS_E also
944 * provides fast clear and partial resolve operations which work as described
945 * above.
946 *
947 * @note
948 * The state machine above isn't quite correct for CCS on TGL. There is a HW
949 * bug (or feature, depending on who you ask) which can cause blocks to enter
950 * the fast-clear state as a side-effect of a regular draw call. This means
951 * that a draw in the resolved or compressed without clear states takes you to
952 * the compressed with clear state, not the compressed without clear state.
953 */
954 enum isl_aux_state {
955 #ifdef IN_UNIT_TEST
956 ISL_AUX_STATE_ASSERT,
957 #endif
958 /** Clear
959 *
960 * In this state, each block in the auxiliary surface contains a magic
961 * value that indicates that the block is in the clear state. If a block
962 * is in the clear state, its values in the primary surface are ignored
963 * and the color of the samples in the block is taken either the
964 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for depth.
965 * Since neither the primary surface nor the auxiliary surface contains the
966 * clear value, the surface can be cleared to a different color by simply
967 * changing the clear color without modifying either surface.
968 */
969 ISL_AUX_STATE_CLEAR,
970
971 /** Partial Clear
972 *
973 * In this state, each block in the auxiliary surface contains either the
974 * magic clear or pass-through value. See Clear and Pass-through for more
975 * details.
976 */
977 ISL_AUX_STATE_PARTIAL_CLEAR,
978
979 /** Compressed with clear color
980 *
981 * In this state, neither the auxiliary surface nor the primary surface has
982 * a complete representation of the data. Instead, both surfaces must be
983 * used together or else rendering corruption may occur. Depending on the
984 * auxiliary compression format and the data, any given block in the
985 * primary surface may contain all, some, or none of the data required to
986 * reconstruct the actual sample values. Blocks may also be in the clear
987 * state (see Clear) and have their value taken from outside the surface.
988 */
989 ISL_AUX_STATE_COMPRESSED_CLEAR,
990
991 /** Compressed without clear color
992 *
993 * This state is identical to the state above except that no blocks are in
994 * the clear state. In this state, all of the data required to reconstruct
995 * the final sample values is contained in the auxiliary and primary
996 * surface and the clear value is not considered.
997 */
998 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
999
1000 /** Resolved
1001 *
1002 * In this state, the primary surface contains 100% of the data. The
1003 * auxiliary surface is also valid so the surface can be validly used with
1004 * or without aux enabled. The auxiliary surface may, however, contain
1005 * non-trivial data and any update to the primary surface with aux disabled
1006 * will cause the two to get out of sync.
1007 */
1008 ISL_AUX_STATE_RESOLVED,
1009
1010 /** Pass-through
1011 *
1012 * In this state, the primary surface contains 100% of the data and every
1013 * block in the auxiliary surface contains a magic value which indicates
1014 * that the auxiliary surface should be ignored and only the primary
1015 * surface should be considered. In this mode, the primary surface can
1016 * safely be written with ISL_AUX_USAGE_NONE or by something that ignores
1017 * compression such as the blit/copy engine or a CPU map and it will stay
1018 * in the pass-through state. Writing to a surface in pass-through mode
1019 * with aux enabled may cause the auxiliary to be updated to contain
1020 * non-trivial data and it will no longer be in the pass-through state.
1021 * Likely, it will end up compressed, with or without clear color.
1022 */
1023 ISL_AUX_STATE_PASS_THROUGH,
1024
1025 /** Aux Invalid
1026 *
1027 * In this state, the primary surface contains 100% of the data and the
1028 * auxiliary surface is completely bogus. Any attempt to use the auxiliary
1029 * surface is liable to result in rendering corruption. The only thing
1030 * that one can do to re-enable aux once this state is reached is to use an
1031 * ambiguate pass to transition into the pass-through state.
1032 */
1033 ISL_AUX_STATE_AUX_INVALID,
1034 };
1035
1036 /** Enum describing explicit aux transition operations
1037 *
1038 * These operations are used to transition from one isl_aux_state to another.
1039 * Even though a draw does transition the state machine, it's not included in
1040 * this enum as it's something of a special case.
1041 */
1042 enum isl_aux_op {
1043 #ifdef IN_UNIT_TEST
1044 ISL_AUX_OP_ASSERT,
1045 #endif
1046
1047 /** Do nothing */
1048 ISL_AUX_OP_NONE,
1049
1050 /** Fast Clear
1051 *
1052 * This operation writes the magic "clear" value to the auxiliary surface.
1053 * This operation will safely transition any slice of a surface from any
1054 * state to the clear state so long as the entire slice is fast cleared at
1055 * once. A fast clear that only covers part of a slice of a surface is
1056 * called a partial fast clear.
1057 */
1058 ISL_AUX_OP_FAST_CLEAR,
1059
1060 /** Full Resolve
1061 *
1062 * This operation combines the auxiliary surface data with the primary
1063 * surface data and writes the result to the primary. For HiZ, the docs
1064 * call this a depth resolve. For CCS, the hardware full resolve operation
1065 * does both a full resolve and an ambiguate so it actually takes you all
1066 * the way to the pass-through state.
1067 */
1068 ISL_AUX_OP_FULL_RESOLVE,
1069
1070 /** Partial Resolve
1071 *
1072 * This operation considers blocks which are in the "clear" state and
1073 * writes the clear value directly into the primary or auxiliary surface.
1074 * Once this operation completes, the surface is still compressed but no
1075 * longer references the clear color. This operation is only available
1076 * for CCS_E.
1077 */
1078 ISL_AUX_OP_PARTIAL_RESOLVE,
1079
1080 /** Ambiguate
1081 *
1082 * This operation throws away the current auxiliary data and replaces it
1083 * with the magic pass-through value. If an ambiguate operation is
1084 * performed when the primary surface does not contain 100% of the data,
1085 * data will be lost. This operation is only implemented in hardware for
1086 * depth where it is called a HiZ resolve.
1087 */
1088 ISL_AUX_OP_AMBIGUATE,
1089 };
1090
1091 /* TODO(chadv): Explain */
1092 enum isl_array_pitch_span {
1093 ISL_ARRAY_PITCH_SPAN_FULL,
1094 ISL_ARRAY_PITCH_SPAN_COMPACT,
1095 };
1096
1097 /**
1098 * @defgroup Surface Usage
1099 * @{
1100 */
1101 typedef uint64_t isl_surf_usage_flags_t;
1102 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
1103 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
1104 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
1105 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
1106 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
1107 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
1108 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
1109 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 7)
1110 #define ISL_SURF_USAGE_HIZ_BIT (1u << 8)
1111 #define ISL_SURF_USAGE_MCS_BIT (1u << 9)
1112 #define ISL_SURF_USAGE_CCS_BIT (1u << 10)
1113 #define ISL_SURF_USAGE_VERTEX_BUFFER_BIT (1u << 11)
1114 #define ISL_SURF_USAGE_INDEX_BUFFER_BIT (1u << 12)
1115 #define ISL_SURF_USAGE_CONSTANT_BUFFER_BIT (1u << 13)
1116 #define ISL_SURF_USAGE_STAGING_BIT (1u << 14)
1117 /** @} */
1118
1119 /**
1120 * @defgroup Channel Mask
1121 *
1122 * These #define values are chosen to match the values of
1123 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
1124 *
1125 * @{
1126 */
1127 typedef uint8_t isl_channel_mask_t;
1128 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
1129 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
1130 #define ISL_CHANNEL_RED_BIT (1 << 2)
1131 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
1132 /** @} */
1133
1134 /**
1135 * @brief A channel select (also known as texture swizzle) value
1136 */
1137 enum PACKED isl_channel_select {
1138 ISL_CHANNEL_SELECT_ZERO = 0,
1139 ISL_CHANNEL_SELECT_ONE = 1,
1140 ISL_CHANNEL_SELECT_RED = 4,
1141 ISL_CHANNEL_SELECT_GREEN = 5,
1142 ISL_CHANNEL_SELECT_BLUE = 6,
1143 ISL_CHANNEL_SELECT_ALPHA = 7,
1144 };
1145
1146 /**
1147 * Identical to VkSampleCountFlagBits.
1148 */
1149 enum isl_sample_count {
1150 ISL_SAMPLE_COUNT_1_BIT = 1u,
1151 ISL_SAMPLE_COUNT_2_BIT = 2u,
1152 ISL_SAMPLE_COUNT_4_BIT = 4u,
1153 ISL_SAMPLE_COUNT_8_BIT = 8u,
1154 ISL_SAMPLE_COUNT_16_BIT = 16u,
1155 };
1156 typedef uint32_t isl_sample_count_mask_t;
1157
1158 /**
1159 * @brief Multisample Format
1160 */
1161 enum isl_msaa_layout {
1162 /**
1163 * @brief Suface is single-sampled.
1164 */
1165 ISL_MSAA_LAYOUT_NONE,
1166
1167 /**
1168 * @brief [SNB+] Interleaved Multisample Format
1169 *
1170 * In this format, multiple samples are interleaved into each cacheline.
1171 * In other words, the sample index is swizzled into the low 6 bits of the
1172 * surface's virtual address space.
1173 *
1174 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
1175 * and its pixel format is 32bpp. Then the first cacheline is arranged
1176 * thus:
1177 *
1178 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
1179 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
1180 *
1181 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
1182 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
1183 *
1184 * The hardware docs refer to this format with multiple terms. In
1185 * Sandybridge, this is the only multisample format; so no term is used.
1186 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
1187 * Multisample Surface). Later hardware docs additionally refer to this
1188 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
1189 * color surfaces).
1190 *
1191 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
1192 * Surface Behavior".
1193 *
1194 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
1195 * Multisampled Surfaces".
1196 */
1197 ISL_MSAA_LAYOUT_INTERLEAVED,
1198
1199 /**
1200 * @brief [IVB+] Array Multisample Format
1201 *
1202 * In this format, the surface's physical layout resembles that of a
1203 * 2D array surface.
1204 *
1205 * Suppose the multisample surface's logical extent is (w, h) and its
1206 * sample count is N. Then surface's physical extent is the same as
1207 * a singlesample 2D surface whose logical extent is (w, h) and array
1208 * length is N. Array slice `i` contains the pixel values for sample
1209 * index `i`.
1210 *
1211 * The Ivybridge docs refer to surfaces in this format as UMS
1212 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
1213 * Surface). The Broadwell docs additionally refer to this format as
1214 * MSFMT_MSS (MSS=Multisample Surface Storage).
1215 *
1216 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
1217 * Multisample Surfaces".
1218 *
1219 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
1220 * Multisample Surfaces".
1221 */
1222 ISL_MSAA_LAYOUT_ARRAY,
1223 };
1224
1225 typedef enum {
1226 ISL_MEMCPY = 0,
1227 ISL_MEMCPY_BGRA8,
1228 ISL_MEMCPY_STREAMING_LOAD,
1229 ISL_MEMCPY_INVALID,
1230 } isl_memcpy_type;
1231
1232 struct isl_device {
1233 const struct intel_device_info *info;
1234 bool use_separate_stencil;
1235 bool has_bit6_swizzling;
1236
1237 /**
1238 * Describes the layout of a RENDER_SURFACE_STATE structure for the
1239 * current gen.
1240 */
1241 struct {
1242 uint8_t size;
1243 uint8_t align;
1244 uint8_t addr_offset;
1245 uint8_t aux_addr_offset;
1246
1247 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
1248
1249 /* size of the state buffer used to store the clear color + extra
1250 * additional space used by the hardware */
1251 uint8_t clear_color_state_size;
1252 uint8_t clear_color_state_offset;
1253 /* size of the clear color itself - used to copy it to/from a BO */
1254 uint8_t clear_value_size;
1255 uint8_t clear_value_offset;
1256 } ss;
1257
1258 uint64_t max_buffer_size;
1259
1260 /**
1261 * Describes the layout of the depth/stencil/hiz commands as emitted by
1262 * isl_emit_depth_stencil_hiz.
1263 */
1264 struct {
1265 uint8_t size;
1266 uint8_t depth_offset;
1267 uint8_t stencil_offset;
1268 uint8_t hiz_offset;
1269 } ds;
1270
1271 struct {
1272 uint32_t internal;
1273 uint32_t external;
1274 uint32_t l1_hdc_l3_llc;
1275 } mocs;
1276 };
1277
1278 struct isl_extent2d {
1279 union { uint32_t w, width; };
1280 union { uint32_t h, height; };
1281 };
1282
1283 struct isl_extent3d {
1284 union { uint32_t w, width; };
1285 union { uint32_t h, height; };
1286 union { uint32_t d, depth; };
1287 };
1288
1289 struct isl_extent4d {
1290 union { uint32_t w, width; };
1291 union { uint32_t h, height; };
1292 union { uint32_t d, depth; };
1293 union { uint32_t a, array_len; };
1294 };
1295
1296 /**
1297 * Describes a single channel of an isl_format
1298 */
1299 struct isl_channel_layout {
1300 enum isl_base_type type; /**< Channel data encoding */
1301 uint8_t start_bit; /**< Bit at which this channel starts */
1302 uint8_t bits; /**< Size in bits */
1303 };
1304
1305 /**
1306 * Describes the layout of an isl_format
1307 *
1308 * Each format has 3D block extent (width, height, depth). The block extent of
1309 * compressed formats is that of the format's compression block. For example,
1310 * the block extent of `ISL_FORMAT_ETC2_RGB8` is `(w=4, h=4, d=1)`. The block
1311 * extent of uncompressed pixel formats, such as `ISL_FORMAT_R8G8B8A8_UNORM`,
1312 * is `(w=1, h=1, d=1)`.
1313 */
1314 struct isl_format_layout {
1315 enum isl_format format; /**< Format */
1316
1317 uint16_t bpb; /**< Bits per block */
1318 uint8_t bw; /**< Block width, in pixels */
1319 uint8_t bh; /**< Block height, in pixels */
1320 uint8_t bd; /**< Block depth, in pixels */
1321
1322 union {
1323 struct {
1324 struct isl_channel_layout r; /**< Red channel */
1325 struct isl_channel_layout g; /**< Green channel */
1326 struct isl_channel_layout b; /**< Blue channel */
1327 struct isl_channel_layout a; /**< Alpha channel */
1328 struct isl_channel_layout l; /**< Luminance channel */
1329 struct isl_channel_layout i; /**< Intensity channel */
1330 struct isl_channel_layout p; /**< Palette channel */
1331 } channels;
1332 struct isl_channel_layout channels_array[7];
1333 };
1334
1335 /** Set if all channels have the same isl_base_type. Otherwise, ISL_VOID. */
1336 enum isl_base_type uniform_channel_type;
1337
1338 enum isl_colorspace colorspace;
1339 enum isl_txc txc;
1340 };
1341
1342 struct isl_tile_info {
1343 /** Tiling represented by this isl_tile_info */
1344 enum isl_tiling tiling;
1345
1346 /**
1347 * The size (in bits per block) of a single surface element
1348 *
1349 * For surfaces with power-of-two formats, this is the same as
1350 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1351 * The logical_extent_el field is in terms of elements of this size.
1352 *
1353 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1354 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1355 * of the tiling formats can actually hold an integer number of 96-bit
1356 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1357 * 32-bit element size. It is the responsibility of the caller to
1358 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1359 * the width of a surface in tiles, you would do:
1360 *
1361 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1362 * tile_info.logical_extent_el.width);
1363 */
1364 uint32_t format_bpb;
1365
1366 /**
1367 * The logical size of the tile in units of format_bpb size elements
1368 *
1369 * This field determines how a given surface is cut up into tiles. It is
1370 * used to compute the size of a surface in tiles and can be used to
1371 * determine the location of the tile containing any given surface element.
1372 * The exact value of this field depends heavily on the bits-per-block of
1373 * the format being used.
1374 */
1375 struct isl_extent4d logical_extent_el;
1376
1377 /**
1378 * The physical size of the tile in bytes and rows of bytes
1379 *
1380 * This field determines how the tiles of a surface are physically layed
1381 * out in memory. The logical and physical tile extent are frequently the
1382 * same but this is not always the case. For instance, a W-tile (which is
1383 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1384 * its physical size is 128B x 32rows, the same as a Y-tile.
1385 *
1386 * @see isl_surf::row_pitch_B
1387 */
1388 struct isl_extent2d phys_extent_B;
1389 };
1390
1391 /**
1392 * Metadata about a DRM format modifier.
1393 */
1394 struct isl_drm_modifier_info {
1395 uint64_t modifier;
1396
1397 /** Text name of the modifier */
1398 const char *name;
1399
1400 /** ISL tiling implied by this modifier */
1401 enum isl_tiling tiling;
1402
1403 /** ISL aux usage implied by this modifier */
1404 enum isl_aux_usage aux_usage;
1405
1406 /** Whether or not this modifier supports clear color */
1407 bool supports_clear_color;
1408 };
1409
1410 /**
1411 * @brief Input to surface initialization
1412 *
1413 * @invariant width >= 1
1414 * @invariant height >= 1
1415 * @invariant depth >= 1
1416 * @invariant levels >= 1
1417 * @invariant samples >= 1
1418 * @invariant array_len >= 1
1419 *
1420 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1421 * @invariant if 2D then depth == 1
1422 * @invariant if 3D then array_len == 1 and samples == 1
1423 */
1424 struct isl_surf_init_info {
1425 enum isl_surf_dim dim;
1426 enum isl_format format;
1427
1428 uint32_t width;
1429 uint32_t height;
1430 uint32_t depth;
1431 uint32_t levels;
1432 uint32_t array_len;
1433 uint32_t samples;
1434
1435 /** Lower bound for isl_surf::alignment, in bytes. */
1436 uint32_t min_alignment_B;
1437
1438 /**
1439 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1440 * will fail if this is misaligned or out of bounds.
1441 */
1442 uint32_t row_pitch_B;
1443
1444 isl_surf_usage_flags_t usage;
1445
1446 /** Flags that alter how ISL selects isl_surf::tiling. */
1447 isl_tiling_flags_t tiling_flags;
1448 };
1449
1450 struct isl_surf {
1451 /** Dimensionality of the surface */
1452 enum isl_surf_dim dim;
1453
1454 /**
1455 * Spatial layout of the surface in memory
1456 *
1457 * This is dependent on isl_surf::dim and hardware generation.
1458 */
1459 enum isl_dim_layout dim_layout;
1460
1461 /** Spatial layout of the samples if isl_surf::samples > 1 */
1462 enum isl_msaa_layout msaa_layout;
1463
1464 /** Memory tiling used by the surface */
1465 enum isl_tiling tiling;
1466
1467 /**
1468 * Base image format of the surface
1469 *
1470 * This need not be the same as the format specified in isl_view::format
1471 * when a surface state is constructed. It must, however, have the same
1472 * number of bits per pixel or else memory calculations will go wrong.
1473 */
1474 enum isl_format format;
1475
1476 /**
1477 * Alignment of the upper-left sample of each subimage, in units of surface
1478 * elements.
1479 */
1480 struct isl_extent3d image_alignment_el;
1481
1482 /**
1483 * Logical extent of the surface's base level, in units of pixels. This is
1484 * identical to the extent defined in isl_surf_init_info.
1485 */
1486 struct isl_extent4d logical_level0_px;
1487
1488 /**
1489 * Physical extent of the surface's base level, in units of physical
1490 * surface samples.
1491 *
1492 * Consider isl_dim_layout as an operator that transforms a logical surface
1493 * layout to a physical surface layout. Then
1494 *
1495 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1496 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1497 */
1498 struct isl_extent4d phys_level0_sa;
1499
1500 /** Number of miplevels in the surface */
1501 uint32_t levels;
1502
1503 /**
1504 * Number of samples in the surface
1505 *
1506 * @invariant samples >= 1
1507 */
1508 uint32_t samples;
1509
1510 /** Total size of the surface, in bytes. */
1511 uint64_t size_B;
1512
1513 /** Required alignment for the surface's base address. */
1514 uint32_t alignment_B;
1515
1516 /**
1517 * The interpretation of this field depends on the value of
1518 * isl_tile_info::physical_extent_B. In particular, the width of the
1519 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1520 * and the distance in bytes between vertically adjacent tiles in the image
1521 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1522 *
1523 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1524 * this cleanly reduces to being the distance, in bytes, between vertically
1525 * adjacent surface elements.
1526 *
1527 * @see isl_tile_info::phys_extent_B;
1528 */
1529 uint32_t row_pitch_B;
1530
1531 /**
1532 * Pitch between physical array slices, in rows of surface elements.
1533 */
1534 uint32_t array_pitch_el_rows;
1535
1536 enum isl_array_pitch_span array_pitch_span;
1537
1538 /** Copy of isl_surf_init_info::usage. */
1539 isl_surf_usage_flags_t usage;
1540 };
1541
1542 struct isl_swizzle {
1543 enum isl_channel_select r:4;
1544 enum isl_channel_select g:4;
1545 enum isl_channel_select b:4;
1546 enum isl_channel_select a:4;
1547 };
1548
1549 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1550 .r = ISL_CHANNEL_SELECT_##R, \
1551 .g = ISL_CHANNEL_SELECT_##G, \
1552 .b = ISL_CHANNEL_SELECT_##B, \
1553 .a = ISL_CHANNEL_SELECT_##A, \
1554 })
1555
1556 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1557
1558 struct isl_view {
1559 /**
1560 * Indicates the usage of the particular view
1561 *
1562 * Normally, this is one bit. However, for a cube map texture, it
1563 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1564 */
1565 isl_surf_usage_flags_t usage;
1566
1567 /**
1568 * The format to use in the view
1569 *
1570 * This may differ from the format of the actual isl_surf but must have
1571 * the same block size.
1572 */
1573 enum isl_format format;
1574
1575 uint32_t base_level;
1576 uint32_t levels;
1577
1578 /**
1579 * Base array layer
1580 *
1581 * For cube maps, both base_array_layer and array_len should be
1582 * specified in terms of 2-D layers and must be a multiple of 6.
1583 *
1584 * 3-D textures are effectively treated as 2-D arrays when used as a
1585 * storage image or render target. If `usage` contains
1586 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1587 * base_array_layer and array_len are applied. If the surface is only used
1588 * for texturing, they are ignored.
1589 */
1590 uint32_t base_array_layer;
1591
1592 /**
1593 * Array Length
1594 *
1595 * Indicates the number of array elements starting at Base Array Layer.
1596 */
1597 uint32_t array_len;
1598
1599 struct isl_swizzle swizzle;
1600 };
1601
1602 union isl_color_value {
1603 float f32[4];
1604 uint32_t u32[4];
1605 int32_t i32[4];
1606 };
1607
1608 struct isl_surf_fill_state_info {
1609 const struct isl_surf *surf;
1610 const struct isl_view *view;
1611
1612 /**
1613 * The address of the surface in GPU memory.
1614 */
1615 uint64_t address;
1616
1617 /**
1618 * The Memory Object Control state for the filled surface state.
1619 *
1620 * The exact format of this value depends on hardware generation.
1621 */
1622 uint32_t mocs;
1623
1624 /**
1625 * The auxilary surface or NULL if no auxilary surface is to be used.
1626 */
1627 const struct isl_surf *aux_surf;
1628 enum isl_aux_usage aux_usage;
1629 uint64_t aux_address;
1630
1631 /**
1632 * The clear color for this surface
1633 *
1634 * Valid values depend on hardware generation.
1635 */
1636 union isl_color_value clear_color;
1637
1638 /**
1639 * Send only the clear value address
1640 *
1641 * If set, we only pass the clear address to the GPU and it will fetch it
1642 * from wherever it is.
1643 */
1644 bool use_clear_address;
1645 uint64_t clear_address;
1646
1647 /**
1648 * Surface write disables for gfx4-5
1649 */
1650 isl_channel_mask_t write_disables;
1651
1652 /**
1653 * blend enable for gfx4-5
1654 */
1655 bool blend_enable;
1656
1657 /* Intra-tile offset */
1658 uint16_t x_offset_sa, y_offset_sa;
1659 };
1660
1661 struct isl_buffer_fill_state_info {
1662 /**
1663 * The address of the surface in GPU memory.
1664 */
1665 uint64_t address;
1666
1667 /**
1668 * The size of the buffer
1669 */
1670 uint64_t size_B;
1671
1672 /**
1673 * The Memory Object Control state for the filled surface state.
1674 *
1675 * The exact format of this value depends on hardware generation.
1676 */
1677 uint32_t mocs;
1678
1679 /**
1680 * The format to use in the surface state
1681 *
1682 * This may differ from the format of the actual isl_surf but have the
1683 * same block size.
1684 */
1685 enum isl_format format;
1686
1687 /**
1688 * The swizzle to use in the surface state
1689 */
1690 struct isl_swizzle swizzle;
1691
1692 uint32_t stride_B;
1693
1694 bool is_scratch;
1695 };
1696
1697 struct isl_depth_stencil_hiz_emit_info {
1698 /**
1699 * The depth surface
1700 */
1701 const struct isl_surf *depth_surf;
1702
1703 /**
1704 * The stencil surface
1705 *
1706 * If separate stencil is not available, this must point to the same
1707 * isl_surf as depth_surf.
1708 */
1709 const struct isl_surf *stencil_surf;
1710
1711 /**
1712 * The view into the depth and stencil surfaces.
1713 *
1714 * This view applies to both surfaces simultaneously.
1715 */
1716 const struct isl_view *view;
1717
1718 /**
1719 * The address of the depth surface in GPU memory
1720 */
1721 uint64_t depth_address;
1722
1723 /**
1724 * The address of the stencil surface in GPU memory
1725 *
1726 * If separate stencil is not available, this must have the same value as
1727 * depth_address.
1728 */
1729 uint64_t stencil_address;
1730
1731 /**
1732 * The Memory Object Control state for depth and stencil buffers
1733 *
1734 * Both depth and stencil will get the same MOCS value. The exact format
1735 * of this value depends on hardware generation.
1736 */
1737 uint32_t mocs;
1738
1739 /**
1740 * The HiZ surface or NULL if HiZ is disabled.
1741 */
1742 const struct isl_surf *hiz_surf;
1743 enum isl_aux_usage hiz_usage;
1744 uint64_t hiz_address;
1745
1746 /**
1747 * The depth clear value
1748 */
1749 float depth_clear_value;
1750
1751 /**
1752 * Track stencil aux usage for Gen >= 12
1753 */
1754 enum isl_aux_usage stencil_aux_usage;
1755 };
1756
1757 struct isl_null_fill_state_info {
1758 struct isl_extent3d size;
1759 uint32_t levels;
1760 uint32_t minimum_array_element;
1761 };
1762
1763 extern const struct isl_format_layout isl_format_layouts[];
1764 extern const char isl_format_names[];
1765 extern const uint16_t isl_format_name_offsets[];
1766
1767 void
1768 isl_device_init(struct isl_device *dev,
1769 const struct intel_device_info *info,
1770 bool has_bit6_swizzling);
1771
1772 isl_sample_count_mask_t ATTRIBUTE_CONST
1773 isl_device_get_sample_counts(struct isl_device *dev);
1774
1775 /**
1776 * \return The isl_format_layout for the given isl_format
1777 */
1778 static inline const struct isl_format_layout * ATTRIBUTE_CONST
isl_format_get_layout(enum isl_format fmt)1779 isl_format_get_layout(enum isl_format fmt)
1780 {
1781 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1782 assert(fmt < ISL_NUM_FORMATS);
1783 return &isl_format_layouts[fmt];
1784 }
1785
1786 bool isl_format_is_valid(enum isl_format);
1787
1788 static inline const char * ATTRIBUTE_CONST
isl_format_get_name(enum isl_format fmt)1789 isl_format_get_name(enum isl_format fmt)
1790 {
1791 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1792 assert(fmt < ISL_NUM_FORMATS);
1793 return isl_format_names + isl_format_name_offsets[fmt];
1794 }
1795
1796 enum isl_format isl_format_for_pipe_format(enum pipe_format pf);
1797
1798 bool isl_format_supports_rendering(const struct intel_device_info *devinfo,
1799 enum isl_format format);
1800 bool isl_format_supports_alpha_blending(const struct intel_device_info *devinfo,
1801 enum isl_format format);
1802 bool isl_format_supports_sampling(const struct intel_device_info *devinfo,
1803 enum isl_format format);
1804 bool isl_format_supports_filtering(const struct intel_device_info *devinfo,
1805 enum isl_format format);
1806 bool isl_format_supports_vertex_fetch(const struct intel_device_info *devinfo,
1807 enum isl_format format);
1808 bool isl_format_supports_typed_writes(const struct intel_device_info *devinfo,
1809 enum isl_format format);
1810 bool isl_format_supports_typed_reads(const struct intel_device_info *devinfo,
1811 enum isl_format format);
1812 bool isl_format_supports_ccs_d(const struct intel_device_info *devinfo,
1813 enum isl_format format);
1814 bool isl_format_supports_ccs_e(const struct intel_device_info *devinfo,
1815 enum isl_format format);
1816 bool isl_format_supports_multisampling(const struct intel_device_info *devinfo,
1817 enum isl_format format);
1818
1819 bool isl_formats_are_ccs_e_compatible(const struct intel_device_info *devinfo,
1820 enum isl_format format1,
1821 enum isl_format format2);
1822 uint8_t isl_format_get_aux_map_encoding(enum isl_format format);
1823 uint8_t isl_get_render_compression_format(enum isl_format format);
1824
1825 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1826 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1827 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1828 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1829 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1830 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1831
1832 static inline bool
isl_format_has_normalized_channel(enum isl_format fmt)1833 isl_format_has_normalized_channel(enum isl_format fmt)
1834 {
1835 return isl_format_has_unorm_channel(fmt) ||
1836 isl_format_has_snorm_channel(fmt);
1837 }
1838
1839 static inline bool
isl_format_has_float_channel(enum isl_format fmt)1840 isl_format_has_float_channel(enum isl_format fmt)
1841 {
1842 return isl_format_has_ufloat_channel(fmt) ||
1843 isl_format_has_sfloat_channel(fmt);
1844 }
1845
1846 static inline bool
isl_format_has_int_channel(enum isl_format fmt)1847 isl_format_has_int_channel(enum isl_format fmt)
1848 {
1849 return isl_format_has_uint_channel(fmt) ||
1850 isl_format_has_sint_channel(fmt);
1851 }
1852
1853 bool isl_format_has_color_component(enum isl_format fmt,
1854 int component) ATTRIBUTE_CONST;
1855
1856 unsigned isl_format_get_num_channels(enum isl_format fmt);
1857
1858 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1859
1860 static inline bool
isl_format_is_compressed(enum isl_format fmt)1861 isl_format_is_compressed(enum isl_format fmt)
1862 {
1863 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1864
1865 return fmtl->txc != ISL_TXC_NONE;
1866 }
1867
1868 static inline bool
isl_format_has_bc_compression(enum isl_format fmt)1869 isl_format_has_bc_compression(enum isl_format fmt)
1870 {
1871 switch (isl_format_get_layout(fmt)->txc) {
1872 case ISL_TXC_DXT1:
1873 case ISL_TXC_DXT3:
1874 case ISL_TXC_DXT5:
1875 return true;
1876 case ISL_TXC_NONE:
1877 case ISL_TXC_FXT1:
1878 case ISL_TXC_RGTC1:
1879 case ISL_TXC_RGTC2:
1880 case ISL_TXC_BPTC:
1881 case ISL_TXC_ETC1:
1882 case ISL_TXC_ETC2:
1883 case ISL_TXC_ASTC:
1884 return false;
1885
1886 case ISL_TXC_HIZ:
1887 case ISL_TXC_MCS:
1888 case ISL_TXC_CCS:
1889 unreachable("Should not be called on an aux surface");
1890 }
1891
1892 unreachable("bad texture compression mode");
1893 return false;
1894 }
1895
1896 static inline bool
isl_format_is_mcs(enum isl_format fmt)1897 isl_format_is_mcs(enum isl_format fmt)
1898 {
1899 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1900
1901 return fmtl->txc == ISL_TXC_MCS;
1902 }
1903
1904 static inline bool
isl_format_is_planar(enum isl_format fmt)1905 isl_format_is_planar(enum isl_format fmt)
1906 {
1907 return fmt == ISL_FORMAT_PLANAR_420_8 ||
1908 fmt == ISL_FORMAT_PLANAR_420_10 ||
1909 fmt == ISL_FORMAT_PLANAR_420_12 ||
1910 fmt == ISL_FORMAT_PLANAR_420_16;
1911 }
1912
1913 static inline bool
isl_format_is_yuv(enum isl_format fmt)1914 isl_format_is_yuv(enum isl_format fmt)
1915 {
1916 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1917
1918 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1919 }
1920
1921 static inline bool
isl_format_block_is_1x1x1(enum isl_format fmt)1922 isl_format_block_is_1x1x1(enum isl_format fmt)
1923 {
1924 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1925
1926 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1927 }
1928
1929 static inline bool
isl_format_is_srgb(enum isl_format fmt)1930 isl_format_is_srgb(enum isl_format fmt)
1931 {
1932 return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
1933 }
1934
1935 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
1936
1937 static inline bool
isl_format_is_rgb(enum isl_format fmt)1938 isl_format_is_rgb(enum isl_format fmt)
1939 {
1940 if (isl_format_is_yuv(fmt))
1941 return false;
1942
1943 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1944
1945 return fmtl->channels.r.bits > 0 &&
1946 fmtl->channels.g.bits > 0 &&
1947 fmtl->channels.b.bits > 0 &&
1948 fmtl->channels.a.bits == 0;
1949 }
1950
1951 static inline bool
isl_format_is_rgbx(enum isl_format fmt)1952 isl_format_is_rgbx(enum isl_format fmt)
1953 {
1954 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1955
1956 return fmtl->channels.r.bits > 0 &&
1957 fmtl->channels.g.bits > 0 &&
1958 fmtl->channels.b.bits > 0 &&
1959 fmtl->channels.a.bits > 0 &&
1960 fmtl->channels.a.type == ISL_VOID;
1961 }
1962
1963 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1964 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1965 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1966
1967 union isl_color_value
1968 isl_color_value_swizzle_inv(union isl_color_value src,
1969 struct isl_swizzle swizzle);
1970
1971 void isl_color_value_pack(const union isl_color_value *value,
1972 enum isl_format format,
1973 uint32_t *data_out);
1974 void isl_color_value_unpack(union isl_color_value *value,
1975 enum isl_format format,
1976 const uint32_t *data_in);
1977
1978 bool isl_is_storage_image_format(enum isl_format fmt);
1979
1980 enum isl_format
1981 isl_lower_storage_image_format(const struct intel_device_info *devinfo,
1982 enum isl_format fmt);
1983
1984 /* Returns true if this hardware supports typed load/store on a format with
1985 * the same size as the given format.
1986 */
1987 bool
1988 isl_has_matching_typed_storage_image_format(const struct intel_device_info *devinfo,
1989 enum isl_format fmt);
1990
1991 void
1992 isl_tiling_get_info(enum isl_tiling tiling,
1993 enum isl_surf_dim dim,
1994 enum isl_msaa_layout msaa_layout,
1995 uint32_t format_bpb,
1996 uint32_t samples,
1997 struct isl_tile_info *tile_info);
1998
1999 static inline enum isl_tiling
isl_tiling_flag_to_enum(isl_tiling_flags_t flag)2000 isl_tiling_flag_to_enum(isl_tiling_flags_t flag)
2001 {
2002 assert(__builtin_popcount(flag) == 1);
2003 return (enum isl_tiling) (__builtin_ffs(flag) - 1);
2004 }
2005
2006 static inline bool
isl_tiling_is_any_y(enum isl_tiling tiling)2007 isl_tiling_is_any_y(enum isl_tiling tiling)
2008 {
2009 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
2010 }
2011
2012 static inline bool
isl_tiling_is_std_y(enum isl_tiling tiling)2013 isl_tiling_is_std_y(enum isl_tiling tiling)
2014 {
2015 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
2016 }
2017
2018 uint32_t
2019 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
2020
2021 enum isl_tiling
2022 isl_tiling_from_i915_tiling(uint32_t tiling);
2023
2024 /**
2025 * Return an isl_aux_op needed to enable an access to occur in an
2026 * isl_aux_state suitable for the isl_aux_usage.
2027 *
2028 * @note
2029 * If the access will invalidate the main surface, this function should not be
2030 * called and the isl_aux_op of NONE should be used instead. Otherwise, an
2031 * extra (but still lossless) ambiguate may occur.
2032 *
2033 * @invariant initial_state is possible with an isl_aux_usage compatible with
2034 * the given usage. Two usages are compatible if it's possible to
2035 * switch between them (e.g. CCS_E <-> CCS_D).
2036 * @invariant fast_clear is false if the aux doesn't support fast clears.
2037 */
2038 enum isl_aux_op
2039 isl_aux_prepare_access(enum isl_aux_state initial_state,
2040 enum isl_aux_usage usage,
2041 bool fast_clear_supported);
2042
2043 /**
2044 * Return the isl_aux_state entered after performing an isl_aux_op.
2045 *
2046 * @invariant initial_state is possible with the given usage.
2047 * @invariant op is possible with the given usage.
2048 * @invariant op must not cause HW to read from an invalid aux.
2049 */
2050 enum isl_aux_state
2051 isl_aux_state_transition_aux_op(enum isl_aux_state initial_state,
2052 enum isl_aux_usage usage,
2053 enum isl_aux_op op);
2054
2055 /**
2056 * Return the isl_aux_state entered after performing a write.
2057 *
2058 * @note
2059 * full_surface should be true if the write covers the entire slice. Setting
2060 * it to false in this case will still result in a correct (but imprecise) aux
2061 * state.
2062 *
2063 * @invariant if usage is not ISL_AUX_USAGE_NONE, then initial_state is
2064 * possible with the given usage.
2065 * @invariant usage can be ISL_AUX_USAGE_NONE iff:
2066 * * the main surface is valid, or
2067 * * the main surface is being invalidated/replaced.
2068 */
2069 enum isl_aux_state
2070 isl_aux_state_transition_write(enum isl_aux_state initial_state,
2071 enum isl_aux_usage usage,
2072 bool full_surface);
2073
2074 bool
2075 isl_aux_usage_has_fast_clears(enum isl_aux_usage usage);
2076
2077 bool
2078 isl_aux_usage_has_compression(enum isl_aux_usage usage);
2079
2080 static inline bool
isl_aux_usage_has_hiz(enum isl_aux_usage usage)2081 isl_aux_usage_has_hiz(enum isl_aux_usage usage)
2082 {
2083 return usage == ISL_AUX_USAGE_HIZ ||
2084 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
2085 usage == ISL_AUX_USAGE_HIZ_CCS;
2086 }
2087
2088 static inline bool
isl_aux_usage_has_mcs(enum isl_aux_usage usage)2089 isl_aux_usage_has_mcs(enum isl_aux_usage usage)
2090 {
2091 return usage == ISL_AUX_USAGE_MCS ||
2092 usage == ISL_AUX_USAGE_MCS_CCS;
2093 }
2094
2095 static inline bool
isl_aux_usage_has_ccs(enum isl_aux_usage usage)2096 isl_aux_usage_has_ccs(enum isl_aux_usage usage)
2097 {
2098 return usage == ISL_AUX_USAGE_CCS_D ||
2099 usage == ISL_AUX_USAGE_CCS_E ||
2100 usage == ISL_AUX_USAGE_GFX12_CCS_E ||
2101 usage == ISL_AUX_USAGE_MC ||
2102 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
2103 usage == ISL_AUX_USAGE_HIZ_CCS ||
2104 usage == ISL_AUX_USAGE_MCS_CCS ||
2105 usage == ISL_AUX_USAGE_STC_CCS;
2106 }
2107
2108 static inline bool
isl_aux_state_has_valid_primary(enum isl_aux_state state)2109 isl_aux_state_has_valid_primary(enum isl_aux_state state)
2110 {
2111 return state == ISL_AUX_STATE_RESOLVED ||
2112 state == ISL_AUX_STATE_PASS_THROUGH ||
2113 state == ISL_AUX_STATE_AUX_INVALID;
2114 }
2115
2116 static inline bool
isl_aux_state_has_valid_aux(enum isl_aux_state state)2117 isl_aux_state_has_valid_aux(enum isl_aux_state state)
2118 {
2119 return state != ISL_AUX_STATE_AUX_INVALID;
2120 }
2121
2122 extern const struct isl_drm_modifier_info isl_drm_modifier_info_list[];
2123
2124 #define isl_drm_modifier_info_for_each(__info) \
2125 for (const struct isl_drm_modifier_info *__info = isl_drm_modifier_info_list; \
2126 __info->modifier != DRM_FORMAT_MOD_INVALID; \
2127 ++__info)
2128
2129 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
2130 isl_drm_modifier_get_info(uint64_t modifier);
2131
2132 static inline bool
isl_drm_modifier_has_aux(uint64_t modifier)2133 isl_drm_modifier_has_aux(uint64_t modifier)
2134 {
2135 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE;
2136 }
2137
2138 /** Returns the default isl_aux_state for the given modifier.
2139 *
2140 * If we have a modifier which supports compression, then the auxiliary data
2141 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
2142 * can be in any of the following:
2143 *
2144 * - ISL_AUX_STATE_CLEAR
2145 * - ISL_AUX_STATE_PARTIAL_CLEAR
2146 * - ISL_AUX_STATE_COMPRESSED_CLEAR
2147 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
2148 * - ISL_AUX_STATE_RESOLVED
2149 * - ISL_AUX_STATE_PASS_THROUGH
2150 *
2151 * If the modifier does not support fast-clears, then we are guaranteed
2152 * that the surface is at least partially resolved and the first three not
2153 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
2154 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
2155 * because they are the least common denominator of the set of possible aux
2156 * states and will yield a valid interpretation of the aux data.
2157 *
2158 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
2159 */
2160 static inline enum isl_aux_state
isl_drm_modifier_get_default_aux_state(uint64_t modifier)2161 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
2162 {
2163 const struct isl_drm_modifier_info *mod_info =
2164 isl_drm_modifier_get_info(modifier);
2165
2166 if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
2167 return ISL_AUX_STATE_AUX_INVALID;
2168
2169 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
2170 mod_info->aux_usage == ISL_AUX_USAGE_GFX12_CCS_E ||
2171 mod_info->aux_usage == ISL_AUX_USAGE_MC);
2172 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
2173 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
2174 }
2175
2176 /**
2177 * Return the modifier's score, which indicates the driver's preference for the
2178 * modifier relative to others. A higher score is better. Zero means
2179 * unsupported.
2180 *
2181 * Intended to assist selection of a modifier from an externally provided list,
2182 * such as VkImageDrmFormatModifierListCreateInfoEXT.
2183 */
2184 uint32_t
2185 isl_drm_modifier_get_score(const struct intel_device_info *devinfo,
2186 uint64_t modifier);
2187
2188 struct isl_extent2d ATTRIBUTE_CONST
2189 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
2190
2191 static inline bool
isl_surf_usage_is_display(isl_surf_usage_flags_t usage)2192 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
2193 {
2194 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
2195 }
2196
2197 static inline bool
isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)2198 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
2199 {
2200 return usage & ISL_SURF_USAGE_DEPTH_BIT;
2201 }
2202
2203 static inline bool
isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)2204 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
2205 {
2206 return usage & ISL_SURF_USAGE_STENCIL_BIT;
2207 }
2208
2209 static inline bool
isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)2210 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
2211 {
2212 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2213 (usage & ISL_SURF_USAGE_STENCIL_BIT);
2214 }
2215
2216 static inline bool
isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)2217 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
2218 {
2219 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
2220 }
2221
2222 static inline bool
isl_surf_info_is_z16(const struct isl_surf_init_info * info)2223 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
2224 {
2225 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2226 (info->format == ISL_FORMAT_R16_UNORM);
2227 }
2228
2229 static inline bool
isl_surf_info_is_z32_float(const struct isl_surf_init_info * info)2230 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
2231 {
2232 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2233 (info->format == ISL_FORMAT_R32_FLOAT);
2234 }
2235
2236 static inline struct isl_extent2d
isl_extent2d(uint32_t width,uint32_t height)2237 isl_extent2d(uint32_t width, uint32_t height)
2238 {
2239 struct isl_extent2d e = { { 0 } };
2240
2241 e.width = width;
2242 e.height = height;
2243
2244 return e;
2245 }
2246
2247 static inline struct isl_extent3d
isl_extent3d(uint32_t width,uint32_t height,uint32_t depth)2248 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
2249 {
2250 struct isl_extent3d e = { { 0 } };
2251
2252 e.width = width;
2253 e.height = height;
2254 e.depth = depth;
2255
2256 return e;
2257 }
2258
2259 static inline struct isl_extent4d
isl_extent4d(uint32_t width,uint32_t height,uint32_t depth,uint32_t array_len)2260 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
2261 uint32_t array_len)
2262 {
2263 struct isl_extent4d e = { { 0 } };
2264
2265 e.width = width;
2266 e.height = height;
2267 e.depth = depth;
2268 e.array_len = array_len;
2269
2270 return e;
2271 }
2272
2273 bool isl_color_value_is_zero(union isl_color_value value,
2274 enum isl_format format);
2275
2276 bool isl_color_value_is_zero_one(union isl_color_value value,
2277 enum isl_format format);
2278
2279 static inline bool
isl_swizzle_is_identity(struct isl_swizzle swizzle)2280 isl_swizzle_is_identity(struct isl_swizzle swizzle)
2281 {
2282 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
2283 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
2284 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
2285 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
2286 }
2287
2288 bool
2289 isl_swizzle_supports_rendering(const struct intel_device_info *devinfo,
2290 struct isl_swizzle swizzle);
2291
2292 struct isl_swizzle
2293 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
2294 struct isl_swizzle
2295 isl_swizzle_invert(struct isl_swizzle swizzle);
2296
2297 uint32_t isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
2298 bool external);
2299
2300 #define isl_surf_init(dev, surf, ...) \
2301 isl_surf_init_s((dev), (surf), \
2302 &(struct isl_surf_init_info) { __VA_ARGS__ });
2303
2304 bool
2305 isl_surf_init_s(const struct isl_device *dev,
2306 struct isl_surf *surf,
2307 const struct isl_surf_init_info *restrict info);
2308
2309 void
2310 isl_surf_get_tile_info(const struct isl_surf *surf,
2311 struct isl_tile_info *tile_info);
2312
2313 /**
2314 * @param[in] surf The main surface
2315 * @param[in] hiz_or_mcs_surf HiZ or MCS surface associated with the main
2316 * surface
2317 * @returns true if the given surface supports CCS.
2318 */
2319 bool
2320 isl_surf_supports_ccs(const struct isl_device *dev,
2321 const struct isl_surf *surf,
2322 const struct isl_surf *hiz_or_mcs_surf);
2323
2324 /** Constructs a HiZ surface for the given main surface.
2325 *
2326 * @param[in] surf The main surface
2327 * @param[out] hiz_surf The HiZ surface to populate on success
2328 * @returns false if the main surface cannot support HiZ.
2329 */
2330 bool
2331 isl_surf_get_hiz_surf(const struct isl_device *dev,
2332 const struct isl_surf *surf,
2333 struct isl_surf *hiz_surf);
2334
2335 /** Constructs a MCS for the given main surface.
2336 *
2337 * @param[in] surf The main surface
2338 * @param[out] mcs_surf The MCS to populate on success
2339 * @returns false if the main surface cannot support MCS.
2340 */
2341 bool
2342 isl_surf_get_mcs_surf(const struct isl_device *dev,
2343 const struct isl_surf *surf,
2344 struct isl_surf *mcs_surf);
2345
2346 /** Constructs a CCS for the given main surface.
2347 *
2348 * @note
2349 * Starting with Tigerlake, the CCS is no longer really a surface. It's not
2350 * laid out as an independent surface and isn't referenced by
2351 * RENDER_SURFACE_STATE::"Auxiliary Surface Base Address" like other auxiliary
2352 * compression surfaces. It's a blob of memory that's a 1:256 scale-down from
2353 * the main surfaced that's attached side-band via a second set of page
2354 * tables.
2355 *
2356 * @par
2357 * In spite of this, it's sometimes useful to think of it as being a linear
2358 * buffer-like surface, at least for the purposes of allocation. When invoked
2359 * on Tigerlake or later, this function still works and produces such a linear
2360 * surface.
2361 *
2362 * @param[in] surf The main surface
2363 * @param[in] hiz_or_mcs_surf HiZ or MCS surface associated with the main
2364 * surface
2365 * @param[out] ccs_surf The CCS to populate on success
2366 * @param row_pitch_B: The row pitch for the CCS in bytes or 0 if
2367 * ISL should calculate the row pitch.
2368 * @returns false if the main surface cannot support CCS.
2369 */
2370 bool
2371 isl_surf_get_ccs_surf(const struct isl_device *dev,
2372 const struct isl_surf *surf,
2373 const struct isl_surf *hiz_or_mcs_surf,
2374 struct isl_surf *ccs_surf,
2375 uint32_t row_pitch_B);
2376
2377 #define isl_surf_fill_state(dev, state, ...) \
2378 isl_surf_fill_state_s((dev), (state), \
2379 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
2380
2381 void
2382 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
2383 const struct isl_surf_fill_state_info *restrict info);
2384
2385 #define isl_buffer_fill_state(dev, state, ...) \
2386 isl_buffer_fill_state_s((dev), (state), \
2387 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
2388
2389 void
2390 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
2391 const struct isl_buffer_fill_state_info *restrict info);
2392
2393 void
2394 isl_null_fill_state_s(const struct isl_device *dev, void *state,
2395 const struct isl_null_fill_state_info *restrict info);
2396
2397 #define isl_null_fill_state(dev, state, ...) \
2398 isl_null_fill_state_s((dev), (state), \
2399 &(struct isl_null_fill_state_info) { __VA_ARGS__ });
2400
2401 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
2402 isl_emit_depth_stencil_hiz_s((dev), (batch), \
2403 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
2404
2405 void
2406 isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
2407 const struct isl_depth_stencil_hiz_emit_info *restrict info);
2408
2409 void
2410 isl_surf_fill_image_param(const struct isl_device *dev,
2411 struct brw_image_param *param,
2412 const struct isl_surf *surf,
2413 const struct isl_view *view);
2414
2415 void
2416 isl_buffer_fill_image_param(const struct isl_device *dev,
2417 struct brw_image_param *param,
2418 enum isl_format format,
2419 uint64_t size);
2420
2421 /**
2422 * Alignment of the upper-left sample of each subimage, in units of surface
2423 * elements.
2424 */
2425 static inline struct isl_extent3d
isl_surf_get_image_alignment_el(const struct isl_surf * surf)2426 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
2427 {
2428 return surf->image_alignment_el;
2429 }
2430
2431 /**
2432 * Alignment of the upper-left sample of each subimage, in units of surface
2433 * samples.
2434 */
2435 static inline struct isl_extent3d
isl_surf_get_image_alignment_sa(const struct isl_surf * surf)2436 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
2437 {
2438 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2439
2440 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
2441 fmtl->bh * surf->image_alignment_el.h,
2442 fmtl->bd * surf->image_alignment_el.d);
2443 }
2444
2445 /**
2446 * Logical extent of level 0 in units of surface elements.
2447 */
2448 static inline struct isl_extent4d
isl_surf_get_logical_level0_el(const struct isl_surf * surf)2449 isl_surf_get_logical_level0_el(const struct isl_surf *surf)
2450 {
2451 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2452
2453 return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw),
2454 DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh),
2455 DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd),
2456 surf->logical_level0_px.a);
2457 }
2458
2459 /**
2460 * Physical extent of level 0 in units of surface elements.
2461 */
2462 static inline struct isl_extent4d
isl_surf_get_phys_level0_el(const struct isl_surf * surf)2463 isl_surf_get_phys_level0_el(const struct isl_surf *surf)
2464 {
2465 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2466
2467 return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
2468 DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
2469 DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
2470 surf->phys_level0_sa.a);
2471 }
2472
2473 /**
2474 * Pitch between vertically adjacent surface elements, in bytes.
2475 */
2476 static inline uint32_t
isl_surf_get_row_pitch_B(const struct isl_surf * surf)2477 isl_surf_get_row_pitch_B(const struct isl_surf *surf)
2478 {
2479 return surf->row_pitch_B;
2480 }
2481
2482 /**
2483 * Pitch between vertically adjacent surface elements, in units of surface elements.
2484 */
2485 static inline uint32_t
isl_surf_get_row_pitch_el(const struct isl_surf * surf)2486 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
2487 {
2488 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2489
2490 assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
2491 return surf->row_pitch_B / (fmtl->bpb / 8);
2492 }
2493
2494 /**
2495 * Pitch between physical array slices, in rows of surface elements.
2496 */
2497 static inline uint32_t
isl_surf_get_array_pitch_el_rows(const struct isl_surf * surf)2498 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
2499 {
2500 return surf->array_pitch_el_rows;
2501 }
2502
2503 /**
2504 * Pitch between physical array slices, in units of surface elements.
2505 */
2506 static inline uint32_t
isl_surf_get_array_pitch_el(const struct isl_surf * surf)2507 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
2508 {
2509 return isl_surf_get_array_pitch_el_rows(surf) *
2510 isl_surf_get_row_pitch_el(surf);
2511 }
2512
2513 /**
2514 * Pitch between physical array slices, in rows of surface samples.
2515 */
2516 static inline uint32_t
isl_surf_get_array_pitch_sa_rows(const struct isl_surf * surf)2517 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
2518 {
2519 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2520 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
2521 }
2522
2523 /**
2524 * Pitch between physical array slices, in bytes.
2525 */
2526 static inline uint32_t
isl_surf_get_array_pitch(const struct isl_surf * surf)2527 isl_surf_get_array_pitch(const struct isl_surf *surf)
2528 {
2529 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
2530 }
2531
2532 /**
2533 * Calculate the offset, in units of surface samples, to a subimage in the
2534 * surface.
2535 *
2536 * @invariant level < surface levels
2537 * @invariant logical_array_layer < logical array length of surface
2538 * @invariant logical_z_offset_px < logical depth of surface at level
2539 */
2540 void
2541 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
2542 uint32_t level,
2543 uint32_t logical_array_layer,
2544 uint32_t logical_z_offset_px,
2545 uint32_t *x_offset_sa,
2546 uint32_t *y_offset_sa,
2547 uint32_t *z_offset_sa,
2548 uint32_t *array_offset);
2549
2550 /**
2551 * Calculate the offset, in units of surface elements, to a subimage in the
2552 * surface.
2553 *
2554 * @invariant level < surface levels
2555 * @invariant logical_array_layer < logical array length of surface
2556 * @invariant logical_z_offset_px < logical depth of surface at level
2557 */
2558 void
2559 isl_surf_get_image_offset_el(const struct isl_surf *surf,
2560 uint32_t level,
2561 uint32_t logical_array_layer,
2562 uint32_t logical_z_offset_px,
2563 uint32_t *x_offset_el,
2564 uint32_t *y_offset_el,
2565 uint32_t *z_offset_el,
2566 uint32_t *array_offset);
2567
2568 /**
2569 * Calculate the offset, in bytes and intratile surface samples, to a
2570 * subimage in the surface.
2571 *
2572 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2573 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2574 * offsets to samples.
2575 *
2576 * @invariant level < surface levels
2577 * @invariant logical_array_layer < logical array length of surface
2578 * @invariant logical_z_offset_px < logical depth of surface at level
2579 */
2580 void
2581 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2582 uint32_t level,
2583 uint32_t logical_array_layer,
2584 uint32_t logical_z_offset_px,
2585 uint64_t *offset_B,
2586 uint32_t *x_offset_sa,
2587 uint32_t *y_offset_sa);
2588
2589 /**
2590 * Calculate the offset, in bytes and intratile surface elements, to a
2591 * subimage in the surface.
2592 *
2593 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2594 * result to isl_tiling_get_intratile_offset_el.
2595 *
2596 * @invariant level < surface levels
2597 * @invariant logical_array_layer < logical array length of surface
2598 * @invariant logical_z_offset_px < logical depth of surface at level
2599 */
2600 void
2601 isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
2602 uint32_t level,
2603 uint32_t logical_array_layer,
2604 uint32_t logical_z_offset_px,
2605 uint64_t *offset_B,
2606 uint32_t *x_offset_el,
2607 uint32_t *y_offset_el);
2608
2609 /**
2610 * Calculate the range in bytes occupied by a subimage, to the nearest tile.
2611 *
2612 * The range returned will be the smallest memory range in which the give
2613 * subimage fits, rounded to even tiles. Intel images do not usually have a
2614 * direct subimage -> range mapping so the range returned may contain data
2615 * from other sub-images. The returned range is a half-open interval where
2616 * all of the addresses within the subimage are < end_tile_B.
2617 *
2618 * @invariant level < surface levels
2619 * @invariant logical_array_layer < logical array length of surface
2620 * @invariant logical_z_offset_px < logical depth of surface at level
2621 */
2622 void
2623 isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
2624 uint32_t level,
2625 uint32_t logical_array_layer,
2626 uint32_t logical_z_offset_px,
2627 uint64_t *start_tile_B,
2628 uint64_t *end_tile_B);
2629
2630 /**
2631 * Create an isl_surf that represents a particular subimage in the surface.
2632 *
2633 * The newly created surface will have a single miplevel and array slice. The
2634 * surface lives at the returned byte and intratile offsets, in samples.
2635 *
2636 * It is safe to call this function with surf == image_surf.
2637 *
2638 * @invariant level < surface levels
2639 * @invariant logical_array_layer < logical array length of surface
2640 * @invariant logical_z_offset_px < logical depth of surface at level
2641 */
2642 void
2643 isl_surf_get_image_surf(const struct isl_device *dev,
2644 const struct isl_surf *surf,
2645 uint32_t level,
2646 uint32_t logical_array_layer,
2647 uint32_t logical_z_offset_px,
2648 struct isl_surf *image_surf,
2649 uint64_t *offset_B,
2650 uint32_t *x_offset_sa,
2651 uint32_t *y_offset_sa);
2652
2653 /**
2654 * Create an isl_surf that is an uncompressed view of a compressed isl_surf
2655 *
2656 * The incoming surface must have a compressed format. The incoming view must
2657 * be a valid view for the given surface with the exception that it's format
2658 * is an umcompressed format with the same bpb as the surface format. The
2659 * incoming view must have isl_view::levels == 1.
2660 *
2661 * When the function returns, the resulting combination of uncompressed_surf
2662 * and uncompressed_view will be a valid view giving an uncompressed view of
2663 * the incoming surface. Depending on tiling, uncompressed_surf may have a
2664 * different isl_surf::dim from surf and uncompressed_view may or may not have
2665 * a zero base_array_layer. For legacy tiling (not Yf or Ys), an intratile
2666 * offset is returned in x_offset_sa and y_offset_sa. For standard Y tilings
2667 * (Yf and Ys), x_offset_sa and y_offset_sa will be set to zero.
2668 *
2669 * It is safe to call this function with surf == uncompressed_surf and
2670 * view == uncompressed_view.
2671 */
2672 bool MUST_CHECK
2673 isl_surf_get_uncompressed_surf(const struct isl_device *dev,
2674 const struct isl_surf *surf,
2675 const struct isl_view *view,
2676 struct isl_surf *uncompressed_surf,
2677 struct isl_view *uncompressed_view,
2678 uint64_t *offset_B,
2679 uint32_t *x_offset_el,
2680 uint32_t *y_offset_el);
2681
2682 /**
2683 * Calculate the intratile offsets to a surface coordinate, in elements.
2684 *
2685 * This function takes a coordinate in global tile space and returns the byte
2686 * offset to the specific tile as well as the offset within that tile to the
2687 * given coordinate in tile space. The returned x/y/z/array offsets are
2688 * guaranteed to lie within the tile.
2689 *
2690 * @param[in] tiling The tiling of the surface
2691 * @param[in] bpb The size of the surface format in bits per
2692 * block
2693 * @param[in] array_pitch_el_rows The array pitch of the surface for flat 2D
2694 * tilings such as ISL_TILING_Y0
2695 * @param[in] total_x_offset_el The X offset in tile space, in elements
2696 * @param[in] total_y_offset_el The Y offset in tile space, in elements
2697 * @param[in] total_z_offset_el The Z offset in tile space, in elements
2698 * @param[in] total_array_offset The array offset in tile space
2699 * @param[out] tile_offset_B The returned byte offset to the tile
2700 * @param[out] x_offset_el The X offset within the tile, in elements
2701 * @param[out] y_offset_el The Y offset within the tile, in elements
2702 * @param[out] z_offset_el The Z offset within the tile, in elements
2703 * @param[out] array_offset The array offset within the tile
2704 */
2705 void
2706 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
2707 enum isl_surf_dim dim,
2708 enum isl_msaa_layout msaa_layout,
2709 uint32_t bpb,
2710 uint32_t samples,
2711 uint32_t row_pitch_B,
2712 uint32_t array_pitch_el_rows,
2713 uint32_t total_x_offset_el,
2714 uint32_t total_y_offset_el,
2715 uint32_t total_z_offset_el,
2716 uint32_t total_array_offset,
2717 uint64_t *tile_offset_B,
2718 uint32_t *x_offset_el,
2719 uint32_t *y_offset_el,
2720 uint32_t *z_offset_el,
2721 uint32_t *array_offset);
2722
2723 /**
2724 * Calculate the intratile offsets to a surface coordinate, in samples.
2725 *
2726 * This function takes a coordinate in global tile space and returns the byte
2727 * offset to the specific tile as well as the offset within that tile to the
2728 * given coordinate in tile space. The returned x/y/z/array offsets are
2729 * guaranteed to lie within the tile.
2730 *
2731 * @param[in] tiling The tiling of the surface
2732 * @param[in] bpb The size of the surface format in bits per
2733 * block
2734 * @param[in] array_pitch_el_rows The array pitch of the surface for flat 2D
2735 * tilings such as ISL_TILING_Y0
2736 * @param[in] total_x_offset_sa The X offset in tile space, in samples
2737 * @param[in] total_y_offset_sa The Y offset in tile space, in samples
2738 * @param[in] total_z_offset_sa The Z offset in tile space, in samples
2739 * @param[in] total_array_offset The array offset in tile space
2740 * @param[out] tile_offset_B The returned byte offset to the tile
2741 * @param[out] x_offset_sa The X offset within the tile, in samples
2742 * @param[out] y_offset_sa The Y offset within the tile, in samples
2743 * @param[out] z_offset_sa The Z offset within the tile, in samples
2744 * @param[out] array_offset The array offset within the tile
2745 */
2746 static inline void
isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,enum isl_surf_dim dim,enum isl_msaa_layout msaa_layout,enum isl_format format,uint32_t samples,uint32_t row_pitch_B,uint32_t array_pitch_el_rows,uint32_t total_x_offset_sa,uint32_t total_y_offset_sa,uint32_t total_z_offset_sa,uint32_t total_array_offset,uint64_t * tile_offset_B,uint32_t * x_offset_sa,uint32_t * y_offset_sa,uint32_t * z_offset_sa,uint32_t * array_offset)2747 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
2748 enum isl_surf_dim dim,
2749 enum isl_msaa_layout msaa_layout,
2750 enum isl_format format,
2751 uint32_t samples,
2752 uint32_t row_pitch_B,
2753 uint32_t array_pitch_el_rows,
2754 uint32_t total_x_offset_sa,
2755 uint32_t total_y_offset_sa,
2756 uint32_t total_z_offset_sa,
2757 uint32_t total_array_offset,
2758 uint64_t *tile_offset_B,
2759 uint32_t *x_offset_sa,
2760 uint32_t *y_offset_sa,
2761 uint32_t *z_offset_sa,
2762 uint32_t *array_offset)
2763 {
2764 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
2765
2766 /* For computing the intratile offsets, we actually want a strange unit
2767 * which is samples for multisampled surfaces but elements for compressed
2768 * surfaces.
2769 */
2770 assert(total_x_offset_sa % fmtl->bw == 0);
2771 assert(total_y_offset_sa % fmtl->bh == 0);
2772 assert(total_z_offset_sa % fmtl->bd == 0);
2773 const uint32_t total_x_offset_el = total_x_offset_sa / fmtl->bw;
2774 const uint32_t total_y_offset_el = total_y_offset_sa / fmtl->bh;
2775 const uint32_t total_z_offset_el = total_z_offset_sa / fmtl->bd;
2776
2777 isl_tiling_get_intratile_offset_el(tiling, dim, msaa_layout, fmtl->bpb,
2778 samples, row_pitch_B,
2779 array_pitch_el_rows,
2780 total_x_offset_el,
2781 total_y_offset_el,
2782 total_z_offset_el,
2783 total_array_offset,
2784 tile_offset_B,
2785 x_offset_sa, y_offset_sa,
2786 z_offset_sa, array_offset);
2787 *x_offset_sa *= fmtl->bw;
2788 *y_offset_sa *= fmtl->bh;
2789 *z_offset_sa *= fmtl->bd;
2790 }
2791
2792 /**
2793 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2794 *
2795 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2796 * @pre surf->format must be a valid format for depth surfaces
2797 */
2798 uint32_t
2799 isl_surf_get_depth_format(const struct isl_device *dev,
2800 const struct isl_surf *surf);
2801
2802 /**
2803 * @brief performs a copy from linear to tiled surface
2804 *
2805 */
2806 void
2807 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
2808 uint32_t yt1, uint32_t yt2,
2809 char *dst, const char *src,
2810 uint32_t dst_pitch, int32_t src_pitch,
2811 bool has_swizzling,
2812 enum isl_tiling tiling,
2813 isl_memcpy_type copy_type);
2814
2815 /**
2816 * @brief performs a copy from tiled to linear surface
2817 *
2818 */
2819 void
2820 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
2821 uint32_t yt1, uint32_t yt2,
2822 char *dst, const char *src,
2823 int32_t dst_pitch, uint32_t src_pitch,
2824 bool has_swizzling,
2825 enum isl_tiling tiling,
2826 isl_memcpy_type copy_type);
2827
2828 /**
2829 * @brief computes the tile_w (in bytes) and tile_h (in rows) of
2830 * different tiling patterns.
2831 */
2832 static inline void
isl_get_tile_dims(enum isl_tiling tiling,uint32_t cpp,uint32_t * tile_w,uint32_t * tile_h)2833 isl_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
2834 uint32_t *tile_w, uint32_t *tile_h)
2835 {
2836 switch (tiling) {
2837 case ISL_TILING_X:
2838 *tile_w = 512;
2839 *tile_h = 8;
2840 break;
2841 case ISL_TILING_Y0:
2842 *tile_w = 128;
2843 *tile_h = 32;
2844 break;
2845 case ISL_TILING_LINEAR:
2846 *tile_w = cpp;
2847 *tile_h = 1;
2848 break;
2849 default:
2850 unreachable("not reached");
2851 }
2852 }
2853
2854 /**
2855 * @brief Computes masks that may be used to select the bits of the X
2856 * and Y coordinates that indicate the offset within a tile. If the BO is
2857 * untiled, the masks are set to 0.
2858 */
2859 static inline void
isl_get_tile_masks(enum isl_tiling tiling,uint32_t cpp,uint32_t * mask_x,uint32_t * mask_y)2860 isl_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
2861 uint32_t *mask_x, uint32_t *mask_y)
2862 {
2863 uint32_t tile_w_bytes, tile_h;
2864
2865 isl_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);
2866
2867 *mask_x = tile_w_bytes / cpp - 1;
2868 *mask_y = tile_h - 1;
2869 }
2870 #ifdef __cplusplus
2871 }
2872 #endif
2873
2874 #endif /* ISL_H */
2875