1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5 #ifndef __ASM_CPUTYPE_H
6 #define __ASM_CPUTYPE_H
7
8 #define INVALID_HWID ULONG_MAX
9
10 #define MPIDR_UP_BITMASK (0x1 << 30)
11 #define MPIDR_MT_BITMASK (0x1 << 24)
12 #define MPIDR_HWID_BITMASK UL(0xff00ffffff)
13
14 #define MPIDR_LEVEL_BITS_SHIFT 3
15 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
16 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
17
18 #define MPIDR_LEVEL_SHIFT(level) \
19 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
20
21 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
22 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
23
24 #define MIDR_REVISION_MASK 0xf
25 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
26 #define MIDR_PARTNUM_SHIFT 4
27 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
28 #define MIDR_PARTNUM(midr) \
29 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
30 #define MIDR_ARCHITECTURE_SHIFT 16
31 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
32 #define MIDR_ARCHITECTURE(midr) \
33 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
34 #define MIDR_VARIANT_SHIFT 20
35 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
36 #define MIDR_VARIANT(midr) \
37 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
38 #define MIDR_IMPLEMENTOR_SHIFT 24
39 #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
40 #define MIDR_IMPLEMENTOR(midr) \
41 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
42
43 #define MIDR_CPU_MODEL(imp, partnum) \
44 (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
45 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
46 ((partnum) << MIDR_PARTNUM_SHIFT))
47
48 #define MIDR_CPU_VAR_REV(var, rev) \
49 (((var) << MIDR_VARIANT_SHIFT) | (rev))
50
51 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
52 MIDR_ARCHITECTURE_MASK)
53
54 #define ARM_CPU_IMP_ARM 0x41
55 #define ARM_CPU_IMP_APM 0x50
56 #define ARM_CPU_IMP_CAVIUM 0x43
57 #define ARM_CPU_IMP_BRCM 0x42
58 #define ARM_CPU_IMP_QCOM 0x51
59 #define ARM_CPU_IMP_NVIDIA 0x4E
60 #define ARM_CPU_IMP_FUJITSU 0x46
61 #define ARM_CPU_IMP_HISI 0x48
62
63 #define ARM_CPU_PART_AEM_V8 0xD0F
64 #define ARM_CPU_PART_FOUNDATION 0xD00
65 #define ARM_CPU_PART_CORTEX_A57 0xD07
66 #define ARM_CPU_PART_CORTEX_A72 0xD08
67 #define ARM_CPU_PART_CORTEX_A53 0xD03
68 #define ARM_CPU_PART_CORTEX_A73 0xD09
69 #define ARM_CPU_PART_CORTEX_A75 0xD0A
70 #define ARM_CPU_PART_CORTEX_A35 0xD04
71 #define ARM_CPU_PART_CORTEX_A55 0xD05
72 #define ARM_CPU_PART_CORTEX_A76 0xD0B
73 #define ARM_CPU_PART_NEOVERSE_N1 0xD0C
74 #define ARM_CPU_PART_CORTEX_A77 0xD0D
75 #define ARM_CPU_PART_NEOVERSE_V1 0xD40
76 #define ARM_CPU_PART_CORTEX_A78 0xD41
77 #define ARM_CPU_PART_CORTEX_X1 0xD44
78 #define ARM_CPU_PART_CORTEX_A78C 0xD4B
79
80 #define APM_CPU_PART_POTENZA 0x000
81
82 #define CAVIUM_CPU_PART_THUNDERX 0x0A1
83 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
84 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
85 #define CAVIUM_CPU_PART_THUNDERX2 0x0AF
86
87 #define BRCM_CPU_PART_BRAHMA_B53 0x100
88 #define BRCM_CPU_PART_VULCAN 0x516
89
90 #define QCOM_CPU_PART_FALKOR_V1 0x800
91 #define QCOM_CPU_PART_FALKOR 0xC00
92 #define QCOM_CPU_PART_KRYO 0x200
93 #define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
94 #define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
95 #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
96 #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
97 #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
98
99 #define NVIDIA_CPU_PART_DENVER 0x003
100 #define NVIDIA_CPU_PART_CARMEL 0x004
101
102 #define FUJITSU_CPU_PART_A64FX 0x001
103
104 #define HISI_CPU_PART_TSV110 0xD01
105
106 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
107 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
108 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
109 #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
110 #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
111 #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
112 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
113 #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
114 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
115 #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
116 #define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
117 #define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
118 #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
119 #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
120 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
121 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
122 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
123 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
124 #define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
125 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
126 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
127 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
128 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
129 #define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
130 #define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
131 #define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
132 #define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
133 #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
134 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
135 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
136 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
137 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
138
139 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
140 #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
141 #define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
142 #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
143
144 #ifndef __ASSEMBLY__
145
146 #include <asm/sysreg.h>
147
148 #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
149
150 /*
151 * Represent a range of MIDR values for a given CPU model and a
152 * range of variant/revision values.
153 *
154 * @model - CPU model as defined by MIDR_CPU_MODEL
155 * @rv_min - Minimum value for the revision/variant as defined by
156 * MIDR_CPU_VAR_REV
157 * @rv_max - Maximum value for the variant/revision for the range.
158 */
159 struct midr_range {
160 u32 model;
161 u32 rv_min;
162 u32 rv_max;
163 };
164
165 #define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
166 { \
167 .model = m, \
168 .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
169 .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
170 }
171
172 #define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
173 #define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
174 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
175
midr_is_cpu_model_range(u32 midr,u32 model,u32 rv_min,u32 rv_max)176 static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
177 u32 rv_max)
178 {
179 u32 _model = midr & MIDR_CPU_MODEL_MASK;
180 u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);
181
182 return _model == model && rv >= rv_min && rv <= rv_max;
183 }
184
is_midr_in_range(u32 midr,struct midr_range const * range)185 static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
186 {
187 return midr_is_cpu_model_range(midr, range->model,
188 range->rv_min, range->rv_max);
189 }
190
191 static inline bool
is_midr_in_range_list(u32 midr,struct midr_range const * ranges)192 is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
193 {
194 while (ranges->model)
195 if (is_midr_in_range(midr, ranges++))
196 return true;
197 return false;
198 }
199
200 /*
201 * The CPU ID never changes at run time, so we might as well tell the
202 * compiler that it's constant. Use this function to read the CPU ID
203 * rather than directly reading processor_id or read_cpuid() directly.
204 */
read_cpuid_id(void)205 static inline u32 __attribute_const__ read_cpuid_id(void)
206 {
207 return read_cpuid(MIDR_EL1);
208 }
209
read_cpuid_mpidr(void)210 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
211 {
212 return read_cpuid(MPIDR_EL1);
213 }
214
read_cpuid_implementor(void)215 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
216 {
217 return MIDR_IMPLEMENTOR(read_cpuid_id());
218 }
219
read_cpuid_part_number(void)220 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
221 {
222 return MIDR_PARTNUM(read_cpuid_id());
223 }
224
read_cpuid_cachetype(void)225 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
226 {
227 return read_cpuid(CTR_EL0);
228 }
229 #endif /* __ASSEMBLY__ */
230
231 #endif
232