1 /* 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /** 33 * @defgroup los_mmu_descriptor_v6 MMU Descriptor v6 34 * @ingroup kernel 35 */ 36 37 #ifndef __LOS_MMU_DESCRIPTOR_V6_H__ 38 #define __LOS_MMU_DESCRIPTOR_V6_H__ 39 40 #include "los_vm_common.h" 41 42 #ifdef __cplusplus 43 #if __cplusplus 44 extern "C" { 45 #endif /* __cplusplus */ 46 #endif /* __cplusplus */ 47 48 #define __iomem 49 #ifndef IS_ALIGNED 50 #define IS_ALIGNED(a, b) (!(((UINTPTR)(a)) & (((UINTPTR)(b))-1))) 51 #endif 52 53 #define MMU_DESCRIPTOR_TEX_0 0 54 #define MMU_DESCRIPTOR_TEX_1 1 55 #define MMU_DESCRIPTOR_TEX_2 2 56 #define MMU_DESCRIPTOR_TEX_MASK 7 57 58 #define MMU_DESCRIPTOR_CACHE_BUFFER_SHIFT 2 59 #define MMU_DESCRIPTOR_CACHE_BUFFER(x) ((x) << MMU_DESCRIPTOR_CACHE_BUFFER_SHIFT) 60 #define MMU_DESCRIPTOR_NON_CACHEABLE MMU_DESCRIPTOR_CACHE_BUFFER(0) 61 #define MMU_DESCRIPTOR_WRITE_BACK_ALLOCATE MMU_DESCRIPTOR_CACHE_BUFFER(1) 62 #define MMU_DESCRIPTOR_WRITE_THROUGH_NO_ALLOCATE MMU_DESCRIPTOR_CACHE_BUFFER(2) 63 #define MMU_DESCRIPTOR_WRITE_BACK_NO_ALLOCATE MMU_DESCRIPTOR_CACHE_BUFFER(3) 64 65 /* user space mmu access permission define begin */ 66 #define MMU_DESCRIPTOR_DOMAIN_MANAGER 0 67 #define MMU_DESCRIPTOR_DOMAIN_CLIENT 1 68 #define MMU_DESCRIPTOR_DOMAIN_NA 2 69 70 /* L1 descriptor type */ 71 #define MMU_DESCRIPTOR_L1_TYPE_INVALID (0x0 << 0) 72 #define MMU_DESCRIPTOR_L1_TYPE_PAGE_TABLE (0x1 << 0) 73 #define MMU_DESCRIPTOR_L1_TYPE_SECTION (0x2 << 0) 74 #define MMU_DESCRIPTOR_L1_TYPE_MASK (0x3 << 0) 75 76 /* L2 descriptor type */ 77 #define MMU_DESCRIPTOR_L2_TYPE_INVALID (0x0 << 0) 78 #define MMU_DESCRIPTOR_L2_TYPE_LARGE_PAGE (0x1 << 0) 79 #define MMU_DESCRIPTOR_L2_TYPE_SMALL_PAGE (0x2 << 0) 80 #define MMU_DESCRIPTOR_L2_TYPE_SMALL_PAGE_XN (0x3 << 0) 81 #define MMU_DESCRIPTOR_L2_TYPE_MASK (0x3 << 0) 82 83 #define MMU_DESCRIPTOR_IS_L1_SIZE_ALIGNED(x) IS_ALIGNED(x, MMU_DESCRIPTOR_L1_SMALL_SIZE) 84 #define MMU_DESCRIPTOR_L1_SMALL_SIZE 0x100000 85 #define MMU_DESCRIPTOR_L1_SMALL_MASK (MMU_DESCRIPTOR_L1_SMALL_SIZE - 1) 86 #define MMU_DESCRIPTOR_L1_SMALL_FRAME (~MMU_DESCRIPTOR_L1_SMALL_MASK) 87 #define MMU_DESCRIPTOR_L1_SMALL_SHIFT 20 88 #define MMU_DESCRIPTOR_L1_SECTION_ADDR(x) ((x) & MMU_DESCRIPTOR_L1_SMALL_FRAME) 89 #define MMU_DESCRIPTOR_L1_PAGE_TABLE_ADDR(x) ((x) & ~((1 << 10)-1)) 90 #define MMU_DESCRIPTOR_L1_SMALL_L2_TABLES_PER_PAGE 4 91 #define MMU_DESCRIPTOR_L1_SMALL_ENTRY_NUMBERS 0x4000U 92 #define MMU_DESCRIPTOR_L1_SMALL_DOMAIN_MASK (~(0x0f << 5)) /* 4k page section domain mask */ 93 #define MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT (MMU_DESCRIPTOR_DOMAIN_CLIENT << 5) 94 95 #define MMU_DESCRIPTOR_L1_PAGETABLE_NON_SECURE (1 << 3) 96 #define MMU_DESCRIPTOR_L1_SECTION_NON_SECURE (1 << 19) 97 #define MMU_DESCRIPTOR_L1_SECTION_SHAREABLE (1 << 16) 98 #define MMU_DESCRIPTOR_L1_SECTION_NON_GLOBAL (1 << 17) 99 #define MMU_DESCRIPTOR_L1_SECTION_XN (1 << 4) 100 101 /* TEX CB */ 102 #define MMU_DESCRIPTOR_L1_TEX_SHIFT 12 /* type extension field shift */ 103 #define MMU_DESCRIPTOR_L1_TEX(x) \ 104 ((x) << MMU_DESCRIPTOR_L1_TEX_SHIFT) /* type extension */ 105 #define MMU_DESCRIPTOR_L1_TYPE_STRONGLY_ORDERED \ 106 (MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_0) | MMU_DESCRIPTOR_NON_CACHEABLE) 107 #define MMU_DESCRIPTOR_L1_TYPE_NORMAL_NOCACHE \ 108 (MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_1) | MMU_DESCRIPTOR_NON_CACHEABLE) 109 #define MMU_DESCRIPTOR_L1_TYPE_DEVICE_SHARED \ 110 (MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_0) | MMU_DESCRIPTOR_WRITE_BACK_ALLOCATE) 111 #define MMU_DESCRIPTOR_L1_TYPE_DEVICE_NON_SHARED \ 112 (MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_2) | MMU_DESCRIPTOR_NON_CACHEABLE) 113 #define MMU_DESCRIPTOR_L1_TYPE_NORMAL_WRITE_BACK_ALLOCATE \ 114 (MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_1) | MMU_DESCRIPTOR_WRITE_BACK_NO_ALLOCATE) 115 #define MMU_DESCRIPTOR_L1_TEX_TYPE_MASK \ 116 (MMU_DESCRIPTOR_L1_TEX(MMU_DESCRIPTOR_TEX_MASK) | MMU_DESCRIPTOR_WRITE_BACK_NO_ALLOCATE) 117 118 #define MMU_DESCRIPTOR_L1_AP2_SHIFT 15 119 #define MMU_DESCRIPTOR_L1_AP2(x) ((x) << MMU_DESCRIPTOR_L1_AP2_SHIFT) 120 #define MMU_DESCRIPTOR_L1_AP2_0 (MMU_DESCRIPTOR_L1_AP2(0)) 121 #define MMU_DESCRIPTOR_L1_AP2_1 (MMU_DESCRIPTOR_L1_AP2(1)) 122 #define MMU_DESCRIPTOR_L1_AP01_SHIFT 10 123 #define MMU_DESCRIPTOR_L1_AP01(x) ((x) << MMU_DESCRIPTOR_L1_AP01_SHIFT) 124 #define MMU_DESCRIPTOR_L1_AP01_0 (MMU_DESCRIPTOR_L1_AP01(0)) 125 #define MMU_DESCRIPTOR_L1_AP01_1 (MMU_DESCRIPTOR_L1_AP01(1)) 126 #define MMU_DESCRIPTOR_L1_AP01_3 (MMU_DESCRIPTOR_L1_AP01(3)) 127 #define MMU_DESCRIPTOR_L1_AP_P_NA_U_NA (MMU_DESCRIPTOR_L1_AP2_0 | MMU_DESCRIPTOR_L1_AP01_0) 128 #define MMU_DESCRIPTOR_L1_AP_P_RW_U_RW (MMU_DESCRIPTOR_L1_AP2_0 | MMU_DESCRIPTOR_L1_AP01_3) 129 #define MMU_DESCRIPTOR_L1_AP_P_RW_U_NA (MMU_DESCRIPTOR_L1_AP2_0 | MMU_DESCRIPTOR_L1_AP01_1) 130 #define MMU_DESCRIPTOR_L1_AP_P_RO_U_RO (MMU_DESCRIPTOR_L1_AP2_1 | MMU_DESCRIPTOR_L1_AP01_3) 131 #define MMU_DESCRIPTOR_L1_AP_P_RO_U_NA (MMU_DESCRIPTOR_L1_AP2_1 | MMU_DESCRIPTOR_L1_AP01_1) 132 #define MMU_DESCRIPTOR_L1_AP_MASK (MMU_DESCRIPTOR_L1_AP2_1 | MMU_DESCRIPTOR_L1_AP01_3) 133 134 #define MMU_DESCRIPTOR_L2_SMALL_SIZE 0x1000 135 #define MMU_DESCRIPTOR_L2_SMALL_MASK (MMU_DESCRIPTOR_L2_SMALL_SIZE - 1) 136 #define MMU_DESCRIPTOR_L2_SMALL_FRAME (~MMU_DESCRIPTOR_L2_SMALL_MASK) 137 #define MMU_DESCRIPTOR_L2_SMALL_SHIFT 12 138 #define MMU_DESCRIPTOR_L2_NUMBERS_PER_L1 \ 139 (MMU_DESCRIPTOR_L1_SMALL_SIZE >> MMU_DESCRIPTOR_L2_SMALL_SHIFT) 140 #define MMU_DESCRIPTOR_IS_L2_SIZE_ALIGNED(x) IS_ALIGNED(x, MMU_DESCRIPTOR_L2_SMALL_SIZE) 141 #define MMU_DESCRIPTOR_L2_TEX_SHIFT 6 /* type extension field shift */ 142 #define MMU_DESCRIPTOR_L2_TEX(x) \ 143 ((x) << MMU_DESCRIPTOR_L2_TEX_SHIFT) /* type extension */ 144 #define MMU_DESCRIPTOR_L2_TYPE_STRONGLY_ORDERED \ 145 (MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_0) | MMU_DESCRIPTOR_NON_CACHEABLE) 146 #define MMU_DESCRIPTOR_L2_TYPE_NORMAL_NOCACHE \ 147 (MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_1) | MMU_DESCRIPTOR_NON_CACHEABLE) 148 #define MMU_DESCRIPTOR_L2_TYPE_DEVICE_SHARED \ 149 (MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_0) | MMU_DESCRIPTOR_WRITE_BACK_ALLOCATE) 150 #define MMU_DESCRIPTOR_L2_TYPE_DEVICE_NON_SHARED \ 151 (MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_2) | MMU_DESCRIPTOR_NON_CACHEABLE) 152 #define MMU_DESCRIPTOR_L2_TYPE_NORMAL_WRITE_BACK_ALLOCATE \ 153 (MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_1) | MMU_DESCRIPTOR_WRITE_BACK_NO_ALLOCATE) 154 #define MMU_DESCRIPTOR_L2_TEX_TYPE_MASK \ 155 (MMU_DESCRIPTOR_L2_TEX(MMU_DESCRIPTOR_TEX_MASK) | MMU_DESCRIPTOR_WRITE_BACK_NO_ALLOCATE) 156 #define MMU_DESCRIPTOR_L2_AP2_SHIFT 9 157 #define MMU_DESCRIPTOR_L2_AP2(x) ((x) << MMU_DESCRIPTOR_L2_AP2_SHIFT) 158 #define MMU_DESCRIPTOR_L2_AP2_0 (MMU_DESCRIPTOR_L2_AP2(0)) 159 #define MMU_DESCRIPTOR_L2_AP2_1 (MMU_DESCRIPTOR_L2_AP2(1)) 160 #define MMU_DESCRIPTOR_L2_AP01_SHIFT 4 161 #define MMU_DESCRIPTOR_L2_AP01(x) ((x) << MMU_DESCRIPTOR_L2_AP01_SHIFT) 162 #define MMU_DESCRIPTOR_L2_AP01_0 (MMU_DESCRIPTOR_L2_AP01(0)) 163 #define MMU_DESCRIPTOR_L2_AP01_1 (MMU_DESCRIPTOR_L2_AP01(1)) 164 #define MMU_DESCRIPTOR_L2_AP01_3 (MMU_DESCRIPTOR_L2_AP01(3)) 165 #define MMU_DESCRIPTOR_L2_AP_P_NA_U_NA (MMU_DESCRIPTOR_L2_AP2_0 | MMU_DESCRIPTOR_L2_AP01_0) 166 #define MMU_DESCRIPTOR_L2_AP_P_RW_U_RW (MMU_DESCRIPTOR_L2_AP2_0 | MMU_DESCRIPTOR_L2_AP01_3) 167 #define MMU_DESCRIPTOR_L2_AP_P_RW_U_NA (MMU_DESCRIPTOR_L2_AP2_0 | MMU_DESCRIPTOR_L2_AP01_1) 168 #define MMU_DESCRIPTOR_L2_AP_P_RO_U_RO (MMU_DESCRIPTOR_L2_AP2_1 | MMU_DESCRIPTOR_L2_AP01_3) 169 #define MMU_DESCRIPTOR_L2_AP_P_RO_U_NA (MMU_DESCRIPTOR_L2_AP2_1 | MMU_DESCRIPTOR_L2_AP01_1) 170 #define MMU_DESCRIPTOR_L2_AP_MASK (MMU_DESCRIPTOR_L2_AP2_1 | MMU_DESCRIPTOR_L2_AP01_3) 171 172 #define MMU_DESCRIPTOR_L2_SHAREABLE (1 << 10) 173 #define MMU_DESCRIPTOR_L2_NON_GLOBAL (1 << 11) 174 #define MMU_DESCRIPTOR_L2_SMALL_PAGE_ADDR(x) ((x) & MMU_DESCRIPTOR_L2_SMALL_FRAME) 175 176 #define MMU_DESCRIPTOR_TTBCR_PD0 (1 << 4) 177 #define MMU_DESCRIPTOR_TTBR_WRITE_BACK_ALLOCATE 1 178 #define MMU_DESCRIPTOR_TTBR_RGN(x) (((x) & 0x3) << 3) 179 #define MMU_DESCRIPTOR_TTBR_IRGN(x) ((((x) & 0x1) << 6) | ((((x) >> 1) & 0x1) << 0)) 180 #define MMU_DESCRIPTOR_TTBR_S (1 << 1) 181 #define MMU_DESCRIPTOR_TTBR_NOS (1 << 5) 182 183 #ifdef LOSCFG_KERNEL_SMP 184 #define MMU_TTBRx_SHARABLE_FLAGS (MMU_DESCRIPTOR_TTBR_S | MMU_DESCRIPTOR_TTBR_NOS) 185 #else 186 #define MMU_TTBRx_SHARABLE_FLAGS 0 187 #endif 188 189 #define MMU_TTBRx_FLAGS \ 190 (MMU_DESCRIPTOR_TTBR_RGN(MMU_DESCRIPTOR_TTBR_WRITE_BACK_ALLOCATE) | \ 191 MMU_DESCRIPTOR_TTBR_IRGN(MMU_DESCRIPTOR_TTBR_WRITE_BACK_ALLOCATE) | \ 192 MMU_TTBRx_SHARABLE_FLAGS) 193 194 #ifdef LOSCFG_KERNEL_SMP 195 #define MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS \ 196 (MMU_DESCRIPTOR_L1_TYPE_SECTION | \ 197 MMU_DESCRIPTOR_L1_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \ 198 MMU_DESCRIPTOR_L1_AP_P_RW_U_NA | \ 199 MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT | \ 200 MMU_DESCRIPTOR_L1_SECTION_SHAREABLE) 201 #else 202 #define MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS \ 203 (MMU_DESCRIPTOR_L1_TYPE_SECTION | \ 204 MMU_DESCRIPTOR_L1_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \ 205 MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT | \ 206 MMU_DESCRIPTOR_L1_AP_P_RW_U_NA) 207 #endif 208 209 #define MMU_INITIAL_MAP_STRONGLY_ORDERED \ 210 (MMU_DESCRIPTOR_L1_TYPE_SECTION | \ 211 MMU_DESCRIPTOR_L1_TYPE_STRONGLY_ORDERED | \ 212 MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT | \ 213 MMU_DESCRIPTOR_L1_AP_P_RW_U_NA) 214 215 #define MMU_INITIAL_MAP_NORMAL_NOCACHE \ 216 (MMU_DESCRIPTOR_L1_TYPE_SECTION | \ 217 MMU_DESCRIPTOR_L1_TYPE_NORMAL_NOCACHE | \ 218 MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT | \ 219 MMU_DESCRIPTOR_L1_AP_P_RW_U_NA) 220 221 #define MMU_INITIAL_MAP_DEVICE \ 222 (MMU_DESCRIPTOR_L1_TYPE_SECTION | \ 223 MMU_DESCRIPTOR_L1_TYPE_DEVICE_SHARED | \ 224 MMU_DESCRIPTOR_L1_SMALL_DOMAIN_CLIENT | \ 225 MMU_DESCRIPTOR_L1_AP_P_RW_U_NA) 226 227 #ifdef __cplusplus 228 #if __cplusplus 229 } 230 #endif /* __cplusplus */ 231 #endif /* __cplusplus */ 232 233 #endif /* __LOS_MMU_DESCRIPTOR_V6_H__ */ 234 235