1 /* 2 * Generic definitions of Orion SoC flavors: 3 * Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90. 4 * 5 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12 #ifndef __ASM_ARCH_ORION5X_H 13 #define __ASM_ARCH_ORION5X_H 14 15 #include "irqs.h" 16 17 /***************************************************************************** 18 * Orion Address Maps 19 * 20 * phys 21 * e0000000 PCIe MEM space 22 * e8000000 PCI MEM space 23 * f0000000 PCIe WA space (Orion-1/Orion-NAS only) 24 * f1000000 on-chip peripheral registers 25 * f2000000 PCIe I/O space 26 * f2100000 PCI I/O space 27 * f2200000 SRAM dedicated for the crypto unit 28 * f4000000 device bus mappings (boot) 29 * fa000000 device bus mappings (cs0) 30 * fa800000 device bus mappings (cs2) 31 * fc000000 device bus mappings (cs0/cs1) 32 * 33 * virt phys size 34 * fec00000 f1000000 1M on-chip peripheral registers 35 * fee00000 f2000000 64K PCIe I/O space 36 * fee10000 f2100000 64K PCI I/O space 37 * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) 38 ****************************************************************************/ 39 #define ORION5X_REGS_PHYS_BASE 0xf1000000 40 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000) 41 #define ORION5X_REGS_SIZE SZ_1M 42 43 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 44 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 45 #define ORION5X_PCIE_IO_SIZE SZ_64K 46 47 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 48 #define ORION5X_PCI_IO_BUS_BASE 0x00010000 49 #define ORION5X_PCI_IO_SIZE SZ_64K 50 51 #define ORION5X_SRAM_PHYS_BASE (0xf2200000) 52 #define ORION5X_SRAM_SIZE SZ_8K 53 54 /* Relevant only for Orion-1/Orion-NAS */ 55 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 56 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000) 57 #define ORION5X_PCIE_WA_SIZE SZ_16M 58 59 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 60 #define ORION5X_PCIE_MEM_SIZE SZ_128M 61 62 #define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 63 #define ORION5X_PCI_MEM_SIZE SZ_128M 64 65 /******************************************************************************* 66 * Orion Registers Map 67 ******************************************************************************/ 68 69 #define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000) 70 #define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500) 71 #define ORION5X_DDR_WINS_SZ (0x10) 72 #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) 73 #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) 74 #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) 75 #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) 76 #define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100) 77 #define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600) 78 #define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000) 79 #define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000) 80 #define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000) 81 #define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100) 82 #define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100) 83 84 #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) 85 #define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) 86 #define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE) 87 #define ORION5X_BRIDGE_WINS_SZ (0x80) 88 89 #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) 90 91 #define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000) 92 93 #define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000) 94 #define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000) 95 96 #define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900) 97 #define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900) 98 99 #define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000) 100 #define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000) 101 102 #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000) 103 #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000) 104 105 #define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000) 106 107 #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000) 108 #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000) 109 110 /******************************************************************************* 111 * Device Bus Registers 112 ******************************************************************************/ 113 #define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) 114 #define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) 115 #define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) 116 #define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) 117 #define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) 118 #define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) 119 #define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) 120 #define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) 121 #define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) 122 #define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) 123 #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) 124 #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) 125 126 /******************************************************************************* 127 * Supported Devices & Revisions 128 ******************************************************************************/ 129 /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ 130 #define MV88F5181_DEV_ID 0x5181 131 #define MV88F5181_REV_B1 3 132 #define MV88F5181L_REV_A0 8 133 #define MV88F5181L_REV_A1 9 134 /* Orion-NAS (88F5182) */ 135 #define MV88F5182_DEV_ID 0x5182 136 #define MV88F5182_REV_A2 2 137 /* Orion-2 (88F5281) */ 138 #define MV88F5281_DEV_ID 0x5281 139 #define MV88F5281_REV_D0 4 140 #define MV88F5281_REV_D1 5 141 #define MV88F5281_REV_D2 6 142 /* Orion-1-90 (88F6183) */ 143 #define MV88F6183_DEV_ID 0x6183 144 #define MV88F6183_REV_B0 3 145 146 #endif 147