1 /* 2 * Copyright 2011 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __NV50_IR_DRIVER_H__ 24 #define __NV50_IR_DRIVER_H__ 25 26 #include "pipe/p_shader_tokens.h" 27 28 #include "util/blob.h" 29 #include "tgsi/tgsi_util.h" 30 #include "tgsi/tgsi_parse.h" 31 #include "tgsi/tgsi_scan.h" 32 33 struct nir_shader_compiler_options; 34 35 /* 36 * This struct constitutes linkage information in TGSI terminology. 37 * 38 * It is created by the code generator and handed to the pipe driver 39 * for input/output slot assignment. 40 */ 41 struct nv50_ir_varying 42 { 43 uint8_t slot[4]; /* native slots for xyzw (addresses in 32-bit words) */ 44 45 unsigned mask : 4; /* vec4 mask */ 46 unsigned linear : 1; /* linearly interpolated if true (and not flat) */ 47 unsigned flat : 1; 48 unsigned sc : 1; /* special colour interpolation mode (SHADE_MODEL) */ 49 unsigned centroid : 1; 50 unsigned patch : 1; /* patch constant value */ 51 unsigned regular : 1; /* driver-specific meaning (e.g. input in sreg) */ 52 unsigned input : 1; /* indicates direction of system values */ 53 unsigned oread : 1; /* true if output is read from parallel TCP */ 54 55 ubyte id; /* TGSI register index */ 56 ubyte sn; /* TGSI semantic name */ 57 ubyte si; /* TGSI semantic index */ 58 }; 59 60 #ifndef NDEBUG 61 # define NV50_IR_DEBUG_BASIC (1 << 0) 62 # define NV50_IR_DEBUG_VERBOSE (2 << 0) 63 # define NV50_IR_DEBUG_REG_ALLOC (1 << 2) 64 #else 65 # define NV50_IR_DEBUG_BASIC 0 66 # define NV50_IR_DEBUG_VERBOSE 0 67 # define NV50_IR_DEBUG_REG_ALLOC 0 68 #endif 69 70 struct nv50_ir_prog_symbol 71 { 72 uint32_t label; 73 uint32_t offset; 74 }; 75 76 #define NVISA_GF100_CHIPSET 0xc0 77 #define NVISA_GK104_CHIPSET 0xe0 78 #define NVISA_GK20A_CHIPSET 0xea 79 #define NVISA_GM107_CHIPSET 0x110 80 #define NVISA_GM200_CHIPSET 0x120 81 #define NVISA_GV100_CHIPSET 0x140 82 83 struct nv50_ir_prog_info_out; 84 85 /* used for the input data and assignSlot interface */ 86 struct nv50_ir_prog_info 87 { 88 uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */ 89 90 uint8_t type; /* PIPE_SHADER */ 91 92 uint8_t optLevel; /* optimization level (0 to 3) */ 93 uint8_t dbgFlags; 94 bool omitLineNum; /* only used for printing the prog when dbgFlags is set */ 95 96 struct { 97 uint32_t smemSize; /* required shared memory per block */ 98 uint8_t sourceRep; /* PIPE_SHADER_IR_* */ 99 const void *source; 100 } bin; 101 102 union { 103 struct { 104 uint32_t inputOffset; /* base address for user args */ 105 uint32_t gridInfoBase; /* base address for NTID,NCTAID */ 106 uint16_t numThreads[3]; /* max number of threads */ 107 } cp; 108 } prop; 109 110 struct { 111 int8_t genUserClip; /* request user clip planes for ClipVertex */ 112 uint8_t auxCBSlot; /* driver constant buffer slot */ 113 uint16_t ucpBase; /* base address for UCPs */ 114 uint16_t drawInfoBase; /* base address for draw parameters */ 115 uint16_t alphaRefBase; /* base address for alpha test values */ 116 int8_t viewportId; /* output index of ViewportIndex */ 117 bool mul_zero_wins; /* program wants for x*0 = 0 */ 118 bool nv50styleSurfaces; /* generate gX[] access for raw buffers */ 119 uint16_t texBindBase; /* base address for tex handles (nve4) */ 120 uint16_t fbtexBindBase; /* base address for fbtex handle (nve4) */ 121 uint16_t suInfoBase; /* base address for surface info (nve4) */ 122 uint16_t bindlessBase; /* base address for bindless image info (nve4) */ 123 uint16_t bufInfoBase; /* base address for buffer info */ 124 uint16_t sampleInfoBase; /* base address for sample positions */ 125 uint8_t msInfoCBSlot; /* cX[] used for multisample info */ 126 uint16_t msInfoBase; /* base address for multisample info */ 127 uint16_t uboInfoBase; /* base address for compute UBOs (gk104+) */ 128 129 uint16_t membarOffset; /* base address for membar reads (nv50) */ 130 uint8_t gmemMembar; /* gX[] on which to perform membar reads (nv50) */ 131 } io; 132 133 /* driver callback to assign input/output locations */ 134 int (*assignSlots)(struct nv50_ir_prog_info_out *); 135 }; 136 137 /* the produced binary with metadata */ 138 struct nv50_ir_prog_info_out 139 { 140 uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */ 141 142 uint8_t type; /* PIPE_SHADER */ 143 144 struct { 145 int16_t maxGPR; /* may be -1 if none used */ 146 uint32_t tlsSpace; /* required local memory per thread */ 147 uint32_t smemSize; /* required shared memory per block */ 148 uint32_t *code; 149 uint32_t codeSize; 150 uint32_t instructions; 151 void *relocData; 152 void *fixupData; 153 } bin; 154 155 struct nv50_ir_varying sv[PIPE_MAX_SHADER_INPUTS]; 156 struct nv50_ir_varying in[PIPE_MAX_SHADER_INPUTS]; 157 struct nv50_ir_varying out[PIPE_MAX_SHADER_OUTPUTS]; 158 uint8_t numInputs; 159 uint8_t numOutputs; 160 uint8_t numPatchConstants; /* also included in numInputs/numOutputs */ 161 uint8_t numSysVals; 162 163 union { 164 struct { 165 bool usesDrawParameters; 166 } vp; 167 struct { 168 uint8_t outputPatchSize; 169 uint8_t partitioning; /* PIPE_TESS_PART */ 170 int8_t winding; /* +1 (clockwise) / -1 (counter-clockwise) */ 171 uint8_t domain; /* PIPE_PRIM_{QUADS,TRIANGLES,LINES} */ 172 uint8_t outputPrim; /* PIPE_PRIM_{TRIANGLES,LINES,POINTS} */ 173 } tp; 174 struct { 175 uint8_t outputPrim; 176 unsigned instanceCount; 177 unsigned maxVertices; 178 } gp; 179 struct { 180 unsigned numColourResults; 181 bool writesDepth : 1; 182 bool earlyFragTests : 1; 183 bool postDepthCoverage : 1; 184 bool usesDiscard : 1; 185 bool usesSampleMaskIn : 1; 186 bool readsFramebuffer : 1; 187 bool readsSampleLocations : 1; 188 bool separateFragData : 1; 189 } fp; 190 struct { 191 struct { 192 unsigned valid : 1; 193 unsigned image : 1; 194 unsigned slot : 6; 195 } gmem[16]; /* nv50 only */ 196 } cp; 197 } prop; 198 199 struct { 200 uint8_t clipDistances; /* number of clip distance outputs */ 201 uint8_t cullDistances; /* number of cull distance outputs */ 202 int8_t genUserClip; /* request user clip planes for ClipVertex */ 203 uint8_t instanceId; /* system value index of InstanceID */ 204 uint8_t vertexId; /* system value index of VertexID */ 205 uint8_t edgeFlagIn; 206 uint8_t edgeFlagOut; 207 uint8_t fragDepth; /* output index of FragDepth */ 208 uint8_t sampleMask; /* output index of SampleMask */ 209 uint8_t globalAccess; /* 1 for read, 2 for wr, 3 for rw */ 210 bool fp64; /* program uses fp64 math */ 211 bool layer_viewport_relative; 212 } io; 213 214 uint8_t numBarriers; 215 216 void *driverPriv; 217 }; 218 219 #ifdef __cplusplus 220 extern "C" { 221 #endif 222 223 const struct nir_shader_compiler_options * 224 nv50_ir_nir_shader_compiler_options(int chipset); 225 226 extern int nv50_ir_generate_code(struct nv50_ir_prog_info *, 227 struct nv50_ir_prog_info_out *); 228 229 extern void nv50_ir_relocate_code(void *relocData, uint32_t *code, 230 uint32_t codePos, 231 uint32_t libPos, 232 uint32_t dataPos); 233 234 extern void 235 nv50_ir_apply_fixups(void *fixupData, uint32_t *code, 236 bool force_per_sample, bool flatshade, 237 uint8_t alphatest, bool msaa); 238 239 /* obtain code that will be shared among programs */ 240 extern void nv50_ir_get_target_library(uint32_t chipset, 241 const uint32_t **code, uint32_t *size); 242 243 244 #ifdef __cplusplus 245 namespace nv50_ir 246 { 247 struct FixupEntry; 248 struct FixupData; 249 250 void 251 gk110_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 252 const nv50_ir::FixupData& data); 253 void 254 gm107_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 255 const nv50_ir::FixupData& data); 256 void 257 nv50_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 258 const nv50_ir::FixupData& data); 259 void 260 nvc0_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 261 const nv50_ir::FixupData& data); 262 void 263 gv100_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 264 const nv50_ir::FixupData& data); 265 void 266 gk110_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 267 const nv50_ir::FixupData& data); 268 void 269 gm107_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 270 const nv50_ir::FixupData& data); 271 void 272 nvc0_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 273 const nv50_ir::FixupData& data); 274 void 275 gv100_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 276 const nv50_ir::FixupData& data); 277 } 278 #endif 279 280 extern void 281 nv50_ir_prog_info_out_print(struct nv50_ir_prog_info_out *); 282 283 /* Serialize a nv50_ir_prog_info structure and save it into blob */ 284 extern bool 285 nv50_ir_prog_info_serialize(struct blob *, struct nv50_ir_prog_info *); 286 287 /* Serialize a nv50_ir_prog_info_out structure and save it into blob */ 288 extern bool MUST_CHECK 289 nv50_ir_prog_info_out_serialize(struct blob *, struct nv50_ir_prog_info_out *); 290 291 /* Deserialize from data and save into a nv50_ir_prog_info_out structure 292 * using a pointer. Size is a total size of the serialized data. 293 * Offset points to where info_out in data is located. */ 294 extern bool MUST_CHECK 295 nv50_ir_prog_info_out_deserialize(void *data, size_t size, size_t offset, 296 struct nv50_ir_prog_info_out *); 297 298 #ifdef __cplusplus 299 } 300 #endif 301 302 #endif // __NV50_IR_DRIVER_H__ 303