1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9
10 #include <linux/types.h>
11 #include <linux/uuid.h>
12
13 /* NQN names in commands fields specified one size */
14 #define NVMF_NQN_FIELD_LEN 256
15
16 /* However the max length of a qualified name is another size */
17 #define NVMF_NQN_SIZE 223
18
19 #define NVMF_TRSVCID_SIZE 32
20 #define NVMF_TRADDR_SIZE 256
21 #define NVMF_TSAS_SIZE 256
22
23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
24
25 #define NVME_RDMA_IP_PORT 4420
26
27 #define NVME_NSID_ALL 0xffffffff
28
29 enum nvme_subsys_type {
30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
31 NVME_NQN_NVME = 2, /* NVME type target subsystem */
32 };
33
34 /* Address Family codes for Discovery Log Page entry ADRFAM field */
35 enum {
36 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
37 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
38 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
39 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
40 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
41 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
42 NVMF_ADDR_FAMILY_MAX,
43 };
44
45 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
46 enum {
47 NVMF_TRTYPE_RDMA = 1, /* RDMA */
48 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
49 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
50 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
51 NVMF_TRTYPE_MAX,
52 };
53
54 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
55 enum {
56 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
57 NVMF_TREQ_REQUIRED = 1, /* Required */
58 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
59 #define NVME_TREQ_SECURE_CHANNEL_MASK \
60 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
61
62 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
63 };
64
65 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
66 * RDMA_QPTYPE field
67 */
68 enum {
69 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
70 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
71 };
72
73 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
74 * RDMA_QPTYPE field
75 */
76 enum {
77 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
78 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
79 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
80 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
81 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
82 };
83
84 /* RDMA Connection Management Service Type codes for Discovery Log Page
85 * entry TSAS RDMA_CMS field
86 */
87 enum {
88 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
89 };
90
91 #define NVME_AQ_DEPTH 32
92 #define NVME_NR_AEN_COMMANDS 1
93 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
94
95 /*
96 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
97 * NVM-Express 1.2 specification, section 4.1.2.
98 */
99 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
100
101 enum {
102 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
103 NVME_REG_VS = 0x0008, /* Version */
104 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
105 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
106 NVME_REG_CC = 0x0014, /* Controller Configuration */
107 NVME_REG_CSTS = 0x001c, /* Controller Status */
108 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
109 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
110 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
111 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
112 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
113 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
114 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
115 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
116 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
117 * Location
118 */
119 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
120 * Space Control
121 */
122 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
123 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
124 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
125 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
126 * Buffer Size
127 */
128 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
129 * Write Throughput
130 */
131 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
132 };
133
134 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
135 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
136 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
137 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
138 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
139 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
140 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
141 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
142
143 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
144 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
145
146 enum {
147 NVME_CMBSZ_SQS = 1 << 0,
148 NVME_CMBSZ_CQS = 1 << 1,
149 NVME_CMBSZ_LISTS = 1 << 2,
150 NVME_CMBSZ_RDS = 1 << 3,
151 NVME_CMBSZ_WDS = 1 << 4,
152
153 NVME_CMBSZ_SZ_SHIFT = 12,
154 NVME_CMBSZ_SZ_MASK = 0xfffff,
155
156 NVME_CMBSZ_SZU_SHIFT = 8,
157 NVME_CMBSZ_SZU_MASK = 0xf,
158 };
159
160 /*
161 * Submission and Completion Queue Entry Sizes for the NVM command set.
162 * (In bytes and specified as a power of two (2^n)).
163 */
164 #define NVME_ADM_SQES 6
165 #define NVME_NVM_IOSQES 6
166 #define NVME_NVM_IOCQES 4
167
168 enum {
169 NVME_CC_ENABLE = 1 << 0,
170 NVME_CC_EN_SHIFT = 0,
171 NVME_CC_CSS_SHIFT = 4,
172 NVME_CC_MPS_SHIFT = 7,
173 NVME_CC_AMS_SHIFT = 11,
174 NVME_CC_SHN_SHIFT = 14,
175 NVME_CC_IOSQES_SHIFT = 16,
176 NVME_CC_IOCQES_SHIFT = 20,
177 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
178 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
179 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
180 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
181 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
182 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
183 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
184 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
185 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
186 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
187 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
188 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
189 NVME_CAP_CSS_NVM = 1 << 0,
190 NVME_CAP_CSS_CSI = 1 << 6,
191 NVME_CSTS_RDY = 1 << 0,
192 NVME_CSTS_CFS = 1 << 1,
193 NVME_CSTS_NSSRO = 1 << 4,
194 NVME_CSTS_PP = 1 << 5,
195 NVME_CSTS_SHST_NORMAL = 0 << 2,
196 NVME_CSTS_SHST_OCCUR = 1 << 2,
197 NVME_CSTS_SHST_CMPLT = 2 << 2,
198 NVME_CSTS_SHST_MASK = 3 << 2,
199 NVME_CMBMSC_CRE = 1 << 0,
200 NVME_CMBMSC_CMSE = 1 << 1,
201 };
202
203 struct nvme_id_power_state {
204 __le16 max_power; /* centiwatts */
205 __u8 rsvd2;
206 __u8 flags;
207 __le32 entry_lat; /* microseconds */
208 __le32 exit_lat; /* microseconds */
209 __u8 read_tput;
210 __u8 read_lat;
211 __u8 write_tput;
212 __u8 write_lat;
213 __le16 idle_power;
214 __u8 idle_scale;
215 __u8 rsvd19;
216 __le16 active_power;
217 __u8 active_work_scale;
218 __u8 rsvd23[9];
219 };
220
221 enum {
222 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
223 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
224 };
225
226 enum nvme_ctrl_attr {
227 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
228 NVME_CTRL_ATTR_TBKAS = (1 << 6),
229 };
230
231 struct nvme_id_ctrl {
232 __le16 vid;
233 __le16 ssvid;
234 char sn[20];
235 char mn[40];
236 char fr[8];
237 __u8 rab;
238 __u8 ieee[3];
239 __u8 cmic;
240 __u8 mdts;
241 __le16 cntlid;
242 __le32 ver;
243 __le32 rtd3r;
244 __le32 rtd3e;
245 __le32 oaes;
246 __le32 ctratt;
247 __u8 rsvd100[28];
248 __le16 crdt1;
249 __le16 crdt2;
250 __le16 crdt3;
251 __u8 rsvd134[122];
252 __le16 oacs;
253 __u8 acl;
254 __u8 aerl;
255 __u8 frmw;
256 __u8 lpa;
257 __u8 elpe;
258 __u8 npss;
259 __u8 avscc;
260 __u8 apsta;
261 __le16 wctemp;
262 __le16 cctemp;
263 __le16 mtfa;
264 __le32 hmpre;
265 __le32 hmmin;
266 __u8 tnvmcap[16];
267 __u8 unvmcap[16];
268 __le32 rpmbs;
269 __le16 edstt;
270 __u8 dsto;
271 __u8 fwug;
272 __le16 kas;
273 __le16 hctma;
274 __le16 mntmt;
275 __le16 mxtmt;
276 __le32 sanicap;
277 __le32 hmminds;
278 __le16 hmmaxd;
279 __u8 rsvd338[4];
280 __u8 anatt;
281 __u8 anacap;
282 __le32 anagrpmax;
283 __le32 nanagrpid;
284 __u8 rsvd352[160];
285 __u8 sqes;
286 __u8 cqes;
287 __le16 maxcmd;
288 __le32 nn;
289 __le16 oncs;
290 __le16 fuses;
291 __u8 fna;
292 __u8 vwc;
293 __le16 awun;
294 __le16 awupf;
295 __u8 nvscc;
296 __u8 nwpc;
297 __le16 acwu;
298 __u8 rsvd534[2];
299 __le32 sgls;
300 __le32 mnan;
301 __u8 rsvd544[224];
302 char subnqn[256];
303 __u8 rsvd1024[768];
304 __le32 ioccsz;
305 __le32 iorcsz;
306 __le16 icdoff;
307 __u8 ctrattr;
308 __u8 msdbd;
309 __u8 rsvd1804[244];
310 struct nvme_id_power_state psd[32];
311 __u8 vs[1024];
312 };
313
314 enum {
315 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
316 NVME_CTRL_CMIC_ANA = 1 << 3,
317 NVME_CTRL_ONCS_COMPARE = 1 << 0,
318 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
319 NVME_CTRL_ONCS_DSM = 1 << 2,
320 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
321 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
322 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
323 NVME_CTRL_VWC_PRESENT = 1 << 0,
324 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
325 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
326 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
327 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
328 NVME_CTRL_CTRATT_128_ID = 1 << 0,
329 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
330 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
331 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
332 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
333 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
334 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
335 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
336 };
337
338 struct nvme_lbaf {
339 __le16 ms;
340 __u8 ds;
341 __u8 rp;
342 };
343
344 struct nvme_id_ns {
345 __le64 nsze;
346 __le64 ncap;
347 __le64 nuse;
348 __u8 nsfeat;
349 __u8 nlbaf;
350 __u8 flbas;
351 __u8 mc;
352 __u8 dpc;
353 __u8 dps;
354 __u8 nmic;
355 __u8 rescap;
356 __u8 fpi;
357 __u8 dlfeat;
358 __le16 nawun;
359 __le16 nawupf;
360 __le16 nacwu;
361 __le16 nabsn;
362 __le16 nabo;
363 __le16 nabspf;
364 __le16 noiob;
365 __u8 nvmcap[16];
366 __le16 npwg;
367 __le16 npwa;
368 __le16 npdg;
369 __le16 npda;
370 __le16 nows;
371 __u8 rsvd74[18];
372 __le32 anagrpid;
373 __u8 rsvd96[3];
374 __u8 nsattr;
375 __le16 nvmsetid;
376 __le16 endgid;
377 __u8 nguid[16];
378 __u8 eui64[8];
379 struct nvme_lbaf lbaf[16];
380 __u8 rsvd192[192];
381 __u8 vs[3712];
382 };
383
384 struct nvme_zns_lbafe {
385 __le64 zsze;
386 __u8 zdes;
387 __u8 rsvd9[7];
388 };
389
390 struct nvme_id_ns_zns {
391 __le16 zoc;
392 __le16 ozcs;
393 __le32 mar;
394 __le32 mor;
395 __le32 rrl;
396 __le32 frl;
397 __u8 rsvd20[2796];
398 struct nvme_zns_lbafe lbafe[16];
399 __u8 rsvd3072[768];
400 __u8 vs[256];
401 };
402
403 struct nvme_id_ctrl_zns {
404 __u8 zasl;
405 __u8 rsvd1[4095];
406 };
407
408 enum {
409 NVME_ID_CNS_NS = 0x00,
410 NVME_ID_CNS_CTRL = 0x01,
411 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
412 NVME_ID_CNS_NS_DESC_LIST = 0x03,
413 NVME_ID_CNS_CS_NS = 0x05,
414 NVME_ID_CNS_CS_CTRL = 0x06,
415 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
416 NVME_ID_CNS_NS_PRESENT = 0x11,
417 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
418 NVME_ID_CNS_CTRL_LIST = 0x13,
419 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
420 NVME_ID_CNS_NS_GRANULARITY = 0x16,
421 NVME_ID_CNS_UUID_LIST = 0x17,
422 };
423
424 enum {
425 NVME_CSI_NVM = 0,
426 NVME_CSI_ZNS = 2,
427 };
428
429 enum {
430 NVME_DIR_IDENTIFY = 0x00,
431 NVME_DIR_STREAMS = 0x01,
432 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
433 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
434 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
435 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
436 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
437 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
438 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
439 NVME_DIR_ENDIR = 0x01,
440 };
441
442 enum {
443 NVME_NS_FEAT_THIN = 1 << 0,
444 NVME_NS_FEAT_ATOMICS = 1 << 1,
445 NVME_NS_FEAT_IO_OPT = 1 << 4,
446 NVME_NS_ATTR_RO = 1 << 0,
447 NVME_NS_FLBAS_LBA_MASK = 0xf,
448 NVME_NS_FLBAS_META_EXT = 0x10,
449 NVME_NS_NMIC_SHARED = 1 << 0,
450 NVME_LBAF_RP_BEST = 0,
451 NVME_LBAF_RP_BETTER = 1,
452 NVME_LBAF_RP_GOOD = 2,
453 NVME_LBAF_RP_DEGRADED = 3,
454 NVME_NS_DPC_PI_LAST = 1 << 4,
455 NVME_NS_DPC_PI_FIRST = 1 << 3,
456 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
457 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
458 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
459 NVME_NS_DPS_PI_FIRST = 1 << 3,
460 NVME_NS_DPS_PI_MASK = 0x7,
461 NVME_NS_DPS_PI_TYPE1 = 1,
462 NVME_NS_DPS_PI_TYPE2 = 2,
463 NVME_NS_DPS_PI_TYPE3 = 3,
464 };
465
466 /* Identify Namespace Metadata Capabilities (MC): */
467 enum {
468 NVME_MC_EXTENDED_LBA = (1 << 0),
469 NVME_MC_METADATA_PTR = (1 << 1),
470 };
471
472 struct nvme_ns_id_desc {
473 __u8 nidt;
474 __u8 nidl;
475 __le16 reserved;
476 };
477
478 #define NVME_NIDT_EUI64_LEN 8
479 #define NVME_NIDT_NGUID_LEN 16
480 #define NVME_NIDT_UUID_LEN 16
481 #define NVME_NIDT_CSI_LEN 1
482
483 enum {
484 NVME_NIDT_EUI64 = 0x01,
485 NVME_NIDT_NGUID = 0x02,
486 NVME_NIDT_UUID = 0x03,
487 NVME_NIDT_CSI = 0x04,
488 };
489
490 struct nvme_smart_log {
491 __u8 critical_warning;
492 __u8 temperature[2];
493 __u8 avail_spare;
494 __u8 spare_thresh;
495 __u8 percent_used;
496 __u8 endu_grp_crit_warn_sumry;
497 __u8 rsvd7[25];
498 __u8 data_units_read[16];
499 __u8 data_units_written[16];
500 __u8 host_reads[16];
501 __u8 host_writes[16];
502 __u8 ctrl_busy_time[16];
503 __u8 power_cycles[16];
504 __u8 power_on_hours[16];
505 __u8 unsafe_shutdowns[16];
506 __u8 media_errors[16];
507 __u8 num_err_log_entries[16];
508 __le32 warning_temp_time;
509 __le32 critical_comp_time;
510 __le16 temp_sensor[8];
511 __le32 thm_temp1_trans_count;
512 __le32 thm_temp2_trans_count;
513 __le32 thm_temp1_total_time;
514 __le32 thm_temp2_total_time;
515 __u8 rsvd232[280];
516 };
517
518 struct nvme_fw_slot_info_log {
519 __u8 afi;
520 __u8 rsvd1[7];
521 __le64 frs[7];
522 __u8 rsvd64[448];
523 };
524
525 enum {
526 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
527 NVME_CMD_EFFECTS_LBCC = 1 << 1,
528 NVME_CMD_EFFECTS_NCC = 1 << 2,
529 NVME_CMD_EFFECTS_NIC = 1 << 3,
530 NVME_CMD_EFFECTS_CCC = 1 << 4,
531 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
532 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
533 };
534
535 struct nvme_effects_log {
536 __le32 acs[256];
537 __le32 iocs[256];
538 __u8 resv[2048];
539 };
540
541 enum nvme_ana_state {
542 NVME_ANA_OPTIMIZED = 0x01,
543 NVME_ANA_NONOPTIMIZED = 0x02,
544 NVME_ANA_INACCESSIBLE = 0x03,
545 NVME_ANA_PERSISTENT_LOSS = 0x04,
546 NVME_ANA_CHANGE = 0x0f,
547 };
548
549 struct nvme_ana_group_desc {
550 __le32 grpid;
551 __le32 nnsids;
552 __le64 chgcnt;
553 __u8 state;
554 __u8 rsvd17[15];
555 __le32 nsids[];
556 };
557
558 /* flag for the log specific field of the ANA log */
559 #define NVME_ANA_LOG_RGO (1 << 0)
560
561 struct nvme_ana_rsp_hdr {
562 __le64 chgcnt;
563 __le16 ngrps;
564 __le16 rsvd10[3];
565 };
566
567 struct nvme_zone_descriptor {
568 __u8 zt;
569 __u8 zs;
570 __u8 za;
571 __u8 rsvd3[5];
572 __le64 zcap;
573 __le64 zslba;
574 __le64 wp;
575 __u8 rsvd32[32];
576 };
577
578 enum {
579 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
580 };
581
582 struct nvme_zone_report {
583 __le64 nr_zones;
584 __u8 resv8[56];
585 struct nvme_zone_descriptor entries[];
586 };
587
588 enum {
589 NVME_SMART_CRIT_SPARE = 1 << 0,
590 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
591 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
592 NVME_SMART_CRIT_MEDIA = 1 << 3,
593 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
594 };
595
596 enum {
597 NVME_AER_ERROR = 0,
598 NVME_AER_SMART = 1,
599 NVME_AER_NOTICE = 2,
600 NVME_AER_CSS = 6,
601 NVME_AER_VS = 7,
602 };
603
604 enum {
605 NVME_AER_NOTICE_NS_CHANGED = 0x00,
606 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
607 NVME_AER_NOTICE_ANA = 0x03,
608 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
609 };
610
611 enum {
612 NVME_AEN_BIT_NS_ATTR = 8,
613 NVME_AEN_BIT_FW_ACT = 9,
614 NVME_AEN_BIT_ANA_CHANGE = 11,
615 NVME_AEN_BIT_DISC_CHANGE = 31,
616 };
617
618 enum {
619 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
620 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
621 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
622 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
623 };
624
625 struct nvme_lba_range_type {
626 __u8 type;
627 __u8 attributes;
628 __u8 rsvd2[14];
629 __u64 slba;
630 __u64 nlb;
631 __u8 guid[16];
632 __u8 rsvd48[16];
633 };
634
635 enum {
636 NVME_LBART_TYPE_FS = 0x01,
637 NVME_LBART_TYPE_RAID = 0x02,
638 NVME_LBART_TYPE_CACHE = 0x03,
639 NVME_LBART_TYPE_SWAP = 0x04,
640
641 NVME_LBART_ATTRIB_TEMP = 1 << 0,
642 NVME_LBART_ATTRIB_HIDE = 1 << 1,
643 };
644
645 struct nvme_reservation_status {
646 __le32 gen;
647 __u8 rtype;
648 __u8 regctl[2];
649 __u8 resv5[2];
650 __u8 ptpls;
651 __u8 resv10[13];
652 struct {
653 __le16 cntlid;
654 __u8 rcsts;
655 __u8 resv3[5];
656 __le64 hostid;
657 __le64 rkey;
658 } regctl_ds[];
659 };
660
661 enum nvme_async_event_type {
662 NVME_AER_TYPE_ERROR = 0,
663 NVME_AER_TYPE_SMART = 1,
664 NVME_AER_TYPE_NOTICE = 2,
665 };
666
667 /* I/O commands */
668
669 enum nvme_opcode {
670 nvme_cmd_flush = 0x00,
671 nvme_cmd_write = 0x01,
672 nvme_cmd_read = 0x02,
673 nvme_cmd_write_uncor = 0x04,
674 nvme_cmd_compare = 0x05,
675 nvme_cmd_write_zeroes = 0x08,
676 nvme_cmd_dsm = 0x09,
677 nvme_cmd_verify = 0x0c,
678 nvme_cmd_resv_register = 0x0d,
679 nvme_cmd_resv_report = 0x0e,
680 nvme_cmd_resv_acquire = 0x11,
681 nvme_cmd_resv_release = 0x15,
682 nvme_cmd_zone_mgmt_send = 0x79,
683 nvme_cmd_zone_mgmt_recv = 0x7a,
684 nvme_cmd_zone_append = 0x7d,
685 };
686
687 #define nvme_opcode_name(opcode) { opcode, #opcode }
688 #define show_nvm_opcode_name(val) \
689 __print_symbolic(val, \
690 nvme_opcode_name(nvme_cmd_flush), \
691 nvme_opcode_name(nvme_cmd_write), \
692 nvme_opcode_name(nvme_cmd_read), \
693 nvme_opcode_name(nvme_cmd_write_uncor), \
694 nvme_opcode_name(nvme_cmd_compare), \
695 nvme_opcode_name(nvme_cmd_write_zeroes), \
696 nvme_opcode_name(nvme_cmd_dsm), \
697 nvme_opcode_name(nvme_cmd_resv_register), \
698 nvme_opcode_name(nvme_cmd_resv_report), \
699 nvme_opcode_name(nvme_cmd_resv_acquire), \
700 nvme_opcode_name(nvme_cmd_resv_release))
701
702
703 /*
704 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
705 *
706 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
707 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
708 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
709 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
710 * request subtype
711 */
712 enum {
713 NVME_SGL_FMT_ADDRESS = 0x00,
714 NVME_SGL_FMT_OFFSET = 0x01,
715 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
716 NVME_SGL_FMT_INVALIDATE = 0x0f,
717 };
718
719 /*
720 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
721 *
722 * For struct nvme_sgl_desc:
723 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
724 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
725 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
726 *
727 * For struct nvme_keyed_sgl_desc:
728 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
729 *
730 * Transport-specific SGL types:
731 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
732 */
733 enum {
734 NVME_SGL_FMT_DATA_DESC = 0x00,
735 NVME_SGL_FMT_SEG_DESC = 0x02,
736 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
737 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
738 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
739 };
740
741 struct nvme_sgl_desc {
742 __le64 addr;
743 __le32 length;
744 __u8 rsvd[3];
745 __u8 type;
746 };
747
748 struct nvme_keyed_sgl_desc {
749 __le64 addr;
750 __u8 length[3];
751 __u8 key[4];
752 __u8 type;
753 };
754
755 union nvme_data_ptr {
756 struct {
757 __le64 prp1;
758 __le64 prp2;
759 };
760 struct nvme_sgl_desc sgl;
761 struct nvme_keyed_sgl_desc ksgl;
762 };
763
764 /*
765 * Lowest two bits of our flags field (FUSE field in the spec):
766 *
767 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
768 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
769 *
770 * Highest two bits in our flags field (PSDT field in the spec):
771 *
772 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
773 * If used, MPTR contains addr of single physical buffer (byte aligned).
774 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
775 * If used, MPTR contains an address of an SGL segment containing
776 * exactly 1 SGL descriptor (qword aligned).
777 */
778 enum {
779 NVME_CMD_FUSE_FIRST = (1 << 0),
780 NVME_CMD_FUSE_SECOND = (1 << 1),
781
782 NVME_CMD_SGL_METABUF = (1 << 6),
783 NVME_CMD_SGL_METASEG = (1 << 7),
784 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
785 };
786
787 struct nvme_common_command {
788 __u8 opcode;
789 __u8 flags;
790 __u16 command_id;
791 __le32 nsid;
792 __le32 cdw2[2];
793 __le64 metadata;
794 union nvme_data_ptr dptr;
795 __le32 cdw10;
796 __le32 cdw11;
797 __le32 cdw12;
798 __le32 cdw13;
799 __le32 cdw14;
800 __le32 cdw15;
801 };
802
803 struct nvme_rw_command {
804 __u8 opcode;
805 __u8 flags;
806 __u16 command_id;
807 __le32 nsid;
808 __u64 rsvd2;
809 __le64 metadata;
810 union nvme_data_ptr dptr;
811 __le64 slba;
812 __le16 length;
813 __le16 control;
814 __le32 dsmgmt;
815 __le32 reftag;
816 __le16 apptag;
817 __le16 appmask;
818 };
819
820 enum {
821 NVME_RW_LR = 1 << 15,
822 NVME_RW_FUA = 1 << 14,
823 NVME_RW_APPEND_PIREMAP = 1 << 9,
824 NVME_RW_DSM_FREQ_UNSPEC = 0,
825 NVME_RW_DSM_FREQ_TYPICAL = 1,
826 NVME_RW_DSM_FREQ_RARE = 2,
827 NVME_RW_DSM_FREQ_READS = 3,
828 NVME_RW_DSM_FREQ_WRITES = 4,
829 NVME_RW_DSM_FREQ_RW = 5,
830 NVME_RW_DSM_FREQ_ONCE = 6,
831 NVME_RW_DSM_FREQ_PREFETCH = 7,
832 NVME_RW_DSM_FREQ_TEMP = 8,
833 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
834 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
835 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
836 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
837 NVME_RW_DSM_SEQ_REQ = 1 << 6,
838 NVME_RW_DSM_COMPRESSED = 1 << 7,
839 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
840 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
841 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
842 NVME_RW_PRINFO_PRACT = 1 << 13,
843 NVME_RW_DTYPE_STREAMS = 1 << 4,
844 };
845
846 struct nvme_dsm_cmd {
847 __u8 opcode;
848 __u8 flags;
849 __u16 command_id;
850 __le32 nsid;
851 __u64 rsvd2[2];
852 union nvme_data_ptr dptr;
853 __le32 nr;
854 __le32 attributes;
855 __u32 rsvd12[4];
856 };
857
858 enum {
859 NVME_DSMGMT_IDR = 1 << 0,
860 NVME_DSMGMT_IDW = 1 << 1,
861 NVME_DSMGMT_AD = 1 << 2,
862 };
863
864 #define NVME_DSM_MAX_RANGES 256
865
866 struct nvme_dsm_range {
867 __le32 cattr;
868 __le32 nlb;
869 __le64 slba;
870 };
871
872 struct nvme_write_zeroes_cmd {
873 __u8 opcode;
874 __u8 flags;
875 __u16 command_id;
876 __le32 nsid;
877 __u64 rsvd2;
878 __le64 metadata;
879 union nvme_data_ptr dptr;
880 __le64 slba;
881 __le16 length;
882 __le16 control;
883 __le32 dsmgmt;
884 __le32 reftag;
885 __le16 apptag;
886 __le16 appmask;
887 };
888
889 enum nvme_zone_mgmt_action {
890 NVME_ZONE_CLOSE = 0x1,
891 NVME_ZONE_FINISH = 0x2,
892 NVME_ZONE_OPEN = 0x3,
893 NVME_ZONE_RESET = 0x4,
894 NVME_ZONE_OFFLINE = 0x5,
895 NVME_ZONE_SET_DESC_EXT = 0x10,
896 };
897
898 struct nvme_zone_mgmt_send_cmd {
899 __u8 opcode;
900 __u8 flags;
901 __u16 command_id;
902 __le32 nsid;
903 __le32 cdw2[2];
904 __le64 metadata;
905 union nvme_data_ptr dptr;
906 __le64 slba;
907 __le32 cdw12;
908 __u8 zsa;
909 __u8 select_all;
910 __u8 rsvd13[2];
911 __le32 cdw14[2];
912 };
913
914 struct nvme_zone_mgmt_recv_cmd {
915 __u8 opcode;
916 __u8 flags;
917 __u16 command_id;
918 __le32 nsid;
919 __le64 rsvd2[2];
920 union nvme_data_ptr dptr;
921 __le64 slba;
922 __le32 numd;
923 __u8 zra;
924 __u8 zrasf;
925 __u8 pr;
926 __u8 rsvd13;
927 __le32 cdw14[2];
928 };
929
930 enum {
931 NVME_ZRA_ZONE_REPORT = 0,
932 NVME_ZRASF_ZONE_REPORT_ALL = 0,
933 NVME_REPORT_ZONE_PARTIAL = 1,
934 };
935
936 /* Features */
937
938 enum {
939 NVME_TEMP_THRESH_MASK = 0xffff,
940 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
941 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
942 };
943
944 struct nvme_feat_auto_pst {
945 __le64 entries[32];
946 };
947
948 enum {
949 NVME_HOST_MEM_ENABLE = (1 << 0),
950 NVME_HOST_MEM_RETURN = (1 << 1),
951 };
952
953 struct nvme_feat_host_behavior {
954 __u8 acre;
955 __u8 resv1[511];
956 };
957
958 enum {
959 NVME_ENABLE_ACRE = 1,
960 };
961
962 /* Admin commands */
963
964 enum nvme_admin_opcode {
965 nvme_admin_delete_sq = 0x00,
966 nvme_admin_create_sq = 0x01,
967 nvme_admin_get_log_page = 0x02,
968 nvme_admin_delete_cq = 0x04,
969 nvme_admin_create_cq = 0x05,
970 nvme_admin_identify = 0x06,
971 nvme_admin_abort_cmd = 0x08,
972 nvme_admin_set_features = 0x09,
973 nvme_admin_get_features = 0x0a,
974 nvme_admin_async_event = 0x0c,
975 nvme_admin_ns_mgmt = 0x0d,
976 nvme_admin_activate_fw = 0x10,
977 nvme_admin_download_fw = 0x11,
978 nvme_admin_dev_self_test = 0x14,
979 nvme_admin_ns_attach = 0x15,
980 nvme_admin_keep_alive = 0x18,
981 nvme_admin_directive_send = 0x19,
982 nvme_admin_directive_recv = 0x1a,
983 nvme_admin_virtual_mgmt = 0x1c,
984 nvme_admin_nvme_mi_send = 0x1d,
985 nvme_admin_nvme_mi_recv = 0x1e,
986 nvme_admin_dbbuf = 0x7C,
987 nvme_admin_format_nvm = 0x80,
988 nvme_admin_security_send = 0x81,
989 nvme_admin_security_recv = 0x82,
990 nvme_admin_sanitize_nvm = 0x84,
991 nvme_admin_get_lba_status = 0x86,
992 nvme_admin_vendor_start = 0xC0,
993 };
994
995 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
996 #define show_admin_opcode_name(val) \
997 __print_symbolic(val, \
998 nvme_admin_opcode_name(nvme_admin_delete_sq), \
999 nvme_admin_opcode_name(nvme_admin_create_sq), \
1000 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1001 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1002 nvme_admin_opcode_name(nvme_admin_create_cq), \
1003 nvme_admin_opcode_name(nvme_admin_identify), \
1004 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1005 nvme_admin_opcode_name(nvme_admin_set_features), \
1006 nvme_admin_opcode_name(nvme_admin_get_features), \
1007 nvme_admin_opcode_name(nvme_admin_async_event), \
1008 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1009 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1010 nvme_admin_opcode_name(nvme_admin_download_fw), \
1011 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1012 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1013 nvme_admin_opcode_name(nvme_admin_directive_send), \
1014 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1015 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1016 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1017 nvme_admin_opcode_name(nvme_admin_security_send), \
1018 nvme_admin_opcode_name(nvme_admin_security_recv), \
1019 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1020 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1021
1022 enum {
1023 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1024 NVME_CQ_IRQ_ENABLED = (1 << 1),
1025 NVME_SQ_PRIO_URGENT = (0 << 1),
1026 NVME_SQ_PRIO_HIGH = (1 << 1),
1027 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1028 NVME_SQ_PRIO_LOW = (3 << 1),
1029 NVME_FEAT_ARBITRATION = 0x01,
1030 NVME_FEAT_POWER_MGMT = 0x02,
1031 NVME_FEAT_LBA_RANGE = 0x03,
1032 NVME_FEAT_TEMP_THRESH = 0x04,
1033 NVME_FEAT_ERR_RECOVERY = 0x05,
1034 NVME_FEAT_VOLATILE_WC = 0x06,
1035 NVME_FEAT_NUM_QUEUES = 0x07,
1036 NVME_FEAT_IRQ_COALESCE = 0x08,
1037 NVME_FEAT_IRQ_CONFIG = 0x09,
1038 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1039 NVME_FEAT_ASYNC_EVENT = 0x0b,
1040 NVME_FEAT_AUTO_PST = 0x0c,
1041 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1042 NVME_FEAT_TIMESTAMP = 0x0e,
1043 NVME_FEAT_KATO = 0x0f,
1044 NVME_FEAT_HCTM = 0x10,
1045 NVME_FEAT_NOPSC = 0x11,
1046 NVME_FEAT_RRL = 0x12,
1047 NVME_FEAT_PLM_CONFIG = 0x13,
1048 NVME_FEAT_PLM_WINDOW = 0x14,
1049 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1050 NVME_FEAT_SANITIZE = 0x17,
1051 NVME_FEAT_SW_PROGRESS = 0x80,
1052 NVME_FEAT_HOST_ID = 0x81,
1053 NVME_FEAT_RESV_MASK = 0x82,
1054 NVME_FEAT_RESV_PERSIST = 0x83,
1055 NVME_FEAT_WRITE_PROTECT = 0x84,
1056 NVME_FEAT_VENDOR_START = 0xC0,
1057 NVME_FEAT_VENDOR_END = 0xFF,
1058 NVME_LOG_ERROR = 0x01,
1059 NVME_LOG_SMART = 0x02,
1060 NVME_LOG_FW_SLOT = 0x03,
1061 NVME_LOG_CHANGED_NS = 0x04,
1062 NVME_LOG_CMD_EFFECTS = 0x05,
1063 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1064 NVME_LOG_TELEMETRY_HOST = 0x07,
1065 NVME_LOG_TELEMETRY_CTRL = 0x08,
1066 NVME_LOG_ENDURANCE_GROUP = 0x09,
1067 NVME_LOG_ANA = 0x0c,
1068 NVME_LOG_DISC = 0x70,
1069 NVME_LOG_RESERVATION = 0x80,
1070 NVME_FWACT_REPL = (0 << 3),
1071 NVME_FWACT_REPL_ACTV = (1 << 3),
1072 NVME_FWACT_ACTV = (2 << 3),
1073 };
1074
1075 /* NVMe Namespace Write Protect State */
1076 enum {
1077 NVME_NS_NO_WRITE_PROTECT = 0,
1078 NVME_NS_WRITE_PROTECT,
1079 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1080 NVME_NS_WRITE_PROTECT_PERMANENT,
1081 };
1082
1083 #define NVME_MAX_CHANGED_NAMESPACES 1024
1084
1085 struct nvme_identify {
1086 __u8 opcode;
1087 __u8 flags;
1088 __u16 command_id;
1089 __le32 nsid;
1090 __u64 rsvd2[2];
1091 union nvme_data_ptr dptr;
1092 __u8 cns;
1093 __u8 rsvd3;
1094 __le16 ctrlid;
1095 __u8 rsvd11[3];
1096 __u8 csi;
1097 __u32 rsvd12[4];
1098 };
1099
1100 #define NVME_IDENTIFY_DATA_SIZE 4096
1101
1102 struct nvme_features {
1103 __u8 opcode;
1104 __u8 flags;
1105 __u16 command_id;
1106 __le32 nsid;
1107 __u64 rsvd2[2];
1108 union nvme_data_ptr dptr;
1109 __le32 fid;
1110 __le32 dword11;
1111 __le32 dword12;
1112 __le32 dword13;
1113 __le32 dword14;
1114 __le32 dword15;
1115 };
1116
1117 struct nvme_host_mem_buf_desc {
1118 __le64 addr;
1119 __le32 size;
1120 __u32 rsvd;
1121 };
1122
1123 struct nvme_create_cq {
1124 __u8 opcode;
1125 __u8 flags;
1126 __u16 command_id;
1127 __u32 rsvd1[5];
1128 __le64 prp1;
1129 __u64 rsvd8;
1130 __le16 cqid;
1131 __le16 qsize;
1132 __le16 cq_flags;
1133 __le16 irq_vector;
1134 __u32 rsvd12[4];
1135 };
1136
1137 struct nvme_create_sq {
1138 __u8 opcode;
1139 __u8 flags;
1140 __u16 command_id;
1141 __u32 rsvd1[5];
1142 __le64 prp1;
1143 __u64 rsvd8;
1144 __le16 sqid;
1145 __le16 qsize;
1146 __le16 sq_flags;
1147 __le16 cqid;
1148 __u32 rsvd12[4];
1149 };
1150
1151 struct nvme_delete_queue {
1152 __u8 opcode;
1153 __u8 flags;
1154 __u16 command_id;
1155 __u32 rsvd1[9];
1156 __le16 qid;
1157 __u16 rsvd10;
1158 __u32 rsvd11[5];
1159 };
1160
1161 struct nvme_abort_cmd {
1162 __u8 opcode;
1163 __u8 flags;
1164 __u16 command_id;
1165 __u32 rsvd1[9];
1166 __le16 sqid;
1167 __u16 cid;
1168 __u32 rsvd11[5];
1169 };
1170
1171 struct nvme_download_firmware {
1172 __u8 opcode;
1173 __u8 flags;
1174 __u16 command_id;
1175 __u32 rsvd1[5];
1176 union nvme_data_ptr dptr;
1177 __le32 numd;
1178 __le32 offset;
1179 __u32 rsvd12[4];
1180 };
1181
1182 struct nvme_format_cmd {
1183 __u8 opcode;
1184 __u8 flags;
1185 __u16 command_id;
1186 __le32 nsid;
1187 __u64 rsvd2[4];
1188 __le32 cdw10;
1189 __u32 rsvd11[5];
1190 };
1191
1192 struct nvme_get_log_page_command {
1193 __u8 opcode;
1194 __u8 flags;
1195 __u16 command_id;
1196 __le32 nsid;
1197 __u64 rsvd2[2];
1198 union nvme_data_ptr dptr;
1199 __u8 lid;
1200 __u8 lsp; /* upper 4 bits reserved */
1201 __le16 numdl;
1202 __le16 numdu;
1203 __u16 rsvd11;
1204 union {
1205 struct {
1206 __le32 lpol;
1207 __le32 lpou;
1208 };
1209 __le64 lpo;
1210 };
1211 __u8 rsvd14[3];
1212 __u8 csi;
1213 __u32 rsvd15;
1214 };
1215
1216 struct nvme_directive_cmd {
1217 __u8 opcode;
1218 __u8 flags;
1219 __u16 command_id;
1220 __le32 nsid;
1221 __u64 rsvd2[2];
1222 union nvme_data_ptr dptr;
1223 __le32 numd;
1224 __u8 doper;
1225 __u8 dtype;
1226 __le16 dspec;
1227 __u8 endir;
1228 __u8 tdtype;
1229 __u16 rsvd15;
1230
1231 __u32 rsvd16[3];
1232 };
1233
1234 /*
1235 * Fabrics subcommands.
1236 */
1237 enum nvmf_fabrics_opcode {
1238 nvme_fabrics_command = 0x7f,
1239 };
1240
1241 enum nvmf_capsule_command {
1242 nvme_fabrics_type_property_set = 0x00,
1243 nvme_fabrics_type_connect = 0x01,
1244 nvme_fabrics_type_property_get = 0x04,
1245 };
1246
1247 #define nvme_fabrics_type_name(type) { type, #type }
1248 #define show_fabrics_type_name(type) \
1249 __print_symbolic(type, \
1250 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1251 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1252 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1253
1254 /*
1255 * If not fabrics command, fctype will be ignored.
1256 */
1257 #define show_opcode_name(qid, opcode, fctype) \
1258 ((opcode) == nvme_fabrics_command ? \
1259 show_fabrics_type_name(fctype) : \
1260 ((qid) ? \
1261 show_nvm_opcode_name(opcode) : \
1262 show_admin_opcode_name(opcode)))
1263
1264 struct nvmf_common_command {
1265 __u8 opcode;
1266 __u8 resv1;
1267 __u16 command_id;
1268 __u8 fctype;
1269 __u8 resv2[35];
1270 __u8 ts[24];
1271 };
1272
1273 /*
1274 * The legal cntlid range a NVMe Target will provide.
1275 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1276 * Devices based on earlier specs did not have the subsystem concept;
1277 * therefore, those devices had their cntlid value set to 0 as a result.
1278 */
1279 #define NVME_CNTLID_MIN 1
1280 #define NVME_CNTLID_MAX 0xffef
1281 #define NVME_CNTLID_DYNAMIC 0xffff
1282
1283 #define MAX_DISC_LOGS 255
1284
1285 /* Discovery log page entry */
1286 struct nvmf_disc_rsp_page_entry {
1287 __u8 trtype;
1288 __u8 adrfam;
1289 __u8 subtype;
1290 __u8 treq;
1291 __le16 portid;
1292 __le16 cntlid;
1293 __le16 asqsz;
1294 __u8 resv8[22];
1295 char trsvcid[NVMF_TRSVCID_SIZE];
1296 __u8 resv64[192];
1297 char subnqn[NVMF_NQN_FIELD_LEN];
1298 char traddr[NVMF_TRADDR_SIZE];
1299 union tsas {
1300 char common[NVMF_TSAS_SIZE];
1301 struct rdma {
1302 __u8 qptype;
1303 __u8 prtype;
1304 __u8 cms;
1305 __u8 resv3[5];
1306 __u16 pkey;
1307 __u8 resv10[246];
1308 } rdma;
1309 } tsas;
1310 };
1311
1312 /* Discovery log page header */
1313 struct nvmf_disc_rsp_page_hdr {
1314 __le64 genctr;
1315 __le64 numrec;
1316 __le16 recfmt;
1317 __u8 resv14[1006];
1318 struct nvmf_disc_rsp_page_entry entries[];
1319 };
1320
1321 enum {
1322 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1323 };
1324
1325 struct nvmf_connect_command {
1326 __u8 opcode;
1327 __u8 resv1;
1328 __u16 command_id;
1329 __u8 fctype;
1330 __u8 resv2[19];
1331 union nvme_data_ptr dptr;
1332 __le16 recfmt;
1333 __le16 qid;
1334 __le16 sqsize;
1335 __u8 cattr;
1336 __u8 resv3;
1337 __le32 kato;
1338 __u8 resv4[12];
1339 };
1340
1341 struct nvmf_connect_data {
1342 uuid_t hostid;
1343 __le16 cntlid;
1344 char resv4[238];
1345 char subsysnqn[NVMF_NQN_FIELD_LEN];
1346 char hostnqn[NVMF_NQN_FIELD_LEN];
1347 char resv5[256];
1348 };
1349
1350 struct nvmf_property_set_command {
1351 __u8 opcode;
1352 __u8 resv1;
1353 __u16 command_id;
1354 __u8 fctype;
1355 __u8 resv2[35];
1356 __u8 attrib;
1357 __u8 resv3[3];
1358 __le32 offset;
1359 __le64 value;
1360 __u8 resv4[8];
1361 };
1362
1363 struct nvmf_property_get_command {
1364 __u8 opcode;
1365 __u8 resv1;
1366 __u16 command_id;
1367 __u8 fctype;
1368 __u8 resv2[35];
1369 __u8 attrib;
1370 __u8 resv3[3];
1371 __le32 offset;
1372 __u8 resv4[16];
1373 };
1374
1375 struct nvme_dbbuf {
1376 __u8 opcode;
1377 __u8 flags;
1378 __u16 command_id;
1379 __u32 rsvd1[5];
1380 __le64 prp1;
1381 __le64 prp2;
1382 __u32 rsvd12[6];
1383 };
1384
1385 struct streams_directive_params {
1386 __le16 msl;
1387 __le16 nssa;
1388 __le16 nsso;
1389 __u8 rsvd[10];
1390 __le32 sws;
1391 __le16 sgs;
1392 __le16 nsa;
1393 __le16 nso;
1394 __u8 rsvd2[6];
1395 };
1396
1397 struct nvme_command {
1398 union {
1399 struct nvme_common_command common;
1400 struct nvme_rw_command rw;
1401 struct nvme_identify identify;
1402 struct nvme_features features;
1403 struct nvme_create_cq create_cq;
1404 struct nvme_create_sq create_sq;
1405 struct nvme_delete_queue delete_queue;
1406 struct nvme_download_firmware dlfw;
1407 struct nvme_format_cmd format;
1408 struct nvme_dsm_cmd dsm;
1409 struct nvme_write_zeroes_cmd write_zeroes;
1410 struct nvme_zone_mgmt_send_cmd zms;
1411 struct nvme_zone_mgmt_recv_cmd zmr;
1412 struct nvme_abort_cmd abort;
1413 struct nvme_get_log_page_command get_log_page;
1414 struct nvmf_common_command fabrics;
1415 struct nvmf_connect_command connect;
1416 struct nvmf_property_set_command prop_set;
1417 struct nvmf_property_get_command prop_get;
1418 struct nvme_dbbuf dbbuf;
1419 struct nvme_directive_cmd directive;
1420 };
1421 };
1422
nvme_is_fabrics(struct nvme_command * cmd)1423 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1424 {
1425 return cmd->common.opcode == nvme_fabrics_command;
1426 }
1427
1428 struct nvme_error_slot {
1429 __le64 error_count;
1430 __le16 sqid;
1431 __le16 cmdid;
1432 __le16 status_field;
1433 __le16 param_error_location;
1434 __le64 lba;
1435 __le32 nsid;
1436 __u8 vs;
1437 __u8 resv[3];
1438 __le64 cs;
1439 __u8 resv2[24];
1440 };
1441
nvme_is_write(struct nvme_command * cmd)1442 static inline bool nvme_is_write(struct nvme_command *cmd)
1443 {
1444 /*
1445 * What a mess...
1446 *
1447 * Why can't we simply have a Fabrics In and Fabrics out command?
1448 */
1449 if (unlikely(nvme_is_fabrics(cmd)))
1450 return cmd->fabrics.fctype & 1;
1451 return cmd->common.opcode & 1;
1452 }
1453
1454 enum {
1455 /*
1456 * Generic Command Status:
1457 */
1458 NVME_SC_SUCCESS = 0x0,
1459 NVME_SC_INVALID_OPCODE = 0x1,
1460 NVME_SC_INVALID_FIELD = 0x2,
1461 NVME_SC_CMDID_CONFLICT = 0x3,
1462 NVME_SC_DATA_XFER_ERROR = 0x4,
1463 NVME_SC_POWER_LOSS = 0x5,
1464 NVME_SC_INTERNAL = 0x6,
1465 NVME_SC_ABORT_REQ = 0x7,
1466 NVME_SC_ABORT_QUEUE = 0x8,
1467 NVME_SC_FUSED_FAIL = 0x9,
1468 NVME_SC_FUSED_MISSING = 0xa,
1469 NVME_SC_INVALID_NS = 0xb,
1470 NVME_SC_CMD_SEQ_ERROR = 0xc,
1471 NVME_SC_SGL_INVALID_LAST = 0xd,
1472 NVME_SC_SGL_INVALID_COUNT = 0xe,
1473 NVME_SC_SGL_INVALID_DATA = 0xf,
1474 NVME_SC_SGL_INVALID_METADATA = 0x10,
1475 NVME_SC_SGL_INVALID_TYPE = 0x11,
1476
1477 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1478 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1479
1480 NVME_SC_SANITIZE_FAILED = 0x1C,
1481 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1482
1483 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1484 NVME_SC_CMD_INTERRUPTED = 0x21,
1485
1486 NVME_SC_LBA_RANGE = 0x80,
1487 NVME_SC_CAP_EXCEEDED = 0x81,
1488 NVME_SC_NS_NOT_READY = 0x82,
1489 NVME_SC_RESERVATION_CONFLICT = 0x83,
1490
1491 /*
1492 * Command Specific Status:
1493 */
1494 NVME_SC_CQ_INVALID = 0x100,
1495 NVME_SC_QID_INVALID = 0x101,
1496 NVME_SC_QUEUE_SIZE = 0x102,
1497 NVME_SC_ABORT_LIMIT = 0x103,
1498 NVME_SC_ABORT_MISSING = 0x104,
1499 NVME_SC_ASYNC_LIMIT = 0x105,
1500 NVME_SC_FIRMWARE_SLOT = 0x106,
1501 NVME_SC_FIRMWARE_IMAGE = 0x107,
1502 NVME_SC_INVALID_VECTOR = 0x108,
1503 NVME_SC_INVALID_LOG_PAGE = 0x109,
1504 NVME_SC_INVALID_FORMAT = 0x10a,
1505 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1506 NVME_SC_INVALID_QUEUE = 0x10c,
1507 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1508 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1509 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1510 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1511 NVME_SC_FW_NEEDS_RESET = 0x111,
1512 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1513 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1514 NVME_SC_OVERLAPPING_RANGE = 0x114,
1515 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1516 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1517 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1518 NVME_SC_NS_IS_PRIVATE = 0x119,
1519 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1520 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1521 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1522 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1523 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1524
1525 /*
1526 * I/O Command Set Specific - NVM commands:
1527 */
1528 NVME_SC_BAD_ATTRIBUTES = 0x180,
1529 NVME_SC_INVALID_PI = 0x181,
1530 NVME_SC_READ_ONLY = 0x182,
1531 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1532
1533 /*
1534 * I/O Command Set Specific - Fabrics commands:
1535 */
1536 NVME_SC_CONNECT_FORMAT = 0x180,
1537 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1538 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1539 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1540 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1541
1542 NVME_SC_DISCOVERY_RESTART = 0x190,
1543 NVME_SC_AUTH_REQUIRED = 0x191,
1544
1545 /*
1546 * I/O Command Set Specific - Zoned commands:
1547 */
1548 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1549 NVME_SC_ZONE_FULL = 0x1b9,
1550 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1551 NVME_SC_ZONE_OFFLINE = 0x1bb,
1552 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1553 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1554 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1555 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1556
1557 /*
1558 * Media and Data Integrity Errors:
1559 */
1560 NVME_SC_WRITE_FAULT = 0x280,
1561 NVME_SC_READ_ERROR = 0x281,
1562 NVME_SC_GUARD_CHECK = 0x282,
1563 NVME_SC_APPTAG_CHECK = 0x283,
1564 NVME_SC_REFTAG_CHECK = 0x284,
1565 NVME_SC_COMPARE_FAILED = 0x285,
1566 NVME_SC_ACCESS_DENIED = 0x286,
1567 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1568
1569 /*
1570 * Path-related Errors:
1571 */
1572 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1573 NVME_SC_ANA_INACCESSIBLE = 0x302,
1574 NVME_SC_ANA_TRANSITION = 0x303,
1575 NVME_SC_HOST_PATH_ERROR = 0x370,
1576 NVME_SC_HOST_ABORTED_CMD = 0x371,
1577
1578 NVME_SC_CRD = 0x1800,
1579 NVME_SC_DNR = 0x4000,
1580 };
1581
1582 struct nvme_completion {
1583 /*
1584 * Used by Admin and Fabrics commands to return data:
1585 */
1586 union nvme_result {
1587 __le16 u16;
1588 __le32 u32;
1589 __le64 u64;
1590 } result;
1591 __le16 sq_head; /* how much of this queue may be reclaimed */
1592 __le16 sq_id; /* submission queue that generated this entry */
1593 __u16 command_id; /* of the command which completed */
1594 __le16 status; /* did the command fail, and if so, why? */
1595 };
1596
1597 #define NVME_VS(major, minor, tertiary) \
1598 (((major) << 16) | ((minor) << 8) | (tertiary))
1599
1600 #define NVME_MAJOR(ver) ((ver) >> 16)
1601 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1602 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1603
1604 #endif /* _LINUX_NVME_H */
1605