1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32
33 #ifndef __LOS_ARM_H__
34 #define __LOS_ARM_H__
35
36 #define CPSR_MODE_USR 0x10
37 #define CPSR_MODE_MASK 0x1f
38
OsArmReadSctlr(VOID)39 STATIC INLINE UINT32 OsArmReadSctlr(VOID)
40 {
41 UINT32 val;
42 __asm__ volatile("mrc p15, 0, %0, c1,c0,0" : "=r"(val));
43 return val;
44 }
45
OsArmWriteSctlr(UINT32 val)46 STATIC INLINE VOID OsArmWriteSctlr(UINT32 val)
47 {
48 __asm__ volatile("mcr p15, 0, %0, c1,c0,0" ::"r"(val));
49 __asm__ volatile("isb" ::: "memory");
50 }
51
OsArmReadActlr(VOID)52 STATIC INLINE UINT32 OsArmReadActlr(VOID)
53 {
54 UINT32 val;
55 __asm__ volatile("mrc p15, 0, %0, c1,c0,1" : "=r"(val));
56 return val;
57 }
58
OsArmWriteActlr(UINT32 val)59 STATIC INLINE VOID OsArmWriteActlr(UINT32 val)
60 {
61 __asm__ volatile("mcr p15, 0, %0, c1,c0,1" ::"r"(val));
62 __asm__ volatile("isb" ::: "memory");
63 }
64
OsArmReadCpacr(VOID)65 STATIC INLINE UINT32 OsArmReadCpacr(VOID)
66 {
67 UINT32 val;
68 __asm__ volatile("mrc p15, 0, %0, c1,c0,2" : "=r"(val));
69 return val;
70 }
71
OsArmWriteCpacr(UINT32 val)72 STATIC INLINE VOID OsArmWriteCpacr(UINT32 val)
73 {
74 __asm__ volatile("mcr p15, 0, %0, c1,c0,2" ::"r"(val));
75 __asm__ volatile("isb" ::: "memory");
76 }
77
OsArmReadTtbr(VOID)78 STATIC INLINE UINT32 OsArmReadTtbr(VOID)
79 {
80 UINT32 val;
81 __asm__ volatile("mrc p15, 0, %0, c2,c0,0" : "=r"(val));
82 return val;
83 }
84
OsArmWriteTtbr(UINT32 val)85 STATIC INLINE VOID OsArmWriteTtbr(UINT32 val)
86 {
87 __asm__ volatile("mcr p15, 0, %0, c2,c0,0" ::"r"(val));
88 __asm__ volatile("isb" ::: "memory");
89 }
90
OsArmReadTtbr0(VOID)91 STATIC INLINE UINT32 OsArmReadTtbr0(VOID)
92 {
93 UINT32 val;
94 __asm__ volatile("mrc p15, 0, %0, c2,c0,0" : "=r"(val));
95 return val;
96 }
97
OsArmWriteTtbr0(UINT32 val)98 STATIC INLINE VOID OsArmWriteTtbr0(UINT32 val)
99 {
100 __asm__ volatile("mcr p15, 0, %0, c2,c0,0" ::"r"(val));
101 __asm__ volatile("isb" ::: "memory");
102 }
103
OsArmReadTtbr1(VOID)104 STATIC INLINE UINT32 OsArmReadTtbr1(VOID)
105 {
106 UINT32 val;
107 __asm__ volatile("mrc p15, 0, %0, c2,c0,1" : "=r"(val));
108 return val;
109 }
110
OsArmWriteTtbr1(UINT32 val)111 STATIC INLINE VOID OsArmWriteTtbr1(UINT32 val)
112 {
113 __asm__ volatile("mcr p15, 0, %0, c2,c0,1" ::"r"(val));
114 __asm__ volatile("isb" ::: "memory");
115 }
116
OsArmReadTtbcr(VOID)117 STATIC INLINE UINT32 OsArmReadTtbcr(VOID)
118 {
119 UINT32 val;
120 __asm__ volatile("mrc p15, 0, %0, c2,c0,2" : "=r"(val));
121 return val;
122 }
123
OsArmWriteTtbcr(UINT32 val)124 STATIC INLINE VOID OsArmWriteTtbcr(UINT32 val)
125 {
126 __asm__ volatile("mcr p15, 0, %0, c2,c0,2" ::"r"(val));
127 __asm__ volatile("isb" ::: "memory");
128 }
129
OsArmReadDacr(VOID)130 STATIC INLINE UINT32 OsArmReadDacr(VOID)
131 {
132 UINT32 val;
133 __asm__ volatile("mrc p15, 0, %0, c3,c0,0" : "=r"(val));
134 return val;
135 }
136
OsArmWriteDacr(UINT32 val)137 STATIC INLINE VOID OsArmWriteDacr(UINT32 val)
138 {
139 __asm__ volatile("mcr p15, 0, %0, c3,c0,0" ::"r"(val));
140 __asm__ volatile("isb" ::: "memory");
141 }
142
OsArmReadDfsr(VOID)143 STATIC INLINE UINT32 OsArmReadDfsr(VOID)
144 {
145 UINT32 val;
146 __asm__ volatile("mrc p15, 0, %0, c5,c0,0" : "=r"(val));
147 return val;
148 }
149
OsArmWriteDfsr(UINT32 val)150 STATIC INLINE VOID OsArmWriteDfsr(UINT32 val)
151 {
152 __asm__ volatile("mcr p15, 0, %0, c5,c0,0" ::"r"(val));
153 __asm__ volatile("isb" ::: "memory");
154 }
155
OsArmReadIfsr(VOID)156 STATIC INLINE UINT32 OsArmReadIfsr(VOID)
157 {
158 UINT32 val;
159 __asm__ volatile("mrc p15, 0, %0, c5,c0,1" : "=r"(val));
160 return val;
161 }
162
OsArmWriteIfsr(UINT32 val)163 STATIC INLINE VOID OsArmWriteIfsr(UINT32 val)
164 {
165 __asm__ volatile("mcr p15, 0, %0, c5,c0,1" ::"r"(val));
166 __asm__ volatile("isb" ::: "memory");
167 }
168
OsArmReadDfar(VOID)169 STATIC INLINE UINT32 OsArmReadDfar(VOID)
170 {
171 UINT32 val;
172 __asm__ volatile("mrc p15, 0, %0, c6,c0,0" : "=r"(val));
173 return val;
174 }
175
OsArmWriteDfar(UINT32 val)176 STATIC INLINE VOID OsArmWriteDfar(UINT32 val)
177 {
178 __asm__ volatile("mcr p15, 0, %0, c6,c0,0" ::"r"(val));
179 __asm__ volatile("isb" ::: "memory");
180 }
181
OsArmReadWfar(VOID)182 STATIC INLINE UINT32 OsArmReadWfar(VOID)
183 {
184 UINT32 val;
185 __asm__ volatile("mrc p15, 0, %0, c6,c0,1" : "=r"(val));
186 return val;
187 }
188
OsArmWriteWfar(UINT32 val)189 STATIC INLINE VOID OsArmWriteWfar(UINT32 val)
190 {
191 __asm__ volatile("mcr p15, 0, %0, c6,c0,1" ::"r"(val));
192 __asm__ volatile("isb" ::: "memory");
193 }
194
OsArmReadIfar(VOID)195 STATIC INLINE UINT32 OsArmReadIfar(VOID)
196 {
197 UINT32 val;
198 __asm__ volatile("mrc p15, 0, %0, c6,c0,2" : "=r"(val));
199 return val;
200 }
201
OsArmWriteIfar(UINT32 val)202 STATIC INLINE VOID OsArmWriteIfar(UINT32 val)
203 {
204 __asm__ volatile("mcr p15, 0, %0, c6,c0,2" ::"r"(val));
205 __asm__ volatile("isb" ::: "memory");
206 }
207
OsArmReadFcseidr(VOID)208 STATIC INLINE UINT32 OsArmReadFcseidr(VOID)
209 {
210 UINT32 val;
211 __asm__ volatile("mrc p15, 0, %0, c13,c0,0" : "=r"(val));
212 return val;
213 }
214
OsArmWriteFcseidr(UINT32 val)215 STATIC INLINE VOID OsArmWriteFcseidr(UINT32 val)
216 {
217 __asm__ volatile("mcr p15, 0, %0, c13,c0,0" ::"r"(val));
218 __asm__ volatile("isb" ::: "memory");
219 }
220
OsArmReadContextidr(VOID)221 STATIC INLINE UINT32 OsArmReadContextidr(VOID)
222 {
223 UINT32 val;
224 __asm__ volatile("mrc p15, 0, %0, c13,c0,1" : "=r"(val));
225 return val;
226 }
227
OsArmWriteContextidr(UINT32 val)228 STATIC INLINE VOID OsArmWriteContextidr(UINT32 val)
229 {
230 __asm__ volatile("mcr p15, 0, %0, c13,c0,1" ::"r"(val));
231 __asm__ volatile("isb" ::: "memory");
232 }
233
OsArmReadTpidrurw(VOID)234 STATIC INLINE UINT32 OsArmReadTpidrurw(VOID)
235 {
236 UINT32 val;
237 __asm__ volatile("mrc p15, 0, %0, c13,c0,2" : "=r"(val));
238 return val;
239 }
240
OsArmWriteTpidrurw(UINT32 val)241 STATIC INLINE VOID OsArmWriteTpidrurw(UINT32 val)
242 {
243 __asm__ volatile("mcr p15, 0, %0, c13,c0,2" ::"r"(val));
244 __asm__ volatile("isb" ::: "memory");
245 }
246
OsArmReadTpidruro(VOID)247 STATIC INLINE UINT32 OsArmReadTpidruro(VOID)
248 {
249 UINT32 val;
250 __asm__ volatile("mrc p15, 0, %0, c13,c0,3" : "=r"(val));
251 return val;
252 }
253
OsArmWriteTpidruro(UINT32 val)254 STATIC INLINE VOID OsArmWriteTpidruro(UINT32 val)
255 {
256 __asm__ volatile("mcr p15, 0, %0, c13,c0,3" ::"r"(val));
257 __asm__ volatile("isb" ::: "memory");
258 }
259
OsArmReadTpidrprw(VOID)260 STATIC INLINE UINT32 OsArmReadTpidrprw(VOID)
261 {
262 UINT32 val;
263 __asm__ volatile("mrc p15, 0, %0, c13,c0,4" : "=r"(val));
264 return val;
265 }
266
OsArmWriteTpidrprw(UINT32 val)267 STATIC INLINE VOID OsArmWriteTpidrprw(UINT32 val)
268 {
269 __asm__ volatile("mcr p15, 0, %0, c13,c0,4" ::"r"(val));
270 __asm__ volatile("isb" ::: "memory");
271 }
272
OsArmReadMidr(VOID)273 STATIC INLINE UINT32 OsArmReadMidr(VOID)
274 {
275 UINT32 val;
276 __asm__ volatile("mrc p15, 0, %0, c0,c0,0" : "=r"(val));
277 return val;
278 }
279
OsArmWriteMidr(UINT32 val)280 STATIC INLINE VOID OsArmWriteMidr(UINT32 val)
281 {
282 __asm__ volatile("mcr p15, 0, %0, c0,c0,0" ::"r"(val));
283 __asm__ volatile("isb" ::: "memory");
284 }
285
OsArmReadMpidr(VOID)286 STATIC INLINE UINT32 OsArmReadMpidr(VOID)
287 {
288 UINT32 val;
289 __asm__ volatile("mrc p15, 0, %0, c0,c0,5" : "=r"(val));
290 return val;
291 }
292
OsArmWriteMpidr(UINT32 val)293 STATIC INLINE VOID OsArmWriteMpidr(UINT32 val)
294 {
295 __asm__ volatile("mcr p15, 0, %0, c0,c0,5" ::"r"(val));
296 __asm__ volatile("isb" ::: "memory");
297 }
298
OsArmReadVbar(VOID)299 STATIC INLINE UINT32 OsArmReadVbar(VOID)
300 {
301 UINT32 val;
302 __asm__ volatile("mrc p15, 0, %0, c12,c0,0" : "=r"(val));
303 return val;
304 }
305
OsArmWriteVbar(UINT32 val)306 STATIC INLINE VOID OsArmWriteVbar(UINT32 val)
307 {
308 __asm__ volatile("mcr p15, 0, %0, c12,c0,0" ::"r"(val));
309 __asm__ volatile("isb" ::: "memory");
310 }
311
OsArmReadCbar(VOID)312 STATIC INLINE UINT32 OsArmReadCbar(VOID)
313 {
314 UINT32 val;
315 __asm__ volatile("mrc p15, 4, %0, c15,c0,0" : "=r"(val));
316 return val;
317 }
318
OsArmWriteCbar(UINT32 val)319 STATIC INLINE VOID OsArmWriteCbar(UINT32 val)
320 {
321 __asm__ volatile("mcr p15, 4, %0, c15,c0,0" ::"r"(val));
322 __asm__ volatile("isb" ::: "memory");
323 }
324
OsArmReadAts1cpr(VOID)325 STATIC INLINE UINT32 OsArmReadAts1cpr(VOID)
326 {
327 UINT32 val;
328 __asm__ volatile("mrc p15, 0, %0, c7,c8,0" : "=r"(val));
329 return val;
330 }
331
OsArmWriteAts1cpr(UINT32 val)332 STATIC INLINE VOID OsArmWriteAts1cpr(UINT32 val)
333 {
334 __asm__ volatile("mcr p15, 0, %0, c7,c8,0" ::"r"(val));
335 __asm__ volatile("isb" ::: "memory");
336 }
337
OsArmReadAts1cpw(VOID)338 STATIC INLINE UINT32 OsArmReadAts1cpw(VOID)
339 {
340 UINT32 val;
341 __asm__ volatile("mrc p15, 0, %0, c7,c8,1" : "=r"(val));
342 return val;
343 }
344
OsArmWriteAts1cpw(UINT32 val)345 STATIC INLINE VOID OsArmWriteAts1cpw(UINT32 val)
346 {
347 __asm__ volatile("mcr p15, 0, %0, c7,c8,1" ::"r"(val));
348 __asm__ volatile("isb" ::: "memory");
349 }
350
OsArmReadAts1cur(VOID)351 STATIC INLINE UINT32 OsArmReadAts1cur(VOID)
352 {
353 UINT32 val;
354 __asm__ volatile("mrc p15, 0, %0, c7,c8,2" : "=r"(val));
355 return val;
356 }
357
OsArmWriteAts1cur(UINT32 val)358 STATIC INLINE VOID OsArmWriteAts1cur(UINT32 val)
359 {
360 __asm__ volatile("mcr p15, 0, %0, c7,c8,2" ::"r"(val));
361 __asm__ volatile("isb" ::: "memory");
362 }
363
OsArmReadAts1cuw(VOID)364 STATIC INLINE UINT32 OsArmReadAts1cuw(VOID)
365 {
366 UINT32 val;
367 __asm__ volatile("mrc p15, 0, %0, c7,c8,3" : "=r"(val));
368 return val;
369 }
370
OsArmWriteAts1cuw(UINT32 val)371 STATIC INLINE VOID OsArmWriteAts1cuw(UINT32 val)
372 {
373 __asm__ volatile("mcr p15, 0, %0, c7,c8,3" ::"r"(val));
374 __asm__ volatile("isb" ::: "memory");
375 }
376
OsArmReadAts12nsopr(VOID)377 STATIC INLINE UINT32 OsArmReadAts12nsopr(VOID)
378 {
379 UINT32 val;
380 __asm__ volatile("mrc p15, 0, %0, c7,c8,4" : "=r"(val));
381 return val;
382 }
383
OsArmWriteAts12nsopr(UINT32 val)384 STATIC INLINE VOID OsArmWriteAts12nsopr(UINT32 val)
385 {
386 __asm__ volatile("mcr p15, 0, %0, c7,c8,4" ::"r"(val));
387 __asm__ volatile("isb" ::: "memory");
388 }
389
OsArmReadAts12nsopw(VOID)390 STATIC INLINE UINT32 OsArmReadAts12nsopw(VOID)
391 {
392 UINT32 val;
393 __asm__ volatile("mrc p15, 0, %0, c7,c8,5" : "=r"(val));
394 return val;
395 }
396
OsArmWriteAts12nsopw(UINT32 val)397 STATIC INLINE VOID OsArmWriteAts12nsopw(UINT32 val)
398 {
399 __asm__ volatile("mcr p15, 0, %0, c7,c8,5" ::"r"(val));
400 __asm__ volatile("isb" ::: "memory");
401 }
402
OsArmReadAts12nsour(VOID)403 STATIC INLINE UINT32 OsArmReadAts12nsour(VOID)
404 {
405 UINT32 val;
406 __asm__ volatile("mrc p15, 0, %0, c7,c8,6" : "=r"(val));
407 return val;
408 }
409
OsArmWriteAts12nsour(UINT32 val)410 STATIC INLINE VOID OsArmWriteAts12nsour(UINT32 val)
411 {
412 __asm__ volatile("mcr p15, 0, %0, c7,c8,6" ::"r"(val));
413 __asm__ volatile("isb" ::: "memory");
414 }
415
OsArmReadAts12nsouw(VOID)416 STATIC INLINE UINT32 OsArmReadAts12nsouw(VOID)
417 {
418 UINT32 val;
419 __asm__ volatile("mrc p15, 0, %0, c7,c8,7" : "=r"(val));
420 return val;
421 }
422
OsArmWriteAts12nsouw(UINT32 val)423 STATIC INLINE VOID OsArmWriteAts12nsouw(UINT32 val)
424 {
425 __asm__ volatile("mcr p15, 0, %0, c7,c8,7" ::"r"(val));
426 __asm__ volatile("isb" ::: "memory");
427 }
428
OsArmReadPar(VOID)429 STATIC INLINE UINT32 OsArmReadPar(VOID)
430 {
431 UINT32 val;
432 __asm__ volatile("mrc p15, 0, %0, c7,c4,0" : "=r"(val));
433 return val;
434 }
435
OsArmWritePar(UINT32 val)436 STATIC INLINE VOID OsArmWritePar(UINT32 val)
437 {
438 __asm__ volatile("mcr p15, 0, %0, c7,c4,0" ::"r"(val));
439 __asm__ volatile("isb" ::: "memory");
440 }
441
OsArmReadBpiall(VOID)442 STATIC INLINE UINT32 OsArmReadBpiall(VOID)
443 {
444 UINT32 val;
445 __asm__ volatile("mrc p15, 0, %0, c7,c5,6" : "=r"(val));
446 return val;
447 }
448
OsArmWriteBpiall(UINT32 val)449 STATIC INLINE VOID OsArmWriteBpiall(UINT32 val)
450 {
451 __asm__ volatile("mcr p15, 0, %0, c7,c5,6" ::"r"(val));
452 __asm__ volatile("isb" ::: "memory");
453 }
454
OsArmReadBpimva(VOID)455 STATIC INLINE UINT32 OsArmReadBpimva(VOID)
456 {
457 UINT32 val;
458 __asm__ volatile("mrc p15, 0, %0, c7,c5,7" : "=r"(val));
459 return val;
460 }
461
OsArmWriteBpimva(UINT32 val)462 STATIC INLINE VOID OsArmWriteBpimva(UINT32 val)
463 {
464 __asm__ volatile("mcr p15, 0, %0, c7,c5,7" ::"r"(val));
465 __asm__ volatile("isb" ::: "memory");
466 }
467
OsArmReadBpiallis(VOID)468 STATIC INLINE UINT32 OsArmReadBpiallis(VOID)
469 {
470 UINT32 val;
471 __asm__ volatile("mrc p15, 0, %0, c7,c1,6" : "=r"(val));
472 return val;
473 }
474
OsArmWriteBpiallis(UINT32 val)475 STATIC INLINE VOID OsArmWriteBpiallis(UINT32 val)
476 {
477 __asm__ volatile("mcr p15, 0, %0, c7,c1,6" ::"r"(val));
478 __asm__ volatile("isb" ::: "memory");
479 }
480
OsArmReadTlbiallis(VOID)481 STATIC INLINE UINT32 OsArmReadTlbiallis(VOID)
482 {
483 UINT32 val;
484 __asm__ volatile("mrc p15, 0, %0, c8,c3,0" : "=r"(val));
485 return val;
486 }
487
OsArmWriteTlbiallis(UINT32 val)488 STATIC INLINE VOID OsArmWriteTlbiallis(UINT32 val)
489 {
490 __asm__ volatile("mcr p15, 0, %0, c8,c3,0" ::"r"(val));
491 __asm__ volatile("isb" ::: "memory");
492 }
493
OsArmReadTlbimvais(VOID)494 STATIC INLINE UINT32 OsArmReadTlbimvais(VOID)
495 {
496 UINT32 val;
497 __asm__ volatile("mrc p15, 0, %0, c8,c3,1" : "=r"(val));
498 return val;
499 }
500
OsArmWriteTlbimvais(UINT32 val)501 STATIC INLINE VOID OsArmWriteTlbimvais(UINT32 val)
502 {
503 __asm__ volatile("mcr p15, 0, %0, c8,c3,1" ::"r"(val));
504 __asm__ volatile("isb" ::: "memory");
505 }
506
OsArmReadTlbiasidis(VOID)507 STATIC INLINE UINT32 OsArmReadTlbiasidis(VOID)
508 {
509 UINT32 val;
510 __asm__ volatile("mrc p15, 0, %0, c8,c3,2" : "=r"(val));
511 return val;
512 }
513
OsArmWriteTlbiasidis(UINT32 val)514 STATIC INLINE VOID OsArmWriteTlbiasidis(UINT32 val)
515 {
516 __asm__ volatile("mcr p15, 0, %0, c8,c3,2" ::"r"(val));
517 __asm__ volatile("isb" ::: "memory");
518 }
519
OsArmReadTlbimvaais(VOID)520 STATIC INLINE UINT32 OsArmReadTlbimvaais(VOID)
521 {
522 UINT32 val;
523 __asm__ volatile("mrc p15, 0, %0, c8,c3,3" : "=r"(val));
524 return val;
525 }
526
OsArmWriteTlbimvaais(UINT32 val)527 STATIC INLINE VOID OsArmWriteTlbimvaais(UINT32 val)
528 {
529 __asm__ volatile("mcr p15, 0, %0, c8,c3,3" ::"r"(val));
530 __asm__ volatile("isb" ::: "memory");
531 }
532
OsArmReadItlbiall(VOID)533 STATIC INLINE UINT32 OsArmReadItlbiall(VOID)
534 {
535 UINT32 val;
536 __asm__ volatile("mrc p15, 0, %0, c8,c5,0" : "=r"(val));
537 return val;
538 }
539
OsArmWriteItlbiall(UINT32 val)540 STATIC INLINE VOID OsArmWriteItlbiall(UINT32 val)
541 {
542 __asm__ volatile("mcr p15, 0, %0, c8,c5,0" ::"r"(val));
543 __asm__ volatile("isb" ::: "memory");
544 }
545
OsArmReadItlbimva(VOID)546 STATIC INLINE UINT32 OsArmReadItlbimva(VOID)
547 {
548 UINT32 val;
549 __asm__ volatile("mrc p15, 0, %0, c8,c5,1" : "=r"(val));
550 return val;
551 }
552
OsArmWriteItlbimva(UINT32 val)553 STATIC INLINE VOID OsArmWriteItlbimva(UINT32 val)
554 {
555 __asm__ volatile("mcr p15, 0, %0, c8,c5,1" ::"r"(val));
556 __asm__ volatile("isb" ::: "memory");
557 }
558
OsArmReadItlbiasid(VOID)559 STATIC INLINE UINT32 OsArmReadItlbiasid(VOID)
560 {
561 UINT32 val;
562 __asm__ volatile("mrc p15, 0, %0, c8,c5,2" : "=r"(val));
563 return val;
564 }
565
OsArmWriteItlbiasid(UINT32 val)566 STATIC INLINE VOID OsArmWriteItlbiasid(UINT32 val)
567 {
568 __asm__ volatile("mcr p15, 0, %0, c8,c5,2" ::"r"(val));
569 __asm__ volatile("isb" ::: "memory");
570 }
571
OsArmReadDtlbiall(VOID)572 STATIC INLINE UINT32 OsArmReadDtlbiall(VOID)
573 {
574 UINT32 val;
575 __asm__ volatile("mrc p15, 0, %0, c8,c6,0" : "=r"(val));
576 return val;
577 }
578
OsArmWriteDtlbiall(UINT32 val)579 STATIC INLINE VOID OsArmWriteDtlbiall(UINT32 val)
580 {
581 __asm__ volatile("mcr p15, 0, %0, c8,c6,0" ::"r"(val));
582 __asm__ volatile("isb" ::: "memory");
583 }
584
OsArmReadDtlbimva(VOID)585 STATIC INLINE UINT32 OsArmReadDtlbimva(VOID)
586 {
587 UINT32 val;
588 __asm__ volatile("mrc p15, 0, %0, c8,c6,1" : "=r"(val));
589 return val;
590 }
591
OsArmWriteDtlbimva(UINT32 val)592 STATIC INLINE VOID OsArmWriteDtlbimva(UINT32 val)
593 {
594 __asm__ volatile("mcr p15, 0, %0, c8,c6,1" ::"r"(val));
595 __asm__ volatile("isb" ::: "memory");
596 }
597
OsArmReadDtlbiasid(VOID)598 STATIC INLINE UINT32 OsArmReadDtlbiasid(VOID)
599 {
600 UINT32 val;
601 __asm__ volatile("mrc p15, 0, %0, c8,c6,2" : "=r"(val));
602 return val;
603 }
604
OsArmWriteDtlbiasid(UINT32 val)605 STATIC INLINE VOID OsArmWriteDtlbiasid(UINT32 val)
606 {
607 __asm__ volatile("mcr p15, 0, %0, c8,c6,2" ::"r"(val));
608 __asm__ volatile("isb" ::: "memory");
609 }
610
OsArmReadTlbiall(VOID)611 STATIC INLINE UINT32 OsArmReadTlbiall(VOID)
612 {
613 UINT32 val;
614 __asm__ volatile("mrc p15, 0, %0, c8,c7,0" : "=r"(val));
615 return val;
616 }
617
OsArmWriteTlbiall(UINT32 val)618 STATIC INLINE VOID OsArmWriteTlbiall(UINT32 val)
619 {
620 __asm__ volatile("mcr p15, 0, %0, c8,c7,0" ::"r"(val));
621 __asm__ volatile("isb" ::: "memory");
622 }
623
OsArmReadTlbimva(VOID)624 STATIC INLINE UINT32 OsArmReadTlbimva(VOID)
625 {
626 UINT32 val;
627 __asm__ volatile("mrc p15, 0, %0, c8,c7,1" : "=r"(val));
628 return val;
629 }
630
OsArmWriteTlbimva(UINT32 val)631 STATIC INLINE VOID OsArmWriteTlbimva(UINT32 val)
632 {
633 __asm__ volatile("mcr p15, 0, %0, c8,c7,1" ::"r"(val));
634 __asm__ volatile("isb" ::: "memory");
635 }
636
OsArmReadTlbiasid(VOID)637 STATIC INLINE UINT32 OsArmReadTlbiasid(VOID)
638 {
639 UINT32 val;
640 __asm__ volatile("mrc p15, 0, %0, c8,c7,2" : "=r"(val));
641 return val;
642 }
643
OsArmWriteTlbiasid(UINT32 val)644 STATIC INLINE VOID OsArmWriteTlbiasid(UINT32 val)
645 {
646 __asm__ volatile("mcr p15, 0, %0, c8,c7,2" ::"r"(val));
647 __asm__ volatile("isb" ::: "memory");
648 }
649
OsArmReadTlbimvaa(VOID)650 STATIC INLINE UINT32 OsArmReadTlbimvaa(VOID)
651 {
652 UINT32 val;
653 __asm__ volatile("mrc p15, 0, %0, c8,c7,3" : "=r"(val));
654 return val;
655 }
656
OsArmWriteTlbimvaa(UINT32 val)657 STATIC INLINE VOID OsArmWriteTlbimvaa(UINT32 val)
658 {
659 __asm__ volatile("mcr p15, 0, %0, c8,c7,3" ::"r"(val));
660 __asm__ volatile("isb" ::: "memory");
661 }
662
OsArmReadL2ctlr(VOID)663 STATIC INLINE UINT32 OsArmReadL2ctlr(VOID)
664 {
665 UINT32 val;
666 __asm__ volatile("mrc p15, 1, %0, c9,c0,2" : "=r"(val));
667 return val;
668 }
669
OsArmWriteL2ctlr(UINT32 val)670 STATIC INLINE VOID OsArmWriteL2ctlr(UINT32 val)
671 {
672 __asm__ volatile("mcr p15, 1, %0, c9,c0,2" ::"r"(val));
673 __asm__ volatile("isb" ::: "memory");
674 }
675
OsArmReadL2ectlr(VOID)676 STATIC INLINE UINT32 OsArmReadL2ectlr(VOID)
677 {
678 UINT32 val;
679 __asm__ volatile("mrc p15, 1, %0, c9,c0,3" : "=r"(val));
680 return val;
681 }
682
OsArmWriteL2ectlr(UINT32 val)683 STATIC INLINE VOID OsArmWriteL2ectlr(UINT32 val)
684 {
685 __asm__ volatile("mcr p15, 1, %0, c9,c0,3" ::"r"(val));
686 __asm__ volatile("isb" ::: "memory");
687 }
688
OsArmReadDbddidr(VOID)689 STATIC INLINE UINT32 OsArmReadDbddidr(VOID)
690 {
691 UINT32 val;
692 __asm__ volatile("mrc p14, 0, %0, c0,c0,0" : "=r"(val));
693 return val;
694 }
695
OsArmWriteDbddidr(UINT32 val)696 STATIC INLINE VOID OsArmWriteDbddidr(UINT32 val)
697 {
698 __asm__ volatile("mcr p14, 0, %0, c0,c0,0" ::"r"(val));
699 __asm__ volatile("isb" ::: "memory");
700 }
701
OsArmReadDbgdrar(VOID)702 STATIC INLINE UINT32 OsArmReadDbgdrar(VOID)
703 {
704 UINT32 val;
705 __asm__ volatile("mrc p14, 0, %0, c1,c0,0" : "=r"(val));
706 return val;
707 }
708
OsArmWriteDbgdrar(UINT32 val)709 STATIC INLINE VOID OsArmWriteDbgdrar(UINT32 val)
710 {
711 __asm__ volatile("mcr p14, 0, %0, c1,c0,0" ::"r"(val));
712 __asm__ volatile("isb" ::: "memory");
713 }
714
OsArmReadDbgdsar(VOID)715 STATIC INLINE UINT32 OsArmReadDbgdsar(VOID)
716 {
717 UINT32 val;
718 __asm__ volatile("mrc p14, 0, %0, c2,c0,0" : "=r"(val));
719 return val;
720 }
721
OsArmWriteDbgdsar(UINT32 val)722 STATIC INLINE VOID OsArmWriteDbgdsar(UINT32 val)
723 {
724 __asm__ volatile("mcr p14, 0, %0, c2,c0,0" ::"r"(val));
725 __asm__ volatile("isb" ::: "memory");
726 }
727
OsArmReadDbgdscr(VOID)728 STATIC INLINE UINT32 OsArmReadDbgdscr(VOID)
729 {
730 UINT32 val;
731 __asm__ volatile("mrc p14, 0, %0, c0,c1,0" : "=r"(val));
732 return val;
733 }
734
OsArmWriteDbgdscr(UINT32 val)735 STATIC INLINE VOID OsArmWriteDbgdscr(UINT32 val)
736 {
737 __asm__ volatile("mcr p14, 0, %0, c0,c1,0" ::"r"(val));
738 __asm__ volatile("isb" ::: "memory");
739 }
740
OsArmReadDbgdtrtxint(VOID)741 STATIC INLINE UINT32 OsArmReadDbgdtrtxint(VOID)
742 {
743 UINT32 val;
744 __asm__ volatile("mrc p14, 0, %0, c0,c5,0" : "=r"(val));
745 return val;
746 }
747
OsArmWriteDbgdtrtxint(UINT32 val)748 STATIC INLINE VOID OsArmWriteDbgdtrtxint(UINT32 val)
749 {
750 __asm__ volatile("mcr p14, 0, %0, c0,c5,0" ::"r"(val));
751 __asm__ volatile("isb" ::: "memory");
752 }
753
OsArmReadDbgdtrrxint(VOID)754 STATIC INLINE UINT32 OsArmReadDbgdtrrxint(VOID)
755 {
756 UINT32 val;
757 __asm__ volatile("mrc p14, 0, %0, c0,c5,0" : "=r"(val));
758 return val;
759 }
760
OsArmWriteDbgdtrrxint(UINT32 val)761 STATIC INLINE VOID OsArmWriteDbgdtrrxint(UINT32 val)
762 {
763 __asm__ volatile("mcr p14, 0, %0, c0,c5,0" ::"r"(val));
764 __asm__ volatile("isb" ::: "memory");
765 }
766
OsArmReadDbgwfar(VOID)767 STATIC INLINE UINT32 OsArmReadDbgwfar(VOID)
768 {
769 UINT32 val;
770 __asm__ volatile("mrc p14, 0, %0, c0,c6,0" : "=r"(val));
771 return val;
772 }
773
OsArmWriteDbgwfar(UINT32 val)774 STATIC INLINE VOID OsArmWriteDbgwfar(UINT32 val)
775 {
776 __asm__ volatile("mcr p14, 0, %0, c0,c6,0" ::"r"(val));
777 __asm__ volatile("isb" ::: "memory");
778 }
779
OsArmReadDbgvcr(VOID)780 STATIC INLINE UINT32 OsArmReadDbgvcr(VOID)
781 {
782 UINT32 val;
783 __asm__ volatile("mrc p14, 0, %0, c0,c7,0" : "=r"(val));
784 return val;
785 }
786
OsArmWriteDbgvcr(UINT32 val)787 STATIC INLINE VOID OsArmWriteDbgvcr(UINT32 val)
788 {
789 __asm__ volatile("mcr p14, 0, %0, c0,c7,0" ::"r"(val));
790 __asm__ volatile("isb" ::: "memory");
791 }
792
OsArmReadDbgecr(VOID)793 STATIC INLINE UINT32 OsArmReadDbgecr(VOID)
794 {
795 UINT32 val;
796 __asm__ volatile("mrc p14, 0, %0, c0,c9,0" : "=r"(val));
797 return val;
798 }
799
OsArmWriteDbgecr(UINT32 val)800 STATIC INLINE VOID OsArmWriteDbgecr(UINT32 val)
801 {
802 __asm__ volatile("mcr p14, 0, %0, c0,c9,0" ::"r"(val));
803 __asm__ volatile("isb" ::: "memory");
804 }
805
OsArmReadDbgdsccr(VOID)806 STATIC INLINE UINT32 OsArmReadDbgdsccr(VOID)
807 {
808 UINT32 val;
809 __asm__ volatile("mrc p14, 0, %0, c0,c10,0" : "=r"(val));
810 return val;
811 }
812
OsArmWriteDbgdsccr(UINT32 val)813 STATIC INLINE VOID OsArmWriteDbgdsccr(UINT32 val)
814 {
815 __asm__ volatile("mcr p14, 0, %0, c0,c10,0" ::"r"(val));
816 __asm__ volatile("isb" ::: "memory");
817 }
818
OsArmReadDbgdsmcr(VOID)819 STATIC INLINE UINT32 OsArmReadDbgdsmcr(VOID)
820 {
821 UINT32 val;
822 __asm__ volatile("mrc p14, 0, %0, c0,c11,0" : "=r"(val));
823 return val;
824 }
825
OsArmWriteDbgdsmcr(UINT32 val)826 STATIC INLINE VOID OsArmWriteDbgdsmcr(UINT32 val)
827 {
828 __asm__ volatile("mcr p14, 0, %0, c0,c11,0" ::"r"(val));
829 __asm__ volatile("isb" ::: "memory");
830 }
831
OsArmReadDbgdtrrxext(VOID)832 STATIC INLINE UINT32 OsArmReadDbgdtrrxext(VOID)
833 {
834 UINT32 val;
835 __asm__ volatile("mrc p14, 0, %0, c0,c0,2" : "=r"(val));
836 return val;
837 }
838
OsArmWriteDbgdtrrxext(UINT32 val)839 STATIC INLINE VOID OsArmWriteDbgdtrrxext(UINT32 val)
840 {
841 __asm__ volatile("mcr p14, 0, %0, c0,c0,2" ::"r"(val));
842 __asm__ volatile("isb" ::: "memory");
843 }
844
OsArmReadDbgdscrext(VOID)845 STATIC INLINE UINT32 OsArmReadDbgdscrext(VOID)
846 {
847 UINT32 val;
848 __asm__ volatile("mrc p14, 0, %0, c0,c2,2" : "=r"(val));
849 return val;
850 }
851
OsArmWriteDbgdscrext(UINT32 val)852 STATIC INLINE VOID OsArmWriteDbgdscrext(UINT32 val)
853 {
854 __asm__ volatile("mcr p14, 0, %0, c0,c2,2" ::"r"(val));
855 __asm__ volatile("isb" ::: "memory");
856 }
857
OsArmReadDbgdtrtxext(VOID)858 STATIC INLINE UINT32 OsArmReadDbgdtrtxext(VOID)
859 {
860 UINT32 val;
861 __asm__ volatile("mrc p14, 0, %0, c0,c3,2" : "=r"(val));
862 return val;
863 }
864
OsArmWriteDbgdtrtxext(UINT32 val)865 STATIC INLINE VOID OsArmWriteDbgdtrtxext(UINT32 val)
866 {
867 __asm__ volatile("mcr p14, 0, %0, c0,c3,2" ::"r"(val));
868 __asm__ volatile("isb" ::: "memory");
869 }
870
OsArmReadDbgdrcr(VOID)871 STATIC INLINE UINT32 OsArmReadDbgdrcr(VOID)
872 {
873 UINT32 val;
874 __asm__ volatile("mrc p14, 0, %0, c0,c4,2" : "=r"(val));
875 return val;
876 }
877
OsArmWriteDbgdrcr(UINT32 val)878 STATIC INLINE VOID OsArmWriteDbgdrcr(UINT32 val)
879 {
880 __asm__ volatile("mcr p14, 0, %0, c0,c4,2" ::"r"(val));
881 __asm__ volatile("isb" ::: "memory");
882 }
883
OsArmReadDbgvr0(VOID)884 STATIC INLINE UINT32 OsArmReadDbgvr0(VOID)
885 {
886 UINT32 val;
887 __asm__ volatile("mrc p14, 0, %0, c0,c0,4" : "=r"(val));
888 return val;
889 }
890
OsArmWriteDbgvr0(UINT32 val)891 STATIC INLINE VOID OsArmWriteDbgvr0(UINT32 val)
892 {
893 __asm__ volatile("mcr p14, 0, %0, c0,c0,4" ::"r"(val));
894 __asm__ volatile("isb" ::: "memory");
895 }
896
OsArmReadDbgvr1(VOID)897 STATIC INLINE UINT32 OsArmReadDbgvr1(VOID)
898 {
899 UINT32 val;
900 __asm__ volatile("mrc p14, 0, %0, c0,c1,4" : "=r"(val));
901 return val;
902 }
903
OsArmWriteDbgvr1(UINT32 val)904 STATIC INLINE VOID OsArmWriteDbgvr1(UINT32 val)
905 {
906 __asm__ volatile("mcr p14, 0, %0, c0,c1,4" ::"r"(val));
907 __asm__ volatile("isb" ::: "memory");
908 }
909
OsArmReadDbgvr2(VOID)910 STATIC INLINE UINT32 OsArmReadDbgvr2(VOID)
911 {
912 UINT32 val;
913 __asm__ volatile("mrc p14, 0, %0, c0,c2,4" : "=r"(val));
914 return val;
915 }
916
OsArmWriteDbgvr2(UINT32 val)917 STATIC INLINE VOID OsArmWriteDbgvr2(UINT32 val)
918 {
919 __asm__ volatile("mcr p14, 0, %0, c0,c2,4" ::"r"(val));
920 __asm__ volatile("isb" ::: "memory");
921 }
922
OsArmReadDbgbcr0(VOID)923 STATIC INLINE UINT32 OsArmReadDbgbcr0(VOID)
924 {
925 UINT32 val;
926 __asm__ volatile("mrc p14, 0, %0, c0,c0,5" : "=r"(val));
927 return val;
928 }
929
OsArmWriteDbgbcr0(UINT32 val)930 STATIC INLINE VOID OsArmWriteDbgbcr0(UINT32 val)
931 {
932 __asm__ volatile("mcr p14, 0, %0, c0,c0,5" ::"r"(val));
933 __asm__ volatile("isb" ::: "memory");
934 }
935
OsArmReadDbgbcr1(VOID)936 STATIC INLINE UINT32 OsArmReadDbgbcr1(VOID)
937 {
938 UINT32 val;
939 __asm__ volatile("mrc p14, 0, %0, c0,c1,5" : "=r"(val));
940 return val;
941 }
942
OsArmWriteDbgbcr1(UINT32 val)943 STATIC INLINE VOID OsArmWriteDbgbcr1(UINT32 val)
944 {
945 __asm__ volatile("mcr p14, 0, %0, c0,c1,5" ::"r"(val));
946 __asm__ volatile("isb" ::: "memory");
947 }
948
OsArmReadDbgbcr2(VOID)949 STATIC INLINE UINT32 OsArmReadDbgbcr2(VOID)
950 {
951 UINT32 val;
952 __asm__ volatile("mrc p14, 0, %0, c0,c2,5" : "=r"(val));
953 return val;
954 }
955
OsArmWriteDbgbcr2(UINT32 val)956 STATIC INLINE VOID OsArmWriteDbgbcr2(UINT32 val)
957 {
958 __asm__ volatile("mcr p14, 0, %0, c0,c2,5" ::"r"(val));
959 __asm__ volatile("isb" ::: "memory");
960 }
961
OsArmReadDbgwvr0(VOID)962 STATIC INLINE UINT32 OsArmReadDbgwvr0(VOID)
963 {
964 UINT32 val;
965 __asm__ volatile("mrc p14, 0, %0, c0,c0,6" : "=r"(val));
966 return val;
967 }
968
OsArmWriteDbgwvr0(UINT32 val)969 STATIC INLINE VOID OsArmWriteDbgwvr0(UINT32 val)
970 {
971 __asm__ volatile("mcr p14, 0, %0, c0,c0,6" ::"r"(val));
972 __asm__ volatile("isb" ::: "memory");
973 }
974
OsArmReadDbgwvr1(VOID)975 STATIC INLINE UINT32 OsArmReadDbgwvr1(VOID)
976 {
977 UINT32 val;
978 __asm__ volatile("mrc p14, 0, %0, c0,c1,6" : "=r"(val));
979 return val;
980 }
981
OsArmWriteDbgwvr1(UINT32 val)982 STATIC INLINE VOID OsArmWriteDbgwvr1(UINT32 val)
983 {
984 __asm__ volatile("mcr p14, 0, %0, c0,c1,6" ::"r"(val));
985 __asm__ volatile("isb" ::: "memory");
986 }
987
OsArmReadDbgwcr0(VOID)988 STATIC INLINE UINT32 OsArmReadDbgwcr0(VOID)
989 {
990 UINT32 val;
991 __asm__ volatile("mrc p14, 0, %0, c0,c0,7" : "=r"(val));
992 return val;
993 }
994
OsArmWriteDbgwcr0(UINT32 val)995 STATIC INLINE VOID OsArmWriteDbgwcr0(UINT32 val)
996 {
997 __asm__ volatile("mcr p14, 0, %0, c0,c0,7" ::"r"(val));
998 __asm__ volatile("isb" ::: "memory");
999 }
1000
OsArmReadDbgwcr1(VOID)1001 STATIC INLINE UINT32 OsArmReadDbgwcr1(VOID)
1002 {
1003 UINT32 val;
1004 __asm__ volatile("mrc p14, 0, %0, c0,c1,7" : "=r"(val));
1005 return val;
1006 }
1007
OsArmWriteDbgwcr1(UINT32 val)1008 STATIC INLINE VOID OsArmWriteDbgwcr1(UINT32 val)
1009 {
1010 __asm__ volatile("mcr p14, 0, %0, c0,c1,7" ::"r"(val));
1011 __asm__ volatile("isb" ::: "memory");
1012 }
1013
OsArmReadDbgoslar(VOID)1014 STATIC INLINE UINT32 OsArmReadDbgoslar(VOID)
1015 {
1016 UINT32 val;
1017 __asm__ volatile("mrc p14, 0, %0, c1,c0,4" : "=r"(val));
1018 return val;
1019 }
1020
OsArmWriteDbgoslar(UINT32 val)1021 STATIC INLINE VOID OsArmWriteDbgoslar(UINT32 val)
1022 {
1023 __asm__ volatile("mcr p14, 0, %0, c1,c0,4" ::"r"(val));
1024 __asm__ volatile("isb" ::: "memory");
1025 }
1026
OsArmReadDbgoslsr(VOID)1027 STATIC INLINE UINT32 OsArmReadDbgoslsr(VOID)
1028 {
1029 UINT32 val;
1030 __asm__ volatile("mrc p14, 0, %0, c1,c1,4" : "=r"(val));
1031 return val;
1032 }
1033
OsArmWriteDbgoslsr(UINT32 val)1034 STATIC INLINE VOID OsArmWriteDbgoslsr(UINT32 val)
1035 {
1036 __asm__ volatile("mcr p14, 0, %0, c1,c1,4" ::"r"(val));
1037 __asm__ volatile("isb" ::: "memory");
1038 }
1039
OsArmReadDbgossrr(VOID)1040 STATIC INLINE UINT32 OsArmReadDbgossrr(VOID)
1041 {
1042 UINT32 val;
1043 __asm__ volatile("mrc p14, 0, %0, c1,c2,4" : "=r"(val));
1044 return val;
1045 }
1046
OsArmWriteDbgossrr(UINT32 val)1047 STATIC INLINE VOID OsArmWriteDbgossrr(UINT32 val)
1048 {
1049 __asm__ volatile("mcr p14, 0, %0, c1,c2,4" ::"r"(val));
1050 __asm__ volatile("isb" ::: "memory");
1051 }
1052
OsArmReadDbgprcr(VOID)1053 STATIC INLINE UINT32 OsArmReadDbgprcr(VOID)
1054 {
1055 UINT32 val;
1056 __asm__ volatile("mrc p14, 0, %0, c1,c4,4" : "=r"(val));
1057 return val;
1058 }
1059
OsArmWriteDbgprcr(UINT32 val)1060 STATIC INLINE VOID OsArmWriteDbgprcr(UINT32 val)
1061 {
1062 __asm__ volatile("mcr p14, 0, %0, c1,c4,4" ::"r"(val));
1063 __asm__ volatile("isb" ::: "memory");
1064 }
1065
OsArmReadDbgprsr(VOID)1066 STATIC INLINE UINT32 OsArmReadDbgprsr(VOID)
1067 {
1068 UINT32 val;
1069 __asm__ volatile("mrc p14, 0, %0, c1,c5,4" : "=r"(val));
1070 return val;
1071 }
1072
OsArmWriteDbgprsr(UINT32 val)1073 STATIC INLINE VOID OsArmWriteDbgprsr(UINT32 val)
1074 {
1075 __asm__ volatile("mcr p14, 0, %0, c1,c5,4" ::"r"(val));
1076 __asm__ volatile("isb" ::: "memory");
1077 }
1078
OsArmReadDbgclaimset(VOID)1079 STATIC INLINE UINT32 OsArmReadDbgclaimset(VOID)
1080 {
1081 UINT32 val;
1082 __asm__ volatile("mrc p14, 0, %0, c7,c8,6" : "=r"(val));
1083 return val;
1084 }
1085
OsArmWriteDbgclaimset(UINT32 val)1086 STATIC INLINE VOID OsArmWriteDbgclaimset(UINT32 val)
1087 {
1088 __asm__ volatile("mcr p14, 0, %0, c7,c8,6" ::"r"(val));
1089 __asm__ volatile("isb" ::: "memory");
1090 }
1091
OsArmReadDbgclaimclr(VOID)1092 STATIC INLINE UINT32 OsArmReadDbgclaimclr(VOID)
1093 {
1094 UINT32 val;
1095 __asm__ volatile("mrc p14, 0, %0, c7,c9,6" : "=r"(val));
1096 return val;
1097 }
1098
OsArmWriteDbgclaimclr(UINT32 val)1099 STATIC INLINE VOID OsArmWriteDbgclaimclr(UINT32 val)
1100 {
1101 __asm__ volatile("mcr p14, 0, %0, c7,c9,6" ::"r"(val));
1102 __asm__ volatile("isb" ::: "memory");
1103 }
1104
OsArmReadDbgauthstatus(VOID)1105 STATIC INLINE UINT32 OsArmReadDbgauthstatus(VOID)
1106 {
1107 UINT32 val;
1108 __asm__ volatile("mrc p14, 0, %0, c7,c14,6" : "=r"(val));
1109 return val;
1110 }
1111
OsArmWriteDbgauthstatus(UINT32 val)1112 STATIC INLINE VOID OsArmWriteDbgauthstatus(UINT32 val)
1113 {
1114 __asm__ volatile("mcr p14, 0, %0, c7,c14,6" ::"r"(val));
1115 __asm__ volatile("isb" ::: "memory");
1116 }
1117
OsArmReadDbgdevid(VOID)1118 STATIC INLINE UINT32 OsArmReadDbgdevid(VOID)
1119 {
1120 UINT32 val;
1121 __asm__ volatile("mrc p14, 0, %0, c7,c2,7" : "=r"(val));
1122 return val;
1123 }
1124
OsArmWriteDbgdevid(UINT32 val)1125 STATIC INLINE VOID OsArmWriteDbgdevid(UINT32 val)
1126 {
1127 __asm__ volatile("mcr p14, 0, %0, c7,c2,7" ::"r"(val));
1128 __asm__ volatile("isb" ::: "memory");
1129 }
1130
1131 #endif /* __LOS_ARM_H__ */
1132