1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /**
33 * @defgroup los_pte_ops page table entry operations
34 * @ingroup kernel
35 */
36
37 #ifndef __LOS_PTE_OPS_H__
38 #define __LOS_PTE_OPS_H__
39
40 #include "los_typedef.h"
41 #include "arm.h"
42 #include "los_mmu_descriptor_v6.h"
43
44 #ifdef __cplusplus
45 #if __cplusplus
46 extern "C" {
47 #endif /* __cplusplus */
48 #endif /* __cplusplus */
49
OsSavePte1(PTE_T * pte1Ptr,PTE_T pte1)50 STATIC INLINE VOID OsSavePte1(PTE_T *pte1Ptr, PTE_T pte1)
51 {
52 DMB;
53 *pte1Ptr = pte1;
54 DSB;
55 }
56
OsTruncPte1(ADDR_T addr)57 STATIC INLINE ADDR_T OsTruncPte1(ADDR_T addr)
58 {
59 return MMU_DESCRIPTOR_L1_SECTION_ADDR(addr);
60 }
61
OsGetPte1Index(vaddr_t va)62 STATIC INLINE UINT32 OsGetPte1Index(vaddr_t va)
63 {
64 return va >> MMU_DESCRIPTOR_L1_SMALL_SHIFT;
65 }
66
OsClearPte1(PTE_T * pte1Ptr)67 STATIC INLINE VOID OsClearPte1(PTE_T *pte1Ptr)
68 {
69 OsSavePte1(pte1Ptr, 0);
70 }
71
OsGetPte1Paddr(PADDR_T PhysTtb,vaddr_t va)72 STATIC INLINE PADDR_T OsGetPte1Paddr(PADDR_T PhysTtb, vaddr_t va)
73 {
74 return (PhysTtb + (OsGetPte1Index(va) * sizeof(PADDR_T)));
75 }
76
OsGetPte1Ptr(PTE_T * pte1BasePtr,vaddr_t va)77 STATIC INLINE PTE_T *OsGetPte1Ptr(PTE_T *pte1BasePtr, vaddr_t va)
78 {
79 return (pte1BasePtr + OsGetPte1Index(va));
80 }
81
OsGetPte1(PTE_T * pte1BasePtr,vaddr_t va)82 STATIC INLINE PTE_T OsGetPte1(PTE_T *pte1BasePtr, vaddr_t va)
83 {
84 return *OsGetPte1Ptr(pte1BasePtr, va);
85 }
86
OsIsPte1PageTable(PTE_T pte1)87 STATIC INLINE BOOL OsIsPte1PageTable(PTE_T pte1)
88 {
89 return (pte1 & MMU_DESCRIPTOR_L1_TYPE_MASK) == MMU_DESCRIPTOR_L1_TYPE_PAGE_TABLE;
90 }
91
OsIsPte1Invalid(PTE_T pte1)92 STATIC INLINE BOOL OsIsPte1Invalid(PTE_T pte1)
93 {
94 return (pte1 & MMU_DESCRIPTOR_L1_TYPE_MASK) == MMU_DESCRIPTOR_L1_TYPE_INVALID;
95 }
96
OsIsPte1Section(PTE_T pte1)97 STATIC INLINE BOOL OsIsPte1Section(PTE_T pte1)
98 {
99 return (pte1 & MMU_DESCRIPTOR_L1_TYPE_MASK) == MMU_DESCRIPTOR_L1_TYPE_SECTION;
100 }
101
OsGetPte2Index(vaddr_t va)102 STATIC INLINE UINT32 OsGetPte2Index(vaddr_t va)
103 {
104 return (va % MMU_DESCRIPTOR_L1_SMALL_SIZE) >> MMU_DESCRIPTOR_L2_SMALL_SHIFT;
105 }
106
OsGetPte2Ptr(PTE_T * pte2BasePtr,vaddr_t va)107 STATIC INLINE PTE_T *OsGetPte2Ptr(PTE_T *pte2BasePtr, vaddr_t va)
108 {
109 return (pte2BasePtr + OsGetPte2Index(va));
110 }
111
OsGetPte2(PTE_T * pte2BasePtr,vaddr_t va)112 STATIC INLINE PTE_T OsGetPte2(PTE_T *pte2BasePtr, vaddr_t va)
113 {
114 return *(pte2BasePtr + OsGetPte2Index(va));
115 }
116
OsSavePte2(PTE_T * pte2Ptr,PTE_T pte2)117 STATIC INLINE VOID OsSavePte2(PTE_T *pte2Ptr, PTE_T pte2)
118 {
119 DMB;
120 *pte2Ptr = pte2;
121 DSB;
122 }
123
OsSavePte2Continuous(PTE_T * pte2BasePtr,UINT32 index,PTE_T pte2,UINT32 count)124 STATIC INLINE UINT32 OsSavePte2Continuous(PTE_T *pte2BasePtr, UINT32 index, PTE_T pte2, UINT32 count)
125 {
126 UINT32 saveCounts = 0;
127 if (count == 0) {
128 return 0;
129 }
130
131 DMB;
132 do {
133 pte2BasePtr[index++] = pte2;
134 count--;
135 pte2 += MMU_DESCRIPTOR_L2_SMALL_SIZE;
136 saveCounts++;
137 } while ((count != 0) && (index != MMU_DESCRIPTOR_L2_NUMBERS_PER_L1));
138 DSB;
139
140 return saveCounts;
141 }
142
OsClearPte2Continuous(PTE_T * pte2Ptr,UINT32 count)143 STATIC INLINE VOID OsClearPte2Continuous(PTE_T *pte2Ptr, UINT32 count)
144 {
145 UINT32 index = 0;
146
147 DMB;
148 while (count > 0) {
149 pte2Ptr[index++] = 0;
150 count--;
151 }
152 DSB;
153 }
154
OsIsPte2SmallPage(PTE_T pte2)155 STATIC INLINE BOOL OsIsPte2SmallPage(PTE_T pte2)
156 {
157 return (pte2 & MMU_DESCRIPTOR_L2_TYPE_MASK) == MMU_DESCRIPTOR_L2_TYPE_SMALL_PAGE;
158 }
159
OsIsPte2SmallPageXN(PTE_T pte2)160 STATIC INLINE BOOL OsIsPte2SmallPageXN(PTE_T pte2)
161 {
162 return (pte2 & MMU_DESCRIPTOR_L2_TYPE_MASK) == MMU_DESCRIPTOR_L2_TYPE_SMALL_PAGE_XN;
163 }
164
OsIsPte2LargePage(PTE_T pte2)165 STATIC INLINE BOOL OsIsPte2LargePage(PTE_T pte2)
166 {
167 return (pte2 & MMU_DESCRIPTOR_L2_TYPE_MASK) == MMU_DESCRIPTOR_L2_TYPE_LARGE_PAGE;
168 }
169
OsIsPte2Invalid(PTE_T pte2)170 STATIC INLINE BOOL OsIsPte2Invalid(PTE_T pte2)
171 {
172 return (pte2 & MMU_DESCRIPTOR_L2_TYPE_MASK) == MMU_DESCRIPTOR_L2_TYPE_INVALID;
173 }
174
175 #ifdef __cplusplus
176 #if __cplusplus
177 }
178 #endif /* __cplusplus */
179 #endif /* __cplusplus */
180
181 #endif /* __LOS_PTE_OPS_H__ */
182