1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
42
43 #include <linux/pci_ids.h>
44
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
50 PCI_STATUS_PARITY)
51
52 /*
53 * The PCI interface treats multi-function devices as independent
54 * devices. The slot/function address of each device is encoded
55 * in a single byte as follows:
56 *
57 * 7:3 = slot
58 * 2:0 = function
59 *
60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
61 * In the interest of not exposing interfaces to user-space unnecessarily,
62 * the following kernel-only defines are being added here.
63 */
64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
67
68 /* pci_slot represents a physical slot */
69 struct pci_slot {
70 struct pci_bus *bus; /* Bus this slot is on */
71 struct list_head list; /* Node in list of slots */
72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
74 struct kobject kobj;
75 };
76
pci_slot_name(const struct pci_slot * slot)77 static inline const char *pci_slot_name(const struct pci_slot *slot)
78 {
79 return kobject_name(&slot->kobj);
80 }
81
82 /* File state for mmap()s on /proc/bus/pci/X/Y */
83 enum pci_mmap_state {
84 pci_mmap_io,
85 pci_mmap_mem
86 };
87
88 /* For PCI devices, the region numbers are assigned this way: */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* Device-specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* PCI-to-PCI (P2P) bridge windows */
104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
107
108 /* CardBus bridge windows */
109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
113
114 /* Total number of bridge resources for P2P and CardBus */
115 #define PCI_BRIDGE_RESOURCE_NUM 4
116
117 /* Resources assigned to buses behind the bridge */
118 PCI_BRIDGE_RESOURCES,
119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
120 PCI_BRIDGE_RESOURCE_NUM - 1,
121
122 /* Total resources associated with a PCI device */
123 PCI_NUM_RESOURCES,
124
125 /* Preserve this for compatibility */
126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
127 };
128
129 /**
130 * enum pci_interrupt_pin - PCI INTx interrupt values
131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
132 * @PCI_INTERRUPT_INTA: PCI INTA pin
133 * @PCI_INTERRUPT_INTB: PCI INTB pin
134 * @PCI_INTERRUPT_INTC: PCI INTC pin
135 * @PCI_INTERRUPT_INTD: PCI INTD pin
136 *
137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
138 * PCI_INTERRUPT_PIN register.
139 */
140 enum pci_interrupt_pin {
141 PCI_INTERRUPT_UNKNOWN,
142 PCI_INTERRUPT_INTA,
143 PCI_INTERRUPT_INTB,
144 PCI_INTERRUPT_INTC,
145 PCI_INTERRUPT_INTD,
146 };
147
148 /* The number of legacy PCI INTx interrupts */
149 #define PCI_NUM_INTX 4
150
151 /*
152 * pci_power_t values must match the bits in the Capabilities PME_Support
153 * and Control/Status PowerState fields in the Power Management capability.
154 */
155 typedef int __bitwise pci_power_t;
156
157 #define PCI_D0 ((pci_power_t __force) 0)
158 #define PCI_D1 ((pci_power_t __force) 1)
159 #define PCI_D2 ((pci_power_t __force) 2)
160 #define PCI_D3hot ((pci_power_t __force) 3)
161 #define PCI_D3cold ((pci_power_t __force) 4)
162 #define PCI_UNKNOWN ((pci_power_t __force) 5)
163 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
164
165 /* Remember to update this when the list above changes! */
166 extern const char *pci_power_names[];
167
pci_power_name(pci_power_t state)168 static inline const char *pci_power_name(pci_power_t state)
169 {
170 return pci_power_names[1 + (__force int) state];
171 }
172
173 /**
174 * typedef pci_channel_state_t
175 *
176 * The pci_channel state describes connectivity between the CPU and
177 * the PCI device. If some PCI bus between here and the PCI device
178 * has crashed or locked up, this info is reflected here.
179 */
180 typedef unsigned int __bitwise pci_channel_state_t;
181
182 enum {
183 /* I/O channel is in normal state */
184 pci_channel_io_normal = (__force pci_channel_state_t) 1,
185
186 /* I/O to channel is blocked */
187 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
188
189 /* PCI card is dead */
190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
191 };
192
193 typedef unsigned int __bitwise pcie_reset_state_t;
194
195 enum pcie_reset_state {
196 /* Reset is NOT asserted (Use to deassert reset) */
197 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
198
199 /* Use #PERST to reset PCIe device */
200 pcie_warm_reset = (__force pcie_reset_state_t) 2,
201
202 /* Use PCIe Hot Reset to reset device */
203 pcie_hot_reset = (__force pcie_reset_state_t) 3
204 };
205
206 typedef unsigned short __bitwise pci_dev_flags_t;
207 enum pci_dev_flags {
208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
210 /* Device configuration is irrevocably lost if disabled into D3 */
211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
212 /* Provide indication device is assigned by a Virtual Machine Manager */
213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
214 /* Flag for quirk use to store if quirk-specific ACS is enabled */
215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
218 /* Do not use bus resets for device */
219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
220 /* Do not use PM reset even if device advertises NoSoftRst- */
221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
222 /* Get VPD from function 0 VPD */
223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
224 /* A non-root bridge where translation occurs, stop alias search here */
225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
226 /* Do not use FLR even if device advertises PCI_AF_CAP */
227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
228 /* Don't use Relaxed Ordering for TLPs directed at this device */
229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
230 /* Device does honor MSI masking despite saying otherwise */
231 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
232 };
233
234 enum pci_irq_reroute_variant {
235 INTEL_IRQ_REROUTE_VARIANT = 1,
236 MAX_IRQ_REROUTE_VARIANTS = 3
237 };
238
239 typedef unsigned short __bitwise pci_bus_flags_t;
240 enum pci_bus_flags {
241 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
242 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
243 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
244 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
245 };
246
247 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
248 enum pcie_link_width {
249 PCIE_LNK_WIDTH_RESRV = 0x00,
250 PCIE_LNK_X1 = 0x01,
251 PCIE_LNK_X2 = 0x02,
252 PCIE_LNK_X4 = 0x04,
253 PCIE_LNK_X8 = 0x08,
254 PCIE_LNK_X12 = 0x0c,
255 PCIE_LNK_X16 = 0x10,
256 PCIE_LNK_X32 = 0x20,
257 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
258 };
259
260 /* See matching string table in pci_speed_string() */
261 enum pci_bus_speed {
262 PCI_SPEED_33MHz = 0x00,
263 PCI_SPEED_66MHz = 0x01,
264 PCI_SPEED_66MHz_PCIX = 0x02,
265 PCI_SPEED_100MHz_PCIX = 0x03,
266 PCI_SPEED_133MHz_PCIX = 0x04,
267 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
268 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
269 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
270 PCI_SPEED_66MHz_PCIX_266 = 0x09,
271 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
272 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
273 AGP_UNKNOWN = 0x0c,
274 AGP_1X = 0x0d,
275 AGP_2X = 0x0e,
276 AGP_4X = 0x0f,
277 AGP_8X = 0x10,
278 PCI_SPEED_66MHz_PCIX_533 = 0x11,
279 PCI_SPEED_100MHz_PCIX_533 = 0x12,
280 PCI_SPEED_133MHz_PCIX_533 = 0x13,
281 PCIE_SPEED_2_5GT = 0x14,
282 PCIE_SPEED_5_0GT = 0x15,
283 PCIE_SPEED_8_0GT = 0x16,
284 PCIE_SPEED_16_0GT = 0x17,
285 PCIE_SPEED_32_0GT = 0x18,
286 PCI_SPEED_UNKNOWN = 0xff,
287 };
288
289 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
290 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
291
292 struct pci_cap_saved_data {
293 u16 cap_nr;
294 bool cap_extended;
295 unsigned int size;
296 u32 data[];
297 };
298
299 struct pci_cap_saved_state {
300 struct hlist_node next;
301 struct pci_cap_saved_data cap;
302 };
303
304 struct irq_affinity;
305 struct pcie_link_state;
306 struct pci_vpd;
307 struct pci_sriov;
308 struct pci_p2pdma;
309
310 /* The pci_dev structure describes PCI devices */
311 struct pci_dev {
312 struct list_head bus_list; /* Node in per-bus list */
313 struct pci_bus *bus; /* Bus this device is on */
314 struct pci_bus *subordinate; /* Bus this device bridges to */
315
316 void *sysdata; /* Hook for sys-specific extension */
317 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
318 struct pci_slot *slot; /* Physical slot this device is in */
319
320 unsigned int devfn; /* Encoded device & function index */
321 unsigned short vendor;
322 unsigned short device;
323 unsigned short subsystem_vendor;
324 unsigned short subsystem_device;
325 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
326 u8 revision; /* PCI revision, low byte of class word */
327 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
328 #ifdef CONFIG_PCIEAER
329 u16 aer_cap; /* AER capability offset */
330 struct aer_stats *aer_stats; /* AER stats for this device */
331 #endif
332 u8 pcie_cap; /* PCIe capability offset */
333 u8 msi_cap; /* MSI capability offset */
334 u8 msix_cap; /* MSI-X capability offset */
335 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
336 u8 rom_base_reg; /* Config register controlling ROM */
337 u8 pin; /* Interrupt pin this device uses */
338 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
339 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
340
341 struct pci_driver *driver; /* Driver bound to this device */
342 u64 dma_mask; /* Mask of the bits of bus address this
343 device implements. Normally this is
344 0xffffffff. You only need to change
345 this if your device has broken DMA
346 or supports 64-bit transfers. */
347
348 struct device_dma_parameters dma_parms;
349
350 pci_power_t current_state; /* Current operating state. In ACPI,
351 this is D0-D3, D0 being fully
352 functional, and D3 being off. */
353 unsigned int imm_ready:1; /* Supports Immediate Readiness */
354 u8 pm_cap; /* PM capability offset */
355 unsigned int pme_support:5; /* Bitmask of states from which PME#
356 can be generated */
357 unsigned int pme_poll:1; /* Poll device's PME status bit */
358 unsigned int d1_support:1; /* Low power state D1 is supported */
359 unsigned int d2_support:1; /* Low power state D2 is supported */
360 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
361 unsigned int no_d3cold:1; /* D3cold is forbidden */
362 unsigned int bridge_d3:1; /* Allow D3 for bridge */
363 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
364 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
365 decoding during BAR sizing */
366 unsigned int wakeup_prepared:1;
367 unsigned int runtime_d3cold:1; /* Whether go through runtime
368 D3cold, not set for devices
369 powered on/off by the
370 corresponding bridge */
371 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
372 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
373 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
374 controlled exclusively by
375 user sysfs */
376 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
377 bit manually */
378 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
379 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
380
381 #ifdef CONFIG_PCIEASPM
382 struct pcie_link_state *link_state; /* ASPM link state */
383 unsigned int ltr_path:1; /* Latency Tolerance Reporting
384 supported from root to here */
385 int l1ss; /* L1SS Capability pointer */
386 #endif
387 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
388
389 pci_channel_state_t error_state; /* Current connectivity state */
390 struct device dev; /* Generic device interface */
391
392 int cfg_size; /* Size of config space */
393
394 /*
395 * Instead of touching interrupt line and base address registers
396 * directly, use the values stored here. They might be different!
397 */
398 unsigned int irq;
399 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
400
401 bool match_driver; /* Skip attaching driver */
402
403 unsigned int transparent:1; /* Subtractive decode bridge */
404 unsigned int io_window:1; /* Bridge has I/O window */
405 unsigned int pref_window:1; /* Bridge has pref mem window */
406 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
407 unsigned int multifunction:1; /* Multi-function device */
408
409 unsigned int is_busmaster:1; /* Is busmaster */
410 unsigned int no_msi:1; /* May not use MSI */
411 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
412 unsigned int block_cfg_access:1; /* Config space access blocked */
413 unsigned int broken_parity_status:1; /* Generates false positive parity */
414 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
415 unsigned int msi_enabled:1;
416 unsigned int msix_enabled:1;
417 unsigned int ari_enabled:1; /* ARI forwarding */
418 unsigned int ats_enabled:1; /* Address Translation Svc */
419 unsigned int pasid_enabled:1; /* Process Address Space ID */
420 unsigned int pri_enabled:1; /* Page Request Interface */
421 unsigned int is_managed:1;
422 unsigned int needs_freset:1; /* Requires fundamental reset */
423 unsigned int state_saved:1;
424 unsigned int is_physfn:1;
425 unsigned int is_virtfn:1;
426 unsigned int reset_fn:1;
427 unsigned int is_hotplug_bridge:1;
428 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
429 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
430 /*
431 * Devices marked being untrusted are the ones that can potentially
432 * execute DMA attacks and similar. They are typically connected
433 * through external ports such as Thunderbolt but not limited to
434 * that. When an IOMMU is enabled they should be getting full
435 * mappings to make sure they cannot access arbitrary memory.
436 */
437 unsigned int untrusted:1;
438 /*
439 * Info from the platform, e.g., ACPI or device tree, may mark a
440 * device as "external-facing". An external-facing device is
441 * itself internal but devices downstream from it are external.
442 */
443 unsigned int external_facing:1;
444 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
445 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
446 unsigned int irq_managed:1;
447 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
448 unsigned int is_probed:1; /* Device probing in progress */
449 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
450 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
451 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
452 pci_dev_flags_t dev_flags;
453 atomic_t enable_cnt; /* pci_enable_device has been called */
454
455 u32 saved_config_space[16]; /* Config space saved at suspend time */
456 struct hlist_head saved_cap_space;
457 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
458 int rom_attr_enabled; /* Display of ROM attribute enabled? */
459 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
460 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
461
462 #ifdef CONFIG_HOTPLUG_PCI_PCIE
463 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
464 #endif
465 #ifdef CONFIG_PCIE_PTM
466 unsigned int ptm_root:1;
467 unsigned int ptm_enabled:1;
468 u8 ptm_granularity;
469 #endif
470 #ifdef CONFIG_PCI_MSI
471 const struct attribute_group **msi_irq_groups;
472 #endif
473 struct pci_vpd *vpd;
474 #ifdef CONFIG_PCIE_DPC
475 u16 dpc_cap;
476 unsigned int dpc_rp_extensions:1;
477 u8 dpc_rp_log_size;
478 #endif
479 #ifdef CONFIG_PCI_ATS
480 union {
481 struct pci_sriov *sriov; /* PF: SR-IOV info */
482 struct pci_dev *physfn; /* VF: related PF */
483 };
484 u16 ats_cap; /* ATS Capability offset */
485 u8 ats_stu; /* ATS Smallest Translation Unit */
486 #endif
487 #ifdef CONFIG_PCI_PRI
488 u16 pri_cap; /* PRI Capability offset */
489 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
490 unsigned int pasid_required:1; /* PRG Response PASID Required */
491 #endif
492 #ifdef CONFIG_PCI_PASID
493 u16 pasid_cap; /* PASID Capability offset */
494 u16 pasid_features;
495 #endif
496 #ifdef CONFIG_PCI_P2PDMA
497 struct pci_p2pdma *p2pdma;
498 #endif
499 u16 acs_cap; /* ACS Capability offset */
500 phys_addr_t rom; /* Physical address if not from BAR */
501 size_t romlen; /* Length if not from BAR */
502 char *driver_override; /* Driver name to force a match */
503
504 unsigned long priv_flags; /* Private flags for the PCI driver */
505 };
506
pci_physfn(struct pci_dev * dev)507 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
508 {
509 #ifdef CONFIG_PCI_IOV
510 if (dev->is_virtfn)
511 dev = dev->physfn;
512 #endif
513 return dev;
514 }
515
516 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
517
518 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
519 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
520
pci_channel_offline(struct pci_dev * pdev)521 static inline int pci_channel_offline(struct pci_dev *pdev)
522 {
523 return (pdev->error_state != pci_channel_io_normal);
524 }
525
526 struct pci_host_bridge {
527 struct device dev;
528 struct pci_bus *bus; /* Root bus */
529 struct pci_ops *ops;
530 struct pci_ops *child_ops;
531 void *sysdata;
532 int busnr;
533 struct list_head windows; /* resource_entry */
534 struct list_head dma_ranges; /* dma ranges resource list */
535 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
536 int (*map_irq)(const struct pci_dev *, u8, u8);
537 void (*release_fn)(struct pci_host_bridge *);
538 void *release_data;
539 struct msi_controller *msi;
540 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
541 unsigned int no_ext_tags:1; /* No Extended Tags */
542 unsigned int native_aer:1; /* OS may use PCIe AER */
543 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
544 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
545 unsigned int native_pme:1; /* OS may use PCIe PME */
546 unsigned int native_ltr:1; /* OS may use PCIe LTR */
547 unsigned int native_dpc:1; /* OS may use PCIe DPC */
548 unsigned int preserve_config:1; /* Preserve FW resource setup */
549 unsigned int size_windows:1; /* Enable root bus sizing */
550
551 /* Resource alignment requirements */
552 resource_size_t (*align_resource)(struct pci_dev *dev,
553 const struct resource *res,
554 resource_size_t start,
555 resource_size_t size,
556 resource_size_t align);
557 unsigned long private[] ____cacheline_aligned;
558 };
559
560 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
561
pci_host_bridge_priv(struct pci_host_bridge * bridge)562 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
563 {
564 return (void *)bridge->private;
565 }
566
pci_host_bridge_from_priv(void * priv)567 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
568 {
569 return container_of(priv, struct pci_host_bridge, private);
570 }
571
572 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
573 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
574 size_t priv);
575 void pci_free_host_bridge(struct pci_host_bridge *bridge);
576 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
577
578 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
579 void (*release_fn)(struct pci_host_bridge *),
580 void *release_data);
581
582 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
583
584 /*
585 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
586 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
587 * buses below host bridges or subtractive decode bridges) go in the list.
588 * Use pci_bus_for_each_resource() to iterate through all the resources.
589 */
590
591 /*
592 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
593 * and there's no way to program the bridge with the details of the window.
594 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
595 * decode bit set, because they are explicit and can be programmed with _SRS.
596 */
597 #define PCI_SUBTRACTIVE_DECODE 0x1
598
599 struct pci_bus_resource {
600 struct list_head list;
601 struct resource *res;
602 unsigned int flags;
603 };
604
605 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
606
607 struct pci_bus {
608 struct list_head node; /* Node in list of buses */
609 struct pci_bus *parent; /* Parent bus this bridge is on */
610 struct list_head children; /* List of child buses */
611 struct list_head devices; /* List of devices on this bus */
612 struct pci_dev *self; /* Bridge device as seen by parent */
613 struct list_head slots; /* List of slots on this bus;
614 protected by pci_slot_mutex */
615 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
616 struct list_head resources; /* Address space routed to this bus */
617 struct resource busn_res; /* Bus numbers routed to this bus */
618
619 struct pci_ops *ops; /* Configuration access functions */
620 struct pci_ops *backup_ops;
621 struct msi_controller *msi; /* MSI controller */
622 void *sysdata; /* Hook for sys-specific extension */
623 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
624
625 unsigned char number; /* Bus number */
626 unsigned char primary; /* Number of primary bridge */
627 unsigned char max_bus_speed; /* enum pci_bus_speed */
628 unsigned char cur_bus_speed; /* enum pci_bus_speed */
629 #ifdef CONFIG_PCI_DOMAINS_GENERIC
630 int domain_nr;
631 #endif
632
633 char name[48];
634
635 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
636 pci_bus_flags_t bus_flags; /* Inherited by child buses */
637 struct device *bridge;
638 struct device dev;
639 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
640 struct bin_attribute *legacy_mem; /* Legacy mem */
641 unsigned int is_added:1;
642 };
643
644 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
645
pci_dev_id(struct pci_dev * dev)646 static inline u16 pci_dev_id(struct pci_dev *dev)
647 {
648 return PCI_DEVID(dev->bus->number, dev->devfn);
649 }
650
651 /*
652 * Returns true if the PCI bus is root (behind host-PCI bridge),
653 * false otherwise
654 *
655 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
656 * This is incorrect because "virtual" buses added for SR-IOV (via
657 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
658 */
pci_is_root_bus(struct pci_bus * pbus)659 static inline bool pci_is_root_bus(struct pci_bus *pbus)
660 {
661 return !(pbus->parent);
662 }
663
664 /**
665 * pci_is_bridge - check if the PCI device is a bridge
666 * @dev: PCI device
667 *
668 * Return true if the PCI device is bridge whether it has subordinate
669 * or not.
670 */
pci_is_bridge(struct pci_dev * dev)671 static inline bool pci_is_bridge(struct pci_dev *dev)
672 {
673 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
674 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
675 }
676
677 #define for_each_pci_bridge(dev, bus) \
678 list_for_each_entry(dev, &bus->devices, bus_list) \
679 if (!pci_is_bridge(dev)) {} else
680
pci_upstream_bridge(struct pci_dev * dev)681 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
682 {
683 dev = pci_physfn(dev);
684 if (pci_is_root_bus(dev->bus))
685 return NULL;
686
687 return dev->bus->self;
688 }
689
690 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)691 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
692 {
693 return pci_dev->msi_enabled || pci_dev->msix_enabled;
694 }
695 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)696 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
697 #endif
698
699 /* Error values that may be returned by PCI functions */
700 #define PCIBIOS_SUCCESSFUL 0x00
701 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
702 #define PCIBIOS_BAD_VENDOR_ID 0x83
703 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
704 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
705 #define PCIBIOS_SET_FAILED 0x88
706 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
707
708 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)709 static inline int pcibios_err_to_errno(int err)
710 {
711 if (err <= PCIBIOS_SUCCESSFUL)
712 return err; /* Assume already errno */
713
714 switch (err) {
715 case PCIBIOS_FUNC_NOT_SUPPORTED:
716 return -ENOENT;
717 case PCIBIOS_BAD_VENDOR_ID:
718 return -ENOTTY;
719 case PCIBIOS_DEVICE_NOT_FOUND:
720 return -ENODEV;
721 case PCIBIOS_BAD_REGISTER_NUMBER:
722 return -EFAULT;
723 case PCIBIOS_SET_FAILED:
724 return -EIO;
725 case PCIBIOS_BUFFER_TOO_SMALL:
726 return -ENOSPC;
727 }
728
729 return -ERANGE;
730 }
731
732 /* Low-level architecture-dependent routines */
733
734 struct pci_ops {
735 int (*add_bus)(struct pci_bus *bus);
736 void (*remove_bus)(struct pci_bus *bus);
737 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
738 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
739 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
740 };
741
742 /*
743 * ACPI needs to be able to access PCI config space before we've done a
744 * PCI bus scan and created pci_bus structures.
745 */
746 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
747 int reg, int len, u32 *val);
748 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
749 int reg, int len, u32 val);
750
751 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
752 typedef u64 pci_bus_addr_t;
753 #else
754 typedef u32 pci_bus_addr_t;
755 #endif
756
757 struct pci_bus_region {
758 pci_bus_addr_t start;
759 pci_bus_addr_t end;
760 };
761
762 struct pci_dynids {
763 spinlock_t lock; /* Protects list, index */
764 struct list_head list; /* For IDs added at runtime */
765 };
766
767
768 /*
769 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
770 * a set of callbacks in struct pci_error_handlers, that device driver
771 * will be notified of PCI bus errors, and will be driven to recovery
772 * when an error occurs.
773 */
774
775 typedef unsigned int __bitwise pci_ers_result_t;
776
777 enum pci_ers_result {
778 /* No result/none/not supported in device driver */
779 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
780
781 /* Device driver can recover without slot reset */
782 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
783
784 /* Device driver wants slot to be reset */
785 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
786
787 /* Device has completely failed, is unrecoverable */
788 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
789
790 /* Device driver is fully recovered and operational */
791 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
792
793 /* No AER capabilities registered for the driver */
794 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
795 };
796
797 /* PCI bus error event callbacks */
798 struct pci_error_handlers {
799 /* PCI bus error detected on this device */
800 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
801 pci_channel_state_t error);
802
803 /* MMIO has been re-enabled, but not DMA */
804 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
805
806 /* PCI slot has been reset */
807 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
808
809 /* PCI function reset prepare or completed */
810 void (*reset_prepare)(struct pci_dev *dev);
811 void (*reset_done)(struct pci_dev *dev);
812
813 /* Device driver may resume normal operations */
814 void (*resume)(struct pci_dev *dev);
815 };
816
817
818 struct module;
819
820 /**
821 * struct pci_driver - PCI driver structure
822 * @node: List of driver structures.
823 * @name: Driver name.
824 * @id_table: Pointer to table of device IDs the driver is
825 * interested in. Most drivers should export this
826 * table using MODULE_DEVICE_TABLE(pci,...).
827 * @probe: This probing function gets called (during execution
828 * of pci_register_driver() for already existing
829 * devices or later if a new device gets inserted) for
830 * all PCI devices which match the ID table and are not
831 * "owned" by the other drivers yet. This function gets
832 * passed a "struct pci_dev \*" for each device whose
833 * entry in the ID table matches the device. The probe
834 * function returns zero when the driver chooses to
835 * take "ownership" of the device or an error code
836 * (negative number) otherwise.
837 * The probe function always gets called from process
838 * context, so it can sleep.
839 * @remove: The remove() function gets called whenever a device
840 * being handled by this driver is removed (either during
841 * deregistration of the driver or when it's manually
842 * pulled out of a hot-pluggable slot).
843 * The remove function always gets called from process
844 * context, so it can sleep.
845 * @suspend: Put device into low power state.
846 * @resume: Wake device from low power state.
847 * (Please see Documentation/power/pci.rst for descriptions
848 * of PCI Power Management and the related functions.)
849 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
850 * Intended to stop any idling DMA operations.
851 * Useful for enabling wake-on-lan (NIC) or changing
852 * the power state of a device before reboot.
853 * e.g. drivers/net/e100.c.
854 * @sriov_configure: Optional driver callback to allow configuration of
855 * number of VFs to enable via sysfs "sriov_numvfs" file.
856 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
857 * @groups: Sysfs attribute groups.
858 * @driver: Driver model structure.
859 * @dynids: List of dynamically added device IDs.
860 */
861 struct pci_driver {
862 struct list_head node;
863 const char *name;
864 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
865 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
866 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
867 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
868 int (*resume)(struct pci_dev *dev); /* Device woken up */
869 void (*shutdown)(struct pci_dev *dev);
870 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
871 const struct pci_error_handlers *err_handler;
872 const struct attribute_group **groups;
873 struct device_driver driver;
874 struct pci_dynids dynids;
875 };
876
877 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
878
879 /**
880 * PCI_DEVICE - macro used to describe a specific PCI device
881 * @vend: the 16 bit PCI Vendor ID
882 * @dev: the 16 bit PCI Device ID
883 *
884 * This macro is used to create a struct pci_device_id that matches a
885 * specific device. The subvendor and subdevice fields will be set to
886 * PCI_ANY_ID.
887 */
888 #define PCI_DEVICE(vend,dev) \
889 .vendor = (vend), .device = (dev), \
890 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
891
892 /**
893 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
894 * @vend: the 16 bit PCI Vendor ID
895 * @dev: the 16 bit PCI Device ID
896 * @subvend: the 16 bit PCI Subvendor ID
897 * @subdev: the 16 bit PCI Subdevice ID
898 *
899 * This macro is used to create a struct pci_device_id that matches a
900 * specific device with subsystem information.
901 */
902 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
903 .vendor = (vend), .device = (dev), \
904 .subvendor = (subvend), .subdevice = (subdev)
905
906 /**
907 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
908 * @dev_class: the class, subclass, prog-if triple for this device
909 * @dev_class_mask: the class mask for this device
910 *
911 * This macro is used to create a struct pci_device_id that matches a
912 * specific PCI class. The vendor, device, subvendor, and subdevice
913 * fields will be set to PCI_ANY_ID.
914 */
915 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
916 .class = (dev_class), .class_mask = (dev_class_mask), \
917 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
918 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
919
920 /**
921 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
922 * @vend: the vendor name
923 * @dev: the 16 bit PCI Device ID
924 *
925 * This macro is used to create a struct pci_device_id that matches a
926 * specific PCI device. The subvendor, and subdevice fields will be set
927 * to PCI_ANY_ID. The macro allows the next field to follow as the device
928 * private data.
929 */
930 #define PCI_VDEVICE(vend, dev) \
931 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
932 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
933
934 /**
935 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
936 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
937 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
938 * @data: the driver data to be filled
939 *
940 * This macro is used to create a struct pci_device_id that matches a
941 * specific PCI device. The subvendor, and subdevice fields will be set
942 * to PCI_ANY_ID.
943 */
944 #define PCI_DEVICE_DATA(vend, dev, data) \
945 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
946 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
947 .driver_data = (kernel_ulong_t)(data)
948
949 enum {
950 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
951 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
952 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
953 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
954 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
955 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
956 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
957 };
958
959 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
960 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
961 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
962 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
963
964 /* These external functions are only available when PCI support is enabled */
965 #ifdef CONFIG_PCI
966
967 extern unsigned int pci_flags;
968
pci_set_flags(int flags)969 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)970 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)971 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)972 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
973
974 void pcie_bus_configure_settings(struct pci_bus *bus);
975
976 enum pcie_bus_config_types {
977 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
978 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
979 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
980 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
981 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
982 };
983
984 extern enum pcie_bus_config_types pcie_bus_config;
985
986 extern struct bus_type pci_bus_type;
987
988 /* Do NOT directly access these two variables, unless you are arch-specific PCI
989 * code, or PCI core code. */
990 extern struct list_head pci_root_buses; /* List of all known PCI buses */
991 /* Some device drivers need know if PCI is initiated */
992 int no_pci_devices(void);
993
994 void pcibios_resource_survey_bus(struct pci_bus *bus);
995 void pcibios_bus_add_device(struct pci_dev *pdev);
996 void pcibios_add_bus(struct pci_bus *bus);
997 void pcibios_remove_bus(struct pci_bus *bus);
998 void pcibios_fixup_bus(struct pci_bus *);
999 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1000 /* Architecture-specific versions may override this (weak) */
1001 char *pcibios_setup(char *str);
1002
1003 /* Used only when drivers/pci/setup.c is used */
1004 resource_size_t pcibios_align_resource(void *, const struct resource *,
1005 resource_size_t,
1006 resource_size_t);
1007
1008 /* Weak but can be overridden by arch */
1009 void pci_fixup_cardbus(struct pci_bus *);
1010
1011 /* Generic PCI functions used internally */
1012
1013 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1014 struct resource *res);
1015 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1016 struct pci_bus_region *region);
1017 void pcibios_scan_specific_bus(int busn);
1018 struct pci_bus *pci_find_bus(int domain, int busnr);
1019 void pci_bus_add_devices(const struct pci_bus *bus);
1020 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1021 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1022 struct pci_ops *ops, void *sysdata,
1023 struct list_head *resources);
1024 int pci_host_probe(struct pci_host_bridge *bridge);
1025 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1026 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1027 void pci_bus_release_busn_res(struct pci_bus *b);
1028 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1029 struct pci_ops *ops, void *sysdata,
1030 struct list_head *resources);
1031 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1032 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1033 int busnr);
1034 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1035 const char *name,
1036 struct hotplug_slot *hotplug);
1037 void pci_destroy_slot(struct pci_slot *slot);
1038 #ifdef CONFIG_SYSFS
1039 void pci_dev_assign_slot(struct pci_dev *dev);
1040 #else
pci_dev_assign_slot(struct pci_dev * dev)1041 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1042 #endif
1043 int pci_scan_slot(struct pci_bus *bus, int devfn);
1044 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1045 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1046 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1047 void pci_bus_add_device(struct pci_dev *dev);
1048 void pci_read_bridge_bases(struct pci_bus *child);
1049 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1050 struct resource *res);
1051 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1052 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1053 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1054 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1055 void pci_dev_put(struct pci_dev *dev);
1056 void pci_remove_bus(struct pci_bus *b);
1057 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1058 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1059 void pci_stop_root_bus(struct pci_bus *bus);
1060 void pci_remove_root_bus(struct pci_bus *bus);
1061 void pci_setup_cardbus(struct pci_bus *bus);
1062 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1063 void pci_sort_breadthfirst(void);
1064 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1065 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1066
1067 /* Generic PCI functions exported to card drivers */
1068
1069 int pci_find_capability(struct pci_dev *dev, int cap);
1070 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1071 int pci_find_ext_capability(struct pci_dev *dev, int cap);
1072 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1073 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1074 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1075 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1076
1077 u64 pci_get_dsn(struct pci_dev *dev);
1078
1079 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1080 struct pci_dev *from);
1081 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1082 unsigned int ss_vendor, unsigned int ss_device,
1083 struct pci_dev *from);
1084 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1085 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1086 unsigned int devfn);
1087 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1088 int pci_dev_present(const struct pci_device_id *ids);
1089
1090 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1091 int where, u8 *val);
1092 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1093 int where, u16 *val);
1094 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1095 int where, u32 *val);
1096 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1097 int where, u8 val);
1098 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1099 int where, u16 val);
1100 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1101 int where, u32 val);
1102
1103 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1104 int where, int size, u32 *val);
1105 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1106 int where, int size, u32 val);
1107 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1108 int where, int size, u32 *val);
1109 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1110 int where, int size, u32 val);
1111
1112 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1113
1114 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1115 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1116 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1117 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1118 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1119 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1120
1121 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1122 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1123 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1124 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1125 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1126 u16 clear, u16 set);
1127 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1128 u32 clear, u32 set);
1129
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1130 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1131 u16 set)
1132 {
1133 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1134 }
1135
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1136 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1137 u32 set)
1138 {
1139 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1140 }
1141
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1142 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1143 u16 clear)
1144 {
1145 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1146 }
1147
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1148 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1149 u32 clear)
1150 {
1151 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1152 }
1153
1154 /* User-space driven config access */
1155 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1156 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1157 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1158 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1159 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1160 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1161
1162 int __must_check pci_enable_device(struct pci_dev *dev);
1163 int __must_check pci_enable_device_io(struct pci_dev *dev);
1164 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1165 int __must_check pci_reenable_device(struct pci_dev *);
1166 int __must_check pcim_enable_device(struct pci_dev *pdev);
1167 void pcim_pin_device(struct pci_dev *pdev);
1168
pci_intx_mask_supported(struct pci_dev * pdev)1169 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1170 {
1171 /*
1172 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1173 * writable and no quirk has marked the feature broken.
1174 */
1175 return !pdev->broken_intx_masking;
1176 }
1177
pci_is_enabled(struct pci_dev * pdev)1178 static inline int pci_is_enabled(struct pci_dev *pdev)
1179 {
1180 return (atomic_read(&pdev->enable_cnt) > 0);
1181 }
1182
pci_is_managed(struct pci_dev * pdev)1183 static inline int pci_is_managed(struct pci_dev *pdev)
1184 {
1185 return pdev->is_managed;
1186 }
1187
1188 void pci_disable_device(struct pci_dev *dev);
1189
1190 extern unsigned int pcibios_max_latency;
1191 void pci_set_master(struct pci_dev *dev);
1192 void pci_clear_master(struct pci_dev *dev);
1193
1194 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1195 int pci_set_cacheline_size(struct pci_dev *dev);
1196 #define HAVE_PCI_SET_MWI
1197 int __must_check pci_set_mwi(struct pci_dev *dev);
1198 int __must_check pcim_set_mwi(struct pci_dev *dev);
1199 int pci_try_set_mwi(struct pci_dev *dev);
1200 void pci_clear_mwi(struct pci_dev *dev);
1201 void pci_intx(struct pci_dev *dev, int enable);
1202 bool pci_check_and_mask_intx(struct pci_dev *dev);
1203 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1204 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1205 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1206 int pcix_get_max_mmrbc(struct pci_dev *dev);
1207 int pcix_get_mmrbc(struct pci_dev *dev);
1208 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1209 int pcie_get_readrq(struct pci_dev *dev);
1210 int pcie_set_readrq(struct pci_dev *dev, int rq);
1211 int pcie_get_mps(struct pci_dev *dev);
1212 int pcie_set_mps(struct pci_dev *dev, int mps);
1213 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1214 enum pci_bus_speed *speed,
1215 enum pcie_link_width *width);
1216 void pcie_print_link_status(struct pci_dev *dev);
1217 bool pcie_has_flr(struct pci_dev *dev);
1218 int pcie_flr(struct pci_dev *dev);
1219 int __pci_reset_function_locked(struct pci_dev *dev);
1220 int pci_reset_function(struct pci_dev *dev);
1221 int pci_reset_function_locked(struct pci_dev *dev);
1222 int pci_try_reset_function(struct pci_dev *dev);
1223 int pci_probe_reset_slot(struct pci_slot *slot);
1224 int pci_probe_reset_bus(struct pci_bus *bus);
1225 int pci_reset_bus(struct pci_dev *dev);
1226 void pci_reset_secondary_bus(struct pci_dev *dev);
1227 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1228 void pci_update_resource(struct pci_dev *dev, int resno);
1229 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1230 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1231 void pci_release_resource(struct pci_dev *dev, int resno);
1232 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1233 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1234 bool pci_device_is_present(struct pci_dev *pdev);
1235 void pci_ignore_hotplug(struct pci_dev *dev);
1236 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1237 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1238
1239 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1240 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1241 const char *fmt, ...);
1242 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1243
1244 /* ROM control related routines */
1245 int pci_enable_rom(struct pci_dev *pdev);
1246 void pci_disable_rom(struct pci_dev *pdev);
1247 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1248 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1249
1250 /* Power management related routines */
1251 int pci_save_state(struct pci_dev *dev);
1252 void pci_restore_state(struct pci_dev *dev);
1253 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1254 int pci_load_saved_state(struct pci_dev *dev,
1255 struct pci_saved_state *state);
1256 int pci_load_and_free_saved_state(struct pci_dev *dev,
1257 struct pci_saved_state **state);
1258 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1259 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1260 u16 cap);
1261 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1262 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1263 u16 cap, unsigned int size);
1264 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1265 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1266 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1267 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1268 void pci_pme_active(struct pci_dev *dev, bool enable);
1269 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1270 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1271 int pci_prepare_to_sleep(struct pci_dev *dev);
1272 int pci_back_from_sleep(struct pci_dev *dev);
1273 bool pci_dev_run_wake(struct pci_dev *dev);
1274 void pci_d3cold_enable(struct pci_dev *dev);
1275 void pci_d3cold_disable(struct pci_dev *dev);
1276 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1277 void pci_wakeup_bus(struct pci_bus *bus);
1278 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1279
1280 /* For use by arch with custom probe code */
1281 void set_pcie_port_type(struct pci_dev *pdev);
1282 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1283
1284 /* Functions for PCI Hotplug drivers to use */
1285 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1286 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1287 unsigned int pci_rescan_bus(struct pci_bus *bus);
1288 void pci_lock_rescan_remove(void);
1289 void pci_unlock_rescan_remove(void);
1290
1291 /* Vital Product Data routines */
1292 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1293 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1294 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1295
1296 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1297 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1298 void pci_bus_assign_resources(const struct pci_bus *bus);
1299 void pci_bus_claim_resources(struct pci_bus *bus);
1300 void pci_bus_size_bridges(struct pci_bus *bus);
1301 int pci_claim_resource(struct pci_dev *, int);
1302 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1303 void pci_assign_unassigned_resources(void);
1304 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1305 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1306 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1307 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1308 void pdev_enable_device(struct pci_dev *);
1309 int pci_enable_resources(struct pci_dev *, int mask);
1310 void pci_assign_irq(struct pci_dev *dev);
1311 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1312 #define HAVE_PCI_REQ_REGIONS 2
1313 int __must_check pci_request_regions(struct pci_dev *, const char *);
1314 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1315 void pci_release_regions(struct pci_dev *);
1316 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1317 void pci_release_region(struct pci_dev *, int);
1318 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1319 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1320 void pci_release_selected_regions(struct pci_dev *, int);
1321
1322 /* drivers/pci/bus.c */
1323 void pci_add_resource(struct list_head *resources, struct resource *res);
1324 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1325 resource_size_t offset);
1326 void pci_free_resource_list(struct list_head *resources);
1327 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1328 unsigned int flags);
1329 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1330 void pci_bus_remove_resources(struct pci_bus *bus);
1331 int devm_request_pci_bus_resources(struct device *dev,
1332 struct list_head *resources);
1333
1334 /* Temporary until new and working PCI SBR API in place */
1335 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1336
1337 #define pci_bus_for_each_resource(bus, res, i) \
1338 for (i = 0; \
1339 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1340 i++)
1341
1342 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1343 struct resource *res, resource_size_t size,
1344 resource_size_t align, resource_size_t min,
1345 unsigned long type_mask,
1346 resource_size_t (*alignf)(void *,
1347 const struct resource *,
1348 resource_size_t,
1349 resource_size_t),
1350 void *alignf_data);
1351
1352
1353 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1354 resource_size_t size);
1355 unsigned long pci_address_to_pio(phys_addr_t addr);
1356 phys_addr_t pci_pio_to_address(unsigned long pio);
1357 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1358 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1359 phys_addr_t phys_addr);
1360 void pci_unmap_iospace(struct resource *res);
1361 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1362 resource_size_t offset,
1363 resource_size_t size);
1364 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1365 struct resource *res);
1366
pci_bus_address(struct pci_dev * pdev,int bar)1367 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1368 {
1369 struct pci_bus_region region;
1370
1371 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1372 return region.start;
1373 }
1374
1375 /* Proper probing supporting hot-pluggable devices */
1376 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1377 const char *mod_name);
1378
1379 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1380 #define pci_register_driver(driver) \
1381 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1382
1383 void pci_unregister_driver(struct pci_driver *dev);
1384
1385 /**
1386 * module_pci_driver() - Helper macro for registering a PCI driver
1387 * @__pci_driver: pci_driver struct
1388 *
1389 * Helper macro for PCI drivers which do not do anything special in module
1390 * init/exit. This eliminates a lot of boilerplate. Each module may only
1391 * use this macro once, and calling it replaces module_init() and module_exit()
1392 */
1393 #define module_pci_driver(__pci_driver) \
1394 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1395
1396 /**
1397 * builtin_pci_driver() - Helper macro for registering a PCI driver
1398 * @__pci_driver: pci_driver struct
1399 *
1400 * Helper macro for PCI drivers which do not do anything special in their
1401 * init code. This eliminates a lot of boilerplate. Each driver may only
1402 * use this macro once, and calling it replaces device_initcall(...)
1403 */
1404 #define builtin_pci_driver(__pci_driver) \
1405 builtin_driver(__pci_driver, pci_register_driver)
1406
1407 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1408 int pci_add_dynid(struct pci_driver *drv,
1409 unsigned int vendor, unsigned int device,
1410 unsigned int subvendor, unsigned int subdevice,
1411 unsigned int class, unsigned int class_mask,
1412 unsigned long driver_data);
1413 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1414 struct pci_dev *dev);
1415 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1416 int pass);
1417
1418 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1419 void *userdata);
1420 int pci_cfg_space_size(struct pci_dev *dev);
1421 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1422 void pci_setup_bridge(struct pci_bus *bus);
1423 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1424 unsigned long type);
1425
1426 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1427 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1428
1429 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1430 unsigned int command_bits, u32 flags);
1431
1432 /*
1433 * Virtual interrupts allow for more interrupts to be allocated
1434 * than the device has interrupts for. These are not programmed
1435 * into the device's MSI-X table and must be handled by some
1436 * other driver means.
1437 */
1438 #define PCI_IRQ_VIRTUAL (1 << 4)
1439
1440 #define PCI_IRQ_ALL_TYPES \
1441 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1442
1443 /* kmem_cache style wrapper around pci_alloc_consistent() */
1444
1445 #include <linux/dmapool.h>
1446
1447 #define pci_pool dma_pool
1448 #define pci_pool_create(name, pdev, size, align, allocation) \
1449 dma_pool_create(name, &pdev->dev, size, align, allocation)
1450 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1451 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1452 #define pci_pool_zalloc(pool, flags, handle) \
1453 dma_pool_zalloc(pool, flags, handle)
1454 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1455
1456 struct msix_entry {
1457 u32 vector; /* Kernel uses to write allocated vector */
1458 u16 entry; /* Driver uses to specify entry, OS writes */
1459 };
1460
1461 #ifdef CONFIG_PCI_MSI
1462 int pci_msi_vec_count(struct pci_dev *dev);
1463 void pci_disable_msi(struct pci_dev *dev);
1464 int pci_msix_vec_count(struct pci_dev *dev);
1465 void pci_disable_msix(struct pci_dev *dev);
1466 void pci_restore_msi_state(struct pci_dev *dev);
1467 int pci_msi_enabled(void);
1468 int pci_enable_msi(struct pci_dev *dev);
1469 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1470 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1471 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1472 struct msix_entry *entries, int nvec)
1473 {
1474 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1475 if (rc < 0)
1476 return rc;
1477 return 0;
1478 }
1479 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1480 unsigned int max_vecs, unsigned int flags,
1481 struct irq_affinity *affd);
1482
1483 void pci_free_irq_vectors(struct pci_dev *dev);
1484 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1485 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1486
1487 #else
pci_msi_vec_count(struct pci_dev * dev)1488 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1489 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1490 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1491 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1492 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1493 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1494 static inline int pci_enable_msi(struct pci_dev *dev)
1495 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1496 static inline int pci_enable_msix_range(struct pci_dev *dev,
1497 struct msix_entry *entries, int minvec, int maxvec)
1498 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1499 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1500 struct msix_entry *entries, int nvec)
1501 { return -ENOSYS; }
1502
1503 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1504 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1505 unsigned int max_vecs, unsigned int flags,
1506 struct irq_affinity *aff_desc)
1507 {
1508 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1509 return 1;
1510 return -ENOSPC;
1511 }
1512
pci_free_irq_vectors(struct pci_dev * dev)1513 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1514 {
1515 }
1516
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1517 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1518 {
1519 if (WARN_ON_ONCE(nr > 0))
1520 return -EINVAL;
1521 return dev->irq;
1522 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1523 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1524 int vec)
1525 {
1526 return cpu_possible_mask;
1527 }
1528 #endif
1529
1530 /**
1531 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1532 * @d: the INTx IRQ domain
1533 * @node: the DT node for the device whose interrupt we're translating
1534 * @intspec: the interrupt specifier data from the DT
1535 * @intsize: the number of entries in @intspec
1536 * @out_hwirq: pointer at which to write the hwirq number
1537 * @out_type: pointer at which to write the interrupt type
1538 *
1539 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1540 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1541 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1542 * INTx value to obtain the hwirq number.
1543 *
1544 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1545 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1546 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1547 struct device_node *node,
1548 const u32 *intspec,
1549 unsigned int intsize,
1550 unsigned long *out_hwirq,
1551 unsigned int *out_type)
1552 {
1553 const u32 intx = intspec[0];
1554
1555 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1556 return -EINVAL;
1557
1558 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1559 return 0;
1560 }
1561
1562 #ifdef CONFIG_PCIEPORTBUS
1563 extern bool pcie_ports_disabled;
1564 extern bool pcie_ports_native;
1565 #else
1566 #define pcie_ports_disabled true
1567 #define pcie_ports_native false
1568 #endif
1569
1570 #define PCIE_LINK_STATE_L0S BIT(0)
1571 #define PCIE_LINK_STATE_L1 BIT(1)
1572 #define PCIE_LINK_STATE_CLKPM BIT(2)
1573 #define PCIE_LINK_STATE_L1_1 BIT(3)
1574 #define PCIE_LINK_STATE_L1_2 BIT(4)
1575 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1576 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1577
1578 #ifdef CONFIG_PCIEASPM
1579 int pci_disable_link_state(struct pci_dev *pdev, int state);
1580 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1581 void pcie_no_aspm(void);
1582 bool pcie_aspm_support_enabled(void);
1583 bool pcie_aspm_enabled(struct pci_dev *pdev);
1584 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1585 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1586 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1587 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1588 { return 0; }
pcie_no_aspm(void)1589 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1590 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1591 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1592 #endif
1593
1594 #ifdef CONFIG_PCIEAER
1595 bool pci_aer_available(void);
1596 #else
pci_aer_available(void)1597 static inline bool pci_aer_available(void) { return false; }
1598 #endif
1599
1600 bool pci_ats_disabled(void);
1601
1602 void pci_cfg_access_lock(struct pci_dev *dev);
1603 bool pci_cfg_access_trylock(struct pci_dev *dev);
1604 void pci_cfg_access_unlock(struct pci_dev *dev);
1605
1606 /*
1607 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1608 * a PCI domain is defined to be a set of PCI buses which share
1609 * configuration space.
1610 */
1611 #ifdef CONFIG_PCI_DOMAINS
1612 extern int pci_domains_supported;
1613 #else
1614 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1615 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1616 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1617 #endif /* CONFIG_PCI_DOMAINS */
1618
1619 /*
1620 * Generic implementation for PCI domain support. If your
1621 * architecture does not need custom management of PCI
1622 * domains then this implementation will be used
1623 */
1624 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1625 static inline int pci_domain_nr(struct pci_bus *bus)
1626 {
1627 return bus->domain_nr;
1628 }
1629 #ifdef CONFIG_ACPI
1630 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1631 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1632 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1633 { return 0; }
1634 #endif
1635 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1636 #endif
1637
1638 /* Some architectures require additional setup to direct VGA traffic */
1639 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1640 unsigned int command_bits, u32 flags);
1641 void pci_register_set_vga_state(arch_set_vga_state_t func);
1642
1643 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1644 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1645 {
1646 return pci_request_selected_regions(pdev,
1647 pci_select_bars(pdev, IORESOURCE_IO), name);
1648 }
1649
1650 static inline void
pci_release_io_regions(struct pci_dev * pdev)1651 pci_release_io_regions(struct pci_dev *pdev)
1652 {
1653 return pci_release_selected_regions(pdev,
1654 pci_select_bars(pdev, IORESOURCE_IO));
1655 }
1656
1657 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1658 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1659 {
1660 return pci_request_selected_regions(pdev,
1661 pci_select_bars(pdev, IORESOURCE_MEM), name);
1662 }
1663
1664 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1665 pci_release_mem_regions(struct pci_dev *pdev)
1666 {
1667 return pci_release_selected_regions(pdev,
1668 pci_select_bars(pdev, IORESOURCE_MEM));
1669 }
1670
1671 #else /* CONFIG_PCI is not enabled */
1672
pci_set_flags(int flags)1673 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1674 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1675 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1676 static inline int pci_has_flag(int flag) { return 0; }
1677
1678 /*
1679 * If the system does not have PCI, clearly these return errors. Define
1680 * these as simple inline functions to avoid hair in drivers.
1681 */
1682 #define _PCI_NOP(o, s, t) \
1683 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1684 int where, t val) \
1685 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1686
1687 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1688 _PCI_NOP(o, word, u16 x) \
1689 _PCI_NOP(o, dword, u32 x)
1690 _PCI_NOP_ALL(read, *)
1691 _PCI_NOP_ALL(write,)
1692
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1693 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1694 unsigned int device,
1695 struct pci_dev *from)
1696 { return NULL; }
1697
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1698 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1699 unsigned int device,
1700 unsigned int ss_vendor,
1701 unsigned int ss_device,
1702 struct pci_dev *from)
1703 { return NULL; }
1704
pci_get_class(unsigned int class,struct pci_dev * from)1705 static inline struct pci_dev *pci_get_class(unsigned int class,
1706 struct pci_dev *from)
1707 { return NULL; }
1708
1709 #define pci_dev_present(ids) (0)
1710 #define no_pci_devices() (1)
1711 #define pci_dev_put(dev) do { } while (0)
1712
pci_set_master(struct pci_dev * dev)1713 static inline void pci_set_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1714 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1715 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1716 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1717 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1718 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1719 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1720 struct module *owner,
1721 const char *mod_name)
1722 { return 0; }
pci_register_driver(struct pci_driver * drv)1723 static inline int pci_register_driver(struct pci_driver *drv)
1724 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1725 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1726 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1727 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1728 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1729 int cap)
1730 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1731 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1732 { return 0; }
1733
pci_get_dsn(struct pci_dev * dev)1734 static inline u64 pci_get_dsn(struct pci_dev *dev)
1735 { return 0; }
1736
1737 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1738 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1739 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1740 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1741 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1742 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1743 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1744 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1745 pm_message_t state)
1746 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1747 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1748 int enable)
1749 { return 0; }
1750
pci_find_resource(struct pci_dev * dev,struct resource * res)1751 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1752 struct resource *res)
1753 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1754 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1755 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1756 static inline void pci_release_regions(struct pci_dev *dev) { }
1757
pci_address_to_pio(phys_addr_t addr)1758 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1759
pci_find_next_bus(const struct pci_bus * from)1760 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1761 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1762 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1763 unsigned int devfn)
1764 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1765 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1766 unsigned int bus, unsigned int devfn)
1767 { return NULL; }
1768
pci_domain_nr(struct pci_bus * bus)1769 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1770 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1771
1772 #define dev_is_pci(d) (false)
1773 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1774 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1775 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1776 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1777 struct device_node *node,
1778 const u32 *intspec,
1779 unsigned int intsize,
1780 unsigned long *out_hwirq,
1781 unsigned int *out_type)
1782 { return -EINVAL; }
1783
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1784 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1785 struct pci_dev *dev)
1786 { return NULL; }
pci_ats_disabled(void)1787 static inline bool pci_ats_disabled(void) { return true; }
1788
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1789 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1790 {
1791 return -EINVAL;
1792 }
1793
1794 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1795 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1796 unsigned int max_vecs, unsigned int flags,
1797 struct irq_affinity *aff_desc)
1798 {
1799 return -ENOSPC;
1800 }
1801 #endif /* CONFIG_PCI */
1802
1803 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1804 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1805 unsigned int max_vecs, unsigned int flags)
1806 {
1807 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1808 NULL);
1809 }
1810
1811 /* Include architecture-dependent settings and functions */
1812
1813 #include <asm/pci.h>
1814
1815 /* These two functions provide almost identical functionality. Depending
1816 * on the architecture, one will be implemented as a wrapper around the
1817 * other (in drivers/pci/mmap.c).
1818 *
1819 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1820 * is expected to be an offset within that region.
1821 *
1822 * pci_mmap_page_range() is the legacy architecture-specific interface,
1823 * which accepts a "user visible" resource address converted by
1824 * pci_resource_to_user(), as used in the legacy mmap() interface in
1825 * /proc/bus/pci/.
1826 */
1827 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1828 struct vm_area_struct *vma,
1829 enum pci_mmap_state mmap_state, int write_combine);
1830 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1831 struct vm_area_struct *vma,
1832 enum pci_mmap_state mmap_state, int write_combine);
1833
1834 #ifndef arch_can_pci_mmap_wc
1835 #define arch_can_pci_mmap_wc() 0
1836 #endif
1837
1838 #ifndef arch_can_pci_mmap_io
1839 #define arch_can_pci_mmap_io() 0
1840 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1841 #else
1842 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1843 #endif
1844
1845 #ifndef pci_root_bus_fwnode
1846 #define pci_root_bus_fwnode(bus) NULL
1847 #endif
1848
1849 /*
1850 * These helpers provide future and backwards compatibility
1851 * for accessing popular PCI BAR info
1852 */
1853 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1854 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1855 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1856 #define pci_resource_len(dev,bar) \
1857 ((pci_resource_start((dev), (bar)) == 0 && \
1858 pci_resource_end((dev), (bar)) == \
1859 pci_resource_start((dev), (bar))) ? 0 : \
1860 \
1861 (pci_resource_end((dev), (bar)) - \
1862 pci_resource_start((dev), (bar)) + 1))
1863
1864 /*
1865 * Similar to the helpers above, these manipulate per-pci_dev
1866 * driver-specific data. They are really just a wrapper around
1867 * the generic device structure functions of these calls.
1868 */
pci_get_drvdata(struct pci_dev * pdev)1869 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1870 {
1871 return dev_get_drvdata(&pdev->dev);
1872 }
1873
pci_set_drvdata(struct pci_dev * pdev,void * data)1874 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1875 {
1876 dev_set_drvdata(&pdev->dev, data);
1877 }
1878
pci_name(const struct pci_dev * pdev)1879 static inline const char *pci_name(const struct pci_dev *pdev)
1880 {
1881 return dev_name(&pdev->dev);
1882 }
1883
1884 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1885 const struct resource *rsrc,
1886 resource_size_t *start, resource_size_t *end);
1887
1888 /*
1889 * The world is not perfect and supplies us with broken PCI devices.
1890 * For at least a part of these bugs we need a work-around, so both
1891 * generic (drivers/pci/quirks.c) and per-architecture code can define
1892 * fixup hooks to be called for particular buggy devices.
1893 */
1894
1895 struct pci_fixup {
1896 u16 vendor; /* Or PCI_ANY_ID */
1897 u16 device; /* Or PCI_ANY_ID */
1898 u32 class; /* Or PCI_ANY_ID */
1899 unsigned int class_shift; /* should be 0, 8, 16 */
1900 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1901 int hook_offset;
1902 #else
1903 void (*hook)(struct pci_dev *dev);
1904 #endif
1905 };
1906
1907 enum pci_fixup_pass {
1908 pci_fixup_early, /* Before probing BARs */
1909 pci_fixup_header, /* After reading configuration header */
1910 pci_fixup_final, /* Final phase of device fixups */
1911 pci_fixup_enable, /* pci_enable_device() time */
1912 pci_fixup_resume, /* pci_device_resume() */
1913 pci_fixup_suspend, /* pci_device_suspend() */
1914 pci_fixup_resume_early, /* pci_device_resume_early() */
1915 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1916 };
1917
1918 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1919 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1920 class_shift, hook) \
1921 __ADDRESSABLE(hook) \
1922 asm(".section " #sec ", \"a\" \n" \
1923 ".balign 16 \n" \
1924 ".short " #vendor ", " #device " \n" \
1925 ".long " #class ", " #class_shift " \n" \
1926 ".long " #hook " - . \n" \
1927 ".previous \n");
1928
1929 /*
1930 * Clang's LTO may rename static functions in C, but has no way to
1931 * handle such renamings when referenced from inline asm. To work
1932 * around this, create global C stubs for these cases.
1933 */
1934 #ifdef CONFIG_LTO_CLANG
1935 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1936 class_shift, hook, stub) \
1937 void __cficanonical stub(struct pci_dev *dev); \
1938 void __cficanonical stub(struct pci_dev *dev) \
1939 { \
1940 hook(dev); \
1941 } \
1942 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1943 class_shift, stub)
1944 #else
1945 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1946 class_shift, hook, stub) \
1947 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1948 class_shift, hook)
1949 #endif
1950
1951 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1952 class_shift, hook) \
1953 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1954 class_shift, hook, __UNIQUE_ID(hook))
1955 #else
1956 /* Anonymous variables would be nice... */
1957 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1958 class_shift, hook) \
1959 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1960 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1961 = { vendor, device, class, class_shift, hook };
1962 #endif
1963
1964 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1965 class_shift, hook) \
1966 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1967 hook, vendor, device, class, class_shift, hook)
1968 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1969 class_shift, hook) \
1970 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1971 hook, vendor, device, class, class_shift, hook)
1972 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1973 class_shift, hook) \
1974 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1975 hook, vendor, device, class, class_shift, hook)
1976 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1977 class_shift, hook) \
1978 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1979 hook, vendor, device, class, class_shift, hook)
1980 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1981 class_shift, hook) \
1982 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1983 resume##hook, vendor, device, class, class_shift, hook)
1984 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1985 class_shift, hook) \
1986 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1987 resume_early##hook, vendor, device, class, class_shift, hook)
1988 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1989 class_shift, hook) \
1990 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1991 suspend##hook, vendor, device, class, class_shift, hook)
1992 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1993 class_shift, hook) \
1994 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1995 suspend_late##hook, vendor, device, class, class_shift, hook)
1996
1997 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1998 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1999 hook, vendor, device, PCI_ANY_ID, 0, hook)
2000 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2001 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2002 hook, vendor, device, PCI_ANY_ID, 0, hook)
2003 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2004 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2005 hook, vendor, device, PCI_ANY_ID, 0, hook)
2006 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2007 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2008 hook, vendor, device, PCI_ANY_ID, 0, hook)
2009 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2010 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2011 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2012 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2013 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2014 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2015 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2016 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2017 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2018 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2019 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2020 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2021
2022 #ifdef CONFIG_PCI_QUIRKS
2023 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2024 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2025 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2026 struct pci_dev *dev) { }
2027 #endif
2028
2029 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2030 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2031 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2032 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2033 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2034 const char *name);
2035 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2036
2037 extern int pci_pci_problems;
2038 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2039 #define PCIPCI_TRITON 2
2040 #define PCIPCI_NATOMA 4
2041 #define PCIPCI_VIAETBF 8
2042 #define PCIPCI_VSFX 16
2043 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2044 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2045
2046 extern unsigned long pci_cardbus_io_size;
2047 extern unsigned long pci_cardbus_mem_size;
2048 extern u8 pci_dfl_cache_line_size;
2049 extern u8 pci_cache_line_size;
2050
2051 /* Architecture-specific versions may override these (weak) */
2052 void pcibios_disable_device(struct pci_dev *dev);
2053 void pcibios_set_master(struct pci_dev *dev);
2054 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2055 enum pcie_reset_state state);
2056 int pcibios_add_device(struct pci_dev *dev);
2057 void pcibios_release_device(struct pci_dev *dev);
2058 #ifdef CONFIG_PCI
2059 void pcibios_penalize_isa_irq(int irq, int active);
2060 #else
pcibios_penalize_isa_irq(int irq,int active)2061 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2062 #endif
2063 int pcibios_alloc_irq(struct pci_dev *dev);
2064 void pcibios_free_irq(struct pci_dev *dev);
2065 resource_size_t pcibios_default_alignment(void);
2066
2067 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2068 void __init pci_mmcfg_early_init(void);
2069 void __init pci_mmcfg_late_init(void);
2070 #else
pci_mmcfg_early_init(void)2071 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2072 static inline void pci_mmcfg_late_init(void) { }
2073 #endif
2074
2075 int pci_ext_cfg_avail(void);
2076
2077 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2078 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2079
2080 #ifdef CONFIG_PCI_IOV
2081 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2082 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2083
2084 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2085 void pci_disable_sriov(struct pci_dev *dev);
2086
2087 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2088 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2089 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2090 int pci_num_vf(struct pci_dev *dev);
2091 int pci_vfs_assigned(struct pci_dev *dev);
2092 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2093 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2094 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2095 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2096 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2097
2098 /* Arch may override these (weak) */
2099 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2100 int pcibios_sriov_disable(struct pci_dev *pdev);
2101 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2102 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2103 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2104 {
2105 return -ENOSYS;
2106 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2107 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2108 {
2109 return -ENOSYS;
2110 }
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2111 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2112 { return -ENODEV; }
2113
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2114 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2115 struct pci_dev *virtfn, int id)
2116 {
2117 return -ENODEV;
2118 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2119 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2120 {
2121 return -ENOSYS;
2122 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2123 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2124 int id) { }
pci_disable_sriov(struct pci_dev * dev)2125 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2126 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2127 static inline int pci_vfs_assigned(struct pci_dev *dev)
2128 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2129 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2130 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2131 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2132 { return 0; }
2133 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2134 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2135 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2136 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2137 #endif
2138
2139 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2140 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2141 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2142 #endif
2143
2144 /**
2145 * pci_pcie_cap - get the saved PCIe capability offset
2146 * @dev: PCI device
2147 *
2148 * PCIe capability offset is calculated at PCI device initialization
2149 * time and saved in the data structure. This function returns saved
2150 * PCIe capability offset. Using this instead of pci_find_capability()
2151 * reduces unnecessary search in the PCI configuration space. If you
2152 * need to calculate PCIe capability offset from raw device for some
2153 * reasons, please use pci_find_capability() instead.
2154 */
pci_pcie_cap(struct pci_dev * dev)2155 static inline int pci_pcie_cap(struct pci_dev *dev)
2156 {
2157 return dev->pcie_cap;
2158 }
2159
2160 /**
2161 * pci_is_pcie - check if the PCI device is PCI Express capable
2162 * @dev: PCI device
2163 *
2164 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2165 */
pci_is_pcie(struct pci_dev * dev)2166 static inline bool pci_is_pcie(struct pci_dev *dev)
2167 {
2168 return pci_pcie_cap(dev);
2169 }
2170
2171 /**
2172 * pcie_caps_reg - get the PCIe Capabilities Register
2173 * @dev: PCI device
2174 */
pcie_caps_reg(const struct pci_dev * dev)2175 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2176 {
2177 return dev->pcie_flags_reg;
2178 }
2179
2180 /**
2181 * pci_pcie_type - get the PCIe device/port type
2182 * @dev: PCI device
2183 */
pci_pcie_type(const struct pci_dev * dev)2184 static inline int pci_pcie_type(const struct pci_dev *dev)
2185 {
2186 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2187 }
2188
2189 /**
2190 * pcie_find_root_port - Get the PCIe root port device
2191 * @dev: PCI device
2192 *
2193 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2194 * for a given PCI/PCIe Device.
2195 */
pcie_find_root_port(struct pci_dev * dev)2196 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2197 {
2198 while (dev) {
2199 if (pci_is_pcie(dev) &&
2200 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2201 return dev;
2202 dev = pci_upstream_bridge(dev);
2203 }
2204
2205 return NULL;
2206 }
2207
2208 void pci_request_acs(void);
2209 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2210 bool pci_acs_path_enabled(struct pci_dev *start,
2211 struct pci_dev *end, u16 acs_flags);
2212 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2213
2214 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2215 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2216
2217 /* Large Resource Data Type Tag Item Names */
2218 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2219 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2220 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2221
2222 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2223 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2224 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2225
2226 /* Small Resource Data Type Tag Item Names */
2227 #define PCI_VPD_STIN_END 0x0f /* End */
2228
2229 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2230
2231 #define PCI_VPD_SRDT_TIN_MASK 0x78
2232 #define PCI_VPD_SRDT_LEN_MASK 0x07
2233 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2234
2235 #define PCI_VPD_LRDT_TAG_SIZE 3
2236 #define PCI_VPD_SRDT_TAG_SIZE 1
2237
2238 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2239
2240 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2241 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2242 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2243 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2244 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2245
2246 /**
2247 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2248 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2249 *
2250 * Returns the extracted Large Resource Data Type length.
2251 */
pci_vpd_lrdt_size(const u8 * lrdt)2252 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2253 {
2254 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2255 }
2256
2257 /**
2258 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2259 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2260 *
2261 * Returns the extracted Large Resource Data Type Tag item.
2262 */
pci_vpd_lrdt_tag(const u8 * lrdt)2263 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2264 {
2265 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2266 }
2267
2268 /**
2269 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2270 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2271 *
2272 * Returns the extracted Small Resource Data Type length.
2273 */
pci_vpd_srdt_size(const u8 * srdt)2274 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2275 {
2276 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2277 }
2278
2279 /**
2280 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2281 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2282 *
2283 * Returns the extracted Small Resource Data Type Tag Item.
2284 */
pci_vpd_srdt_tag(const u8 * srdt)2285 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2286 {
2287 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2288 }
2289
2290 /**
2291 * pci_vpd_info_field_size - Extracts the information field length
2292 * @info_field: Pointer to the beginning of an information field header
2293 *
2294 * Returns the extracted information field length.
2295 */
pci_vpd_info_field_size(const u8 * info_field)2296 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2297 {
2298 return info_field[2];
2299 }
2300
2301 /**
2302 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2303 * @buf: Pointer to buffered vpd data
2304 * @off: The offset into the buffer at which to begin the search
2305 * @len: The length of the vpd buffer
2306 * @rdt: The Resource Data Type to search for
2307 *
2308 * Returns the index where the Resource Data Type was found or
2309 * -ENOENT otherwise.
2310 */
2311 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2312
2313 /**
2314 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2315 * @buf: Pointer to buffered vpd data
2316 * @off: The offset into the buffer at which to begin the search
2317 * @len: The length of the buffer area, relative to off, in which to search
2318 * @kw: The keyword to search for
2319 *
2320 * Returns the index where the information field keyword was found or
2321 * -ENOENT otherwise.
2322 */
2323 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2324 unsigned int len, const char *kw);
2325
2326 /* PCI <-> OF binding helpers */
2327 #ifdef CONFIG_OF
2328 struct device_node;
2329 struct irq_domain;
2330 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2331
2332 /* Arch may override this (weak) */
2333 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2334
2335 #else /* CONFIG_OF */
2336 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2337 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2338 #endif /* CONFIG_OF */
2339
2340 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2341 pci_device_to_OF_node(const struct pci_dev *pdev)
2342 {
2343 return pdev ? pdev->dev.of_node : NULL;
2344 }
2345
pci_bus_to_OF_node(struct pci_bus * bus)2346 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2347 {
2348 return bus ? bus->dev.of_node : NULL;
2349 }
2350
2351 #ifdef CONFIG_ACPI
2352 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2353
2354 void
2355 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2356 bool pci_pr3_present(struct pci_dev *pdev);
2357 #else
2358 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2359 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2360 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2361 #endif
2362
2363 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2364 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2365 {
2366 return pdev->dev.archdata.edev;
2367 }
2368 #endif
2369
2370 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2371 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2372 int pci_for_each_dma_alias(struct pci_dev *pdev,
2373 int (*fn)(struct pci_dev *pdev,
2374 u16 alias, void *data), void *data);
2375
2376 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2377 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2378 {
2379 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2380 }
pci_clear_dev_assigned(struct pci_dev * pdev)2381 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2382 {
2383 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2384 }
pci_is_dev_assigned(struct pci_dev * pdev)2385 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2386 {
2387 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2388 }
2389
2390 /**
2391 * pci_ari_enabled - query ARI forwarding status
2392 * @bus: the PCI bus
2393 *
2394 * Returns true if ARI forwarding is enabled.
2395 */
pci_ari_enabled(struct pci_bus * bus)2396 static inline bool pci_ari_enabled(struct pci_bus *bus)
2397 {
2398 return bus->self && bus->self->ari_enabled;
2399 }
2400
2401 /**
2402 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2403 * @pdev: PCI device to check
2404 *
2405 * Walk upwards from @pdev and check for each encountered bridge if it's part
2406 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2407 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2408 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2409 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2410 {
2411 struct pci_dev *parent = pdev;
2412
2413 if (pdev->is_thunderbolt)
2414 return true;
2415
2416 while ((parent = pci_upstream_bridge(parent)))
2417 if (parent->is_thunderbolt)
2418 return true;
2419
2420 return false;
2421 }
2422
2423 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2424 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2425 #endif
2426
2427 /* Provide the legacy pci_dma_* API */
2428 #include <linux/pci-dma-compat.h>
2429
2430 #define pci_printk(level, pdev, fmt, arg...) \
2431 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2432
2433 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2434 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2435 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2436 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2437 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2438 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2439 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2440 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2441
2442 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2443 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2444
2445 #define pci_info_ratelimited(pdev, fmt, arg...) \
2446 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2447
2448 #define pci_WARN(pdev, condition, fmt, arg...) \
2449 WARN(condition, "%s %s: " fmt, \
2450 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2451
2452 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2453 WARN_ONCE(condition, "%s %s: " fmt, \
2454 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2455
2456 #endif /* LINUX_PCI_H */
2457