| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 69 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
117 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
234 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
494 unsigned PredReg; in rewriteT2FrameIndex() local
709 unsigned &PredReg) { in getITInstrPredicate()
730 unsigned &PredReg) { in getVPTInstrPredicate()
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| D | ARMLoadStoreOptimizer.cpp | 486 unsigned PredReg) { in UpdateBaseRegUses()
626 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
833 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble()
903 unsigned PredReg = 0; in MergeOpsUpdate() local
1187 ARMCC::CondCodes Pred, unsigned PredReg) { in isIncrementOrDecrement()
1219 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecBefore()
1239 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecAfter()
1273 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local
1415 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local
1528 unsigned PredReg; in MergeBaseUpdateLSDouble() local
[all …]
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| D | Thumb2SizeReduction.cpp | 471 Register PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
679 unsigned PredReg = 0; in ReduceSpecial() local
721 unsigned PredReg = 0; in ReduceSpecial() local
792 unsigned PredReg = 0; in ReduceTo2Addr() local
885 unsigned PredReg = 0; in ReduceToNarrow() local
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| D | ThumbRegisterInfo.cpp | 65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
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| D | MVEVPTBlockPass.cpp | 103 unsigned PredReg = 0; in InsertVPTBlocks() local
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| D | Thumb2ITBlockPass.cpp | 202 unsigned PredReg = 0; in InsertITInstructions() local
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| D | ARMBaseRegisterInfo.cpp | 461 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
811 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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| D | MLxExpansionPass.cpp | 282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
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| D | ARMConstantIslandPass.cpp | 1368 PredReg = 0; in createNewWater() local
1413 unsigned PredReg = 0; in createNewWater() local
1437 unsigned PredReg; in createNewWater() local
1871 unsigned PredReg = 0; in optimizeThumb2Branches() local
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| D | ARMFrameLowering.cpp | 170 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate()
184 unsigned PredReg = 0) { in emitSPUpdate()
2174 unsigned PredReg = TII.getFramePred(Old); in eliminateCallFramePseudoInstr() local
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| D | ARMBaseInstrInfo.cpp | 2123 unsigned &PredReg) { in getInstrPredicate()
2153 unsigned PredReg = 0; in commuteInstructionImpl() local
2358 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate()
5405 unsigned PredReg = 0; in findCMPToFoldIntoCBZ() local
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| D | ARMISelDAGToDAG.cpp | 1684 SDValue PredReg; in tryMVEIndexedLoad() local
3677 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
3700 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
3722 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
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| D | ARMExpandPseudoInsts.cpp | 830 unsigned PredReg = 0; in ExpandMOV32BitImm() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 66 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, in initReg()
88 unsigned PredReg = Hexagon::NoRegister; in init() local
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| D | HexagonMCDuplexInfo.cpp | 191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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| D | HexagonMCCompound.cpp | 176 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonGenPredicate.cpp | 322 bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) { in isScalarPred()
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| D | HexagonInstrInfo.cpp | 1591 unsigned PredReg, PredRegPos, PredRegFlags; in PredicateInstruction() local
4261 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg()
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| D | HexagonHardwareLoops.cpp | 648 unsigned PredReg, PredPos, PredRegFlags; in getLoopTripCount() local
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