1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * 6 * Authors: 7 * Santosh Yaraganavi <santosh.sy@samsung.com> 8 * Vinayak Holikatti <h.vinayak@samsung.com> 9 */ 10 11 #ifndef _UFSHCI_H 12 #define _UFSHCI_H 13 14 enum { 15 TASK_REQ_UPIU_SIZE_DWORDS = 8, 16 TASK_RSP_UPIU_SIZE_DWORDS = 8, 17 ALIGNED_UPIU_SIZE = 512, 18 }; 19 20 /* UFSHCI Registers */ 21 enum { 22 REG_CONTROLLER_CAPABILITIES = 0x00, 23 REG_UFS_VERSION = 0x08, 24 REG_CONTROLLER_DEV_ID = 0x10, 25 REG_CONTROLLER_PROD_ID = 0x14, 26 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, 27 REG_INTERRUPT_STATUS = 0x20, 28 REG_INTERRUPT_ENABLE = 0x24, 29 REG_CONTROLLER_STATUS = 0x30, 30 REG_CONTROLLER_ENABLE = 0x34, 31 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, 32 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, 33 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, 34 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, 35 REG_UIC_ERROR_CODE_DME = 0x48, 36 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, 37 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, 38 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, 39 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, 40 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, 41 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, 42 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, 43 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, 44 REG_UTP_TASK_REQ_DOOR_BELL = 0x78, 45 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, 46 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, 47 REG_UIC_COMMAND = 0x90, 48 REG_UIC_COMMAND_ARG_1 = 0x94, 49 REG_UIC_COMMAND_ARG_2 = 0x98, 50 REG_UIC_COMMAND_ARG_3 = 0x9C, 51 52 UFSHCI_REG_SPACE_SIZE = 0xA0, 53 54 REG_UFS_CCAP = 0x100, 55 REG_UFS_CRYPTOCAP = 0x104, 56 57 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, 58 }; 59 60 /* Controller capability masks */ 61 enum { 62 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, 63 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, 64 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, 65 MASK_64_ADDRESSING_SUPPORT = 0x01000000, 66 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, 67 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, 68 MASK_CRYPTO_SUPPORT = 0x10000000, 69 }; 70 71 #define UFS_MASK(mask, offset) ((mask) << (offset)) 72 73 /* UFS Version 08h */ 74 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) 75 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) 76 77 /* Controller UFSHCI version */ 78 enum { 79 UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */ 80 UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */ 81 UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */ 82 UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */ 83 }; 84 85 /* 86 * HCDDID - Host Controller Identification Descriptor 87 * - Device ID and Device Class 10h 88 */ 89 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0) 90 #define DEVICE_ID UFS_MASK(0xFF, 24) 91 92 /* 93 * HCPMID - Host Controller Identification Descriptor 94 * - Product/Manufacturer ID 14h 95 */ 96 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) 97 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) 98 99 /* AHIT - Auto-Hibernate Idle Timer */ 100 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0) 101 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10) 102 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10 103 #define UFSHCI_AHIBERN8_MAX (1023 * 100000) 104 105 /* 106 * IS - Interrupt Status - 20h 107 */ 108 #define UTP_TRANSFER_REQ_COMPL 0x1 109 #define UIC_DME_END_PT_RESET 0x2 110 #define UIC_ERROR 0x4 111 #define UIC_TEST_MODE 0x8 112 #define UIC_POWER_MODE 0x10 113 #define UIC_HIBERNATE_EXIT 0x20 114 #define UIC_HIBERNATE_ENTER 0x40 115 #define UIC_LINK_LOST 0x80 116 #define UIC_LINK_STARTUP 0x100 117 #define UTP_TASK_REQ_COMPL 0x200 118 #define UIC_COMMAND_COMPL 0x400 119 #define DEVICE_FATAL_ERROR 0x800 120 #define CONTROLLER_FATAL_ERROR 0x10000 121 #define SYSTEM_BUS_FATAL_ERROR 0x20000 122 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000 123 124 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ 125 UIC_HIBERNATE_EXIT) 126 127 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\ 128 UIC_POWER_MODE) 129 130 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK) 131 132 #define UFSHCD_ERROR_MASK (UIC_ERROR |\ 133 DEVICE_FATAL_ERROR |\ 134 CONTROLLER_FATAL_ERROR |\ 135 SYSTEM_BUS_FATAL_ERROR |\ 136 CRYPTO_ENGINE_FATAL_ERROR) 137 138 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ 139 CONTROLLER_FATAL_ERROR |\ 140 SYSTEM_BUS_FATAL_ERROR |\ 141 CRYPTO_ENGINE_FATAL_ERROR) 142 143 /* HCS - Host Controller Status 30h */ 144 #define DEVICE_PRESENT 0x1 145 #define UTP_TRANSFER_REQ_LIST_READY 0x2 146 #define UTP_TASK_REQ_LIST_READY 0x4 147 #define UIC_COMMAND_READY 0x8 148 #define HOST_ERROR_INDICATOR 0x10 149 #define DEVICE_ERROR_INDICATOR 0x20 150 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) 151 152 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ 153 UTP_TASK_REQ_LIST_READY |\ 154 UIC_COMMAND_READY) 155 156 enum { 157 PWR_OK = 0x0, 158 PWR_LOCAL = 0x01, 159 PWR_REMOTE = 0x02, 160 PWR_BUSY = 0x03, 161 PWR_ERROR_CAP = 0x04, 162 PWR_FATAL_ERROR = 0x05, 163 }; 164 165 /* HCE - Host Controller Enable 34h */ 166 #define CONTROLLER_ENABLE 0x1 167 #define CONTROLLER_DISABLE 0x0 168 #define CRYPTO_GENERAL_ENABLE 0x2 169 170 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ 171 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000 172 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F 173 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF 174 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10 175 176 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */ 177 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000 178 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF 179 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2 180 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4 181 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8 182 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20 183 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 184 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001 185 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002 186 187 /* UECN - Host UIC Error Code Network Layer 40h */ 188 #define UIC_NETWORK_LAYER_ERROR 0x80000000 189 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 190 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1 191 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2 192 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4 193 194 /* UECT - Host UIC Error Code Transport Layer 44h */ 195 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000 196 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F 197 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1 198 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2 199 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4 200 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8 201 #define UIC_TRANSPORT_BAD_TC 0x10 202 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20 203 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40 204 205 /* UECDME - Host UIC Error Code DME 48h */ 206 #define UIC_DME_ERROR 0x80000000 207 #define UIC_DME_ERROR_CODE_MASK 0x1 208 209 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */ 210 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF 211 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) 212 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000 213 #define INT_AGGR_STATUS_BIT 0x100000 214 #define INT_AGGR_PARAM_WRITE 0x1000000 215 #define INT_AGGR_ENABLE 0x80000000 216 217 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ 218 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 219 220 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ 221 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 222 223 /* UICCMD - UIC Command */ 224 #define COMMAND_OPCODE_MASK 0xFF 225 #define GEN_SELECTOR_INDEX_MASK 0xFFFF 226 227 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) 228 #define RESET_LEVEL 0xFF 229 230 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) 231 #define CONFIG_RESULT_CODE_MASK 0xFF 232 #define GENERIC_ERROR_CODE_MASK 0xFF 233 234 /* GenSelectorIndex calculation macros for M-PHY attributes */ 235 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) 236 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) 237 238 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 239 ((sel) & 0xFFFF)) 240 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 241 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 242 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 243 244 /* Link Status*/ 245 enum link_status { 246 UFSHCD_LINK_IS_DOWN = 1, 247 UFSHCD_LINK_IS_UP = 2, 248 }; 249 250 /* UIC Commands */ 251 enum uic_cmd_dme { 252 UIC_CMD_DME_GET = 0x01, 253 UIC_CMD_DME_SET = 0x02, 254 UIC_CMD_DME_PEER_GET = 0x03, 255 UIC_CMD_DME_PEER_SET = 0x04, 256 UIC_CMD_DME_POWERON = 0x10, 257 UIC_CMD_DME_POWEROFF = 0x11, 258 UIC_CMD_DME_ENABLE = 0x12, 259 UIC_CMD_DME_RESET = 0x14, 260 UIC_CMD_DME_END_PT_RST = 0x15, 261 UIC_CMD_DME_LINK_STARTUP = 0x16, 262 UIC_CMD_DME_HIBER_ENTER = 0x17, 263 UIC_CMD_DME_HIBER_EXIT = 0x18, 264 UIC_CMD_DME_TEST_MODE = 0x1A, 265 }; 266 267 /* UIC Config result code / Generic error code */ 268 enum { 269 UIC_CMD_RESULT_SUCCESS = 0x00, 270 UIC_CMD_RESULT_INVALID_ATTR = 0x01, 271 UIC_CMD_RESULT_FAILURE = 0x01, 272 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, 273 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, 274 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, 275 UIC_CMD_RESULT_BAD_INDEX = 0x05, 276 UIC_CMD_RESULT_LOCKED_ATTR = 0x06, 277 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, 278 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, 279 UIC_CMD_RESULT_BUSY = 0x09, 280 UIC_CMD_RESULT_DME_FAILURE = 0x0A, 281 }; 282 283 #define MASK_UIC_COMMAND_RESULT 0xFF 284 285 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8) 286 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0) 287 288 /* Interrupt disable masks */ 289 enum { 290 /* Interrupt disable mask for UFSHCI v1.0 */ 291 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF, 292 INTERRUPT_MASK_RW_VER_10 = 0x30000, 293 294 /* Interrupt disable mask for UFSHCI v1.1 */ 295 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, 296 297 /* Interrupt disable mask for UFSHCI v2.1 */ 298 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, 299 }; 300 301 /* CCAP - Crypto Capability 100h */ 302 union ufs_crypto_capabilities { 303 __le32 reg_val; 304 struct { 305 u8 num_crypto_cap; 306 u8 config_count; 307 u8 reserved; 308 u8 config_array_ptr; 309 }; 310 }; 311 312 enum ufs_crypto_key_size { 313 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0, 314 UFS_CRYPTO_KEY_SIZE_128 = 0x1, 315 UFS_CRYPTO_KEY_SIZE_192 = 0x2, 316 UFS_CRYPTO_KEY_SIZE_256 = 0x3, 317 UFS_CRYPTO_KEY_SIZE_512 = 0x4, 318 }; 319 320 enum ufs_crypto_alg { 321 UFS_CRYPTO_ALG_AES_XTS = 0x0, 322 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, 323 UFS_CRYPTO_ALG_AES_ECB = 0x2, 324 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, 325 }; 326 327 /* x-CRYPTOCAP - Crypto Capability X */ 328 union ufs_crypto_cap_entry { 329 __le32 reg_val; 330 struct { 331 u8 algorithm_id; 332 u8 sdus_mask; /* Supported data unit size mask */ 333 u8 key_size; 334 u8 reserved; 335 }; 336 }; 337 338 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7) 339 #define UFS_CRYPTO_KEY_MAX_SIZE 64 340 /* x-CRYPTOCFG - Crypto Configuration X */ 341 union ufs_crypto_cfg_entry { 342 __le32 reg_val[32]; 343 struct { 344 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE]; 345 u8 data_unit_size; 346 u8 crypto_cap_idx; 347 u8 reserved_1; 348 u8 config_enable; 349 u8 reserved_multi_host; 350 u8 reserved_2; 351 u8 vsb[2]; 352 u8 reserved_3[56]; 353 }; 354 }; 355 356 /* 357 * Request Descriptor Definitions 358 */ 359 360 /* Transfer request command type */ 361 enum { 362 UTP_CMD_TYPE_SCSI = 0x0, 363 UTP_CMD_TYPE_UFS = 0x1, 364 UTP_CMD_TYPE_DEV_MANAGE = 0x2, 365 }; 366 367 /* To accommodate UFS2.0 required Command type */ 368 enum { 369 UTP_CMD_TYPE_UFS_STORAGE = 0x1, 370 }; 371 372 enum { 373 UTP_SCSI_COMMAND = 0x00000000, 374 UTP_NATIVE_UFS_COMMAND = 0x10000000, 375 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, 376 UTP_REQ_DESC_INT_CMD = 0x01000000, 377 UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000, 378 }; 379 380 /* UTP Transfer Request Data Direction (DD) */ 381 enum { 382 UTP_NO_DATA_TRANSFER = 0x00000000, 383 UTP_HOST_TO_DEVICE = 0x02000000, 384 UTP_DEVICE_TO_HOST = 0x04000000, 385 }; 386 387 /* Overall command status values */ 388 enum { 389 OCS_SUCCESS = 0x0, 390 OCS_INVALID_CMD_TABLE_ATTR = 0x1, 391 OCS_INVALID_PRDT_ATTR = 0x2, 392 OCS_MISMATCH_DATA_BUF_SIZE = 0x3, 393 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, 394 OCS_PEER_COMM_FAILURE = 0x5, 395 OCS_ABORTED = 0x6, 396 OCS_FATAL_ERROR = 0x7, 397 OCS_DEVICE_FATAL_ERROR = 0x8, 398 OCS_INVALID_CRYPTO_CONFIG = 0x9, 399 OCS_GENERAL_CRYPTO_ERROR = 0xA, 400 OCS_INVALID_COMMAND_STATUS = 0x0F, 401 MASK_OCS = 0x0F, 402 }; 403 404 /* The maximum length of the data byte count field in the PRDT is 256KB */ 405 #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024) 406 /* The granularity of the data byte count field in the PRDT is 32-bit */ 407 #define PRDT_DATA_BYTE_COUNT_PAD 4 408 409 /** 410 * struct ufshcd_sg_entry - UFSHCI PRD Entry 411 * @base_addr: Lower 32bit physical address DW-0 412 * @upper_addr: Upper 32bit physical address DW-1 413 * @reserved: Reserved for future use DW-2 414 * @size: size of physical segment DW-3 415 */ 416 struct ufshcd_sg_entry { 417 __le32 base_addr; 418 __le32 upper_addr; 419 __le32 reserved; 420 __le32 size; 421 }; 422 423 /** 424 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure 425 * @command_upiu: Command UPIU Frame address 426 * @response_upiu: Response UPIU Frame address 427 * @prd_table: Physical Region Descriptor 428 */ 429 struct utp_transfer_cmd_desc { 430 u8 command_upiu[ALIGNED_UPIU_SIZE]; 431 u8 response_upiu[ALIGNED_UPIU_SIZE]; 432 struct ufshcd_sg_entry prd_table[SG_ALL]; 433 }; 434 435 /** 436 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD 437 * @dword0: Descriptor Header DW0 438 * @dword1: Descriptor Header DW1 439 * @dword2: Descriptor Header DW2 440 * @dword3: Descriptor Header DW3 441 */ 442 struct request_desc_header { 443 __le32 dword_0; 444 __le32 dword_1; 445 __le32 dword_2; 446 __le32 dword_3; 447 }; 448 449 /** 450 * struct utp_transfer_req_desc - UTRD structure 451 * @header: UTRD header DW-0 to DW-3 452 * @command_desc_base_addr_lo: UCD base address low DW-4 453 * @command_desc_base_addr_hi: UCD base address high DW-5 454 * @response_upiu_length: response UPIU length DW-6 455 * @response_upiu_offset: response UPIU offset DW-6 456 * @prd_table_length: Physical region descriptor length DW-7 457 * @prd_table_offset: Physical region descriptor offset DW-7 458 */ 459 struct utp_transfer_req_desc { 460 461 /* DW 0-3 */ 462 struct request_desc_header header; 463 464 /* DW 4-5*/ 465 __le32 command_desc_base_addr_lo; 466 __le32 command_desc_base_addr_hi; 467 468 /* DW 6 */ 469 __le16 response_upiu_length; 470 __le16 response_upiu_offset; 471 472 /* DW 7 */ 473 __le16 prd_table_length; 474 __le16 prd_table_offset; 475 }; 476 477 /* 478 * UTMRD structure. 479 */ 480 struct utp_task_req_desc { 481 /* DW 0-3 */ 482 struct request_desc_header header; 483 484 /* DW 4-11 - Task request UPIU structure */ 485 struct utp_upiu_header req_header; 486 __be32 input_param1; 487 __be32 input_param2; 488 __be32 input_param3; 489 __be32 __reserved1[2]; 490 491 /* DW 12-19 - Task Management Response UPIU structure */ 492 struct utp_upiu_header rsp_header; 493 __be32 output_param1; 494 __be32 output_param2; 495 __be32 __reserved2[3]; 496 }; 497 498 #endif /* End of Header */ 499