1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_PARISC_ROPES_H_
3 #define _ASM_PARISC_ROPES_H_
4
5 #include <asm/parisc-device.h>
6
7 #ifdef CONFIG_64BIT
8 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
9 #define ZX1_SUPPORT
10 #endif
11
12 #ifdef CONFIG_PROC_FS
13 /* depends on proc fs support. But costs CPU performance */
14 #undef SBA_COLLECT_STATS
15 #endif
16
17 /*
18 ** The number of pdir entries to "free" before issuing
19 ** a read to PCOM register to flush out PCOM writes.
20 ** Interacts with allocation granularity (ie 4 or 8 entries
21 ** allocated and free'd/purged at a time might make this
22 ** less interesting).
23 */
24 #define DELAYED_RESOURCE_CNT 16
25
26 #define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
27 #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
28
29 struct ioc {
30 void __iomem *ioc_hpa; /* I/O MMU base address */
31 char *res_map; /* resource map, bit == pdir entry */
32 u64 *pdir_base; /* physical base address */
33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
35 #ifdef ZX1_SUPPORT
36 unsigned long iovp_mask; /* help convert IOVA to IOVP */
37 #endif
38 unsigned long *res_hint; /* next avail IOVP - circular search */
39 spinlock_t res_lock;
40 unsigned int res_bitshift; /* from the LEFT! */
41 unsigned int res_size; /* size of resource map in bytes */
42 #ifdef SBA_HINT_SUPPORT
43 /* FIXME : DMA HINTs not used */
44 unsigned long hint_mask_pdir; /* bits used for DMA hints */
45 unsigned int hint_shift_pdir;
46 #endif
47 #if DELAYED_RESOURCE_CNT > 0
48 int saved_cnt;
49 struct sba_dma_pair {
50 dma_addr_t iova;
51 size_t size;
52 } saved[DELAYED_RESOURCE_CNT];
53 #endif
54
55 #ifdef SBA_COLLECT_STATS
56 #define SBA_SEARCH_SAMPLE 0x100
57 unsigned long avg_search[SBA_SEARCH_SAMPLE];
58 unsigned long avg_idx; /* current index into avg_search */
59 unsigned long used_pages;
60 unsigned long msingle_calls;
61 unsigned long msingle_pages;
62 unsigned long msg_calls;
63 unsigned long msg_pages;
64 unsigned long usingle_calls;
65 unsigned long usingle_pages;
66 unsigned long usg_calls;
67 unsigned long usg_pages;
68 #endif
69 /* STUFF We don't need in performance path */
70 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
71 };
72
73 struct sba_device {
74 struct sba_device *next; /* list of SBA's in system */
75 struct parisc_device *dev; /* dev found in bus walk */
76 const char *name;
77 void __iomem *sba_hpa; /* base address */
78 spinlock_t sba_lock;
79 unsigned int flags; /* state/functionality enabled */
80 unsigned int hw_rev; /* HW revision of chip */
81
82 struct resource chip_resv; /* MMIO reserved for chip */
83 struct resource iommu_resv; /* MMIO reserved for iommu */
84
85 unsigned int num_ioc; /* number of on-board IOC's */
86 struct ioc ioc[MAX_IOC];
87 };
88
89 #define ASTRO_RUNWAY_PORT 0x582
90 #define IKE_MERCED_PORT 0x803
91 #define REO_MERCED_PORT 0x804
92 #define REOG_MERCED_PORT 0x805
93 #define PLUTO_MCKINLEY_PORT 0x880
94
IS_ASTRO(struct parisc_device * d)95 static inline int IS_ASTRO(struct parisc_device *d) {
96 return d->id.hversion == ASTRO_RUNWAY_PORT;
97 }
98
IS_IKE(struct parisc_device * d)99 static inline int IS_IKE(struct parisc_device *d) {
100 return d->id.hversion == IKE_MERCED_PORT;
101 }
102
IS_PLUTO(struct parisc_device * d)103 static inline int IS_PLUTO(struct parisc_device *d) {
104 return d->id.hversion == PLUTO_MCKINLEY_PORT;
105 }
106
107 #define PLUTO_IOVA_BASE (1UL*1024*1024*1024) /* 1GB */
108 #define PLUTO_IOVA_SIZE (1UL*1024*1024*1024) /* 1GB */
109 #define PLUTO_GART_SIZE (PLUTO_IOVA_SIZE / 2)
110
111 #define SBA_PDIR_VALID_BIT 0x8000000000000000ULL
112
113 #define SBA_AGPGART_COOKIE 0x0000badbadc0ffeeULL
114
115 #define SBA_FUNC_ID 0x0000 /* function id */
116 #define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
117
118 #define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
119
120 #define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
121 #define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
122 /* Ike's IOC's occupy functions 2 and 3 */
123 #define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
124
125 #define IOC_CTRL 0x8 /* IOC_CTRL offset */
126 #define IOC_CTRL_TC (1 << 0) /* TOC Enable */
127 #define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
128 #define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
129 #define IOC_CTRL_RM (1 << 8) /* Real Mode */
130 #define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
131 #define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
132 #define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
133
134 /*
135 ** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
136 ** Firmware programs this stuff. Don't touch it.
137 */
138 #define LMMIO_DIRECT0_BASE 0x300
139 #define LMMIO_DIRECT0_MASK 0x308
140 #define LMMIO_DIRECT0_ROUTE 0x310
141
142 #define LMMIO_DIST_BASE 0x360
143 #define LMMIO_DIST_MASK 0x368
144 #define LMMIO_DIST_ROUTE 0x370
145
146 #define IOS_DIST_BASE 0x390
147 #define IOS_DIST_MASK 0x398
148 #define IOS_DIST_ROUTE 0x3A0
149
150 #define IOS_DIRECT_BASE 0x3C0
151 #define IOS_DIRECT_MASK 0x3C8
152 #define IOS_DIRECT_ROUTE 0x3D0
153
154 /*
155 ** Offsets into I/O TLB (Function 2 and 3 on Ike)
156 */
157 #define ROPE0_CTL 0x200 /* "regbus pci0" */
158 #define ROPE1_CTL 0x208
159 #define ROPE2_CTL 0x210
160 #define ROPE3_CTL 0x218
161 #define ROPE4_CTL 0x220
162 #define ROPE5_CTL 0x228
163 #define ROPE6_CTL 0x230
164 #define ROPE7_CTL 0x238
165
166 #define IOC_ROPE0_CFG 0x500 /* pluto only */
167 #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
168
169 #define HF_ENABLE 0x40
170
171 #define IOC_IBASE 0x300 /* IO TLB */
172 #define IOC_IMASK 0x308
173 #define IOC_PCOM 0x310
174 #define IOC_TCNFG 0x318
175 #define IOC_PDIR_BASE 0x320
176
177 /*
178 ** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
179 ** It's safer (avoid memory corruption) to keep DMA page mappings
180 ** equivalently sized to VM PAGE_SIZE.
181 **
182 ** We really can't avoid generating a new mapping for each
183 ** page since the Virtual Coherence Index has to be generated
184 ** and updated for each page.
185 **
186 ** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
187 */
188 #define IOVP_SIZE PAGE_SIZE
189 #define IOVP_SHIFT PAGE_SHIFT
190 #define IOVP_MASK PAGE_MASK
191
192 #define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
193 #define SBA_PERF_MASK1 0x718
194 #define SBA_PERF_MASK2 0x730
195
196 /*
197 ** Offsets into PCI Performance Counters (functions 12 and 13)
198 ** Controlled by PERF registers in function 2 & 3 respectively.
199 */
200 #define SBA_PERF_CNT1 0x200
201 #define SBA_PERF_CNT2 0x208
202 #define SBA_PERF_CNT3 0x210
203
204 /*
205 ** lba_device: Per instance Elroy data structure
206 */
207 struct lba_device {
208 struct pci_hba_data hba;
209
210 spinlock_t lba_lock;
211 void *iosapic_obj;
212
213 #ifdef CONFIG_64BIT
214 void __iomem *iop_base; /* PA_VIEW - for IO port accessor funcs */
215 #endif
216
217 int flags; /* state/functionality enabled */
218 int hw_rev; /* HW revision of chip */
219 };
220
221 #define ELROY_HVERS 0x782
222 #define MERCURY_HVERS 0x783
223 #define QUICKSILVER_HVERS 0x784
224
IS_ELROY(struct parisc_device * d)225 static inline int IS_ELROY(struct parisc_device *d) {
226 return (d->id.hversion == ELROY_HVERS);
227 }
228
IS_MERCURY(struct parisc_device * d)229 static inline int IS_MERCURY(struct parisc_device *d) {
230 return (d->id.hversion == MERCURY_HVERS);
231 }
232
IS_QUICKSILVER(struct parisc_device * d)233 static inline int IS_QUICKSILVER(struct parisc_device *d) {
234 return (d->id.hversion == QUICKSILVER_HVERS);
235 }
236
agp_mode_mercury(void __iomem * hpa)237 static inline int agp_mode_mercury(void __iomem *hpa) {
238 u64 bus_mode;
239
240 bus_mode = readl(hpa + 0x0620);
241 if (bus_mode & 1)
242 return 1;
243
244 return 0;
245 }
246
247 /*
248 ** I/O SAPIC init function
249 ** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
250 ** Call setup as part of per instance initialization.
251 ** (ie *not* init_module() function unless only one is present.)
252 ** fixup_irq is to initialize PCI IRQ line support and
253 ** virtualize pcidev->irq value. To be called by pci_fixup_bus().
254 */
255 extern void *iosapic_register(unsigned long hpa);
256 extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
257
258 #define LBA_FUNC_ID 0x0000 /* function id */
259 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
260 #define LBA_CAPABLE 0x0030 /* capabilities register */
261
262 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
263 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
264
265 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
266 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
267 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
268
269 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
270 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
271 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
272 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
273
274 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
275
276 #define LBA_STAT_CTL 0x0108 /* Status & Control */
277 #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
278 #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
279 #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
280 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
281
282 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
283 #define LBA_LMMIO_MASK 0x0208
284
285 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
286 #define LBA_GMMIO_MASK 0x0218
287
288 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
289 #define LBA_WLMMIO_MASK 0x0228
290
291 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
292 #define LBA_WGMMIO_MASK 0x0238
293
294 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
295 #define LBA_IOS_MASK 0x0248
296
297 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
298 #define LBA_ELMMIO_MASK 0x0258
299
300 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
301 #define LBA_EIOS_MASK 0x0268
302
303 #define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
304 #define LBA_DMA_CTL 0x0278 /* firmware sets this */
305
306 #define LBA_IBASE 0x0300 /* SBA DMA support */
307 #define LBA_IMASK 0x0308
308
309 /* FIXME: ignore DMA Hint stuff until we can measure performance */
310 #define LBA_HINT_CFG 0x0310
311 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
312
313 #define LBA_BUS_MODE 0x0620
314
315 /* ERROR regs are needed for config cycle kluges */
316 #define LBA_ERROR_CONFIG 0x0680
317 #define LBA_SMART_MODE 0x20
318 #define LBA_ERROR_STATUS 0x0688
319 #define LBA_ROPE_CTL 0x06A0
320
321 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
322
323 #endif /*_ASM_PARISC_ROPES_H_*/
324