/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | A15SDOptimizer.cpp | 133 const TargetRegisterClass *TRC) { in usesRegClass() 270 const TargetRegisterClass *TRC = in optimizeSDPattern() local 435 const TargetRegisterClass *TRC) { in createExtractSubreg()
|
D | ARMLoadStoreOptimizer.cpp | 2330 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local
|
D | ARMBaseInstrInfo.cpp | 3299 const TargetRegisterClass *TRC = MRI->getRegClass(Reg); in FoldImmediate() local
|
D | ARMISelLowering.cpp | 9502 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass in SetupEntryBlockForSjLj() local 9616 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass in EmitSjLjDispatchBlock() local 10169 const TargetRegisterClass *TRC = nullptr; in EmitStructByval() local
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyAsmPrinter.cpp | 59 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 499 const TargetRegisterClass *TRC = in EmitSubregNode() local 654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
D | MachineIRBuilder.h | 72 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | MachineRegisterInfo.cpp | 502 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
|
D | RegAllocPBQP.cpp | 604 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
|
D | LiveDebugVariables.cpp | 1204 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg); in rewriteLocations() local
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86AvoidStoreForwardingBlocks.cpp | 566 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
|
D | X86ISelLowering.cpp | 31963 const TargetRegisterClass *TRC = in SetupEntryBlockForSjLj() local
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.h | 1055 const TargetRegisterClass &TRC, in isOfRegClass()
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCMIPeephole.cpp | 776 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode() local
|
D | PPCISelDAGToDAG.cpp | 321 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1); in SelectInlineAsmMemoryOperand() local
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
D | SystemZISelDAGToDAG.cpp | 1669 const TargetRegisterClass *TRC = in SelectInlineAsmMemoryOperand() local
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64ISelDAGToDAG.cpp | 316 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF); in SelectInlineAsmMemoryOperand() local
|
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfo.cpp | 1987 const TargetRegisterClass *TRC; in createVR() local
|