1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012-2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SYSREG_SR_H__
8 #define __ARM64_KVM_HYP_SYSREG_SR_H__
9
10 #include <linux/compiler.h>
11 #include <linux/kvm_host.h>
12
13 #include <asm/kprobes.h>
14 #include <asm/kvm_asm.h>
15 #include <asm/kvm_emulate.h>
16 #include <asm/kvm_hyp.h>
17
__sysreg_save_common_state(struct kvm_cpu_context * ctxt)18 static inline void __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
19 {
20 ctxt_sys_reg(ctxt, MDSCR_EL1) = read_sysreg(mdscr_el1);
21 }
22
__sysreg_save_user_state(struct kvm_cpu_context * ctxt)23 static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
24 {
25 ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0);
26 ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0);
27 }
28
__sysreg_save_el1_state(struct kvm_cpu_context * ctxt)29 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
30 {
31 ctxt_sys_reg(ctxt, CSSELR_EL1) = read_sysreg(csselr_el1);
32 ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR);
33 ctxt_sys_reg(ctxt, CPACR_EL1) = read_sysreg_el1(SYS_CPACR);
34 ctxt_sys_reg(ctxt, TTBR0_EL1) = read_sysreg_el1(SYS_TTBR0);
35 ctxt_sys_reg(ctxt, TTBR1_EL1) = read_sysreg_el1(SYS_TTBR1);
36 ctxt_sys_reg(ctxt, TCR_EL1) = read_sysreg_el1(SYS_TCR);
37 ctxt_sys_reg(ctxt, ESR_EL1) = read_sysreg_el1(SYS_ESR);
38 ctxt_sys_reg(ctxt, AFSR0_EL1) = read_sysreg_el1(SYS_AFSR0);
39 ctxt_sys_reg(ctxt, AFSR1_EL1) = read_sysreg_el1(SYS_AFSR1);
40 ctxt_sys_reg(ctxt, FAR_EL1) = read_sysreg_el1(SYS_FAR);
41 ctxt_sys_reg(ctxt, MAIR_EL1) = read_sysreg_el1(SYS_MAIR);
42 ctxt_sys_reg(ctxt, VBAR_EL1) = read_sysreg_el1(SYS_VBAR);
43 ctxt_sys_reg(ctxt, CONTEXTIDR_EL1) = read_sysreg_el1(SYS_CONTEXTIDR);
44 ctxt_sys_reg(ctxt, AMAIR_EL1) = read_sysreg_el1(SYS_AMAIR);
45 ctxt_sys_reg(ctxt, CNTKCTL_EL1) = read_sysreg_el1(SYS_CNTKCTL);
46 ctxt_sys_reg(ctxt, PAR_EL1) = read_sysreg_par();
47 ctxt_sys_reg(ctxt, TPIDR_EL1) = read_sysreg(tpidr_el1);
48
49 ctxt_sys_reg(ctxt, SP_EL1) = read_sysreg(sp_el1);
50 ctxt_sys_reg(ctxt, ELR_EL1) = read_sysreg_el1(SYS_ELR);
51 ctxt_sys_reg(ctxt, SPSR_EL1) = read_sysreg_el1(SYS_SPSR);
52 }
53
__sysreg_save_el2_return_state(struct kvm_cpu_context * ctxt)54 static inline void __sysreg_save_el2_return_state(struct kvm_cpu_context *ctxt)
55 {
56 ctxt->regs.pc = read_sysreg_el2(SYS_ELR);
57 /*
58 * Guest PSTATE gets saved at guest fixup time in all
59 * cases. We still need to handle the nVHE host side here.
60 */
61 if (!has_vhe() && ctxt->__hyp_running_vcpu)
62 ctxt->regs.pstate = read_sysreg_el2(SYS_SPSR);
63
64 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
65 ctxt_sys_reg(ctxt, DISR_EL1) = read_sysreg_s(SYS_VDISR_EL2);
66 }
67
__sysreg_restore_common_state(struct kvm_cpu_context * ctxt)68 static inline void __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
69 {
70 write_sysreg(ctxt_sys_reg(ctxt, MDSCR_EL1), mdscr_el1);
71 }
72
__sysreg_restore_user_state(struct kvm_cpu_context * ctxt)73 static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
74 {
75 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0);
76 write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0);
77 }
78
__sysreg_restore_el1_state(struct kvm_cpu_context * ctxt)79 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
80 {
81 write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2);
82 write_sysreg(ctxt_sys_reg(ctxt, CSSELR_EL1), csselr_el1);
83
84 if (has_vhe() ||
85 !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
86 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
87 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
88 } else if (!ctxt->__hyp_running_vcpu) {
89 /*
90 * Must only be done for guest registers, hence the context
91 * test. We're coming from the host, so SCTLR.M is already
92 * set. Pairs with nVHE's __activate_traps().
93 */
94 write_sysreg_el1((ctxt_sys_reg(ctxt, TCR_EL1) |
95 TCR_EPD1_MASK | TCR_EPD0_MASK),
96 SYS_TCR);
97 isb();
98 }
99
100 write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1), SYS_CPACR);
101 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1), SYS_TTBR0);
102 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1), SYS_TTBR1);
103 write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1), SYS_ESR);
104 write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL1), SYS_AFSR0);
105 write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL1), SYS_AFSR1);
106 write_sysreg_el1(ctxt_sys_reg(ctxt, FAR_EL1), SYS_FAR);
107 write_sysreg_el1(ctxt_sys_reg(ctxt, MAIR_EL1), SYS_MAIR);
108 write_sysreg_el1(ctxt_sys_reg(ctxt, VBAR_EL1), SYS_VBAR);
109 write_sysreg_el1(ctxt_sys_reg(ctxt, CONTEXTIDR_EL1), SYS_CONTEXTIDR);
110 write_sysreg_el1(ctxt_sys_reg(ctxt, AMAIR_EL1), SYS_AMAIR);
111 write_sysreg_el1(ctxt_sys_reg(ctxt, CNTKCTL_EL1), SYS_CNTKCTL);
112 write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1), par_el1);
113 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1), tpidr_el1);
114
115 if (!has_vhe() &&
116 cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT) &&
117 ctxt->__hyp_running_vcpu) {
118 /*
119 * Must only be done for host registers, hence the context
120 * test. Pairs with nVHE's __deactivate_traps().
121 */
122 isb();
123 /*
124 * At this stage, and thanks to the above isb(), S2 is
125 * deconfigured and disabled. We can now restore the host's
126 * S1 configuration: SCTLR, and only then TCR.
127 */
128 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
129 isb();
130 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
131 }
132
133 write_sysreg(ctxt_sys_reg(ctxt, SP_EL1), sp_el1);
134 write_sysreg_el1(ctxt_sys_reg(ctxt, ELR_EL1), SYS_ELR);
135 write_sysreg_el1(ctxt_sys_reg(ctxt, SPSR_EL1), SYS_SPSR);
136 }
137
__sysreg_restore_el2_return_state(struct kvm_cpu_context * ctxt)138 static inline void __sysreg_restore_el2_return_state(struct kvm_cpu_context *ctxt)
139 {
140 u64 pstate = ctxt->regs.pstate;
141 u64 mode = pstate & PSR_AA32_MODE_MASK;
142
143 /*
144 * Safety check to ensure we're setting the CPU up to enter the guest
145 * in a less privileged mode.
146 *
147 * If we are attempting a return to EL2 or higher in AArch64 state,
148 * program SPSR_EL2 with M=EL2h and the IL bit set which ensures that
149 * we'll take an illegal exception state exception immediately after
150 * the ERET to the guest. Attempts to return to AArch32 Hyp will
151 * result in an illegal exception return because EL2's execution state
152 * is determined by SCR_EL3.RW.
153 */
154 if (!(mode & PSR_MODE32_BIT) && mode >= PSR_MODE_EL2t)
155 pstate = PSR_MODE_EL2h | PSR_IL_BIT;
156
157 write_sysreg_el2(ctxt->regs.pc, SYS_ELR);
158 write_sysreg_el2(pstate, SYS_SPSR);
159
160 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
161 write_sysreg_s(ctxt_sys_reg(ctxt, DISR_EL1), SYS_VDISR_EL2);
162 }
163
__sysreg32_save_state(struct kvm_vcpu * vcpu)164 static inline void __sysreg32_save_state(struct kvm_vcpu *vcpu)
165 {
166 if (!vcpu_el1_is_32bit(vcpu))
167 return;
168
169 vcpu->arch.ctxt.spsr_abt = read_sysreg(spsr_abt);
170 vcpu->arch.ctxt.spsr_und = read_sysreg(spsr_und);
171 vcpu->arch.ctxt.spsr_irq = read_sysreg(spsr_irq);
172 vcpu->arch.ctxt.spsr_fiq = read_sysreg(spsr_fiq);
173
174 __vcpu_sys_reg(vcpu, DACR32_EL2) = read_sysreg(dacr32_el2);
175 __vcpu_sys_reg(vcpu, IFSR32_EL2) = read_sysreg(ifsr32_el2);
176
177 if (has_vhe() || vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)
178 __vcpu_sys_reg(vcpu, DBGVCR32_EL2) = read_sysreg(dbgvcr32_el2);
179 }
180
__sysreg32_restore_state(struct kvm_vcpu * vcpu)181 static inline void __sysreg32_restore_state(struct kvm_vcpu *vcpu)
182 {
183 if (!vcpu_el1_is_32bit(vcpu))
184 return;
185
186 write_sysreg(vcpu->arch.ctxt.spsr_abt, spsr_abt);
187 write_sysreg(vcpu->arch.ctxt.spsr_und, spsr_und);
188 write_sysreg(vcpu->arch.ctxt.spsr_irq, spsr_irq);
189 write_sysreg(vcpu->arch.ctxt.spsr_fiq, spsr_fiq);
190
191 write_sysreg(__vcpu_sys_reg(vcpu, DACR32_EL2), dacr32_el2);
192 write_sysreg(__vcpu_sys_reg(vcpu, IFSR32_EL2), ifsr32_el2);
193
194 if (has_vhe() || vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)
195 write_sysreg(__vcpu_sys_reg(vcpu, DBGVCR32_EL2), dbgvcr32_el2);
196 }
197
198 #endif /* __ARM64_KVM_HYP_SYSREG_SR_H__ */
199