1 /*
2 * Copyright © 2018 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include "aco_ir.h"
26
27 #include "util/memstream.h"
28
29 #include <array>
30 #include <map>
31 #include <set>
32 #include <vector>
33
34 namespace aco {
35
36 static void
aco_log(Program * program,enum radv_compiler_debug_level level,const char * prefix,const char * file,unsigned line,const char * fmt,va_list args)37 aco_log(Program* program, enum radv_compiler_debug_level level, const char* prefix,
38 const char* file, unsigned line, const char* fmt, va_list args)
39 {
40 char* msg;
41
42 if (program->debug.shorten_messages) {
43 msg = ralloc_vasprintf(NULL, fmt, args);
44 } else {
45 msg = ralloc_strdup(NULL, prefix);
46 ralloc_asprintf_append(&msg, " In file %s:%u\n", file, line);
47 ralloc_asprintf_append(&msg, " ");
48 ralloc_vasprintf_append(&msg, fmt, args);
49 }
50
51 if (program->debug.func)
52 program->debug.func(program->debug.private_data, level, msg);
53
54 fprintf(program->debug.output, "%s\n", msg);
55
56 ralloc_free(msg);
57 }
58
59 void
_aco_perfwarn(Program * program,const char * file,unsigned line,const char * fmt,...)60 _aco_perfwarn(Program* program, const char* file, unsigned line, const char* fmt, ...)
61 {
62 va_list args;
63
64 va_start(args, fmt);
65 aco_log(program, RADV_COMPILER_DEBUG_LEVEL_PERFWARN, "ACO PERFWARN:\n", file, line, fmt, args);
66 va_end(args);
67 }
68
69 void
_aco_err(Program * program,const char * file,unsigned line,const char * fmt,...)70 _aco_err(Program* program, const char* file, unsigned line, const char* fmt, ...)
71 {
72 va_list args;
73
74 va_start(args, fmt);
75 aco_log(program, RADV_COMPILER_DEBUG_LEVEL_ERROR, "ACO ERROR:\n", file, line, fmt, args);
76 va_end(args);
77 }
78
79 bool
validate_ir(Program * program)80 validate_ir(Program* program)
81 {
82 bool is_valid = true;
83 auto check = [&program, &is_valid](bool success, const char* msg,
84 aco::Instruction* instr) -> void
85 {
86 if (!success) {
87 char* out;
88 size_t outsize;
89 struct u_memstream mem;
90 u_memstream_open(&mem, &out, &outsize);
91 FILE* const memf = u_memstream_get(&mem);
92
93 fprintf(memf, "%s: ", msg);
94 aco_print_instr(instr, memf);
95 u_memstream_close(&mem);
96
97 aco_err(program, "%s", out);
98 free(out);
99
100 is_valid = false;
101 }
102 };
103
104 auto check_block = [&program, &is_valid](bool success, const char* msg,
105 aco::Block* block) -> void
106 {
107 if (!success) {
108 aco_err(program, "%s: BB%u", msg, block->index);
109 is_valid = false;
110 }
111 };
112
113 for (Block& block : program->blocks) {
114 for (aco_ptr<Instruction>& instr : block.instructions) {
115
116 /* check base format */
117 Format base_format = instr->format;
118 base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::SDWA);
119 base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::DPP);
120 if ((uint32_t)base_format & (uint32_t)Format::VOP1)
121 base_format = Format::VOP1;
122 else if ((uint32_t)base_format & (uint32_t)Format::VOP2)
123 base_format = Format::VOP2;
124 else if ((uint32_t)base_format & (uint32_t)Format::VOPC)
125 base_format = Format::VOPC;
126 else if ((uint32_t)base_format & (uint32_t)Format::VINTRP) {
127 if (instr->opcode == aco_opcode::v_interp_p1ll_f16 ||
128 instr->opcode == aco_opcode::v_interp_p1lv_f16 ||
129 instr->opcode == aco_opcode::v_interp_p2_legacy_f16 ||
130 instr->opcode == aco_opcode::v_interp_p2_f16) {
131 /* v_interp_*_fp16 are considered VINTRP by the compiler but
132 * they are emitted as VOP3.
133 */
134 base_format = Format::VOP3;
135 } else {
136 base_format = Format::VINTRP;
137 }
138 }
139 check(base_format == instr_info.format[(int)instr->opcode],
140 "Wrong base format for instruction", instr.get());
141
142 /* check VOP3 modifiers */
143 if (instr->isVOP3() && instr->format != Format::VOP3) {
144 check(base_format == Format::VOP2 || base_format == Format::VOP1 ||
145 base_format == Format::VOPC || base_format == Format::VINTRP,
146 "Format cannot have VOP3/VOP3B applied", instr.get());
147 }
148
149 /* check SDWA */
150 if (instr->isSDWA()) {
151 check(base_format == Format::VOP2 || base_format == Format::VOP1 ||
152 base_format == Format::VOPC,
153 "Format cannot have SDWA applied", instr.get());
154
155 check(program->chip_class >= GFX8, "SDWA is GFX8+ only", instr.get());
156
157 SDWA_instruction& sdwa = instr->sdwa();
158 check(sdwa.omod == 0 || program->chip_class >= GFX9,
159 "SDWA omod only supported on GFX9+", instr.get());
160 if (base_format == Format::VOPC) {
161 check(sdwa.clamp == false || program->chip_class == GFX8,
162 "SDWA VOPC clamp only supported on GFX8", instr.get());
163 check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) ||
164 program->chip_class >= GFX9,
165 "SDWA+VOPC definition must be fixed to vcc on GFX8", instr.get());
166 } else {
167 const Definition& def = instr->definitions[0];
168 check(def.bytes() <= 4, "SDWA definitions must not be larger than 4 bytes",
169 instr.get());
170 check(def.bytes() >= sdwa.dst_sel.size() + sdwa.dst_sel.offset(),
171 "SDWA definition selection size must be at most definition size", instr.get());
172 check(
173 sdwa.dst_sel.size() == 1 || sdwa.dst_sel.size() == 2 || sdwa.dst_sel.size() == 4,
174 "SDWA definition selection size must be 1, 2 or 4 bytes", instr.get());
175 check(sdwa.dst_sel.offset() % sdwa.dst_sel.size() == 0, "Invalid selection offset",
176 instr.get());
177 check(def.bytes() == 4 || def.bytes() == sdwa.dst_sel.size(),
178 "SDWA dst_sel size must be definition size for subdword definitions",
179 instr.get());
180 check(def.bytes() == 4 || sdwa.dst_sel.offset() == 0,
181 "SDWA dst_sel offset must be 0 for subdword definitions", instr.get());
182 }
183
184 for (unsigned i = 0; i < std::min<unsigned>(2, instr->operands.size()); i++) {
185 const Operand& op = instr->operands[i];
186 check(op.bytes() <= 4, "SDWA operands must not be larger than 4 bytes", instr.get());
187 check(op.bytes() >= sdwa.sel[i].size() + sdwa.sel[i].offset(),
188 "SDWA operand selection size must be at most operand size", instr.get());
189 check(sdwa.sel[i].size() == 1 || sdwa.sel[i].size() == 2 || sdwa.sel[i].size() == 4,
190 "SDWA operand selection size must be 1, 2 or 4 bytes", instr.get());
191 check(sdwa.sel[i].offset() % sdwa.sel[i].size() == 0, "Invalid selection offset",
192 instr.get());
193 }
194 if (instr->operands.size() >= 3) {
195 check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
196 "3rd operand must be fixed to vcc with SDWA", instr.get());
197 }
198 if (instr->definitions.size() >= 2) {
199 check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc,
200 "2nd definition must be fixed to vcc with SDWA", instr.get());
201 }
202
203 const bool sdwa_opcodes =
204 instr->opcode != aco_opcode::v_fmac_f32 && instr->opcode != aco_opcode::v_fmac_f16 &&
205 instr->opcode != aco_opcode::v_fmamk_f32 &&
206 instr->opcode != aco_opcode::v_fmaak_f32 &&
207 instr->opcode != aco_opcode::v_fmamk_f16 &&
208 instr->opcode != aco_opcode::v_fmaak_f16 &&
209 instr->opcode != aco_opcode::v_madmk_f32 &&
210 instr->opcode != aco_opcode::v_madak_f32 &&
211 instr->opcode != aco_opcode::v_madmk_f16 &&
212 instr->opcode != aco_opcode::v_madak_f16 &&
213 instr->opcode != aco_opcode::v_readfirstlane_b32 &&
214 instr->opcode != aco_opcode::v_clrexcp && instr->opcode != aco_opcode::v_swap_b32;
215
216 const bool feature_mac =
217 program->chip_class == GFX8 &&
218 (instr->opcode == aco_opcode::v_mac_f32 && instr->opcode == aco_opcode::v_mac_f16);
219
220 check(sdwa_opcodes || feature_mac, "SDWA can't be used with this opcode", instr.get());
221 }
222
223 /* check opsel */
224 if (instr->isVOP3()) {
225 VOP3_instruction& vop3 = instr->vop3();
226 check(vop3.opsel == 0 || program->chip_class >= GFX9,
227 "Opsel is only supported on GFX9+", instr.get());
228
229 for (unsigned i = 0; i < 3; i++) {
230 if (i >= instr->operands.size() ||
231 (instr->operands[i].hasRegClass() &&
232 instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed()))
233 check((vop3.opsel & (1 << i)) == 0, "Unexpected opsel for operand", instr.get());
234 }
235 if (instr->definitions[0].regClass().is_subdword() && !instr->definitions[0].isFixed())
236 check((vop3.opsel & (1 << 3)) == 0, "Unexpected opsel for sub-dword definition",
237 instr.get());
238 }
239
240 /* check for undefs */
241 for (unsigned i = 0; i < instr->operands.size(); i++) {
242 if (instr->operands[i].isUndefined()) {
243 bool flat = instr->isFlatLike();
244 bool can_be_undef = is_phi(instr) || instr->isEXP() || instr->isReduction() ||
245 instr->opcode == aco_opcode::p_create_vector ||
246 (flat && i == 1) || (instr->isMIMG() && (i == 1 || i == 2)) ||
247 ((instr->isMUBUF() || instr->isMTBUF()) && i == 1);
248 check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
249 } else {
250 check(instr->operands[i].isFixed() || instr->operands[i].isTemp() ||
251 instr->operands[i].isConstant(),
252 "Uninitialized Operand", instr.get());
253 }
254 }
255
256 /* check subdword definitions */
257 for (unsigned i = 0; i < instr->definitions.size(); i++) {
258 if (instr->definitions[i].regClass().is_subdword())
259 check(instr->isPseudo() || instr->definitions[i].bytes() <= 4,
260 "Only Pseudo instructions can write subdword registers larger than 4 bytes",
261 instr.get());
262 }
263
264 if (instr->isSALU() || instr->isVALU()) {
265 /* check literals */
266 Operand literal(s1);
267 for (unsigned i = 0; i < instr->operands.size(); i++) {
268 Operand op = instr->operands[i];
269 if (!op.isLiteral())
270 continue;
271
272 check(!instr->isDPP() && !instr->isSDWA() &&
273 (!instr->isVOP3() || program->chip_class >= GFX10) &&
274 (!instr->isVOP3P() || program->chip_class >= GFX10),
275 "Literal applied on wrong instruction format", instr.get());
276
277 check(literal.isUndefined() || (literal.size() == op.size() &&
278 literal.constantValue() == op.constantValue()),
279 "Only 1 Literal allowed", instr.get());
280 literal = op;
281 check(instr->isSALU() || instr->isVOP3() || instr->isVOP3P() || i == 0 || i == 2,
282 "Wrong source position for Literal argument", instr.get());
283 }
284
285 /* check num sgprs for VALU */
286 if (instr->isVALU()) {
287 bool is_shift64 = instr->opcode == aco_opcode::v_lshlrev_b64 ||
288 instr->opcode == aco_opcode::v_lshrrev_b64 ||
289 instr->opcode == aco_opcode::v_ashrrev_i64;
290 unsigned const_bus_limit = 1;
291 if (program->chip_class >= GFX10 && !is_shift64)
292 const_bus_limit = 2;
293
294 uint32_t scalar_mask = instr->isVOP3() || instr->isVOP3P() ? 0x7 : 0x5;
295 if (instr->isSDWA())
296 scalar_mask = program->chip_class >= GFX9 ? 0x7 : 0x4;
297 else if (instr->isDPP())
298 scalar_mask = 0x4;
299
300 if (instr->isVOPC() || instr->opcode == aco_opcode::v_readfirstlane_b32 ||
301 instr->opcode == aco_opcode::v_readlane_b32 ||
302 instr->opcode == aco_opcode::v_readlane_b32_e64) {
303 check(instr->definitions[0].getTemp().type() == RegType::sgpr,
304 "Wrong Definition type for VALU instruction", instr.get());
305 } else {
306 check(instr->definitions[0].getTemp().type() == RegType::vgpr,
307 "Wrong Definition type for VALU instruction", instr.get());
308 }
309
310 unsigned num_sgprs = 0;
311 unsigned sgpr[] = {0, 0};
312 for (unsigned i = 0; i < instr->operands.size(); i++) {
313 Operand op = instr->operands[i];
314 if (instr->opcode == aco_opcode::v_readfirstlane_b32 ||
315 instr->opcode == aco_opcode::v_readlane_b32 ||
316 instr->opcode == aco_opcode::v_readlane_b32_e64) {
317 check(i != 1 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
318 op.isConstant(),
319 "Must be a SGPR or a constant", instr.get());
320 check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr &&
321 op.bytes() <= 4),
322 "Wrong Operand type for VALU instruction", instr.get());
323 continue;
324 }
325 if (instr->opcode == aco_opcode::v_permlane16_b32 ||
326 instr->opcode == aco_opcode::v_permlanex16_b32) {
327 check(i != 0 || (op.isTemp() && op.regClass().type() == RegType::vgpr),
328 "Operand 0 of v_permlane must be VGPR", instr.get());
329 check(i == 0 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
330 op.isConstant(),
331 "Lane select operands of v_permlane must be SGPR or constant",
332 instr.get());
333 }
334
335 if (instr->opcode == aco_opcode::v_writelane_b32 ||
336 instr->opcode == aco_opcode::v_writelane_b32_e64) {
337 check(i != 2 || (op.isTemp() && op.regClass().type() == RegType::vgpr &&
338 op.bytes() <= 4),
339 "Wrong Operand type for VALU instruction", instr.get());
340 check(i == 2 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
341 op.isConstant(),
342 "Must be a SGPR or a constant", instr.get());
343 continue;
344 }
345 if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
346 check(scalar_mask & (1 << i), "Wrong source position for SGPR argument",
347 instr.get());
348
349 if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
350 if (num_sgprs < 2)
351 sgpr[num_sgprs++] = op.tempId();
352 }
353 }
354
355 if (op.isConstant() && !op.isLiteral())
356 check(scalar_mask & (1 << i), "Wrong source position for constant argument",
357 instr.get());
358 }
359 check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit,
360 "Too many SGPRs/literals", instr.get());
361 }
362
363 if (instr->isSOP1() || instr->isSOP2()) {
364 check(instr->definitions[0].getTemp().type() == RegType::sgpr,
365 "Wrong Definition type for SALU instruction", instr.get());
366 for (const Operand& op : instr->operands) {
367 check(op.isConstant() || op.regClass().type() <= RegType::sgpr,
368 "Wrong Operand type for SALU instruction", instr.get());
369 }
370 }
371 }
372
373 switch (instr->format) {
374 case Format::PSEUDO: {
375 if (instr->opcode == aco_opcode::p_create_vector) {
376 unsigned size = 0;
377 for (const Operand& op : instr->operands) {
378 check(op.bytes() < 4 || size % 4 == 0, "Operand is not aligned", instr.get());
379 size += op.bytes();
380 }
381 check(size == instr->definitions[0].bytes(),
382 "Definition size does not match operand sizes", instr.get());
383 if (instr->definitions[0].getTemp().type() == RegType::sgpr) {
384 for (const Operand& op : instr->operands) {
385 check(op.isConstant() || op.regClass().type() == RegType::sgpr,
386 "Wrong Operand type for scalar vector", instr.get());
387 }
388 }
389 } else if (instr->opcode == aco_opcode::p_extract_vector) {
390 check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(),
391 "Wrong Operand types", instr.get());
392 check((instr->operands[1].constantValue() + 1) * instr->definitions[0].bytes() <=
393 instr->operands[0].bytes(),
394 "Index out of range", instr.get());
395 check(instr->definitions[0].getTemp().type() == RegType::vgpr ||
396 instr->operands[0].regClass().type() == RegType::sgpr,
397 "Cannot extract SGPR value from VGPR vector", instr.get());
398 check(program->chip_class >= GFX9 ||
399 !instr->definitions[0].regClass().is_subdword() ||
400 instr->operands[0].regClass().type() == RegType::vgpr,
401 "Cannot extract subdword from SGPR before GFX9+", instr.get());
402 } else if (instr->opcode == aco_opcode::p_split_vector) {
403 check(instr->operands[0].isTemp(), "Operand must be a temporary", instr.get());
404 unsigned size = 0;
405 for (const Definition& def : instr->definitions) {
406 size += def.bytes();
407 }
408 check(size == instr->operands[0].bytes(),
409 "Operand size does not match definition sizes", instr.get());
410 if (instr->operands[0].getTemp().type() == RegType::vgpr) {
411 for (const Definition& def : instr->definitions)
412 check(def.regClass().type() == RegType::vgpr,
413 "Wrong Definition type for VGPR split_vector", instr.get());
414 } else {
415 for (const Definition& def : instr->definitions)
416 check(program->chip_class >= GFX9 || !def.regClass().is_subdword(),
417 "Cannot split SGPR into subdword VGPRs before GFX9+", instr.get());
418 }
419 } else if (instr->opcode == aco_opcode::p_parallelcopy) {
420 check(instr->definitions.size() == instr->operands.size(),
421 "Number of Operands does not match number of Definitions", instr.get());
422 for (unsigned i = 0; i < instr->operands.size(); i++) {
423 check(instr->definitions[i].bytes() == instr->operands[i].bytes(),
424 "Operand and Definition size must match", instr.get());
425 if (instr->operands[i].isTemp()) {
426 check((instr->definitions[i].getTemp().type() ==
427 instr->operands[i].regClass().type()) ||
428 (instr->definitions[i].getTemp().type() == RegType::vgpr &&
429 instr->operands[i].regClass().type() == RegType::sgpr),
430 "Operand and Definition types do not match", instr.get());
431 check(instr->definitions[i].regClass().is_linear_vgpr() ==
432 instr->operands[i].regClass().is_linear_vgpr(),
433 "Operand and Definition types do not match", instr.get());
434 } else {
435 check(!instr->definitions[i].regClass().is_linear_vgpr(),
436 "Can only copy linear VGPRs into linear VGPRs, not constant/undef",
437 instr.get());
438 }
439 }
440 } else if (instr->opcode == aco_opcode::p_phi) {
441 check(instr->operands.size() == block.logical_preds.size(),
442 "Number of Operands does not match number of predecessors", instr.get());
443 check(instr->definitions[0].getTemp().type() == RegType::vgpr,
444 "Logical Phi Definition must be vgpr", instr.get());
445 for (const Operand& op : instr->operands)
446 check(instr->definitions[0].size() == op.size(),
447 "Operand sizes must match Definition size", instr.get());
448 } else if (instr->opcode == aco_opcode::p_linear_phi) {
449 for (const Operand& op : instr->operands) {
450 check(!op.isTemp() || op.getTemp().is_linear(), "Wrong Operand type",
451 instr.get());
452 check(instr->definitions[0].size() == op.size(),
453 "Operand sizes must match Definition size", instr.get());
454 }
455 check(instr->operands.size() == block.linear_preds.size(),
456 "Number of Operands does not match number of predecessors", instr.get());
457 } else if (instr->opcode == aco_opcode::p_extract ||
458 instr->opcode == aco_opcode::p_insert) {
459 check(instr->operands[0].isTemp(), "Data operand must be temporary", instr.get());
460 check(instr->operands[1].isConstant(), "Index must be constant", instr.get());
461 if (instr->opcode == aco_opcode::p_extract)
462 check(instr->operands[3].isConstant(), "Sign-extend flag must be constant",
463 instr.get());
464
465 check(instr->definitions[0].getTemp().type() != RegType::sgpr ||
466 instr->operands[0].getTemp().type() == RegType::sgpr,
467 "Can't extract/insert VGPR to SGPR", instr.get());
468
469 if (instr->opcode == aco_opcode::p_insert)
470 check(instr->operands[0].bytes() == instr->definitions[0].bytes(),
471 "Sizes of p_insert data operand and definition must match", instr.get());
472
473 if (instr->definitions[0].getTemp().type() == RegType::sgpr)
474 check(instr->definitions.size() >= 2 && instr->definitions[1].isFixed() &&
475 instr->definitions[1].physReg() == scc,
476 "SGPR extract/insert needs an SCC definition", instr.get());
477
478 unsigned data_bits = instr->operands[0].getTemp().bytes() * 8u;
479 unsigned op_bits = instr->operands[2].constantValue();
480
481 if (instr->opcode == aco_opcode::p_insert) {
482 check(op_bits == 8 || op_bits == 16, "Size must be 8 or 16", instr.get());
483 check(op_bits < data_bits, "Size must be smaller than source", instr.get());
484 } else if (instr->opcode == aco_opcode::p_extract) {
485 check(op_bits == 8 || op_bits == 16 || op_bits == 32,
486 "Size must be 8 or 16 or 32", instr.get());
487 check(data_bits >= op_bits, "Can't extract more bits than what the data has.",
488 instr.get());
489 }
490
491 unsigned comp = data_bits / MAX2(op_bits, 1);
492 check(instr->operands[1].constantValue() < comp, "Index must be in-bounds",
493 instr.get());
494 }
495 break;
496 }
497 case Format::PSEUDO_REDUCTION: {
498 for (const Operand& op : instr->operands)
499 check(op.regClass().type() == RegType::vgpr,
500 "All operands of PSEUDO_REDUCTION instructions must be in VGPRs.",
501 instr.get());
502
503 if (instr->opcode == aco_opcode::p_reduce &&
504 instr->reduction().cluster_size == program->wave_size)
505 check(instr->definitions[0].regClass().type() == RegType::sgpr ||
506 program->wave_size == 32,
507 "The result of unclustered reductions must go into an SGPR.", instr.get());
508 else
509 check(instr->definitions[0].regClass().type() == RegType::vgpr,
510 "The result of scans and clustered reductions must go into a VGPR.",
511 instr.get());
512
513 break;
514 }
515 case Format::SMEM: {
516 if (instr->operands.size() >= 1)
517 check((instr->operands[0].isFixed() && !instr->operands[0].isConstant()) ||
518 (instr->operands[0].isTemp() &&
519 instr->operands[0].regClass().type() == RegType::sgpr),
520 "SMEM operands must be sgpr", instr.get());
521 if (instr->operands.size() >= 2)
522 check(instr->operands[1].isConstant() ||
523 (instr->operands[1].isTemp() &&
524 instr->operands[1].regClass().type() == RegType::sgpr),
525 "SMEM offset must be constant or sgpr", instr.get());
526 if (!instr->definitions.empty())
527 check(instr->definitions[0].getTemp().type() == RegType::sgpr,
528 "SMEM result must be sgpr", instr.get());
529 break;
530 }
531 case Format::MTBUF:
532 case Format::MUBUF: {
533 check(instr->operands.size() > 1, "VMEM instructions must have at least one operand",
534 instr.get());
535 check(instr->operands[1].hasRegClass() &&
536 instr->operands[1].regClass().type() == RegType::vgpr,
537 "VADDR must be in vgpr for VMEM instructions", instr.get());
538 check(
539 instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr,
540 "VMEM resource constant must be sgpr", instr.get());
541 check(instr->operands.size() < 4 ||
542 (instr->operands[3].isTemp() &&
543 instr->operands[3].regClass().type() == RegType::vgpr),
544 "VMEM write data must be vgpr", instr.get());
545 break;
546 }
547 case Format::MIMG: {
548 check(instr->operands.size() >= 4, "MIMG instructions must have at least 4 operands",
549 instr.get());
550 check(instr->operands[0].hasRegClass() &&
551 (instr->operands[0].regClass() == s4 || instr->operands[0].regClass() == s8),
552 "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
553 if (instr->operands[1].hasRegClass())
554 check(instr->operands[1].regClass() == s4,
555 "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get());
556 if (!instr->operands[2].isUndefined()) {
557 bool is_cmpswap = instr->opcode == aco_opcode::image_atomic_cmpswap ||
558 instr->opcode == aco_opcode::image_atomic_fcmpswap;
559 check(instr->definitions.empty() ||
560 (instr->definitions[0].regClass() == instr->operands[2].regClass() ||
561 is_cmpswap),
562 "MIMG operands[2] (VDATA) must be the same as definitions[0] for atomics and "
563 "TFE/LWE loads",
564 instr.get());
565 }
566 check(instr->operands.size() == 4 || program->chip_class >= GFX10,
567 "NSA is only supported on GFX10+", instr.get());
568 for (unsigned i = 3; i < instr->operands.size(); i++) {
569 if (instr->operands.size() == 4) {
570 check(instr->operands[i].hasRegClass() &&
571 instr->operands[i].regClass().type() == RegType::vgpr,
572 "MIMG operands[3] (VADDR) must be VGPR", instr.get());
573 } else {
574 check(instr->operands[i].regClass() == v1, "MIMG VADDR must be v1 if NSA is used",
575 instr.get());
576 }
577 }
578 check(instr->definitions.empty() ||
579 (instr->definitions[0].isTemp() &&
580 instr->definitions[0].regClass().type() == RegType::vgpr),
581 "MIMG definitions[0] (VDATA) must be VGPR", instr.get());
582 break;
583 }
584 case Format::DS: {
585 for (const Operand& op : instr->operands) {
586 check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0,
587 "Only VGPRs are valid DS instruction operands", instr.get());
588 }
589 if (!instr->definitions.empty())
590 check(instr->definitions[0].getTemp().type() == RegType::vgpr,
591 "DS instruction must return VGPR", instr.get());
592 break;
593 }
594 case Format::EXP: {
595 for (unsigned i = 0; i < 4; i++)
596 check(instr->operands[i].hasRegClass() &&
597 instr->operands[i].regClass().type() == RegType::vgpr,
598 "Only VGPRs are valid Export arguments", instr.get());
599 break;
600 }
601 case Format::FLAT:
602 check(instr->operands[1].isUndefined(), "Flat instructions don't support SADDR",
603 instr.get());
604 FALLTHROUGH;
605 case Format::GLOBAL:
606 case Format::SCRATCH: {
607 check(
608 instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::vgpr,
609 "FLAT/GLOBAL/SCRATCH address must be vgpr", instr.get());
610 check(instr->operands[1].hasRegClass() &&
611 instr->operands[1].regClass().type() == RegType::sgpr,
612 "FLAT/GLOBAL/SCRATCH sgpr address must be undefined or sgpr", instr.get());
613 if (!instr->definitions.empty())
614 check(instr->definitions[0].getTemp().type() == RegType::vgpr,
615 "FLAT/GLOBAL/SCRATCH result must be vgpr", instr.get());
616 else
617 check(instr->operands[2].regClass().type() == RegType::vgpr,
618 "FLAT/GLOBAL/SCRATCH data must be vgpr", instr.get());
619 break;
620 }
621 default: break;
622 }
623 }
624 }
625
626 /* validate CFG */
627 for (unsigned i = 0; i < program->blocks.size(); i++) {
628 Block& block = program->blocks[i];
629 check_block(block.index == i, "block.index must match actual index", &block);
630
631 /* predecessors/successors should be sorted */
632 for (unsigned j = 0; j + 1 < block.linear_preds.size(); j++)
633 check_block(block.linear_preds[j] < block.linear_preds[j + 1],
634 "linear predecessors must be sorted", &block);
635 for (unsigned j = 0; j + 1 < block.logical_preds.size(); j++)
636 check_block(block.logical_preds[j] < block.logical_preds[j + 1],
637 "logical predecessors must be sorted", &block);
638 for (unsigned j = 0; j + 1 < block.linear_succs.size(); j++)
639 check_block(block.linear_succs[j] < block.linear_succs[j + 1],
640 "linear successors must be sorted", &block);
641 for (unsigned j = 0; j + 1 < block.logical_succs.size(); j++)
642 check_block(block.logical_succs[j] < block.logical_succs[j + 1],
643 "logical successors must be sorted", &block);
644
645 /* critical edges are not allowed */
646 if (block.linear_preds.size() > 1) {
647 for (unsigned pred : block.linear_preds)
648 check_block(program->blocks[pred].linear_succs.size() == 1,
649 "linear critical edges are not allowed", &program->blocks[pred]);
650 for (unsigned pred : block.logical_preds)
651 check_block(program->blocks[pred].logical_succs.size() == 1,
652 "logical critical edges are not allowed", &program->blocks[pred]);
653 }
654 }
655
656 return is_valid;
657 }
658
659 /* RA validation */
660 namespace {
661
662 struct Location {
Locationaco::__anon234597df0311::Location663 Location() : block(NULL), instr(NULL) {}
664
665 Block* block;
666 Instruction* instr; // NULL if it's the block's live-in
667 };
668
669 struct Assignment {
670 Location defloc;
671 Location firstloc;
672 PhysReg reg;
673 };
674
675 bool
ra_fail(Program * program,Location loc,Location loc2,const char * fmt,...)676 ra_fail(Program* program, Location loc, Location loc2, const char* fmt, ...)
677 {
678 va_list args;
679 va_start(args, fmt);
680 char msg[1024];
681 vsprintf(msg, fmt, args);
682 va_end(args);
683
684 char* out;
685 size_t outsize;
686 struct u_memstream mem;
687 u_memstream_open(&mem, &out, &outsize);
688 FILE* const memf = u_memstream_get(&mem);
689
690 fprintf(memf, "RA error found at instruction in BB%d:\n", loc.block->index);
691 if (loc.instr) {
692 aco_print_instr(loc.instr, memf);
693 fprintf(memf, "\n%s", msg);
694 } else {
695 fprintf(memf, "%s", msg);
696 }
697 if (loc2.block) {
698 fprintf(memf, " in BB%d:\n", loc2.block->index);
699 aco_print_instr(loc2.instr, memf);
700 }
701 fprintf(memf, "\n\n");
702 u_memstream_close(&mem);
703
704 aco_err(program, "%s", out);
705 free(out);
706
707 return true;
708 }
709
710 bool
validate_subdword_operand(chip_class chip,const aco_ptr<Instruction> & instr,unsigned index)711 validate_subdword_operand(chip_class chip, const aco_ptr<Instruction>& instr, unsigned index)
712 {
713 Operand op = instr->operands[index];
714 unsigned byte = op.physReg().byte();
715
716 if (instr->opcode == aco_opcode::p_as_uniform)
717 return byte == 0;
718 if (instr->isPseudo() && chip >= GFX8)
719 return true;
720 if (instr->isSDWA())
721 return byte + instr->sdwa().sel[index].offset() + instr->sdwa().sel[index].size() <= 4 &&
722 byte % instr->sdwa().sel[index].size() == 0;
723 if (byte == 2 && can_use_opsel(chip, instr->opcode, index, 1))
724 return true;
725
726 switch (instr->opcode) {
727 case aco_opcode::v_cvt_f32_ubyte1:
728 if (byte == 1)
729 return true;
730 break;
731 case aco_opcode::v_cvt_f32_ubyte2:
732 if (byte == 2)
733 return true;
734 break;
735 case aco_opcode::v_cvt_f32_ubyte3:
736 if (byte == 3)
737 return true;
738 break;
739 case aco_opcode::ds_write_b8_d16_hi:
740 case aco_opcode::ds_write_b16_d16_hi:
741 if (byte == 2 && index == 1)
742 return true;
743 break;
744 case aco_opcode::buffer_store_byte_d16_hi:
745 case aco_opcode::buffer_store_short_d16_hi:
746 if (byte == 2 && index == 3)
747 return true;
748 break;
749 case aco_opcode::flat_store_byte_d16_hi:
750 case aco_opcode::flat_store_short_d16_hi:
751 case aco_opcode::scratch_store_byte_d16_hi:
752 case aco_opcode::scratch_store_short_d16_hi:
753 case aco_opcode::global_store_byte_d16_hi:
754 case aco_opcode::global_store_short_d16_hi:
755 if (byte == 2 && index == 2)
756 return true;
757 break;
758 default: break;
759 }
760
761 return byte == 0;
762 }
763
764 bool
validate_subdword_definition(chip_class chip,const aco_ptr<Instruction> & instr)765 validate_subdword_definition(chip_class chip, const aco_ptr<Instruction>& instr)
766 {
767 Definition def = instr->definitions[0];
768 unsigned byte = def.physReg().byte();
769
770 if (instr->isPseudo() && chip >= GFX8)
771 return true;
772 if (instr->isSDWA())
773 return byte + instr->sdwa().dst_sel.offset() + instr->sdwa().dst_sel.size() <= 4 &&
774 byte % instr->sdwa().dst_sel.size() == 0;
775 if (byte == 2 && can_use_opsel(chip, instr->opcode, -1, 1))
776 return true;
777
778 switch (instr->opcode) {
779 case aco_opcode::buffer_load_ubyte_d16_hi:
780 case aco_opcode::buffer_load_short_d16_hi:
781 case aco_opcode::flat_load_ubyte_d16_hi:
782 case aco_opcode::flat_load_short_d16_hi:
783 case aco_opcode::scratch_load_ubyte_d16_hi:
784 case aco_opcode::scratch_load_short_d16_hi:
785 case aco_opcode::global_load_ubyte_d16_hi:
786 case aco_opcode::global_load_short_d16_hi:
787 case aco_opcode::ds_read_u8_d16_hi:
788 case aco_opcode::ds_read_u16_d16_hi: return byte == 2;
789 default: break;
790 }
791
792 return byte == 0;
793 }
794
795 unsigned
get_subdword_bytes_written(Program * program,const aco_ptr<Instruction> & instr,unsigned index)796 get_subdword_bytes_written(Program* program, const aco_ptr<Instruction>& instr, unsigned index)
797 {
798 chip_class chip = program->chip_class;
799 Definition def = instr->definitions[index];
800
801 if (instr->isPseudo())
802 return chip >= GFX8 ? def.bytes() : def.size() * 4u;
803 if (instr->isVALU()) {
804 assert(def.bytes() <= 2);
805 if (instr->isSDWA())
806 return instr->sdwa().dst_sel.size();
807
808 if (instr_is_16bit(chip, instr->opcode))
809 return 2;
810
811 return 4;
812 }
813
814 switch (instr->opcode) {
815 case aco_opcode::buffer_load_ubyte_d16:
816 case aco_opcode::buffer_load_short_d16:
817 case aco_opcode::flat_load_ubyte_d16:
818 case aco_opcode::flat_load_short_d16:
819 case aco_opcode::scratch_load_ubyte_d16:
820 case aco_opcode::scratch_load_short_d16:
821 case aco_opcode::global_load_ubyte_d16:
822 case aco_opcode::global_load_short_d16:
823 case aco_opcode::ds_read_u8_d16:
824 case aco_opcode::ds_read_u16_d16:
825 case aco_opcode::buffer_load_ubyte_d16_hi:
826 case aco_opcode::buffer_load_short_d16_hi:
827 case aco_opcode::flat_load_ubyte_d16_hi:
828 case aco_opcode::flat_load_short_d16_hi:
829 case aco_opcode::scratch_load_ubyte_d16_hi:
830 case aco_opcode::scratch_load_short_d16_hi:
831 case aco_opcode::global_load_ubyte_d16_hi:
832 case aco_opcode::global_load_short_d16_hi:
833 case aco_opcode::ds_read_u8_d16_hi:
834 case aco_opcode::ds_read_u16_d16_hi: return program->dev.sram_ecc_enabled ? 4 : 2;
835 default: return def.size() * 4;
836 }
837 }
838
839 } /* end namespace */
840
841 bool
validate_ra(Program * program)842 validate_ra(Program* program)
843 {
844 if (!(debug_flags & DEBUG_VALIDATE_RA))
845 return false;
846
847 bool err = false;
848 aco::live live_vars = aco::live_var_analysis(program);
849 std::vector<std::vector<Temp>> phi_sgpr_ops(program->blocks.size());
850 uint16_t sgpr_limit = get_addr_sgpr_from_waves(program, program->num_waves);
851
852 std::map<unsigned, Assignment> assignments;
853 for (Block& block : program->blocks) {
854 Location loc;
855 loc.block = █
856 for (aco_ptr<Instruction>& instr : block.instructions) {
857 if (instr->opcode == aco_opcode::p_phi) {
858 for (unsigned i = 0; i < instr->operands.size(); i++) {
859 if (instr->operands[i].isTemp() &&
860 instr->operands[i].getTemp().type() == RegType::sgpr &&
861 instr->operands[i].isFirstKill())
862 phi_sgpr_ops[block.logical_preds[i]].emplace_back(instr->operands[i].getTemp());
863 }
864 }
865
866 loc.instr = instr.get();
867 for (unsigned i = 0; i < instr->operands.size(); i++) {
868 Operand& op = instr->operands[i];
869 if (!op.isTemp())
870 continue;
871 if (!op.isFixed())
872 err |= ra_fail(program, loc, Location(), "Operand %d is not assigned a register", i);
873 if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg())
874 err |=
875 ra_fail(program, loc, assignments.at(op.tempId()).firstloc,
876 "Operand %d has an inconsistent register assignment with instruction", i);
877 if ((op.getTemp().type() == RegType::vgpr &&
878 op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) ||
879 (op.getTemp().type() == RegType::sgpr &&
880 op.physReg() + op.size() > program->config->num_sgprs &&
881 op.physReg() < sgpr_limit))
882 err |= ra_fail(program, loc, assignments.at(op.tempId()).firstloc,
883 "Operand %d has an out-of-bounds register assignment", i);
884 if (op.physReg() == vcc && !program->needs_vcc)
885 err |= ra_fail(program, loc, Location(),
886 "Operand %d fixed to vcc but needs_vcc=false", i);
887 if (op.regClass().is_subdword() &&
888 !validate_subdword_operand(program->chip_class, instr, i))
889 err |= ra_fail(program, loc, Location(), "Operand %d not aligned correctly", i);
890 if (!assignments[op.tempId()].firstloc.block)
891 assignments[op.tempId()].firstloc = loc;
892 if (!assignments[op.tempId()].defloc.block)
893 assignments[op.tempId()].reg = op.physReg();
894 }
895
896 for (unsigned i = 0; i < instr->definitions.size(); i++) {
897 Definition& def = instr->definitions[i];
898 if (!def.isTemp())
899 continue;
900 if (!def.isFixed())
901 err |=
902 ra_fail(program, loc, Location(), "Definition %d is not assigned a register", i);
903 if (assignments[def.tempId()].defloc.block)
904 err |= ra_fail(program, loc, assignments.at(def.tempId()).defloc,
905 "Temporary %%%d also defined by instruction", def.tempId());
906 if ((def.getTemp().type() == RegType::vgpr &&
907 def.physReg().reg_b + def.bytes() > (256 + program->config->num_vgprs) * 4) ||
908 (def.getTemp().type() == RegType::sgpr &&
909 def.physReg() + def.size() > program->config->num_sgprs &&
910 def.physReg() < sgpr_limit))
911 err |= ra_fail(program, loc, assignments.at(def.tempId()).firstloc,
912 "Definition %d has an out-of-bounds register assignment", i);
913 if (def.physReg() == vcc && !program->needs_vcc)
914 err |= ra_fail(program, loc, Location(),
915 "Definition %d fixed to vcc but needs_vcc=false", i);
916 if (def.regClass().is_subdword() &&
917 !validate_subdword_definition(program->chip_class, instr))
918 err |= ra_fail(program, loc, Location(), "Definition %d not aligned correctly", i);
919 if (!assignments[def.tempId()].firstloc.block)
920 assignments[def.tempId()].firstloc = loc;
921 assignments[def.tempId()].defloc = loc;
922 assignments[def.tempId()].reg = def.physReg();
923 }
924 }
925 }
926
927 for (Block& block : program->blocks) {
928 Location loc;
929 loc.block = █
930
931 std::array<unsigned, 2048> regs; /* register file in bytes */
932 regs.fill(0);
933
934 std::set<Temp> live;
935 for (unsigned id : live_vars.live_out[block.index])
936 live.insert(Temp(id, program->temp_rc[id]));
937 /* remove killed p_phi sgpr operands */
938 for (Temp tmp : phi_sgpr_ops[block.index])
939 live.erase(tmp);
940
941 /* check live out */
942 for (Temp tmp : live) {
943 PhysReg reg = assignments.at(tmp.id()).reg;
944 for (unsigned i = 0; i < tmp.bytes(); i++) {
945 if (regs[reg.reg_b + i]) {
946 err |= ra_fail(program, loc, Location(),
947 "Assignment of element %d of %%%d already taken by %%%d in live-out",
948 i, tmp.id(), regs[reg.reg_b + i]);
949 }
950 regs[reg.reg_b + i] = tmp.id();
951 }
952 }
953 regs.fill(0);
954
955 for (auto it = block.instructions.rbegin(); it != block.instructions.rend(); ++it) {
956 aco_ptr<Instruction>& instr = *it;
957
958 /* check killed p_phi sgpr operands */
959 if (instr->opcode == aco_opcode::p_logical_end) {
960 for (Temp tmp : phi_sgpr_ops[block.index]) {
961 PhysReg reg = assignments.at(tmp.id()).reg;
962 for (unsigned i = 0; i < tmp.bytes(); i++) {
963 if (regs[reg.reg_b + i])
964 err |= ra_fail(
965 program, loc, Location(),
966 "Assignment of element %d of %%%d already taken by %%%d in live-out", i,
967 tmp.id(), regs[reg.reg_b + i]);
968 }
969 live.emplace(tmp);
970 }
971 }
972
973 for (const Definition& def : instr->definitions) {
974 if (!def.isTemp())
975 continue;
976 live.erase(def.getTemp());
977 }
978
979 /* don't count phi operands as live-in, since they are actually
980 * killed when they are copied at the predecessor */
981 if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
982 for (const Operand& op : instr->operands) {
983 if (!op.isTemp())
984 continue;
985 live.insert(op.getTemp());
986 }
987 }
988 }
989
990 for (Temp tmp : live) {
991 PhysReg reg = assignments.at(tmp.id()).reg;
992 for (unsigned i = 0; i < tmp.bytes(); i++)
993 regs[reg.reg_b + i] = tmp.id();
994 }
995
996 for (aco_ptr<Instruction>& instr : block.instructions) {
997 loc.instr = instr.get();
998
999 /* remove killed p_phi operands from regs */
1000 if (instr->opcode == aco_opcode::p_logical_end) {
1001 for (Temp tmp : phi_sgpr_ops[block.index]) {
1002 PhysReg reg = assignments.at(tmp.id()).reg;
1003 for (unsigned i = 0; i < tmp.bytes(); i++)
1004 regs[reg.reg_b + i] = 0;
1005 }
1006 }
1007
1008 if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
1009 for (const Operand& op : instr->operands) {
1010 if (!op.isTemp())
1011 continue;
1012 if (op.isFirstKillBeforeDef()) {
1013 for (unsigned j = 0; j < op.getTemp().bytes(); j++)
1014 regs[op.physReg().reg_b + j] = 0;
1015 }
1016 }
1017 }
1018
1019 for (unsigned i = 0; i < instr->definitions.size(); i++) {
1020 Definition& def = instr->definitions[i];
1021 if (!def.isTemp())
1022 continue;
1023 Temp tmp = def.getTemp();
1024 PhysReg reg = assignments.at(tmp.id()).reg;
1025 for (unsigned j = 0; j < tmp.bytes(); j++) {
1026 if (regs[reg.reg_b + j])
1027 err |= ra_fail(
1028 program, loc, assignments.at(regs[reg.reg_b + j]).defloc,
1029 "Assignment of element %d of %%%d already taken by %%%d from instruction", i,
1030 tmp.id(), regs[reg.reg_b + j]);
1031 regs[reg.reg_b + j] = tmp.id();
1032 }
1033 if (def.regClass().is_subdword() && def.bytes() < 4) {
1034 unsigned written = get_subdword_bytes_written(program, instr, i);
1035 /* If written=4, the instruction still might write the upper half. In that case, it's
1036 * the lower half that isn't preserved */
1037 for (unsigned j = reg.byte() & ~(written - 1); j < written; j++) {
1038 unsigned written_reg = reg.reg() * 4u + j;
1039 if (regs[written_reg] && regs[written_reg] != def.tempId())
1040 err |= ra_fail(program, loc, assignments.at(regs[written_reg]).defloc,
1041 "Assignment of element %d of %%%d overwrites the full register "
1042 "taken by %%%d from instruction",
1043 i, tmp.id(), regs[written_reg]);
1044 }
1045 }
1046 }
1047
1048 for (const Definition& def : instr->definitions) {
1049 if (!def.isTemp())
1050 continue;
1051 if (def.isKill()) {
1052 for (unsigned j = 0; j < def.getTemp().bytes(); j++)
1053 regs[def.physReg().reg_b + j] = 0;
1054 }
1055 }
1056
1057 if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
1058 for (const Operand& op : instr->operands) {
1059 if (!op.isTemp())
1060 continue;
1061 if (op.isLateKill() && op.isFirstKill()) {
1062 for (unsigned j = 0; j < op.getTemp().bytes(); j++)
1063 regs[op.physReg().reg_b + j] = 0;
1064 }
1065 }
1066 }
1067 }
1068 }
1069
1070 return err;
1071 }
1072 } // namespace aco
1073