1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * HD audio interface patch for Creative CA0132 chip
4 *
5 * Copyright (c) 2011, Creative Technology Ltd.
6 *
7 * Based on patch_ca0110.c
8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 */
10
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/mutex.h>
15 #include <linux/module.h>
16 #include <linux/firmware.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/io.h>
20 #include <linux/pci.h>
21 #include <asm/io.h>
22 #include <sound/core.h>
23 #include <sound/hda_codec.h>
24 #include "hda_local.h"
25 #include "hda_auto_parser.h"
26 #include "hda_jack.h"
27
28 #include "ca0132_regs.h"
29
30 /* Enable this to see controls for tuning purpose. */
31 /*#define ENABLE_TUNING_CONTROLS*/
32
33 #ifdef ENABLE_TUNING_CONTROLS
34 #include <sound/tlv.h>
35 #endif
36
37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
45
46 #define UNSOL_TAG_DSP 0x16
47
48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
50
51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
54
55 #define MASTERCONTROL 0x80
56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
58
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
61
62 #define MEM_CONNID_MICIN1 3
63 #define MEM_CONNID_MICIN2 5
64 #define MEM_CONNID_MICOUT1 12
65 #define MEM_CONNID_MICOUT2 14
66 #define MEM_CONNID_WUH 10
67 #define MEM_CONNID_DSP 16
68 #define MEM_CONNID_DMIC 100
69
70 #define SCP_SET 0
71 #define SCP_GET 1
72
73 #define EFX_FILE "ctefx.bin"
74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin"
75 #define R3DI_EFX_FILE "ctefx-r3di.bin"
76
77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
78 MODULE_FIRMWARE(EFX_FILE);
79 MODULE_FIRMWARE(DESKTOP_EFX_FILE);
80 MODULE_FIRMWARE(R3DI_EFX_FILE);
81 #endif
82
83 static const char *const dirstr[2] = { "Playback", "Capture" };
84
85 #define NUM_OF_OUTPUTS 2
86 static const char *const out_type_str[2] = { "Speakers", "Headphone" };
87 enum {
88 SPEAKER_OUT,
89 HEADPHONE_OUT,
90 };
91
92 enum {
93 DIGITAL_MIC,
94 LINE_MIC_IN
95 };
96
97 /* Strings for Input Source Enum Control */
98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
99 #define IN_SRC_NUM_OF_INPUTS 3
100 enum {
101 REAR_MIC,
102 REAR_LINE_IN,
103 FRONT_MIC,
104 };
105
106 enum {
107 #define VNODE_START_NID 0x80
108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
109 VNID_MIC,
110 VNID_HP_SEL,
111 VNID_AMIC1_SEL,
112 VNID_HP_ASEL,
113 VNID_AMIC1_ASEL,
114 VNODE_END_NID,
115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
116
117 #define EFFECT_START_NID 0x90
118 #define OUT_EFFECT_START_NID EFFECT_START_NID
119 SURROUND = OUT_EFFECT_START_NID,
120 CRYSTALIZER,
121 DIALOG_PLUS,
122 SMART_VOLUME,
123 X_BASS,
124 EQUALIZER,
125 OUT_EFFECT_END_NID,
126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
127
128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
129 ECHO_CANCELLATION = IN_EFFECT_START_NID,
130 VOICE_FOCUS,
131 MIC_SVM,
132 NOISE_REDUCTION,
133 IN_EFFECT_END_NID,
134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
135
136 VOICEFX = IN_EFFECT_END_NID,
137 PLAY_ENHANCEMENT,
138 CRYSTAL_VOICE,
139 EFFECT_END_NID,
140 OUTPUT_SOURCE_ENUM,
141 INPUT_SOURCE_ENUM,
142 XBASS_XOVER,
143 EQ_PRESET_ENUM,
144 SMART_VOLUME_ENUM,
145 MIC_BOOST_ENUM,
146 AE5_HEADPHONE_GAIN_ENUM,
147 AE5_SOUND_FILTER_ENUM,
148 ZXR_HEADPHONE_GAIN,
149 SPEAKER_CHANNEL_CFG_ENUM,
150 SPEAKER_FULL_RANGE_FRONT,
151 SPEAKER_FULL_RANGE_REAR,
152 BASS_REDIRECTION,
153 BASS_REDIRECTION_XOVER,
154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
155 };
156
157 /* Effects values size*/
158 #define EFFECT_VALS_MAX_COUNT 12
159
160 /*
161 * Default values for the effect slider controls, they are in order of their
162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
163 * X-bass.
164 */
165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
166 /* Amount of effect level sliders for ca0132_alt controls. */
167 #define EFFECT_LEVEL_SLIDERS 5
168
169 /* Latency introduced by DSP blocks in milliseconds. */
170 #define DSP_CAPTURE_INIT_LATENCY 0
171 #define DSP_CRYSTAL_VOICE_LATENCY 124
172 #define DSP_PLAYBACK_INIT_LATENCY 13
173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
174 #define DSP_SPEAKER_OUT_LATENCY 7
175
176 struct ct_effect {
177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
178 hda_nid_t nid;
179 int mid; /*effect module ID*/
180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
181 int direct; /* 0:output; 1:input*/
182 int params; /* number of default non-on/off params */
183 /*effect default values, 1st is on/off. */
184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
185 };
186
187 #define EFX_DIR_OUT 0
188 #define EFX_DIR_IN 1
189
190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
191 { .name = "Surround",
192 .nid = SURROUND,
193 .mid = 0x96,
194 .reqs = {0, 1},
195 .direct = EFX_DIR_OUT,
196 .params = 1,
197 .def_vals = {0x3F800000, 0x3F2B851F}
198 },
199 { .name = "Crystalizer",
200 .nid = CRYSTALIZER,
201 .mid = 0x96,
202 .reqs = {7, 8},
203 .direct = EFX_DIR_OUT,
204 .params = 1,
205 .def_vals = {0x3F800000, 0x3F266666}
206 },
207 { .name = "Dialog Plus",
208 .nid = DIALOG_PLUS,
209 .mid = 0x96,
210 .reqs = {2, 3},
211 .direct = EFX_DIR_OUT,
212 .params = 1,
213 .def_vals = {0x00000000, 0x3F000000}
214 },
215 { .name = "Smart Volume",
216 .nid = SMART_VOLUME,
217 .mid = 0x96,
218 .reqs = {4, 5, 6},
219 .direct = EFX_DIR_OUT,
220 .params = 2,
221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
222 },
223 { .name = "X-Bass",
224 .nid = X_BASS,
225 .mid = 0x96,
226 .reqs = {24, 23, 25},
227 .direct = EFX_DIR_OUT,
228 .params = 2,
229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
230 },
231 { .name = "Equalizer",
232 .nid = EQUALIZER,
233 .mid = 0x96,
234 .reqs = {9, 10, 11, 12, 13, 14,
235 15, 16, 17, 18, 19, 20},
236 .direct = EFX_DIR_OUT,
237 .params = 11,
238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
239 0x00000000, 0x00000000, 0x00000000, 0x00000000,
240 0x00000000, 0x00000000, 0x00000000, 0x00000000}
241 },
242 { .name = "Echo Cancellation",
243 .nid = ECHO_CANCELLATION,
244 .mid = 0x95,
245 .reqs = {0, 1, 2, 3},
246 .direct = EFX_DIR_IN,
247 .params = 3,
248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
249 },
250 { .name = "Voice Focus",
251 .nid = VOICE_FOCUS,
252 .mid = 0x95,
253 .reqs = {6, 7, 8, 9},
254 .direct = EFX_DIR_IN,
255 .params = 3,
256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
257 },
258 { .name = "Mic SVM",
259 .nid = MIC_SVM,
260 .mid = 0x95,
261 .reqs = {44, 45},
262 .direct = EFX_DIR_IN,
263 .params = 1,
264 .def_vals = {0x00000000, 0x3F3D70A4}
265 },
266 { .name = "Noise Reduction",
267 .nid = NOISE_REDUCTION,
268 .mid = 0x95,
269 .reqs = {4, 5},
270 .direct = EFX_DIR_IN,
271 .params = 1,
272 .def_vals = {0x3F800000, 0x3F000000}
273 },
274 { .name = "VoiceFX",
275 .nid = VOICEFX,
276 .mid = 0x95,
277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
278 .direct = EFX_DIR_IN,
279 .params = 8,
280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
282 0x00000000}
283 }
284 };
285
286 /* Tuning controls */
287 #ifdef ENABLE_TUNING_CONTROLS
288
289 enum {
290 #define TUNING_CTL_START_NID 0xC0
291 WEDGE_ANGLE = TUNING_CTL_START_NID,
292 SVM_LEVEL,
293 EQUALIZER_BAND_0,
294 EQUALIZER_BAND_1,
295 EQUALIZER_BAND_2,
296 EQUALIZER_BAND_3,
297 EQUALIZER_BAND_4,
298 EQUALIZER_BAND_5,
299 EQUALIZER_BAND_6,
300 EQUALIZER_BAND_7,
301 EQUALIZER_BAND_8,
302 EQUALIZER_BAND_9,
303 TUNING_CTL_END_NID
304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
305 };
306
307 struct ct_tuning_ctl {
308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
309 hda_nid_t parent_nid;
310 hda_nid_t nid;
311 int mid; /*effect module ID*/
312 int req; /*effect module request*/
313 int direct; /* 0:output; 1:input*/
314 unsigned int def_val;/*effect default values*/
315 };
316
317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
318 { .name = "Wedge Angle",
319 .parent_nid = VOICE_FOCUS,
320 .nid = WEDGE_ANGLE,
321 .mid = 0x95,
322 .req = 8,
323 .direct = EFX_DIR_IN,
324 .def_val = 0x41F00000
325 },
326 { .name = "SVM Level",
327 .parent_nid = MIC_SVM,
328 .nid = SVM_LEVEL,
329 .mid = 0x95,
330 .req = 45,
331 .direct = EFX_DIR_IN,
332 .def_val = 0x3F3D70A4
333 },
334 { .name = "EQ Band0",
335 .parent_nid = EQUALIZER,
336 .nid = EQUALIZER_BAND_0,
337 .mid = 0x96,
338 .req = 11,
339 .direct = EFX_DIR_OUT,
340 .def_val = 0x00000000
341 },
342 { .name = "EQ Band1",
343 .parent_nid = EQUALIZER,
344 .nid = EQUALIZER_BAND_1,
345 .mid = 0x96,
346 .req = 12,
347 .direct = EFX_DIR_OUT,
348 .def_val = 0x00000000
349 },
350 { .name = "EQ Band2",
351 .parent_nid = EQUALIZER,
352 .nid = EQUALIZER_BAND_2,
353 .mid = 0x96,
354 .req = 13,
355 .direct = EFX_DIR_OUT,
356 .def_val = 0x00000000
357 },
358 { .name = "EQ Band3",
359 .parent_nid = EQUALIZER,
360 .nid = EQUALIZER_BAND_3,
361 .mid = 0x96,
362 .req = 14,
363 .direct = EFX_DIR_OUT,
364 .def_val = 0x00000000
365 },
366 { .name = "EQ Band4",
367 .parent_nid = EQUALIZER,
368 .nid = EQUALIZER_BAND_4,
369 .mid = 0x96,
370 .req = 15,
371 .direct = EFX_DIR_OUT,
372 .def_val = 0x00000000
373 },
374 { .name = "EQ Band5",
375 .parent_nid = EQUALIZER,
376 .nid = EQUALIZER_BAND_5,
377 .mid = 0x96,
378 .req = 16,
379 .direct = EFX_DIR_OUT,
380 .def_val = 0x00000000
381 },
382 { .name = "EQ Band6",
383 .parent_nid = EQUALIZER,
384 .nid = EQUALIZER_BAND_6,
385 .mid = 0x96,
386 .req = 17,
387 .direct = EFX_DIR_OUT,
388 .def_val = 0x00000000
389 },
390 { .name = "EQ Band7",
391 .parent_nid = EQUALIZER,
392 .nid = EQUALIZER_BAND_7,
393 .mid = 0x96,
394 .req = 18,
395 .direct = EFX_DIR_OUT,
396 .def_val = 0x00000000
397 },
398 { .name = "EQ Band8",
399 .parent_nid = EQUALIZER,
400 .nid = EQUALIZER_BAND_8,
401 .mid = 0x96,
402 .req = 19,
403 .direct = EFX_DIR_OUT,
404 .def_val = 0x00000000
405 },
406 { .name = "EQ Band9",
407 .parent_nid = EQUALIZER,
408 .nid = EQUALIZER_BAND_9,
409 .mid = 0x96,
410 .req = 20,
411 .direct = EFX_DIR_OUT,
412 .def_val = 0x00000000
413 }
414 };
415 #endif
416
417 /* Voice FX Presets */
418 #define VOICEFX_MAX_PARAM_COUNT 9
419
420 struct ct_voicefx {
421 char *name;
422 hda_nid_t nid;
423 int mid;
424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
425 };
426
427 struct ct_voicefx_preset {
428 char *name; /*preset name*/
429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
430 };
431
432 static const struct ct_voicefx ca0132_voicefx = {
433 .name = "VoiceFX Capture Switch",
434 .nid = VOICEFX,
435 .mid = 0x95,
436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
437 };
438
439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
440 { .name = "Neutral",
441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
442 0x44FA0000, 0x3F800000, 0x3F800000,
443 0x3F800000, 0x00000000, 0x00000000 }
444 },
445 { .name = "Female2Male",
446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
447 0x44FA0000, 0x3F19999A, 0x3F866666,
448 0x3F800000, 0x00000000, 0x00000000 }
449 },
450 { .name = "Male2Female",
451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 0x450AC000, 0x4017AE14, 0x3F6B851F,
453 0x3F800000, 0x00000000, 0x00000000 }
454 },
455 { .name = "ScrappyKid",
456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
457 0x44FA0000, 0x40400000, 0x3F28F5C3,
458 0x3F800000, 0x00000000, 0x00000000 }
459 },
460 { .name = "Elderly",
461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
462 0x44E10000, 0x3FB33333, 0x3FB9999A,
463 0x3F800000, 0x3E3A2E43, 0x00000000 }
464 },
465 { .name = "Orc",
466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
467 0x45098000, 0x3F266666, 0x3FC00000,
468 0x3F800000, 0x00000000, 0x00000000 }
469 },
470 { .name = "Elf",
471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
472 0x45193000, 0x3F8E147B, 0x3F75C28F,
473 0x3F800000, 0x00000000, 0x00000000 }
474 },
475 { .name = "Dwarf",
476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
477 0x45007000, 0x3F451EB8, 0x3F7851EC,
478 0x3F800000, 0x00000000, 0x00000000 }
479 },
480 { .name = "AlienBrute",
481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
482 0x451F6000, 0x3F266666, 0x3FA7D945,
483 0x3F800000, 0x3CF5C28F, 0x00000000 }
484 },
485 { .name = "Robot",
486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
487 0x44FA0000, 0x3FB2718B, 0x3F800000,
488 0xBC07010E, 0x00000000, 0x00000000 }
489 },
490 { .name = "Marine",
491 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
493 0x3F0A3D71, 0x00000000, 0x00000000 }
494 },
495 { .name = "Emo",
496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
497 0x44FA0000, 0x3F800000, 0x3F800000,
498 0x3E4CCCCD, 0x00000000, 0x00000000 }
499 },
500 { .name = "DeepVoice",
501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
503 0x3F800000, 0x00000000, 0x00000000 }
504 },
505 { .name = "Munchkin",
506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
507 0x44FA0000, 0x3F800000, 0x3F1A043C,
508 0x3F800000, 0x00000000, 0x00000000 }
509 }
510 };
511
512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
513
514 #define EQ_PRESET_MAX_PARAM_COUNT 11
515
516 struct ct_eq {
517 char *name;
518 hda_nid_t nid;
519 int mid;
520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
521 };
522
523 struct ct_eq_preset {
524 char *name; /*preset name*/
525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
526 };
527
528 static const struct ct_eq ca0132_alt_eq_enum = {
529 .name = "FX: Equalizer Preset Switch",
530 .nid = EQ_PRESET_ENUM,
531 .mid = 0x96,
532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
533 };
534
535
536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
537 { .name = "Flat",
538 .vals = { 0x00000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x00000000,
540 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000 }
542 },
543 { .name = "Acoustic",
544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
545 0x40000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000, 0x40000000,
547 0x40000000, 0x40000000 }
548 },
549 { .name = "Classical",
550 .vals = { 0x00000000, 0x00000000, 0x40C00000,
551 0x40C00000, 0x40466666, 0x00000000,
552 0x00000000, 0x00000000, 0x00000000,
553 0x40466666, 0x40466666 }
554 },
555 { .name = "Country",
556 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
558 0x00000000, 0x00000000, 0x40000000,
559 0x40466666, 0x40800000 }
560 },
561 { .name = "Dance",
562 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
563 0x40466666, 0x40866666, 0xBF99999A,
564 0xBF99999A, 0x00000000, 0x00000000,
565 0x40800000, 0x40800000 }
566 },
567 { .name = "Jazz",
568 .vals = { 0x00000000, 0x00000000, 0x00000000,
569 0x3F8CCCCD, 0x40800000, 0x40800000,
570 0x40800000, 0x00000000, 0x3F8CCCCD,
571 0x40466666, 0x40466666 }
572 },
573 { .name = "New Age",
574 .vals = { 0x00000000, 0x00000000, 0x40000000,
575 0x40000000, 0x00000000, 0x00000000,
576 0x00000000, 0x3F8CCCCD, 0x40000000,
577 0x40000000, 0x40000000 }
578 },
579 { .name = "Pop",
580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
581 0x40000000, 0x40000000, 0x00000000,
582 0xBF99999A, 0xBF99999A, 0x00000000,
583 0x40466666, 0x40C00000 }
584 },
585 { .name = "Rock",
586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
587 0x3F8CCCCD, 0x40000000, 0xBF99999A,
588 0xBF99999A, 0x00000000, 0x00000000,
589 0x40800000, 0x40800000 }
590 },
591 { .name = "Vocal",
592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
593 0xBF99999A, 0x00000000, 0x40466666,
594 0x40800000, 0x40466666, 0x00000000,
595 0x00000000, 0x3F8CCCCD }
596 }
597 };
598
599 /*
600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
601 * set as not being full range, and bass redirection is enabled, all
602 * frequencies below the crossover frequency are redirected to the LFE
603 * channel. If the surround configuration has no LFE channel, this can't be
604 * enabled. X-Bass must be disabled when using these.
605 */
606 enum speaker_range_reqs {
607 SPEAKER_BASS_REDIRECT = 0x15,
608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
609 /* Between 0x16-0x1a are the X-Bass reqs. */
610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a,
611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b,
612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c,
613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d,
614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e,
615 };
616
617 /*
618 * Definitions for the DSP req's to handle speaker tuning. These all belong to
619 * module ID 0x96, the output effects module.
620 */
621 enum speaker_tuning_reqs {
622 /*
623 * Currently, this value is always set to 0.0f. However, on Windows,
624 * when selecting certain headphone profiles on the new Sound Blaster
625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
626 * sent. This gets the speaker EQ address area, which is then used to
627 * send over (presumably) an equalizer profile for the specific
628 * headphone setup. It is sent using the same method the DSP
629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
630 * file exists in linux firmware tree but goes unused. It would also
631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
633 * set to 1.0f.
634 */
635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f,
636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20,
637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21,
638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22,
639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23,
640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24,
641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25,
642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26,
643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27,
644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
645 /*
646 * Inversion is used when setting headphone virtualization to line
647 * out. Not sure why this is, but it's the only place it's ever used.
648 */
649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29,
650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a,
651 SPEAKER_TUNING_CENTER_INVERT = 0x2b,
652 SPEAKER_TUNING_LFE_INVERT = 0x2c,
653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d,
654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e,
655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f,
656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30,
657 /* Delay is used when setting surround speaker distance in Windows. */
658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31,
659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32,
660 SPEAKER_TUNING_CENTER_DELAY = 0x33,
661 SPEAKER_TUNING_LFE_DELAY = 0x34,
662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35,
663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36,
664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37,
665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38,
666 /* Of these two, only mute seems to ever be used. */
667 SPEAKER_TUNING_MAIN_VOLUME = 0x39,
668 SPEAKER_TUNING_MUTE = 0x3a,
669 };
670
671 /* Surround output channel count configuration structures. */
672 #define SPEAKER_CHANNEL_CFG_COUNT 5
673 enum {
674 SPEAKER_CHANNELS_2_0,
675 SPEAKER_CHANNELS_2_1,
676 SPEAKER_CHANNELS_4_0,
677 SPEAKER_CHANNELS_4_1,
678 SPEAKER_CHANNELS_5_1,
679 };
680
681 struct ca0132_alt_speaker_channel_cfg {
682 char *name;
683 unsigned int val;
684 };
685
686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
687 { .name = "2.0",
688 .val = FLOAT_ONE
689 },
690 { .name = "2.1",
691 .val = FLOAT_TWO
692 },
693 { .name = "4.0",
694 .val = FLOAT_FIVE
695 },
696 { .name = "4.1",
697 .val = FLOAT_SIX
698 },
699 { .name = "5.1",
700 .val = FLOAT_EIGHT
701 }
702 };
703
704 /*
705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
706 * and I don't know what the third req is, but it's always zero. I assume it's
707 * some sort of update or set command to tell the DSP there's new volume info.
708 */
709 #define DSP_VOL_OUT 0
710 #define DSP_VOL_IN 1
711
712 struct ct_dsp_volume_ctl {
713 hda_nid_t vnid;
714 int mid; /* module ID*/
715 unsigned int reqs[3]; /* scp req ID */
716 };
717
718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
719 { .vnid = VNID_SPK,
720 .mid = 0x32,
721 .reqs = {3, 4, 2}
722 },
723 { .vnid = VNID_MIC,
724 .mid = 0x37,
725 .reqs = {2, 3, 1}
726 }
727 };
728
729 /* Values for ca0113_mmio_command_set for selecting output. */
730 #define AE_CA0113_OUT_SET_COMMANDS 6
731 struct ae_ca0113_output_set {
732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
735 };
736
737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
740 /* Speakers. */
741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
742 /* Headphones. */
743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
744 };
745
746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
749 /* Speakers. */
750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
751 /* Headphones. */
752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
753 };
754
755 /* ae5 ca0113 command sequences to set headphone gain levels. */
756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
757 struct ae5_headphone_gain_set {
758 char *name;
759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
760 };
761
762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
763 { .name = "Low (16-31",
764 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
765 },
766 { .name = "Medium (32-149",
767 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
768 },
769 { .name = "High (150-600",
770 .vals = { 0xff, 0xff, 0xff, 0x7f }
771 }
772 };
773
774 struct ae5_filter_set {
775 char *name;
776 unsigned int val;
777 };
778
779 static const struct ae5_filter_set ae5_filter_presets[] = {
780 { .name = "Slow Roll Off",
781 .val = 0xa0
782 },
783 { .name = "Minimum Phase",
784 .val = 0xc0
785 },
786 { .name = "Fast Roll Off",
787 .val = 0x80
788 }
789 };
790
791 enum hda_cmd_vendor_io {
792 /* for DspIO node */
793 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
794 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
795
796 VENDOR_DSPIO_STATUS = 0xF01,
797 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
798 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
799 VENDOR_DSPIO_DSP_INIT = 0x703,
800 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
801 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
802
803 /* for ChipIO node */
804 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
805 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
806 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
807 VENDOR_CHIPIO_DATA_LOW = 0x300,
808 VENDOR_CHIPIO_DATA_HIGH = 0x400,
809
810 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
811 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
812
813 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
814 VENDOR_CHIPIO_STATUS = 0xF01,
815 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
816 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
817
818 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
819 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
820 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
821 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
822 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
823
824 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
825 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
826
827 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
828 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
829 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
830 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
831 VENDOR_CHIPIO_FLAG_SET = 0x70F,
832 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
833 VENDOR_CHIPIO_PARAM_SET = 0x710,
834 VENDOR_CHIPIO_PARAM_GET = 0xF10,
835
836 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
837 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
838 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
839 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
840
841 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
842 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
843 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
844 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
845
846 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
847 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
848 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
849 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
850 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
851 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
852
853 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
854 };
855
856 /*
857 * Control flag IDs
858 */
859 enum control_flag_id {
860 /* Connection manager stream setup is bypassed/enabled */
861 CONTROL_FLAG_C_MGR = 0,
862 /* DSP DMA is bypassed/enabled */
863 CONTROL_FLAG_DMA = 1,
864 /* 8051 'idle' mode is disabled/enabled */
865 CONTROL_FLAG_IDLE_ENABLE = 2,
866 /* Tracker for the SPDIF-in path is bypassed/enabled */
867 CONTROL_FLAG_TRACKER = 3,
868 /* DigitalOut to Spdif2Out connection is disabled/enabled */
869 CONTROL_FLAG_SPDIF2OUT = 4,
870 /* Digital Microphone is disabled/enabled */
871 CONTROL_FLAG_DMIC = 5,
872 /* ADC_B rate is 48 kHz/96 kHz */
873 CONTROL_FLAG_ADC_B_96KHZ = 6,
874 /* ADC_C rate is 48 kHz/96 kHz */
875 CONTROL_FLAG_ADC_C_96KHZ = 7,
876 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
877 CONTROL_FLAG_DAC_96KHZ = 8,
878 /* DSP rate is 48 kHz/96 kHz */
879 CONTROL_FLAG_DSP_96KHZ = 9,
880 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
881 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
882 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
883 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
884 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
885 CONTROL_FLAG_DECODE_LOOP = 12,
886 /* De-emphasis filter on DAC-1 disabled/enabled */
887 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
888 /* De-emphasis filter on DAC-2 disabled/enabled */
889 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
890 /* De-emphasis filter on DAC-3 disabled/enabled */
891 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
892 /* High-pass filter on ADC_B disabled/enabled */
893 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
894 /* High-pass filter on ADC_C disabled/enabled */
895 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
896 /* Common mode on Port_A disabled/enabled */
897 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
898 /* Common mode on Port_D disabled/enabled */
899 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
900 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
901 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
902 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
903 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
904 /* ASI rate is 48kHz/96kHz */
905 CONTROL_FLAG_ASI_96KHZ = 22,
906 /* DAC power settings able to control attached ports no/yes */
907 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
908 /* Clock Stop OK reporting is disabled/enabled */
909 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
910 /* Number of control flags */
911 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
912 };
913
914 /*
915 * Control parameter IDs
916 */
917 enum control_param_id {
918 /* 0: None, 1: Mic1In*/
919 CONTROL_PARAM_VIP_SOURCE = 1,
920 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
921 CONTROL_PARAM_SPDIF1_SOURCE = 2,
922 /* Port A output stage gain setting to use when 16 Ohm output
923 * impedance is selected*/
924 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
925 /* Port D output stage gain setting to use when 16 Ohm output
926 * impedance is selected*/
927 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
928
929 /*
930 * This control param name was found in the 8051 memory, and makes
931 * sense given the fact the AE-5 uses it and has the ASI flag set.
932 */
933 CONTROL_PARAM_ASI = 23,
934
935 /* Stream Control */
936
937 /* Select stream with the given ID */
938 CONTROL_PARAM_STREAM_ID = 24,
939 /* Source connection point for the selected stream */
940 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
941 /* Destination connection point for the selected stream */
942 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
943 /* Number of audio channels in the selected stream */
944 CONTROL_PARAM_STREAMS_CHANNELS = 27,
945 /*Enable control for the selected stream */
946 CONTROL_PARAM_STREAM_CONTROL = 28,
947
948 /* Connection Point Control */
949
950 /* Select connection point with the given ID */
951 CONTROL_PARAM_CONN_POINT_ID = 29,
952 /* Connection point sample rate */
953 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
954
955 /* Node Control */
956
957 /* Select HDA node with the given ID */
958 CONTROL_PARAM_NODE_ID = 31
959 };
960
961 /*
962 * Dsp Io Status codes
963 */
964 enum hda_vendor_status_dspio {
965 /* Success */
966 VENDOR_STATUS_DSPIO_OK = 0x00,
967 /* Busy, unable to accept new command, the host must retry */
968 VENDOR_STATUS_DSPIO_BUSY = 0x01,
969 /* SCP command queue is full */
970 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
971 /* SCP response queue is empty */
972 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
973 };
974
975 /*
976 * Chip Io Status codes
977 */
978 enum hda_vendor_status_chipio {
979 /* Success */
980 VENDOR_STATUS_CHIPIO_OK = 0x00,
981 /* Busy, unable to accept new command, the host must retry */
982 VENDOR_STATUS_CHIPIO_BUSY = 0x01
983 };
984
985 /*
986 * CA0132 sample rate
987 */
988 enum ca0132_sample_rate {
989 SR_6_000 = 0x00,
990 SR_8_000 = 0x01,
991 SR_9_600 = 0x02,
992 SR_11_025 = 0x03,
993 SR_16_000 = 0x04,
994 SR_22_050 = 0x05,
995 SR_24_000 = 0x06,
996 SR_32_000 = 0x07,
997 SR_44_100 = 0x08,
998 SR_48_000 = 0x09,
999 SR_88_200 = 0x0A,
1000 SR_96_000 = 0x0B,
1001 SR_144_000 = 0x0C,
1002 SR_176_400 = 0x0D,
1003 SR_192_000 = 0x0E,
1004 SR_384_000 = 0x0F,
1005
1006 SR_COUNT = 0x10,
1007
1008 SR_RATE_UNKNOWN = 0x1F
1009 };
1010
1011 enum dsp_download_state {
1012 DSP_DOWNLOAD_FAILED = -1,
1013 DSP_DOWNLOAD_INIT = 0,
1014 DSP_DOWNLOADING = 1,
1015 DSP_DOWNLOADED = 2
1016 };
1017
1018 /* retrieve parameters from hda format */
1019 #define get_hdafmt_chs(fmt) (fmt & 0xf)
1020 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
1021 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
1022 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
1023
1024 /*
1025 * CA0132 specific
1026 */
1027
1028 struct ca0132_spec {
1029 const struct snd_kcontrol_new *mixers[5];
1030 unsigned int num_mixers;
1031 const struct hda_verb *base_init_verbs;
1032 const struct hda_verb *base_exit_verbs;
1033 const struct hda_verb *chip_init_verbs;
1034 const struct hda_verb *desktop_init_verbs;
1035 struct hda_verb *spec_init_verbs;
1036 struct auto_pin_cfg autocfg;
1037
1038 /* Nodes configurations */
1039 struct hda_multi_out multiout;
1040 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1041 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1042 unsigned int num_outputs;
1043 hda_nid_t input_pins[AUTO_PIN_LAST];
1044 hda_nid_t adcs[AUTO_PIN_LAST];
1045 hda_nid_t dig_out;
1046 hda_nid_t dig_in;
1047 unsigned int num_inputs;
1048 hda_nid_t shared_mic_nid;
1049 hda_nid_t shared_out_nid;
1050 hda_nid_t unsol_tag_hp;
1051 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1052 hda_nid_t unsol_tag_amic1;
1053
1054 /* chip access */
1055 struct mutex chipio_mutex; /* chip access mutex */
1056 u32 curr_chip_addx;
1057
1058 /* DSP download related */
1059 enum dsp_download_state dsp_state;
1060 unsigned int dsp_stream_id;
1061 unsigned int wait_scp;
1062 unsigned int wait_scp_header;
1063 unsigned int wait_num_data;
1064 unsigned int scp_resp_header;
1065 unsigned int scp_resp_data[4];
1066 unsigned int scp_resp_count;
1067 bool startup_check_entered;
1068 bool dsp_reload;
1069
1070 /* mixer and effects related */
1071 unsigned char dmic_ctl;
1072 int cur_out_type;
1073 int cur_mic_type;
1074 long vnode_lvol[VNODES_COUNT];
1075 long vnode_rvol[VNODES_COUNT];
1076 long vnode_lswitch[VNODES_COUNT];
1077 long vnode_rswitch[VNODES_COUNT];
1078 long effects_switch[EFFECTS_COUNT];
1079 long voicefx_val;
1080 long cur_mic_boost;
1081 /* ca0132_alt control related values */
1082 unsigned char in_enum_val;
1083 unsigned char out_enum_val;
1084 unsigned char channel_cfg_val;
1085 unsigned char speaker_range_val[2];
1086 unsigned char mic_boost_enum_val;
1087 unsigned char smart_volume_setting;
1088 unsigned char bass_redirection_val;
1089 long bass_redirect_xover_freq;
1090 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1091 long xbass_xover_freq;
1092 long eq_preset_val;
1093 unsigned int tlv[4];
1094 struct hda_vmaster_mute_hook vmaster_mute;
1095 /* AE-5 Control values */
1096 unsigned char ae5_headphone_gain_val;
1097 unsigned char ae5_filter_val;
1098 /* ZxR Control Values */
1099 unsigned char zxr_gain_set;
1100
1101 struct hda_codec *codec;
1102 struct delayed_work unsol_hp_work;
1103 int quirk;
1104
1105 #ifdef ENABLE_TUNING_CONTROLS
1106 long cur_ctl_vals[TUNING_CTLS_COUNT];
1107 #endif
1108 /*
1109 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1110 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1111 * things.
1112 */
1113 bool use_pci_mmio;
1114 void __iomem *mem_base;
1115
1116 /*
1117 * Whether or not to use the alt functions like alt_select_out,
1118 * alt_select_in, etc. Only used on desktop codecs for now, because of
1119 * surround sound support.
1120 */
1121 bool use_alt_functions;
1122
1123 /*
1124 * Whether or not to use alt controls: volume effect sliders, EQ
1125 * presets, smart volume presets, and new control names with FX prefix.
1126 * Renames PlayEnhancement and CrystalVoice too.
1127 */
1128 bool use_alt_controls;
1129 };
1130
1131 /*
1132 * CA0132 quirks table
1133 */
1134 enum {
1135 QUIRK_NONE,
1136 QUIRK_ALIENWARE,
1137 QUIRK_ALIENWARE_M17XR4,
1138 QUIRK_SBZ,
1139 QUIRK_ZXR,
1140 QUIRK_ZXR_DBPRO,
1141 QUIRK_R3DI,
1142 QUIRK_R3D,
1143 QUIRK_AE5,
1144 QUIRK_AE7,
1145 };
1146
1147 #ifdef CONFIG_PCI
1148 #define ca0132_quirk(spec) ((spec)->quirk)
1149 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1150 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1151 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1152 #else
1153 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; })
1154 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; })
1155 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; })
1156 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; })
1157 #endif
1158
1159 static const struct hda_pintbl alienware_pincfgs[] = {
1160 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1161 { 0x0c, 0x411111f0 }, /* N/A */
1162 { 0x0d, 0x411111f0 }, /* N/A */
1163 { 0x0e, 0x411111f0 }, /* N/A */
1164 { 0x0f, 0x0321101f }, /* HP */
1165 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1166 { 0x11, 0x03a11021 }, /* Mic */
1167 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1168 { 0x13, 0x411111f0 }, /* N/A */
1169 { 0x18, 0x411111f0 }, /* N/A */
1170 {}
1171 };
1172
1173 /* Sound Blaster Z pin configs taken from Windows Driver */
1174 static const struct hda_pintbl sbz_pincfgs[] = {
1175 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1176 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1177 { 0x0d, 0x014510f0 }, /* Digital Out */
1178 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1179 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1180 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1181 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1182 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1183 { 0x13, 0x908700f0 }, /* What U Hear In*/
1184 { 0x18, 0x50d000f0 }, /* N/A */
1185 {}
1186 };
1187
1188 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1189 static const struct hda_pintbl zxr_pincfgs[] = {
1190 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1191 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1192 { 0x0d, 0x014510f0 }, /* Digital Out */
1193 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1194 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1195 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1196 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1197 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1198 { 0x13, 0x908700f0 }, /* What U Hear In*/
1199 { 0x18, 0x50d000f0 }, /* N/A */
1200 {}
1201 };
1202
1203 /* Recon3D pin configs taken from Windows Driver */
1204 static const struct hda_pintbl r3d_pincfgs[] = {
1205 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1206 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1207 { 0x0d, 0x014510f0 }, /* Digital Out */
1208 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1209 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1210 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1211 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1212 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1213 { 0x13, 0x908700f0 }, /* What U Hear In*/
1214 { 0x18, 0x50d000f0 }, /* N/A */
1215 {}
1216 };
1217
1218 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1219 static const struct hda_pintbl ae5_pincfgs[] = {
1220 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1221 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1222 { 0x0d, 0x014510f0 }, /* Digital Out */
1223 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1224 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1225 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1226 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1227 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1228 { 0x13, 0x908700f0 }, /* What U Hear In*/
1229 { 0x18, 0x50d000f0 }, /* N/A */
1230 {}
1231 };
1232
1233 /* Recon3D integrated pin configs taken from Windows Driver */
1234 static const struct hda_pintbl r3di_pincfgs[] = {
1235 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1236 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1237 { 0x0d, 0x014510f0 }, /* Digital Out */
1238 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1239 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1240 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1241 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1242 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1243 { 0x13, 0x908700f0 }, /* What U Hear In*/
1244 { 0x18, 0x500000f0 }, /* N/A */
1245 {}
1246 };
1247
1248 static const struct hda_pintbl ae7_pincfgs[] = {
1249 { 0x0b, 0x01017010 },
1250 { 0x0c, 0x014510f0 },
1251 { 0x0d, 0x414510f0 },
1252 { 0x0e, 0x01c520f0 },
1253 { 0x0f, 0x01017114 },
1254 { 0x10, 0x01017011 },
1255 { 0x11, 0x018170ff },
1256 { 0x12, 0x01a170f0 },
1257 { 0x13, 0x908700f0 },
1258 { 0x18, 0x500000f0 },
1259 {}
1260 };
1261
1262 static const struct snd_pci_quirk ca0132_quirks[] = {
1263 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1264 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1265 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1266 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1267 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1268 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1269 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1270 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1271 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1272 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1273 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1274 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1275 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1276 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1277 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1278 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1279 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1280 {}
1281 };
1282
1283 /* Output selection quirk info structures. */
1284 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1285 #define MAX_QUIRK_SCP_SET_VALS 2
1286 struct ca0132_alt_out_set_info {
1287 unsigned int dac2port; /* ParamID 0x0d value. */
1288
1289 bool has_hda_gpio;
1290 char hda_gpio_pin;
1291 char hda_gpio_set;
1292
1293 unsigned int mmio_gpio_count;
1294 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1295 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1296
1297 unsigned int scp_cmds_count;
1298 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1299 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1300 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1301
1302 bool has_chipio_write;
1303 unsigned int chipio_write_addr;
1304 unsigned int chipio_write_data;
1305 };
1306
1307 struct ca0132_alt_out_set_quirk_data {
1308 int quirk_id;
1309
1310 bool has_headphone_gain;
1311 bool is_ae_series;
1312
1313 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1314 };
1315
1316 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1317 { .quirk_id = QUIRK_R3DI,
1318 .has_headphone_gain = false,
1319 .is_ae_series = false,
1320 .out_set_info = {
1321 /* Speakers. */
1322 { .dac2port = 0x24,
1323 .has_hda_gpio = true,
1324 .hda_gpio_pin = 2,
1325 .hda_gpio_set = 1,
1326 .mmio_gpio_count = 0,
1327 .scp_cmds_count = 0,
1328 .has_chipio_write = false,
1329 },
1330 /* Headphones. */
1331 { .dac2port = 0x21,
1332 .has_hda_gpio = true,
1333 .hda_gpio_pin = 2,
1334 .hda_gpio_set = 0,
1335 .mmio_gpio_count = 0,
1336 .scp_cmds_count = 0,
1337 .has_chipio_write = false,
1338 } },
1339 },
1340 { .quirk_id = QUIRK_R3D,
1341 .has_headphone_gain = false,
1342 .is_ae_series = false,
1343 .out_set_info = {
1344 /* Speakers. */
1345 { .dac2port = 0x24,
1346 .has_hda_gpio = false,
1347 .mmio_gpio_count = 1,
1348 .mmio_gpio_pin = { 1 },
1349 .mmio_gpio_set = { 1 },
1350 .scp_cmds_count = 0,
1351 .has_chipio_write = false,
1352 },
1353 /* Headphones. */
1354 { .dac2port = 0x21,
1355 .has_hda_gpio = false,
1356 .mmio_gpio_count = 1,
1357 .mmio_gpio_pin = { 1 },
1358 .mmio_gpio_set = { 0 },
1359 .scp_cmds_count = 0,
1360 .has_chipio_write = false,
1361 } },
1362 },
1363 { .quirk_id = QUIRK_SBZ,
1364 .has_headphone_gain = false,
1365 .is_ae_series = false,
1366 .out_set_info = {
1367 /* Speakers. */
1368 { .dac2port = 0x18,
1369 .has_hda_gpio = false,
1370 .mmio_gpio_count = 3,
1371 .mmio_gpio_pin = { 7, 4, 1 },
1372 .mmio_gpio_set = { 0, 1, 1 },
1373 .scp_cmds_count = 0,
1374 .has_chipio_write = false, },
1375 /* Headphones. */
1376 { .dac2port = 0x12,
1377 .has_hda_gpio = false,
1378 .mmio_gpio_count = 3,
1379 .mmio_gpio_pin = { 7, 4, 1 },
1380 .mmio_gpio_set = { 1, 1, 0 },
1381 .scp_cmds_count = 0,
1382 .has_chipio_write = false,
1383 } },
1384 },
1385 { .quirk_id = QUIRK_ZXR,
1386 .has_headphone_gain = true,
1387 .is_ae_series = false,
1388 .out_set_info = {
1389 /* Speakers. */
1390 { .dac2port = 0x24,
1391 .has_hda_gpio = false,
1392 .mmio_gpio_count = 3,
1393 .mmio_gpio_pin = { 2, 3, 5 },
1394 .mmio_gpio_set = { 1, 1, 0 },
1395 .scp_cmds_count = 0,
1396 .has_chipio_write = false,
1397 },
1398 /* Headphones. */
1399 { .dac2port = 0x21,
1400 .has_hda_gpio = false,
1401 .mmio_gpio_count = 3,
1402 .mmio_gpio_pin = { 2, 3, 5 },
1403 .mmio_gpio_set = { 0, 1, 1 },
1404 .scp_cmds_count = 0,
1405 .has_chipio_write = false,
1406 } },
1407 },
1408 { .quirk_id = QUIRK_AE5,
1409 .has_headphone_gain = true,
1410 .is_ae_series = true,
1411 .out_set_info = {
1412 /* Speakers. */
1413 { .dac2port = 0xa4,
1414 .has_hda_gpio = false,
1415 .mmio_gpio_count = 0,
1416 .scp_cmds_count = 2,
1417 .scp_cmd_mid = { 0x96, 0x96 },
1418 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1419 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1420 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1421 .has_chipio_write = true,
1422 .chipio_write_addr = 0x0018b03c,
1423 .chipio_write_data = 0x00000012
1424 },
1425 /* Headphones. */
1426 { .dac2port = 0xa1,
1427 .has_hda_gpio = false,
1428 .mmio_gpio_count = 0,
1429 .scp_cmds_count = 2,
1430 .scp_cmd_mid = { 0x96, 0x96 },
1431 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1432 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1433 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1434 .has_chipio_write = true,
1435 .chipio_write_addr = 0x0018b03c,
1436 .chipio_write_data = 0x00000012
1437 } },
1438 },
1439 { .quirk_id = QUIRK_AE7,
1440 .has_headphone_gain = true,
1441 .is_ae_series = true,
1442 .out_set_info = {
1443 /* Speakers. */
1444 { .dac2port = 0x58,
1445 .has_hda_gpio = false,
1446 .mmio_gpio_count = 1,
1447 .mmio_gpio_pin = { 0 },
1448 .mmio_gpio_set = { 1 },
1449 .scp_cmds_count = 2,
1450 .scp_cmd_mid = { 0x96, 0x96 },
1451 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1452 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1453 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1454 .has_chipio_write = true,
1455 .chipio_write_addr = 0x0018b03c,
1456 .chipio_write_data = 0x00000000
1457 },
1458 /* Headphones. */
1459 { .dac2port = 0x58,
1460 .has_hda_gpio = false,
1461 .mmio_gpio_count = 1,
1462 .mmio_gpio_pin = { 0 },
1463 .mmio_gpio_set = { 1 },
1464 .scp_cmds_count = 2,
1465 .scp_cmd_mid = { 0x96, 0x96 },
1466 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1467 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1468 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1469 .has_chipio_write = true,
1470 .chipio_write_addr = 0x0018b03c,
1471 .chipio_write_data = 0x00000010
1472 } },
1473 }
1474 };
1475
1476 /*
1477 * CA0132 codec access
1478 */
codec_send_command(struct hda_codec * codec,hda_nid_t nid,unsigned int verb,unsigned int parm,unsigned int * res)1479 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1480 unsigned int verb, unsigned int parm, unsigned int *res)
1481 {
1482 unsigned int response;
1483 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1484 *res = response;
1485
1486 return ((response == -1) ? -1 : 0);
1487 }
1488
codec_set_converter_format(struct hda_codec * codec,hda_nid_t nid,unsigned short converter_format,unsigned int * res)1489 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1490 unsigned short converter_format, unsigned int *res)
1491 {
1492 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1493 converter_format & 0xffff, res);
1494 }
1495
codec_set_converter_stream_channel(struct hda_codec * codec,hda_nid_t nid,unsigned char stream,unsigned char channel,unsigned int * res)1496 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1497 hda_nid_t nid, unsigned char stream,
1498 unsigned char channel, unsigned int *res)
1499 {
1500 unsigned char converter_stream_channel = 0;
1501
1502 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1503 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1504 converter_stream_channel, res);
1505 }
1506
1507 /* Chip access helper function */
chipio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)1508 static int chipio_send(struct hda_codec *codec,
1509 unsigned int reg,
1510 unsigned int data)
1511 {
1512 unsigned int res;
1513 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1514
1515 /* send bits of data specified by reg */
1516 do {
1517 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1518 reg, data);
1519 if (res == VENDOR_STATUS_CHIPIO_OK)
1520 return 0;
1521 msleep(20);
1522 } while (time_before(jiffies, timeout));
1523
1524 return -EIO;
1525 }
1526
1527 /*
1528 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1529 */
chipio_write_address(struct hda_codec * codec,unsigned int chip_addx)1530 static int chipio_write_address(struct hda_codec *codec,
1531 unsigned int chip_addx)
1532 {
1533 struct ca0132_spec *spec = codec->spec;
1534 int res;
1535
1536 if (spec->curr_chip_addx == chip_addx)
1537 return 0;
1538
1539 /* send low 16 bits of the address */
1540 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1541 chip_addx & 0xffff);
1542
1543 if (res != -EIO) {
1544 /* send high 16 bits of the address */
1545 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1546 chip_addx >> 16);
1547 }
1548
1549 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1550
1551 return res;
1552 }
1553
1554 /*
1555 * Write data through the vendor widget -- NOT protected by the Mutex!
1556 */
chipio_write_data(struct hda_codec * codec,unsigned int data)1557 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1558 {
1559 struct ca0132_spec *spec = codec->spec;
1560 int res;
1561
1562 /* send low 16 bits of the data */
1563 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1564
1565 if (res != -EIO) {
1566 /* send high 16 bits of the data */
1567 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1568 data >> 16);
1569 }
1570
1571 /*If no error encountered, automatically increment the address
1572 as per chip behaviour*/
1573 spec->curr_chip_addx = (res != -EIO) ?
1574 (spec->curr_chip_addx + 4) : ~0U;
1575 return res;
1576 }
1577
1578 /*
1579 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1580 */
chipio_write_data_multiple(struct hda_codec * codec,const u32 * data,unsigned int count)1581 static int chipio_write_data_multiple(struct hda_codec *codec,
1582 const u32 *data,
1583 unsigned int count)
1584 {
1585 int status = 0;
1586
1587 if (data == NULL) {
1588 codec_dbg(codec, "chipio_write_data null ptr\n");
1589 return -EINVAL;
1590 }
1591
1592 while ((count-- != 0) && (status == 0))
1593 status = chipio_write_data(codec, *data++);
1594
1595 return status;
1596 }
1597
1598
1599 /*
1600 * Read data through the vendor widget -- NOT protected by the Mutex!
1601 */
chipio_read_data(struct hda_codec * codec,unsigned int * data)1602 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1603 {
1604 struct ca0132_spec *spec = codec->spec;
1605 int res;
1606
1607 /* post read */
1608 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1609
1610 if (res != -EIO) {
1611 /* read status */
1612 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1613 }
1614
1615 if (res != -EIO) {
1616 /* read data */
1617 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1618 VENDOR_CHIPIO_HIC_READ_DATA,
1619 0);
1620 }
1621
1622 /*If no error encountered, automatically increment the address
1623 as per chip behaviour*/
1624 spec->curr_chip_addx = (res != -EIO) ?
1625 (spec->curr_chip_addx + 4) : ~0U;
1626 return res;
1627 }
1628
1629 /*
1630 * Write given value to the given address through the chip I/O widget.
1631 * protected by the Mutex
1632 */
chipio_write(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1633 static int chipio_write(struct hda_codec *codec,
1634 unsigned int chip_addx, const unsigned int data)
1635 {
1636 struct ca0132_spec *spec = codec->spec;
1637 int err;
1638
1639 mutex_lock(&spec->chipio_mutex);
1640
1641 /* write the address, and if successful proceed to write data */
1642 err = chipio_write_address(codec, chip_addx);
1643 if (err < 0)
1644 goto exit;
1645
1646 err = chipio_write_data(codec, data);
1647 if (err < 0)
1648 goto exit;
1649
1650 exit:
1651 mutex_unlock(&spec->chipio_mutex);
1652 return err;
1653 }
1654
1655 /*
1656 * Write given value to the given address through the chip I/O widget.
1657 * not protected by the Mutex
1658 */
chipio_write_no_mutex(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1659 static int chipio_write_no_mutex(struct hda_codec *codec,
1660 unsigned int chip_addx, const unsigned int data)
1661 {
1662 int err;
1663
1664
1665 /* write the address, and if successful proceed to write data */
1666 err = chipio_write_address(codec, chip_addx);
1667 if (err < 0)
1668 goto exit;
1669
1670 err = chipio_write_data(codec, data);
1671 if (err < 0)
1672 goto exit;
1673
1674 exit:
1675 return err;
1676 }
1677
1678 /*
1679 * Write multiple values to the given address through the chip I/O widget.
1680 * protected by the Mutex
1681 */
chipio_write_multiple(struct hda_codec * codec,u32 chip_addx,const u32 * data,unsigned int count)1682 static int chipio_write_multiple(struct hda_codec *codec,
1683 u32 chip_addx,
1684 const u32 *data,
1685 unsigned int count)
1686 {
1687 struct ca0132_spec *spec = codec->spec;
1688 int status;
1689
1690 mutex_lock(&spec->chipio_mutex);
1691 status = chipio_write_address(codec, chip_addx);
1692 if (status < 0)
1693 goto error;
1694
1695 status = chipio_write_data_multiple(codec, data, count);
1696 error:
1697 mutex_unlock(&spec->chipio_mutex);
1698
1699 return status;
1700 }
1701
1702 /*
1703 * Read the given address through the chip I/O widget
1704 * protected by the Mutex
1705 */
chipio_read(struct hda_codec * codec,unsigned int chip_addx,unsigned int * data)1706 static int chipio_read(struct hda_codec *codec,
1707 unsigned int chip_addx, unsigned int *data)
1708 {
1709 struct ca0132_spec *spec = codec->spec;
1710 int err;
1711
1712 mutex_lock(&spec->chipio_mutex);
1713
1714 /* write the address, and if successful proceed to write data */
1715 err = chipio_write_address(codec, chip_addx);
1716 if (err < 0)
1717 goto exit;
1718
1719 err = chipio_read_data(codec, data);
1720 if (err < 0)
1721 goto exit;
1722
1723 exit:
1724 mutex_unlock(&spec->chipio_mutex);
1725 return err;
1726 }
1727
1728 /*
1729 * Set chip control flags through the chip I/O widget.
1730 */
chipio_set_control_flag(struct hda_codec * codec,enum control_flag_id flag_id,bool flag_state)1731 static void chipio_set_control_flag(struct hda_codec *codec,
1732 enum control_flag_id flag_id,
1733 bool flag_state)
1734 {
1735 unsigned int val;
1736 unsigned int flag_bit;
1737
1738 flag_bit = (flag_state ? 1 : 0);
1739 val = (flag_bit << 7) | (flag_id);
1740 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1741 VENDOR_CHIPIO_FLAG_SET, val);
1742 }
1743
1744 /*
1745 * Set chip parameters through the chip I/O widget.
1746 */
chipio_set_control_param(struct hda_codec * codec,enum control_param_id param_id,int param_val)1747 static void chipio_set_control_param(struct hda_codec *codec,
1748 enum control_param_id param_id, int param_val)
1749 {
1750 struct ca0132_spec *spec = codec->spec;
1751 int val;
1752
1753 if ((param_id < 32) && (param_val < 8)) {
1754 val = (param_val << 5) | (param_id);
1755 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1756 VENDOR_CHIPIO_PARAM_SET, val);
1757 } else {
1758 mutex_lock(&spec->chipio_mutex);
1759 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1760 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1761 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1762 param_id);
1763 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1764 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1765 param_val);
1766 }
1767 mutex_unlock(&spec->chipio_mutex);
1768 }
1769 }
1770
1771 /*
1772 * Set chip parameters through the chip I/O widget. NO MUTEX.
1773 */
chipio_set_control_param_no_mutex(struct hda_codec * codec,enum control_param_id param_id,int param_val)1774 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1775 enum control_param_id param_id, int param_val)
1776 {
1777 int val;
1778
1779 if ((param_id < 32) && (param_val < 8)) {
1780 val = (param_val << 5) | (param_id);
1781 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1782 VENDOR_CHIPIO_PARAM_SET, val);
1783 } else {
1784 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1785 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1786 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1787 param_id);
1788 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1789 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1790 param_val);
1791 }
1792 }
1793 }
1794 /*
1795 * Connect stream to a source point, and then connect
1796 * that source point to a destination point.
1797 */
chipio_set_stream_source_dest(struct hda_codec * codec,int streamid,int source_point,int dest_point)1798 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1799 int streamid, int source_point, int dest_point)
1800 {
1801 chipio_set_control_param_no_mutex(codec,
1802 CONTROL_PARAM_STREAM_ID, streamid);
1803 chipio_set_control_param_no_mutex(codec,
1804 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1805 chipio_set_control_param_no_mutex(codec,
1806 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1807 }
1808
1809 /*
1810 * Set number of channels in the selected stream.
1811 */
chipio_set_stream_channels(struct hda_codec * codec,int streamid,unsigned int channels)1812 static void chipio_set_stream_channels(struct hda_codec *codec,
1813 int streamid, unsigned int channels)
1814 {
1815 chipio_set_control_param_no_mutex(codec,
1816 CONTROL_PARAM_STREAM_ID, streamid);
1817 chipio_set_control_param_no_mutex(codec,
1818 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1819 }
1820
1821 /*
1822 * Enable/Disable audio stream.
1823 */
chipio_set_stream_control(struct hda_codec * codec,int streamid,int enable)1824 static void chipio_set_stream_control(struct hda_codec *codec,
1825 int streamid, int enable)
1826 {
1827 chipio_set_control_param_no_mutex(codec,
1828 CONTROL_PARAM_STREAM_ID, streamid);
1829 chipio_set_control_param_no_mutex(codec,
1830 CONTROL_PARAM_STREAM_CONTROL, enable);
1831 }
1832
1833
1834 /*
1835 * Set sampling rate of the connection point. NO MUTEX.
1836 */
chipio_set_conn_rate_no_mutex(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1837 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1838 int connid, enum ca0132_sample_rate rate)
1839 {
1840 chipio_set_control_param_no_mutex(codec,
1841 CONTROL_PARAM_CONN_POINT_ID, connid);
1842 chipio_set_control_param_no_mutex(codec,
1843 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1844 }
1845
1846 /*
1847 * Set sampling rate of the connection point.
1848 */
chipio_set_conn_rate(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1849 static void chipio_set_conn_rate(struct hda_codec *codec,
1850 int connid, enum ca0132_sample_rate rate)
1851 {
1852 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1853 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1854 rate);
1855 }
1856
1857 /*
1858 * Writes to the 8051's internal address space directly instead of indirectly,
1859 * giving access to the special function registers located at addresses
1860 * 0x80-0xFF.
1861 */
chipio_8051_write_direct(struct hda_codec * codec,unsigned int addr,unsigned int data)1862 static void chipio_8051_write_direct(struct hda_codec *codec,
1863 unsigned int addr, unsigned int data)
1864 {
1865 unsigned int verb;
1866
1867 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1868 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1869 }
1870
1871 /*
1872 * Enable clocks.
1873 */
chipio_enable_clocks(struct hda_codec * codec)1874 static void chipio_enable_clocks(struct hda_codec *codec)
1875 {
1876 struct ca0132_spec *spec = codec->spec;
1877
1878 mutex_lock(&spec->chipio_mutex);
1879 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1880 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1881 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1882 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1883 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1884 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1885 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1886 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1887 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1888 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1889 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1890 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1891 mutex_unlock(&spec->chipio_mutex);
1892 }
1893
1894 /*
1895 * CA0132 DSP IO stuffs
1896 */
dspio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)1897 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1898 unsigned int data)
1899 {
1900 int res;
1901 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1902
1903 /* send bits of data specified by reg to dsp */
1904 do {
1905 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1906 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1907 return res;
1908 msleep(20);
1909 } while (time_before(jiffies, timeout));
1910
1911 return -EIO;
1912 }
1913
1914 /*
1915 * Wait for DSP to be ready for commands
1916 */
dspio_write_wait(struct hda_codec * codec)1917 static void dspio_write_wait(struct hda_codec *codec)
1918 {
1919 int status;
1920 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1921
1922 do {
1923 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1924 VENDOR_DSPIO_STATUS, 0);
1925 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1926 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1927 break;
1928 msleep(1);
1929 } while (time_before(jiffies, timeout));
1930 }
1931
1932 /*
1933 * Write SCP data to DSP
1934 */
dspio_write(struct hda_codec * codec,unsigned int scp_data)1935 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1936 {
1937 struct ca0132_spec *spec = codec->spec;
1938 int status;
1939
1940 dspio_write_wait(codec);
1941
1942 mutex_lock(&spec->chipio_mutex);
1943 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1944 scp_data & 0xffff);
1945 if (status < 0)
1946 goto error;
1947
1948 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1949 scp_data >> 16);
1950 if (status < 0)
1951 goto error;
1952
1953 /* OK, now check if the write itself has executed*/
1954 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1955 VENDOR_DSPIO_STATUS, 0);
1956 error:
1957 mutex_unlock(&spec->chipio_mutex);
1958
1959 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1960 -EIO : 0;
1961 }
1962
1963 /*
1964 * Write multiple SCP data to DSP
1965 */
dspio_write_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int size)1966 static int dspio_write_multiple(struct hda_codec *codec,
1967 unsigned int *buffer, unsigned int size)
1968 {
1969 int status = 0;
1970 unsigned int count;
1971
1972 if (buffer == NULL)
1973 return -EINVAL;
1974
1975 count = 0;
1976 while (count < size) {
1977 status = dspio_write(codec, *buffer++);
1978 if (status != 0)
1979 break;
1980 count++;
1981 }
1982
1983 return status;
1984 }
1985
dspio_read(struct hda_codec * codec,unsigned int * data)1986 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1987 {
1988 int status;
1989
1990 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1991 if (status == -EIO)
1992 return status;
1993
1994 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1995 if (status == -EIO ||
1996 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1997 return -EIO;
1998
1999 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2000 VENDOR_DSPIO_SCP_READ_DATA, 0);
2001
2002 return 0;
2003 }
2004
dspio_read_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int * buf_size,unsigned int size_count)2005 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2006 unsigned int *buf_size, unsigned int size_count)
2007 {
2008 int status = 0;
2009 unsigned int size = *buf_size;
2010 unsigned int count;
2011 unsigned int skip_count;
2012 unsigned int dummy;
2013
2014 if (buffer == NULL)
2015 return -1;
2016
2017 count = 0;
2018 while (count < size && count < size_count) {
2019 status = dspio_read(codec, buffer++);
2020 if (status != 0)
2021 break;
2022 count++;
2023 }
2024
2025 skip_count = count;
2026 if (status == 0) {
2027 while (skip_count < size) {
2028 status = dspio_read(codec, &dummy);
2029 if (status != 0)
2030 break;
2031 skip_count++;
2032 }
2033 }
2034 *buf_size = count;
2035
2036 return status;
2037 }
2038
2039 /*
2040 * Construct the SCP header using corresponding fields
2041 */
2042 static inline unsigned int
make_scp_header(unsigned int target_id,unsigned int source_id,unsigned int get_flag,unsigned int req,unsigned int device_flag,unsigned int resp_flag,unsigned int error_flag,unsigned int data_size)2043 make_scp_header(unsigned int target_id, unsigned int source_id,
2044 unsigned int get_flag, unsigned int req,
2045 unsigned int device_flag, unsigned int resp_flag,
2046 unsigned int error_flag, unsigned int data_size)
2047 {
2048 unsigned int header = 0;
2049
2050 header = (data_size & 0x1f) << 27;
2051 header |= (error_flag & 0x01) << 26;
2052 header |= (resp_flag & 0x01) << 25;
2053 header |= (device_flag & 0x01) << 24;
2054 header |= (req & 0x7f) << 17;
2055 header |= (get_flag & 0x01) << 16;
2056 header |= (source_id & 0xff) << 8;
2057 header |= target_id & 0xff;
2058
2059 return header;
2060 }
2061
2062 /*
2063 * Extract corresponding fields from SCP header
2064 */
2065 static inline void
extract_scp_header(unsigned int header,unsigned int * target_id,unsigned int * source_id,unsigned int * get_flag,unsigned int * req,unsigned int * device_flag,unsigned int * resp_flag,unsigned int * error_flag,unsigned int * data_size)2066 extract_scp_header(unsigned int header,
2067 unsigned int *target_id, unsigned int *source_id,
2068 unsigned int *get_flag, unsigned int *req,
2069 unsigned int *device_flag, unsigned int *resp_flag,
2070 unsigned int *error_flag, unsigned int *data_size)
2071 {
2072 if (data_size)
2073 *data_size = (header >> 27) & 0x1f;
2074 if (error_flag)
2075 *error_flag = (header >> 26) & 0x01;
2076 if (resp_flag)
2077 *resp_flag = (header >> 25) & 0x01;
2078 if (device_flag)
2079 *device_flag = (header >> 24) & 0x01;
2080 if (req)
2081 *req = (header >> 17) & 0x7f;
2082 if (get_flag)
2083 *get_flag = (header >> 16) & 0x01;
2084 if (source_id)
2085 *source_id = (header >> 8) & 0xff;
2086 if (target_id)
2087 *target_id = header & 0xff;
2088 }
2089
2090 #define SCP_MAX_DATA_WORDS (16)
2091
2092 /* Structure to contain any SCP message */
2093 struct scp_msg {
2094 unsigned int hdr;
2095 unsigned int data[SCP_MAX_DATA_WORDS];
2096 };
2097
dspio_clear_response_queue(struct hda_codec * codec)2098 static void dspio_clear_response_queue(struct hda_codec *codec)
2099 {
2100 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2101 unsigned int dummy = 0;
2102 int status;
2103
2104 /* clear all from the response queue */
2105 do {
2106 status = dspio_read(codec, &dummy);
2107 } while (status == 0 && time_before(jiffies, timeout));
2108 }
2109
dspio_get_response_data(struct hda_codec * codec)2110 static int dspio_get_response_data(struct hda_codec *codec)
2111 {
2112 struct ca0132_spec *spec = codec->spec;
2113 unsigned int data = 0;
2114 unsigned int count;
2115
2116 if (dspio_read(codec, &data) < 0)
2117 return -EIO;
2118
2119 if ((data & 0x00ffffff) == spec->wait_scp_header) {
2120 spec->scp_resp_header = data;
2121 spec->scp_resp_count = data >> 27;
2122 count = spec->wait_num_data;
2123 dspio_read_multiple(codec, spec->scp_resp_data,
2124 &spec->scp_resp_count, count);
2125 return 0;
2126 }
2127
2128 return -EIO;
2129 }
2130
2131 /*
2132 * Send SCP message to DSP
2133 */
dspio_send_scp_message(struct hda_codec * codec,unsigned char * send_buf,unsigned int send_buf_size,unsigned char * return_buf,unsigned int return_buf_size,unsigned int * bytes_returned)2134 static int dspio_send_scp_message(struct hda_codec *codec,
2135 unsigned char *send_buf,
2136 unsigned int send_buf_size,
2137 unsigned char *return_buf,
2138 unsigned int return_buf_size,
2139 unsigned int *bytes_returned)
2140 {
2141 struct ca0132_spec *spec = codec->spec;
2142 int status = -1;
2143 unsigned int scp_send_size = 0;
2144 unsigned int total_size;
2145 bool waiting_for_resp = false;
2146 unsigned int header;
2147 struct scp_msg *ret_msg;
2148 unsigned int resp_src_id, resp_target_id;
2149 unsigned int data_size, src_id, target_id, get_flag, device_flag;
2150
2151 if (bytes_returned)
2152 *bytes_returned = 0;
2153
2154 /* get scp header from buffer */
2155 header = *((unsigned int *)send_buf);
2156 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2157 &device_flag, NULL, NULL, &data_size);
2158 scp_send_size = data_size + 1;
2159 total_size = (scp_send_size * 4);
2160
2161 if (send_buf_size < total_size)
2162 return -EINVAL;
2163
2164 if (get_flag || device_flag) {
2165 if (!return_buf || return_buf_size < 4 || !bytes_returned)
2166 return -EINVAL;
2167
2168 spec->wait_scp_header = *((unsigned int *)send_buf);
2169
2170 /* swap source id with target id */
2171 resp_target_id = src_id;
2172 resp_src_id = target_id;
2173 spec->wait_scp_header &= 0xffff0000;
2174 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2175 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2176 spec->wait_scp = 1;
2177 waiting_for_resp = true;
2178 }
2179
2180 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2181 scp_send_size);
2182 if (status < 0) {
2183 spec->wait_scp = 0;
2184 return status;
2185 }
2186
2187 if (waiting_for_resp) {
2188 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2189 memset(return_buf, 0, return_buf_size);
2190 do {
2191 msleep(20);
2192 } while (spec->wait_scp && time_before(jiffies, timeout));
2193 waiting_for_resp = false;
2194 if (!spec->wait_scp) {
2195 ret_msg = (struct scp_msg *)return_buf;
2196 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2197 memcpy(&ret_msg->data, spec->scp_resp_data,
2198 spec->wait_num_data);
2199 *bytes_returned = (spec->scp_resp_count + 1) * 4;
2200 status = 0;
2201 } else {
2202 status = -EIO;
2203 }
2204 spec->wait_scp = 0;
2205 }
2206
2207 return status;
2208 }
2209
2210 /**
2211 * Prepare and send the SCP message to DSP
2212 * @codec: the HDA codec
2213 * @mod_id: ID of the DSP module to send the command
2214 * @src_id: ID of the source
2215 * @req: ID of request to send to the DSP module
2216 * @dir: SET or GET
2217 * @data: pointer to the data to send with the request, request specific
2218 * @len: length of the data, in bytes
2219 * @reply: point to the buffer to hold data returned for a reply
2220 * @reply_len: length of the reply buffer returned from GET
2221 *
2222 * Returns zero or a negative error code.
2223 */
dspio_scp(struct hda_codec * codec,int mod_id,int src_id,int req,int dir,const void * data,unsigned int len,void * reply,unsigned int * reply_len)2224 static int dspio_scp(struct hda_codec *codec,
2225 int mod_id, int src_id, int req, int dir, const void *data,
2226 unsigned int len, void *reply, unsigned int *reply_len)
2227 {
2228 int status = 0;
2229 struct scp_msg scp_send, scp_reply;
2230 unsigned int ret_bytes, send_size, ret_size;
2231 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2232 unsigned int reply_data_size;
2233
2234 memset(&scp_send, 0, sizeof(scp_send));
2235 memset(&scp_reply, 0, sizeof(scp_reply));
2236
2237 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2238 return -EINVAL;
2239
2240 if (dir == SCP_GET && reply == NULL) {
2241 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2242 return -EINVAL;
2243 }
2244
2245 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2246 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2247 return -EINVAL;
2248 }
2249
2250 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2251 0, 0, 0, len/sizeof(unsigned int));
2252 if (data != NULL && len > 0) {
2253 len = min((unsigned int)(sizeof(scp_send.data)), len);
2254 memcpy(scp_send.data, data, len);
2255 }
2256
2257 ret_bytes = 0;
2258 send_size = sizeof(unsigned int) + len;
2259 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2260 send_size, (unsigned char *)&scp_reply,
2261 sizeof(scp_reply), &ret_bytes);
2262
2263 if (status < 0) {
2264 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2265 return status;
2266 }
2267
2268 /* extract send and reply headers members */
2269 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2270 NULL, NULL, NULL, NULL, NULL);
2271 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2272 &reply_resp_flag, &reply_error_flag,
2273 &reply_data_size);
2274
2275 if (!send_get_flag)
2276 return 0;
2277
2278 if (reply_resp_flag && !reply_error_flag) {
2279 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2280 / sizeof(unsigned int);
2281
2282 if (*reply_len < ret_size*sizeof(unsigned int)) {
2283 codec_dbg(codec, "reply too long for buf\n");
2284 return -EINVAL;
2285 } else if (ret_size != reply_data_size) {
2286 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2287 return -EINVAL;
2288 } else if (!reply) {
2289 codec_dbg(codec, "NULL reply\n");
2290 return -EINVAL;
2291 } else {
2292 *reply_len = ret_size*sizeof(unsigned int);
2293 memcpy(reply, scp_reply.data, *reply_len);
2294 }
2295 } else {
2296 codec_dbg(codec, "reply ill-formed or errflag set\n");
2297 return -EIO;
2298 }
2299
2300 return status;
2301 }
2302
2303 /*
2304 * Set DSP parameters
2305 */
dspio_set_param(struct hda_codec * codec,int mod_id,int src_id,int req,const void * data,unsigned int len)2306 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2307 int src_id, int req, const void *data, unsigned int len)
2308 {
2309 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2310 NULL);
2311 }
2312
dspio_set_uint_param(struct hda_codec * codec,int mod_id,int req,const unsigned int data)2313 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2314 int req, const unsigned int data)
2315 {
2316 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2317 sizeof(unsigned int));
2318 }
2319
dspio_set_uint_param_no_source(struct hda_codec * codec,int mod_id,int req,const unsigned int data)2320 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2321 int req, const unsigned int data)
2322 {
2323 return dspio_set_param(codec, mod_id, 0x00, req, &data,
2324 sizeof(unsigned int));
2325 }
2326
2327 /*
2328 * Allocate a DSP DMA channel via an SCP message
2329 */
dspio_alloc_dma_chan(struct hda_codec * codec,unsigned int * dma_chan)2330 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2331 {
2332 int status = 0;
2333 unsigned int size = sizeof(dma_chan);
2334
2335 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
2336 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2337 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2338 dma_chan, &size);
2339
2340 if (status < 0) {
2341 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2342 return status;
2343 }
2344
2345 if ((*dma_chan + 1) == 0) {
2346 codec_dbg(codec, "no free dma channels to allocate\n");
2347 return -EBUSY;
2348 }
2349
2350 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2351 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
2352
2353 return status;
2354 }
2355
2356 /*
2357 * Free a DSP DMA via an SCP message
2358 */
dspio_free_dma_chan(struct hda_codec * codec,unsigned int dma_chan)2359 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2360 {
2361 int status = 0;
2362 unsigned int dummy = 0;
2363
2364 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2365 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2366
2367 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2368 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2369 sizeof(dma_chan), NULL, &dummy);
2370
2371 if (status < 0) {
2372 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2373 return status;
2374 }
2375
2376 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
2377
2378 return status;
2379 }
2380
2381 /*
2382 * (Re)start the DSP
2383 */
dsp_set_run_state(struct hda_codec * codec)2384 static int dsp_set_run_state(struct hda_codec *codec)
2385 {
2386 unsigned int dbg_ctrl_reg;
2387 unsigned int halt_state;
2388 int err;
2389
2390 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2391 if (err < 0)
2392 return err;
2393
2394 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2395 DSP_DBGCNTL_STATE_LOBIT;
2396
2397 if (halt_state != 0) {
2398 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2399 DSP_DBGCNTL_SS_MASK);
2400 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2401 dbg_ctrl_reg);
2402 if (err < 0)
2403 return err;
2404
2405 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2406 DSP_DBGCNTL_EXEC_MASK;
2407 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2408 dbg_ctrl_reg);
2409 if (err < 0)
2410 return err;
2411 }
2412
2413 return 0;
2414 }
2415
2416 /*
2417 * Reset the DSP
2418 */
dsp_reset(struct hda_codec * codec)2419 static int dsp_reset(struct hda_codec *codec)
2420 {
2421 unsigned int res;
2422 int retry = 20;
2423
2424 codec_dbg(codec, "dsp_reset\n");
2425 do {
2426 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2427 retry--;
2428 } while (res == -EIO && retry);
2429
2430 if (!retry) {
2431 codec_dbg(codec, "dsp_reset timeout\n");
2432 return -EIO;
2433 }
2434
2435 return 0;
2436 }
2437
2438 /*
2439 * Convert chip address to DSP address
2440 */
dsp_chip_to_dsp_addx(unsigned int chip_addx,bool * code,bool * yram)2441 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2442 bool *code, bool *yram)
2443 {
2444 *code = *yram = false;
2445
2446 if (UC_RANGE(chip_addx, 1)) {
2447 *code = true;
2448 return UC_OFF(chip_addx);
2449 } else if (X_RANGE_ALL(chip_addx, 1)) {
2450 return X_OFF(chip_addx);
2451 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2452 *yram = true;
2453 return Y_OFF(chip_addx);
2454 }
2455
2456 return INVALID_CHIP_ADDRESS;
2457 }
2458
2459 /*
2460 * Check if the DSP DMA is active
2461 */
dsp_is_dma_active(struct hda_codec * codec,unsigned int dma_chan)2462 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2463 {
2464 unsigned int dma_chnlstart_reg;
2465
2466 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2467
2468 return ((dma_chnlstart_reg & (1 <<
2469 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2470 }
2471
dsp_dma_setup_common(struct hda_codec * codec,unsigned int chip_addx,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)2472 static int dsp_dma_setup_common(struct hda_codec *codec,
2473 unsigned int chip_addx,
2474 unsigned int dma_chan,
2475 unsigned int port_map_mask,
2476 bool ovly)
2477 {
2478 int status = 0;
2479 unsigned int chnl_prop;
2480 unsigned int dsp_addx;
2481 unsigned int active;
2482 bool code, yram;
2483
2484 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2485
2486 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2487 codec_dbg(codec, "dma chan num invalid\n");
2488 return -EINVAL;
2489 }
2490
2491 if (dsp_is_dma_active(codec, dma_chan)) {
2492 codec_dbg(codec, "dma already active\n");
2493 return -EBUSY;
2494 }
2495
2496 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2497
2498 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2499 codec_dbg(codec, "invalid chip addr\n");
2500 return -ENXIO;
2501 }
2502
2503 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2504 active = 0;
2505
2506 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2507
2508 if (ovly) {
2509 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2510 &chnl_prop);
2511
2512 if (status < 0) {
2513 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2514 return status;
2515 }
2516 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2517 }
2518
2519 if (!code)
2520 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2521 else
2522 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2523
2524 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2525
2526 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2527 if (status < 0) {
2528 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2529 return status;
2530 }
2531 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2532
2533 if (ovly) {
2534 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2535 &active);
2536
2537 if (status < 0) {
2538 codec_dbg(codec, "read ACTIVE Reg fail\n");
2539 return status;
2540 }
2541 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2542 }
2543
2544 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2545 DSPDMAC_ACTIVE_AAR_MASK;
2546
2547 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2548 if (status < 0) {
2549 codec_dbg(codec, "write ACTIVE Reg fail\n");
2550 return status;
2551 }
2552
2553 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2554
2555 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2556 port_map_mask);
2557 if (status < 0) {
2558 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2559 return status;
2560 }
2561 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2562
2563 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2564 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2565 if (status < 0) {
2566 codec_dbg(codec, "write IRQCNT Reg fail\n");
2567 return status;
2568 }
2569 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2570
2571 codec_dbg(codec,
2572 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2573 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2574 chip_addx, dsp_addx, dma_chan,
2575 port_map_mask, chnl_prop, active);
2576
2577 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2578
2579 return 0;
2580 }
2581
2582 /*
2583 * Setup the DSP DMA per-transfer-specific registers
2584 */
dsp_dma_setup(struct hda_codec * codec,unsigned int chip_addx,unsigned int count,unsigned int dma_chan)2585 static int dsp_dma_setup(struct hda_codec *codec,
2586 unsigned int chip_addx,
2587 unsigned int count,
2588 unsigned int dma_chan)
2589 {
2590 int status = 0;
2591 bool code, yram;
2592 unsigned int dsp_addx;
2593 unsigned int addr_field;
2594 unsigned int incr_field;
2595 unsigned int base_cnt;
2596 unsigned int cur_cnt;
2597 unsigned int dma_cfg = 0;
2598 unsigned int adr_ofs = 0;
2599 unsigned int xfr_cnt = 0;
2600 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2601 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2602
2603 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2604
2605 if (count > max_dma_count) {
2606 codec_dbg(codec, "count too big\n");
2607 return -EINVAL;
2608 }
2609
2610 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2611 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2612 codec_dbg(codec, "invalid chip addr\n");
2613 return -ENXIO;
2614 }
2615
2616 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2617
2618 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2619 incr_field = 0;
2620
2621 if (!code) {
2622 addr_field <<= 1;
2623 if (yram)
2624 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2625
2626 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2627 }
2628
2629 dma_cfg = addr_field + incr_field;
2630 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2631 dma_cfg);
2632 if (status < 0) {
2633 codec_dbg(codec, "write DMACFG Reg fail\n");
2634 return status;
2635 }
2636 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2637
2638 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2639 (code ? 0 : 1));
2640
2641 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2642 adr_ofs);
2643 if (status < 0) {
2644 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2645 return status;
2646 }
2647 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2648
2649 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2650
2651 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2652
2653 xfr_cnt = base_cnt | cur_cnt;
2654
2655 status = chipio_write(codec,
2656 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2657 if (status < 0) {
2658 codec_dbg(codec, "write XFRCNT Reg fail\n");
2659 return status;
2660 }
2661 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2662
2663 codec_dbg(codec,
2664 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2665 "ADROFS=0x%x, XFRCNT=0x%x\n",
2666 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2667
2668 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2669
2670 return 0;
2671 }
2672
2673 /*
2674 * Start the DSP DMA
2675 */
dsp_dma_start(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2676 static int dsp_dma_start(struct hda_codec *codec,
2677 unsigned int dma_chan, bool ovly)
2678 {
2679 unsigned int reg = 0;
2680 int status = 0;
2681
2682 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2683
2684 if (ovly) {
2685 status = chipio_read(codec,
2686 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2687
2688 if (status < 0) {
2689 codec_dbg(codec, "read CHNLSTART reg fail\n");
2690 return status;
2691 }
2692 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2693
2694 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2695 DSPDMAC_CHNLSTART_DIS_MASK);
2696 }
2697
2698 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2699 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2700 if (status < 0) {
2701 codec_dbg(codec, "write CHNLSTART reg fail\n");
2702 return status;
2703 }
2704 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2705
2706 return status;
2707 }
2708
2709 /*
2710 * Stop the DSP DMA
2711 */
dsp_dma_stop(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2712 static int dsp_dma_stop(struct hda_codec *codec,
2713 unsigned int dma_chan, bool ovly)
2714 {
2715 unsigned int reg = 0;
2716 int status = 0;
2717
2718 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2719
2720 if (ovly) {
2721 status = chipio_read(codec,
2722 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2723
2724 if (status < 0) {
2725 codec_dbg(codec, "read CHNLSTART reg fail\n");
2726 return status;
2727 }
2728 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2729 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2730 DSPDMAC_CHNLSTART_DIS_MASK);
2731 }
2732
2733 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2734 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2735 if (status < 0) {
2736 codec_dbg(codec, "write CHNLSTART reg fail\n");
2737 return status;
2738 }
2739 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2740
2741 return status;
2742 }
2743
2744 /**
2745 * Allocate router ports
2746 *
2747 * @codec: the HDA codec
2748 * @num_chans: number of channels in the stream
2749 * @ports_per_channel: number of ports per channel
2750 * @start_device: start device
2751 * @port_map: pointer to the port list to hold the allocated ports
2752 *
2753 * Returns zero or a negative error code.
2754 */
dsp_allocate_router_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int ports_per_channel,unsigned int start_device,unsigned int * port_map)2755 static int dsp_allocate_router_ports(struct hda_codec *codec,
2756 unsigned int num_chans,
2757 unsigned int ports_per_channel,
2758 unsigned int start_device,
2759 unsigned int *port_map)
2760 {
2761 int status = 0;
2762 int res;
2763 u8 val;
2764
2765 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2766 if (status < 0)
2767 return status;
2768
2769 val = start_device << 6;
2770 val |= (ports_per_channel - 1) << 4;
2771 val |= num_chans - 1;
2772
2773 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2774 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2775 val);
2776
2777 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2778 VENDOR_CHIPIO_PORT_ALLOC_SET,
2779 MEM_CONNID_DSP);
2780
2781 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2782 if (status < 0)
2783 return status;
2784
2785 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2786 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2787
2788 *port_map = res;
2789
2790 return (res < 0) ? res : 0;
2791 }
2792
2793 /*
2794 * Free router ports
2795 */
dsp_free_router_ports(struct hda_codec * codec)2796 static int dsp_free_router_ports(struct hda_codec *codec)
2797 {
2798 int status = 0;
2799
2800 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2801 if (status < 0)
2802 return status;
2803
2804 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2805 VENDOR_CHIPIO_PORT_FREE_SET,
2806 MEM_CONNID_DSP);
2807
2808 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2809
2810 return status;
2811 }
2812
2813 /*
2814 * Allocate DSP ports for the download stream
2815 */
dsp_allocate_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int rate_multi,unsigned int * port_map)2816 static int dsp_allocate_ports(struct hda_codec *codec,
2817 unsigned int num_chans,
2818 unsigned int rate_multi, unsigned int *port_map)
2819 {
2820 int status;
2821
2822 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2823
2824 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2825 codec_dbg(codec, "bad rate multiple\n");
2826 return -EINVAL;
2827 }
2828
2829 status = dsp_allocate_router_ports(codec, num_chans,
2830 rate_multi, 0, port_map);
2831
2832 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2833
2834 return status;
2835 }
2836
dsp_allocate_ports_format(struct hda_codec * codec,const unsigned short fmt,unsigned int * port_map)2837 static int dsp_allocate_ports_format(struct hda_codec *codec,
2838 const unsigned short fmt,
2839 unsigned int *port_map)
2840 {
2841 int status;
2842 unsigned int num_chans;
2843
2844 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2845 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2846 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2847
2848 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2849 codec_dbg(codec, "bad rate multiple\n");
2850 return -EINVAL;
2851 }
2852
2853 num_chans = get_hdafmt_chs(fmt) + 1;
2854
2855 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2856
2857 return status;
2858 }
2859
2860 /*
2861 * free DSP ports
2862 */
dsp_free_ports(struct hda_codec * codec)2863 static int dsp_free_ports(struct hda_codec *codec)
2864 {
2865 int status;
2866
2867 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2868
2869 status = dsp_free_router_ports(codec);
2870 if (status < 0) {
2871 codec_dbg(codec, "free router ports fail\n");
2872 return status;
2873 }
2874 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2875
2876 return status;
2877 }
2878
2879 /*
2880 * HDA DMA engine stuffs for DSP code download
2881 */
2882 struct dma_engine {
2883 struct hda_codec *codec;
2884 unsigned short m_converter_format;
2885 struct snd_dma_buffer *dmab;
2886 unsigned int buf_size;
2887 };
2888
2889
2890 enum dma_state {
2891 DMA_STATE_STOP = 0,
2892 DMA_STATE_RUN = 1
2893 };
2894
dma_convert_to_hda_format(struct hda_codec * codec,unsigned int sample_rate,unsigned short channels,unsigned short * hda_format)2895 static int dma_convert_to_hda_format(struct hda_codec *codec,
2896 unsigned int sample_rate,
2897 unsigned short channels,
2898 unsigned short *hda_format)
2899 {
2900 unsigned int format_val;
2901
2902 format_val = snd_hdac_calc_stream_format(sample_rate,
2903 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2904
2905 if (hda_format)
2906 *hda_format = (unsigned short)format_val;
2907
2908 return 0;
2909 }
2910
2911 /*
2912 * Reset DMA for DSP download
2913 */
dma_reset(struct dma_engine * dma)2914 static int dma_reset(struct dma_engine *dma)
2915 {
2916 struct hda_codec *codec = dma->codec;
2917 struct ca0132_spec *spec = codec->spec;
2918 int status;
2919
2920 if (dma->dmab->area)
2921 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2922
2923 status = snd_hda_codec_load_dsp_prepare(codec,
2924 dma->m_converter_format,
2925 dma->buf_size,
2926 dma->dmab);
2927 if (status < 0)
2928 return status;
2929 spec->dsp_stream_id = status;
2930 return 0;
2931 }
2932
dma_set_state(struct dma_engine * dma,enum dma_state state)2933 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2934 {
2935 bool cmd;
2936
2937 switch (state) {
2938 case DMA_STATE_STOP:
2939 cmd = false;
2940 break;
2941 case DMA_STATE_RUN:
2942 cmd = true;
2943 break;
2944 default:
2945 return 0;
2946 }
2947
2948 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2949 return 0;
2950 }
2951
dma_get_buffer_size(struct dma_engine * dma)2952 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2953 {
2954 return dma->dmab->bytes;
2955 }
2956
dma_get_buffer_addr(struct dma_engine * dma)2957 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2958 {
2959 return dma->dmab->area;
2960 }
2961
dma_xfer(struct dma_engine * dma,const unsigned int * data,unsigned int count)2962 static int dma_xfer(struct dma_engine *dma,
2963 const unsigned int *data,
2964 unsigned int count)
2965 {
2966 memcpy(dma->dmab->area, data, count);
2967 return 0;
2968 }
2969
dma_get_converter_format(struct dma_engine * dma,unsigned short * format)2970 static void dma_get_converter_format(
2971 struct dma_engine *dma,
2972 unsigned short *format)
2973 {
2974 if (format)
2975 *format = dma->m_converter_format;
2976 }
2977
dma_get_stream_id(struct dma_engine * dma)2978 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2979 {
2980 struct ca0132_spec *spec = dma->codec->spec;
2981
2982 return spec->dsp_stream_id;
2983 }
2984
2985 struct dsp_image_seg {
2986 u32 magic;
2987 u32 chip_addr;
2988 u32 count;
2989 u32 data[];
2990 };
2991
2992 static const u32 g_magic_value = 0x4c46584d;
2993 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2994
is_valid(const struct dsp_image_seg * p)2995 static bool is_valid(const struct dsp_image_seg *p)
2996 {
2997 return p->magic == g_magic_value;
2998 }
2999
is_hci_prog_list_seg(const struct dsp_image_seg * p)3000 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3001 {
3002 return g_chip_addr_magic_value == p->chip_addr;
3003 }
3004
is_last(const struct dsp_image_seg * p)3005 static bool is_last(const struct dsp_image_seg *p)
3006 {
3007 return p->count == 0;
3008 }
3009
dsp_sizeof(const struct dsp_image_seg * p)3010 static size_t dsp_sizeof(const struct dsp_image_seg *p)
3011 {
3012 return struct_size(p, data, p->count);
3013 }
3014
get_next_seg_ptr(const struct dsp_image_seg * p)3015 static const struct dsp_image_seg *get_next_seg_ptr(
3016 const struct dsp_image_seg *p)
3017 {
3018 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3019 }
3020
3021 /*
3022 * CA0132 chip DSP transfer stuffs. For DSP download.
3023 */
3024 #define INVALID_DMA_CHANNEL (~0U)
3025
3026 /*
3027 * Program a list of address/data pairs via the ChipIO widget.
3028 * The segment data is in the format of successive pairs of words.
3029 * These are repeated as indicated by the segment's count field.
3030 */
dspxfr_hci_write(struct hda_codec * codec,const struct dsp_image_seg * fls)3031 static int dspxfr_hci_write(struct hda_codec *codec,
3032 const struct dsp_image_seg *fls)
3033 {
3034 int status;
3035 const u32 *data;
3036 unsigned int count;
3037
3038 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3039 codec_dbg(codec, "hci_write invalid params\n");
3040 return -EINVAL;
3041 }
3042
3043 count = fls->count;
3044 data = (u32 *)(fls->data);
3045 while (count >= 2) {
3046 status = chipio_write(codec, data[0], data[1]);
3047 if (status < 0) {
3048 codec_dbg(codec, "hci_write chipio failed\n");
3049 return status;
3050 }
3051 count -= 2;
3052 data += 2;
3053 }
3054 return 0;
3055 }
3056
3057 /**
3058 * Write a block of data into DSP code or data RAM using pre-allocated
3059 * DMA engine.
3060 *
3061 * @codec: the HDA codec
3062 * @fls: pointer to a fast load image
3063 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3064 * no relocation
3065 * @dma_engine: pointer to DMA engine to be used for DSP download
3066 * @dma_chan: The number of DMA channels used for DSP download
3067 * @port_map_mask: port mapping
3068 * @ovly: TRUE if overlay format is required
3069 *
3070 * Returns zero or a negative error code.
3071 */
dspxfr_one_seg(struct hda_codec * codec,const struct dsp_image_seg * fls,unsigned int reloc,struct dma_engine * dma_engine,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)3072 static int dspxfr_one_seg(struct hda_codec *codec,
3073 const struct dsp_image_seg *fls,
3074 unsigned int reloc,
3075 struct dma_engine *dma_engine,
3076 unsigned int dma_chan,
3077 unsigned int port_map_mask,
3078 bool ovly)
3079 {
3080 int status = 0;
3081 bool comm_dma_setup_done = false;
3082 const unsigned int *data;
3083 unsigned int chip_addx;
3084 unsigned int words_to_write;
3085 unsigned int buffer_size_words;
3086 unsigned char *buffer_addx;
3087 unsigned short hda_format;
3088 unsigned int sample_rate_div;
3089 unsigned int sample_rate_mul;
3090 unsigned int num_chans;
3091 unsigned int hda_frame_size_words;
3092 unsigned int remainder_words;
3093 const u32 *data_remainder;
3094 u32 chip_addx_remainder;
3095 unsigned int run_size_words;
3096 const struct dsp_image_seg *hci_write = NULL;
3097 unsigned long timeout;
3098 bool dma_active;
3099
3100 if (fls == NULL)
3101 return -EINVAL;
3102 if (is_hci_prog_list_seg(fls)) {
3103 hci_write = fls;
3104 fls = get_next_seg_ptr(fls);
3105 }
3106
3107 if (hci_write && (!fls || is_last(fls))) {
3108 codec_dbg(codec, "hci_write\n");
3109 return dspxfr_hci_write(codec, hci_write);
3110 }
3111
3112 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3113 codec_dbg(codec, "Invalid Params\n");
3114 return -EINVAL;
3115 }
3116
3117 data = fls->data;
3118 chip_addx = fls->chip_addr;
3119 words_to_write = fls->count;
3120
3121 if (!words_to_write)
3122 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3123 if (reloc)
3124 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3125
3126 if (!UC_RANGE(chip_addx, words_to_write) &&
3127 !X_RANGE_ALL(chip_addx, words_to_write) &&
3128 !Y_RANGE_ALL(chip_addx, words_to_write)) {
3129 codec_dbg(codec, "Invalid chip_addx Params\n");
3130 return -EINVAL;
3131 }
3132
3133 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3134 sizeof(u32);
3135
3136 buffer_addx = dma_get_buffer_addr(dma_engine);
3137
3138 if (buffer_addx == NULL) {
3139 codec_dbg(codec, "dma_engine buffer NULL\n");
3140 return -EINVAL;
3141 }
3142
3143 dma_get_converter_format(dma_engine, &hda_format);
3144 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3145 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3146 num_chans = get_hdafmt_chs(hda_format) + 1;
3147
3148 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3149 (num_chans * sample_rate_mul / sample_rate_div));
3150
3151 if (hda_frame_size_words == 0) {
3152 codec_dbg(codec, "frmsz zero\n");
3153 return -EINVAL;
3154 }
3155
3156 buffer_size_words = min(buffer_size_words,
3157 (unsigned int)(UC_RANGE(chip_addx, 1) ?
3158 65536 : 32768));
3159 buffer_size_words -= buffer_size_words % hda_frame_size_words;
3160 codec_dbg(codec,
3161 "chpadr=0x%08x frmsz=%u nchan=%u "
3162 "rate_mul=%u div=%u bufsz=%u\n",
3163 chip_addx, hda_frame_size_words, num_chans,
3164 sample_rate_mul, sample_rate_div, buffer_size_words);
3165
3166 if (buffer_size_words < hda_frame_size_words) {
3167 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3168 return -EINVAL;
3169 }
3170
3171 remainder_words = words_to_write % hda_frame_size_words;
3172 data_remainder = data;
3173 chip_addx_remainder = chip_addx;
3174
3175 data += remainder_words;
3176 chip_addx += remainder_words*sizeof(u32);
3177 words_to_write -= remainder_words;
3178
3179 while (words_to_write != 0) {
3180 run_size_words = min(buffer_size_words, words_to_write);
3181 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3182 words_to_write, run_size_words, remainder_words);
3183 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3184 if (!comm_dma_setup_done) {
3185 status = dsp_dma_stop(codec, dma_chan, ovly);
3186 if (status < 0)
3187 return status;
3188 status = dsp_dma_setup_common(codec, chip_addx,
3189 dma_chan, port_map_mask, ovly);
3190 if (status < 0)
3191 return status;
3192 comm_dma_setup_done = true;
3193 }
3194
3195 status = dsp_dma_setup(codec, chip_addx,
3196 run_size_words, dma_chan);
3197 if (status < 0)
3198 return status;
3199 status = dsp_dma_start(codec, dma_chan, ovly);
3200 if (status < 0)
3201 return status;
3202 if (!dsp_is_dma_active(codec, dma_chan)) {
3203 codec_dbg(codec, "dspxfr:DMA did not start\n");
3204 return -EIO;
3205 }
3206 status = dma_set_state(dma_engine, DMA_STATE_RUN);
3207 if (status < 0)
3208 return status;
3209 if (remainder_words != 0) {
3210 status = chipio_write_multiple(codec,
3211 chip_addx_remainder,
3212 data_remainder,
3213 remainder_words);
3214 if (status < 0)
3215 return status;
3216 remainder_words = 0;
3217 }
3218 if (hci_write) {
3219 status = dspxfr_hci_write(codec, hci_write);
3220 if (status < 0)
3221 return status;
3222 hci_write = NULL;
3223 }
3224
3225 timeout = jiffies + msecs_to_jiffies(2000);
3226 do {
3227 dma_active = dsp_is_dma_active(codec, dma_chan);
3228 if (!dma_active)
3229 break;
3230 msleep(20);
3231 } while (time_before(jiffies, timeout));
3232 if (dma_active)
3233 break;
3234
3235 codec_dbg(codec, "+++++ DMA complete\n");
3236 dma_set_state(dma_engine, DMA_STATE_STOP);
3237 status = dma_reset(dma_engine);
3238
3239 if (status < 0)
3240 return status;
3241
3242 data += run_size_words;
3243 chip_addx += run_size_words*sizeof(u32);
3244 words_to_write -= run_size_words;
3245 }
3246
3247 if (remainder_words != 0) {
3248 status = chipio_write_multiple(codec, chip_addx_remainder,
3249 data_remainder, remainder_words);
3250 }
3251
3252 return status;
3253 }
3254
3255 /**
3256 * Write the entire DSP image of a DSP code/data overlay to DSP memories
3257 *
3258 * @codec: the HDA codec
3259 * @fls_data: pointer to a fast load image
3260 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3261 * no relocation
3262 * @sample_rate: sampling rate of the stream used for DSP download
3263 * @channels: channels of the stream used for DSP download
3264 * @ovly: TRUE if overlay format is required
3265 *
3266 * Returns zero or a negative error code.
3267 */
dspxfr_image(struct hda_codec * codec,const struct dsp_image_seg * fls_data,unsigned int reloc,unsigned int sample_rate,unsigned short channels,bool ovly)3268 static int dspxfr_image(struct hda_codec *codec,
3269 const struct dsp_image_seg *fls_data,
3270 unsigned int reloc,
3271 unsigned int sample_rate,
3272 unsigned short channels,
3273 bool ovly)
3274 {
3275 struct ca0132_spec *spec = codec->spec;
3276 int status;
3277 unsigned short hda_format = 0;
3278 unsigned int response;
3279 unsigned char stream_id = 0;
3280 struct dma_engine *dma_engine;
3281 unsigned int dma_chan;
3282 unsigned int port_map_mask;
3283
3284 if (fls_data == NULL)
3285 return -EINVAL;
3286
3287 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3288 if (!dma_engine)
3289 return -ENOMEM;
3290
3291 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3292 if (!dma_engine->dmab) {
3293 kfree(dma_engine);
3294 return -ENOMEM;
3295 }
3296
3297 dma_engine->codec = codec;
3298 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3299 dma_engine->m_converter_format = hda_format;
3300 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3301 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3302
3303 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3304
3305 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3306 hda_format, &response);
3307
3308 if (status < 0) {
3309 codec_dbg(codec, "set converter format fail\n");
3310 goto exit;
3311 }
3312
3313 status = snd_hda_codec_load_dsp_prepare(codec,
3314 dma_engine->m_converter_format,
3315 dma_engine->buf_size,
3316 dma_engine->dmab);
3317 if (status < 0)
3318 goto exit;
3319 spec->dsp_stream_id = status;
3320
3321 if (ovly) {
3322 status = dspio_alloc_dma_chan(codec, &dma_chan);
3323 if (status < 0) {
3324 codec_dbg(codec, "alloc dmachan fail\n");
3325 dma_chan = INVALID_DMA_CHANNEL;
3326 goto exit;
3327 }
3328 }
3329
3330 port_map_mask = 0;
3331 status = dsp_allocate_ports_format(codec, hda_format,
3332 &port_map_mask);
3333 if (status < 0) {
3334 codec_dbg(codec, "alloc ports fail\n");
3335 goto exit;
3336 }
3337
3338 stream_id = dma_get_stream_id(dma_engine);
3339 status = codec_set_converter_stream_channel(codec,
3340 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3341 if (status < 0) {
3342 codec_dbg(codec, "set stream chan fail\n");
3343 goto exit;
3344 }
3345
3346 while ((fls_data != NULL) && !is_last(fls_data)) {
3347 if (!is_valid(fls_data)) {
3348 codec_dbg(codec, "FLS check fail\n");
3349 status = -EINVAL;
3350 goto exit;
3351 }
3352 status = dspxfr_one_seg(codec, fls_data, reloc,
3353 dma_engine, dma_chan,
3354 port_map_mask, ovly);
3355 if (status < 0)
3356 break;
3357
3358 if (is_hci_prog_list_seg(fls_data))
3359 fls_data = get_next_seg_ptr(fls_data);
3360
3361 if ((fls_data != NULL) && !is_last(fls_data))
3362 fls_data = get_next_seg_ptr(fls_data);
3363 }
3364
3365 if (port_map_mask != 0)
3366 status = dsp_free_ports(codec);
3367
3368 if (status < 0)
3369 goto exit;
3370
3371 status = codec_set_converter_stream_channel(codec,
3372 WIDGET_CHIP_CTRL, 0, 0, &response);
3373
3374 exit:
3375 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3376 dspio_free_dma_chan(codec, dma_chan);
3377
3378 if (dma_engine->dmab->area)
3379 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3380 kfree(dma_engine->dmab);
3381 kfree(dma_engine);
3382
3383 return status;
3384 }
3385
3386 /*
3387 * CA0132 DSP download stuffs.
3388 */
dspload_post_setup(struct hda_codec * codec)3389 static void dspload_post_setup(struct hda_codec *codec)
3390 {
3391 struct ca0132_spec *spec = codec->spec;
3392 codec_dbg(codec, "---- dspload_post_setup ------\n");
3393 if (!ca0132_use_alt_functions(spec)) {
3394 /*set DSP speaker to 2.0 configuration*/
3395 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3396 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3397
3398 /*update write pointer*/
3399 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3400 }
3401 }
3402
3403 /**
3404 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3405 *
3406 * @codec: the HDA codec
3407 * @fls: pointer to a fast load image
3408 * @ovly: TRUE if overlay format is required
3409 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3410 * no relocation
3411 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3412 * @router_chans: number of audio router channels to be allocated (0 means use
3413 * internal defaults; max is 32)
3414 *
3415 * Download DSP from a DSP Image Fast Load structure. This structure is a
3416 * linear, non-constant sized element array of structures, each of which
3417 * contain the count of the data to be loaded, the data itself, and the
3418 * corresponding starting chip address of the starting data location.
3419 * Returns zero or a negative error code.
3420 */
dspload_image(struct hda_codec * codec,const struct dsp_image_seg * fls,bool ovly,unsigned int reloc,bool autostart,int router_chans)3421 static int dspload_image(struct hda_codec *codec,
3422 const struct dsp_image_seg *fls,
3423 bool ovly,
3424 unsigned int reloc,
3425 bool autostart,
3426 int router_chans)
3427 {
3428 int status = 0;
3429 unsigned int sample_rate;
3430 unsigned short channels;
3431
3432 codec_dbg(codec, "---- dspload_image begin ------\n");
3433 if (router_chans == 0) {
3434 if (!ovly)
3435 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3436 else
3437 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3438 }
3439
3440 sample_rate = 48000;
3441 channels = (unsigned short)router_chans;
3442
3443 while (channels > 16) {
3444 sample_rate *= 2;
3445 channels /= 2;
3446 }
3447
3448 do {
3449 codec_dbg(codec, "Ready to program DMA\n");
3450 if (!ovly)
3451 status = dsp_reset(codec);
3452
3453 if (status < 0)
3454 break;
3455
3456 codec_dbg(codec, "dsp_reset() complete\n");
3457 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3458 ovly);
3459
3460 if (status < 0)
3461 break;
3462
3463 codec_dbg(codec, "dspxfr_image() complete\n");
3464 if (autostart && !ovly) {
3465 dspload_post_setup(codec);
3466 status = dsp_set_run_state(codec);
3467 }
3468
3469 codec_dbg(codec, "LOAD FINISHED\n");
3470 } while (0);
3471
3472 return status;
3473 }
3474
3475 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
dspload_is_loaded(struct hda_codec * codec)3476 static bool dspload_is_loaded(struct hda_codec *codec)
3477 {
3478 unsigned int data = 0;
3479 int status = 0;
3480
3481 status = chipio_read(codec, 0x40004, &data);
3482 if ((status < 0) || (data != 1))
3483 return false;
3484
3485 return true;
3486 }
3487 #else
3488 #define dspload_is_loaded(codec) false
3489 #endif
3490
dspload_wait_loaded(struct hda_codec * codec)3491 static bool dspload_wait_loaded(struct hda_codec *codec)
3492 {
3493 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3494
3495 do {
3496 if (dspload_is_loaded(codec)) {
3497 codec_info(codec, "ca0132 DSP downloaded and running\n");
3498 return true;
3499 }
3500 msleep(20);
3501 } while (time_before(jiffies, timeout));
3502
3503 codec_err(codec, "ca0132 failed to download DSP\n");
3504 return false;
3505 }
3506
3507 /*
3508 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3509 * based cards, and has a second mmio region, region2, that's used for special
3510 * commands.
3511 */
3512
3513 /*
3514 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3515 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3516 * The first eight bits are just the number of the pin. So far, I've only seen
3517 * this number go to 7.
3518 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3519 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3520 * then off to send that bit.
3521 */
ca0113_mmio_gpio_set(struct hda_codec * codec,unsigned int gpio_pin,bool enable)3522 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3523 bool enable)
3524 {
3525 struct ca0132_spec *spec = codec->spec;
3526 unsigned short gpio_data;
3527
3528 gpio_data = gpio_pin & 0xF;
3529 gpio_data |= ((enable << 8) & 0x100);
3530
3531 writew(gpio_data, spec->mem_base + 0x320);
3532 }
3533
3534 /*
3535 * Special pci region2 commands that are only used by the AE-5. They follow
3536 * a set format, and require reads at certain points to seemingly 'clear'
3537 * the response data. My first tests didn't do these reads, and would cause
3538 * the card to get locked up until the memory was read. These commands
3539 * seem to work with three distinct values that I've taken to calling group,
3540 * target-id, and value.
3541 */
ca0113_mmio_command_set(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3542 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3543 unsigned int target, unsigned int value)
3544 {
3545 struct ca0132_spec *spec = codec->spec;
3546 unsigned int write_val;
3547
3548 writel(0x0000007e, spec->mem_base + 0x210);
3549 readl(spec->mem_base + 0x210);
3550 writel(0x0000005a, spec->mem_base + 0x210);
3551 readl(spec->mem_base + 0x210);
3552 readl(spec->mem_base + 0x210);
3553
3554 writel(0x00800005, spec->mem_base + 0x20c);
3555 writel(group, spec->mem_base + 0x804);
3556
3557 writel(0x00800005, spec->mem_base + 0x20c);
3558 write_val = (target & 0xff);
3559 write_val |= (value << 8);
3560
3561
3562 writel(write_val, spec->mem_base + 0x204);
3563 /*
3564 * Need delay here or else it goes too fast and works inconsistently.
3565 */
3566 msleep(20);
3567
3568 readl(spec->mem_base + 0x860);
3569 readl(spec->mem_base + 0x854);
3570 readl(spec->mem_base + 0x840);
3571
3572 writel(0x00800004, spec->mem_base + 0x20c);
3573 writel(0x00000000, spec->mem_base + 0x210);
3574 readl(spec->mem_base + 0x210);
3575 readl(spec->mem_base + 0x210);
3576 }
3577
3578 /*
3579 * This second type of command is used for setting the sound filter type.
3580 */
ca0113_mmio_command_set_type2(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3581 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3582 unsigned int group, unsigned int target, unsigned int value)
3583 {
3584 struct ca0132_spec *spec = codec->spec;
3585 unsigned int write_val;
3586
3587 writel(0x0000007e, spec->mem_base + 0x210);
3588 readl(spec->mem_base + 0x210);
3589 writel(0x0000005a, spec->mem_base + 0x210);
3590 readl(spec->mem_base + 0x210);
3591 readl(spec->mem_base + 0x210);
3592
3593 writel(0x00800003, spec->mem_base + 0x20c);
3594 writel(group, spec->mem_base + 0x804);
3595
3596 writel(0x00800005, spec->mem_base + 0x20c);
3597 write_val = (target & 0xff);
3598 write_val |= (value << 8);
3599
3600
3601 writel(write_val, spec->mem_base + 0x204);
3602 msleep(20);
3603 readl(spec->mem_base + 0x860);
3604 readl(spec->mem_base + 0x854);
3605 readl(spec->mem_base + 0x840);
3606
3607 writel(0x00800004, spec->mem_base + 0x20c);
3608 writel(0x00000000, spec->mem_base + 0x210);
3609 readl(spec->mem_base + 0x210);
3610 readl(spec->mem_base + 0x210);
3611 }
3612
3613 /*
3614 * Setup GPIO for the other variants of Core3D.
3615 */
3616
3617 /*
3618 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3619 * the card shows as having no GPIO pins.
3620 */
ca0132_gpio_init(struct hda_codec * codec)3621 static void ca0132_gpio_init(struct hda_codec *codec)
3622 {
3623 struct ca0132_spec *spec = codec->spec;
3624
3625 switch (ca0132_quirk(spec)) {
3626 case QUIRK_SBZ:
3627 case QUIRK_AE5:
3628 case QUIRK_AE7:
3629 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3630 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3631 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3632 break;
3633 case QUIRK_R3DI:
3634 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3635 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3636 break;
3637 default:
3638 break;
3639 }
3640
3641 }
3642
3643 /* Sets the GPIO for audio output. */
ca0132_gpio_setup(struct hda_codec * codec)3644 static void ca0132_gpio_setup(struct hda_codec *codec)
3645 {
3646 struct ca0132_spec *spec = codec->spec;
3647
3648 switch (ca0132_quirk(spec)) {
3649 case QUIRK_SBZ:
3650 snd_hda_codec_write(codec, 0x01, 0,
3651 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3652 snd_hda_codec_write(codec, 0x01, 0,
3653 AC_VERB_SET_GPIO_MASK, 0x07);
3654 snd_hda_codec_write(codec, 0x01, 0,
3655 AC_VERB_SET_GPIO_DATA, 0x04);
3656 snd_hda_codec_write(codec, 0x01, 0,
3657 AC_VERB_SET_GPIO_DATA, 0x06);
3658 break;
3659 case QUIRK_R3DI:
3660 snd_hda_codec_write(codec, 0x01, 0,
3661 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3662 snd_hda_codec_write(codec, 0x01, 0,
3663 AC_VERB_SET_GPIO_MASK, 0x1F);
3664 snd_hda_codec_write(codec, 0x01, 0,
3665 AC_VERB_SET_GPIO_DATA, 0x0C);
3666 break;
3667 default:
3668 break;
3669 }
3670 }
3671
3672 /*
3673 * GPIO control functions for the Recon3D integrated.
3674 */
3675
3676 enum r3di_gpio_bit {
3677 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3678 R3DI_MIC_SELECT_BIT = 1,
3679 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3680 R3DI_OUT_SELECT_BIT = 2,
3681 /*
3682 * I dunno what this actually does, but it stays on until the dsp
3683 * is downloaded.
3684 */
3685 R3DI_GPIO_DSP_DOWNLOADING = 3,
3686 /*
3687 * Same as above, no clue what it does, but it comes on after the dsp
3688 * is downloaded.
3689 */
3690 R3DI_GPIO_DSP_DOWNLOADED = 4
3691 };
3692
3693 enum r3di_mic_select {
3694 /* Set GPIO bit 1 to 0 for rear mic */
3695 R3DI_REAR_MIC = 0,
3696 /* Set GPIO bit 1 to 1 for front microphone*/
3697 R3DI_FRONT_MIC = 1
3698 };
3699
3700 enum r3di_out_select {
3701 /* Set GPIO bit 2 to 0 for headphone */
3702 R3DI_HEADPHONE_OUT = 0,
3703 /* Set GPIO bit 2 to 1 for speaker */
3704 R3DI_LINE_OUT = 1
3705 };
3706 enum r3di_dsp_status {
3707 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3708 R3DI_DSP_DOWNLOADING = 0,
3709 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3710 R3DI_DSP_DOWNLOADED = 1
3711 };
3712
3713
r3di_gpio_mic_set(struct hda_codec * codec,enum r3di_mic_select cur_mic)3714 static void r3di_gpio_mic_set(struct hda_codec *codec,
3715 enum r3di_mic_select cur_mic)
3716 {
3717 unsigned int cur_gpio;
3718
3719 /* Get the current GPIO Data setup */
3720 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3721
3722 switch (cur_mic) {
3723 case R3DI_REAR_MIC:
3724 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3725 break;
3726 case R3DI_FRONT_MIC:
3727 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3728 break;
3729 }
3730 snd_hda_codec_write(codec, codec->core.afg, 0,
3731 AC_VERB_SET_GPIO_DATA, cur_gpio);
3732 }
3733
r3di_gpio_dsp_status_set(struct hda_codec * codec,enum r3di_dsp_status dsp_status)3734 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3735 enum r3di_dsp_status dsp_status)
3736 {
3737 unsigned int cur_gpio;
3738
3739 /* Get the current GPIO Data setup */
3740 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3741
3742 switch (dsp_status) {
3743 case R3DI_DSP_DOWNLOADING:
3744 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3745 snd_hda_codec_write(codec, codec->core.afg, 0,
3746 AC_VERB_SET_GPIO_DATA, cur_gpio);
3747 break;
3748 case R3DI_DSP_DOWNLOADED:
3749 /* Set DOWNLOADING bit to 0. */
3750 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3751
3752 snd_hda_codec_write(codec, codec->core.afg, 0,
3753 AC_VERB_SET_GPIO_DATA, cur_gpio);
3754
3755 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3756 break;
3757 }
3758
3759 snd_hda_codec_write(codec, codec->core.afg, 0,
3760 AC_VERB_SET_GPIO_DATA, cur_gpio);
3761 }
3762
3763 /*
3764 * PCM callbacks
3765 */
ca0132_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3766 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3767 struct hda_codec *codec,
3768 unsigned int stream_tag,
3769 unsigned int format,
3770 struct snd_pcm_substream *substream)
3771 {
3772 struct ca0132_spec *spec = codec->spec;
3773
3774 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3775
3776 return 0;
3777 }
3778
ca0132_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3779 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3780 struct hda_codec *codec,
3781 struct snd_pcm_substream *substream)
3782 {
3783 struct ca0132_spec *spec = codec->spec;
3784
3785 if (spec->dsp_state == DSP_DOWNLOADING)
3786 return 0;
3787
3788 /*If Playback effects are on, allow stream some time to flush
3789 *effects tail*/
3790 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3791 msleep(50);
3792
3793 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3794
3795 return 0;
3796 }
3797
ca0132_playback_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)3798 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3799 struct hda_codec *codec,
3800 struct snd_pcm_substream *substream)
3801 {
3802 struct ca0132_spec *spec = codec->spec;
3803 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3804 struct snd_pcm_runtime *runtime = substream->runtime;
3805
3806 if (spec->dsp_state != DSP_DOWNLOADED)
3807 return 0;
3808
3809 /* Add latency if playback enhancement and either effect is enabled. */
3810 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3811 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3812 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3813 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3814 }
3815
3816 /* Applying Speaker EQ adds latency as well. */
3817 if (spec->cur_out_type == SPEAKER_OUT)
3818 latency += DSP_SPEAKER_OUT_LATENCY;
3819
3820 return (latency * runtime->rate) / 1000;
3821 }
3822
3823 /*
3824 * Digital out
3825 */
ca0132_dig_playback_pcm_open(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3826 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3827 struct hda_codec *codec,
3828 struct snd_pcm_substream *substream)
3829 {
3830 struct ca0132_spec *spec = codec->spec;
3831 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3832 }
3833
ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3834 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3835 struct hda_codec *codec,
3836 unsigned int stream_tag,
3837 unsigned int format,
3838 struct snd_pcm_substream *substream)
3839 {
3840 struct ca0132_spec *spec = codec->spec;
3841 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3842 stream_tag, format, substream);
3843 }
3844
ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3845 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3846 struct hda_codec *codec,
3847 struct snd_pcm_substream *substream)
3848 {
3849 struct ca0132_spec *spec = codec->spec;
3850 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3851 }
3852
ca0132_dig_playback_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3853 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3854 struct hda_codec *codec,
3855 struct snd_pcm_substream *substream)
3856 {
3857 struct ca0132_spec *spec = codec->spec;
3858 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3859 }
3860
3861 /*
3862 * Analog capture
3863 */
ca0132_capture_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3864 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3865 struct hda_codec *codec,
3866 unsigned int stream_tag,
3867 unsigned int format,
3868 struct snd_pcm_substream *substream)
3869 {
3870 snd_hda_codec_setup_stream(codec, hinfo->nid,
3871 stream_tag, 0, format);
3872
3873 return 0;
3874 }
3875
ca0132_capture_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3876 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3877 struct hda_codec *codec,
3878 struct snd_pcm_substream *substream)
3879 {
3880 struct ca0132_spec *spec = codec->spec;
3881
3882 if (spec->dsp_state == DSP_DOWNLOADING)
3883 return 0;
3884
3885 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3886 return 0;
3887 }
3888
ca0132_capture_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)3889 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3890 struct hda_codec *codec,
3891 struct snd_pcm_substream *substream)
3892 {
3893 struct ca0132_spec *spec = codec->spec;
3894 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3895 struct snd_pcm_runtime *runtime = substream->runtime;
3896
3897 if (spec->dsp_state != DSP_DOWNLOADED)
3898 return 0;
3899
3900 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3901 latency += DSP_CRYSTAL_VOICE_LATENCY;
3902
3903 return (latency * runtime->rate) / 1000;
3904 }
3905
3906 /*
3907 * Controls stuffs.
3908 */
3909
3910 /*
3911 * Mixer controls helpers.
3912 */
3913 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3914 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3915 .name = xname, \
3916 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3917 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3918 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3919 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3920 .info = ca0132_volume_info, \
3921 .get = ca0132_volume_get, \
3922 .put = ca0132_volume_put, \
3923 .tlv = { .c = ca0132_volume_tlv }, \
3924 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3925
3926 /*
3927 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3928 * volume put, which is used for setting the DSP volume. This was done because
3929 * the ca0132 functions were taking too much time and causing lag.
3930 */
3931 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3932 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3933 .name = xname, \
3934 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3935 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3936 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3937 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3938 .info = snd_hda_mixer_amp_volume_info, \
3939 .get = snd_hda_mixer_amp_volume_get, \
3940 .put = ca0132_alt_volume_put, \
3941 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3942 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3943
3944 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3945 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3946 .name = xname, \
3947 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3948 .info = snd_hda_mixer_amp_switch_info, \
3949 .get = ca0132_switch_get, \
3950 .put = ca0132_switch_put, \
3951 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3952
3953 /* stereo */
3954 #define CA0132_CODEC_VOL(xname, nid, dir) \
3955 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3956 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3957 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3958 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3959 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3960
3961 /* lookup tables */
3962 /*
3963 * Lookup table with decibel values for the DSP. When volume is changed in
3964 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3965 * these values have decimal points, probably because the Windows driver
3966 * actually uses floating point. We can't here, so I made a lookup table of
3967 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3968 * DAC's, and 9 is the maximum.
3969 */
3970 static const unsigned int float_vol_db_lookup[] = {
3971 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3972 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3973 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3974 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3975 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3976 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3977 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3978 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3979 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3980 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3981 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3982 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3983 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3984 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3985 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3986 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3987 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3988 };
3989
3990 /*
3991 * This table counts from float 0 to 1 in increments of .01, which is
3992 * useful for a few different sliders.
3993 */
3994 static const unsigned int float_zero_to_one_lookup[] = {
3995 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3996 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3997 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3998 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3999 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4000 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4001 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4002 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4003 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4004 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4005 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4006 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4007 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4008 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4009 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4010 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4011 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4012 };
4013
4014 /*
4015 * This table counts from float 10 to 1000, which is the range of the x-bass
4016 * crossover slider in Windows.
4017 */
4018 static const unsigned int float_xbass_xover_lookup[] = {
4019 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4020 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4021 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4022 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4023 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4024 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4025 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4026 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4027 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4028 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4029 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4030 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4031 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4032 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4033 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4034 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4035 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4036 };
4037
4038 /* The following are for tuning of products */
4039 #ifdef ENABLE_TUNING_CONTROLS
4040
4041 static const unsigned int voice_focus_vals_lookup[] = {
4042 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4043 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4044 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4045 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4046 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4047 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4048 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4049 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4050 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4051 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4052 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4053 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4054 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4055 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4056 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4057 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4058 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4059 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4060 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4061 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4062 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4063 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4064 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4065 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4066 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4067 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4068 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4069 };
4070
4071 static const unsigned int mic_svm_vals_lookup[] = {
4072 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4073 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4074 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4075 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4076 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4077 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4078 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4079 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4080 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4081 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4082 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4083 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4084 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4085 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4086 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4087 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4088 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4089 };
4090
4091 static const unsigned int equalizer_vals_lookup[] = {
4092 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4093 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4094 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4095 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4096 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4097 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4098 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4099 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4100 0x41C00000
4101 };
4102
tuning_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)4103 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4104 const unsigned int *lookup, int idx)
4105 {
4106 int i = 0;
4107
4108 for (i = 0; i < TUNING_CTLS_COUNT; i++)
4109 if (nid == ca0132_tuning_ctls[i].nid)
4110 break;
4111
4112 snd_hda_power_up(codec);
4113 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4114 ca0132_tuning_ctls[i].req,
4115 &(lookup[idx]), sizeof(unsigned int));
4116 snd_hda_power_down(codec);
4117
4118 return 1;
4119 }
4120
tuning_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4121 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4122 struct snd_ctl_elem_value *ucontrol)
4123 {
4124 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4125 struct ca0132_spec *spec = codec->spec;
4126 hda_nid_t nid = get_amp_nid(kcontrol);
4127 long *valp = ucontrol->value.integer.value;
4128 int idx = nid - TUNING_CTL_START_NID;
4129
4130 *valp = spec->cur_ctl_vals[idx];
4131 return 0;
4132 }
4133
voice_focus_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4134 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4135 struct snd_ctl_elem_info *uinfo)
4136 {
4137 int chs = get_amp_channels(kcontrol);
4138 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4139 uinfo->count = chs == 3 ? 2 : 1;
4140 uinfo->value.integer.min = 20;
4141 uinfo->value.integer.max = 180;
4142 uinfo->value.integer.step = 1;
4143
4144 return 0;
4145 }
4146
voice_focus_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4147 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4148 struct snd_ctl_elem_value *ucontrol)
4149 {
4150 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4151 struct ca0132_spec *spec = codec->spec;
4152 hda_nid_t nid = get_amp_nid(kcontrol);
4153 long *valp = ucontrol->value.integer.value;
4154 int idx;
4155
4156 idx = nid - TUNING_CTL_START_NID;
4157 /* any change? */
4158 if (spec->cur_ctl_vals[idx] == *valp)
4159 return 0;
4160
4161 spec->cur_ctl_vals[idx] = *valp;
4162
4163 idx = *valp - 20;
4164 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4165
4166 return 1;
4167 }
4168
mic_svm_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4169 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4170 struct snd_ctl_elem_info *uinfo)
4171 {
4172 int chs = get_amp_channels(kcontrol);
4173 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4174 uinfo->count = chs == 3 ? 2 : 1;
4175 uinfo->value.integer.min = 0;
4176 uinfo->value.integer.max = 100;
4177 uinfo->value.integer.step = 1;
4178
4179 return 0;
4180 }
4181
mic_svm_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4182 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4183 struct snd_ctl_elem_value *ucontrol)
4184 {
4185 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4186 struct ca0132_spec *spec = codec->spec;
4187 hda_nid_t nid = get_amp_nid(kcontrol);
4188 long *valp = ucontrol->value.integer.value;
4189 int idx;
4190
4191 idx = nid - TUNING_CTL_START_NID;
4192 /* any change? */
4193 if (spec->cur_ctl_vals[idx] == *valp)
4194 return 0;
4195
4196 spec->cur_ctl_vals[idx] = *valp;
4197
4198 idx = *valp;
4199 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4200
4201 return 0;
4202 }
4203
equalizer_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4204 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4205 struct snd_ctl_elem_info *uinfo)
4206 {
4207 int chs = get_amp_channels(kcontrol);
4208 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4209 uinfo->count = chs == 3 ? 2 : 1;
4210 uinfo->value.integer.min = 0;
4211 uinfo->value.integer.max = 48;
4212 uinfo->value.integer.step = 1;
4213
4214 return 0;
4215 }
4216
equalizer_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4217 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4218 struct snd_ctl_elem_value *ucontrol)
4219 {
4220 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4221 struct ca0132_spec *spec = codec->spec;
4222 hda_nid_t nid = get_amp_nid(kcontrol);
4223 long *valp = ucontrol->value.integer.value;
4224 int idx;
4225
4226 idx = nid - TUNING_CTL_START_NID;
4227 /* any change? */
4228 if (spec->cur_ctl_vals[idx] == *valp)
4229 return 0;
4230
4231 spec->cur_ctl_vals[idx] = *valp;
4232
4233 idx = *valp;
4234 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4235
4236 return 1;
4237 }
4238
4239 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4240 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4241
add_tuning_control(struct hda_codec * codec,hda_nid_t pnid,hda_nid_t nid,const char * name,int dir)4242 static int add_tuning_control(struct hda_codec *codec,
4243 hda_nid_t pnid, hda_nid_t nid,
4244 const char *name, int dir)
4245 {
4246 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4247 int type = dir ? HDA_INPUT : HDA_OUTPUT;
4248 struct snd_kcontrol_new knew =
4249 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4250
4251 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4252 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4253 knew.tlv.c = 0;
4254 knew.tlv.p = 0;
4255 switch (pnid) {
4256 case VOICE_FOCUS:
4257 knew.info = voice_focus_ctl_info;
4258 knew.get = tuning_ctl_get;
4259 knew.put = voice_focus_ctl_put;
4260 knew.tlv.p = voice_focus_db_scale;
4261 break;
4262 case MIC_SVM:
4263 knew.info = mic_svm_ctl_info;
4264 knew.get = tuning_ctl_get;
4265 knew.put = mic_svm_ctl_put;
4266 break;
4267 case EQUALIZER:
4268 knew.info = equalizer_ctl_info;
4269 knew.get = tuning_ctl_get;
4270 knew.put = equalizer_ctl_put;
4271 knew.tlv.p = eq_db_scale;
4272 break;
4273 default:
4274 return 0;
4275 }
4276 knew.private_value =
4277 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4278 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4279 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4280 }
4281
add_tuning_ctls(struct hda_codec * codec)4282 static int add_tuning_ctls(struct hda_codec *codec)
4283 {
4284 int i;
4285 int err;
4286
4287 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4288 err = add_tuning_control(codec,
4289 ca0132_tuning_ctls[i].parent_nid,
4290 ca0132_tuning_ctls[i].nid,
4291 ca0132_tuning_ctls[i].name,
4292 ca0132_tuning_ctls[i].direct);
4293 if (err < 0)
4294 return err;
4295 }
4296
4297 return 0;
4298 }
4299
ca0132_init_tuning_defaults(struct hda_codec * codec)4300 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4301 {
4302 struct ca0132_spec *spec = codec->spec;
4303 int i;
4304
4305 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4306 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4307 /* SVM level defaults to 0.74. */
4308 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4309
4310 /* EQ defaults to 0dB. */
4311 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4312 spec->cur_ctl_vals[i] = 24;
4313 }
4314 #endif /*ENABLE_TUNING_CONTROLS*/
4315
4316 /*
4317 * Select the active output.
4318 * If autodetect is enabled, output will be selected based on jack detection.
4319 * If jack inserted, headphone will be selected, else built-in speakers
4320 * If autodetect is disabled, output will be selected based on selection.
4321 */
ca0132_select_out(struct hda_codec * codec)4322 static int ca0132_select_out(struct hda_codec *codec)
4323 {
4324 struct ca0132_spec *spec = codec->spec;
4325 unsigned int pin_ctl;
4326 int jack_present;
4327 int auto_jack;
4328 unsigned int tmp;
4329 int err;
4330
4331 codec_dbg(codec, "ca0132_select_out\n");
4332
4333 snd_hda_power_up_pm(codec);
4334
4335 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4336
4337 if (auto_jack)
4338 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4339 else
4340 jack_present =
4341 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4342
4343 if (jack_present)
4344 spec->cur_out_type = HEADPHONE_OUT;
4345 else
4346 spec->cur_out_type = SPEAKER_OUT;
4347
4348 if (spec->cur_out_type == SPEAKER_OUT) {
4349 codec_dbg(codec, "ca0132_select_out speaker\n");
4350 /*speaker out config*/
4351 tmp = FLOAT_ONE;
4352 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4353 if (err < 0)
4354 goto exit;
4355 /*enable speaker EQ*/
4356 tmp = FLOAT_ONE;
4357 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4358 if (err < 0)
4359 goto exit;
4360
4361 /* Setup EAPD */
4362 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4363 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4364 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4365 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4366 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4367 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4368 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4369 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4370
4371 /* disable headphone node */
4372 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4373 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4374 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4375 pin_ctl & ~PIN_HP);
4376 /* enable speaker node */
4377 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4378 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4379 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4380 pin_ctl | PIN_OUT);
4381 } else {
4382 codec_dbg(codec, "ca0132_select_out hp\n");
4383 /*headphone out config*/
4384 tmp = FLOAT_ZERO;
4385 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4386 if (err < 0)
4387 goto exit;
4388 /*disable speaker EQ*/
4389 tmp = FLOAT_ZERO;
4390 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4391 if (err < 0)
4392 goto exit;
4393
4394 /* Setup EAPD */
4395 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4396 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4397 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4398 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4399 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4400 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4401 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4402 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4403
4404 /* disable speaker*/
4405 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4406 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4407 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4408 pin_ctl & ~PIN_HP);
4409 /* enable headphone*/
4410 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4411 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4412 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4413 pin_ctl | PIN_HP);
4414 }
4415
4416 exit:
4417 snd_hda_power_down_pm(codec);
4418
4419 return err < 0 ? err : 0;
4420 }
4421
4422 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4423 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4424 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4425
ae5_mmio_select_out(struct hda_codec * codec)4426 static void ae5_mmio_select_out(struct hda_codec *codec)
4427 {
4428 struct ca0132_spec *spec = codec->spec;
4429 const struct ae_ca0113_output_set *out_cmds;
4430 unsigned int i;
4431
4432 if (ca0132_quirk(spec) == QUIRK_AE5)
4433 out_cmds = &ae5_ca0113_output_presets;
4434 else
4435 out_cmds = &ae7_ca0113_output_presets;
4436
4437 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4438 ca0113_mmio_command_set(codec, out_cmds->group[i],
4439 out_cmds->target[i],
4440 out_cmds->vals[spec->cur_out_type][i]);
4441 }
4442
ca0132_alt_set_full_range_speaker(struct hda_codec * codec)4443 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4444 {
4445 struct ca0132_spec *spec = codec->spec;
4446 int quirk = ca0132_quirk(spec);
4447 unsigned int tmp;
4448 int err;
4449
4450 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4451 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4452 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4453 return 0;
4454
4455 /* Set front L/R full range. Zero for full-range, one for redirection. */
4456 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4457 err = dspio_set_uint_param(codec, 0x96,
4458 SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4459 if (err < 0)
4460 return err;
4461
4462 /* When setting full-range rear, both rear and center/lfe are set. */
4463 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4464 err = dspio_set_uint_param(codec, 0x96,
4465 SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4466 if (err < 0)
4467 return err;
4468
4469 err = dspio_set_uint_param(codec, 0x96,
4470 SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4471 if (err < 0)
4472 return err;
4473
4474 /*
4475 * Only the AE series cards set this value when setting full-range,
4476 * and it's always 1.0f.
4477 */
4478 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4479 err = dspio_set_uint_param(codec, 0x96,
4480 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4481 if (err < 0)
4482 return err;
4483 }
4484
4485 return 0;
4486 }
4487
ca0132_alt_surround_set_bass_redirection(struct hda_codec * codec,bool val)4488 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4489 bool val)
4490 {
4491 struct ca0132_spec *spec = codec->spec;
4492 unsigned int tmp;
4493 int err;
4494
4495 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4496 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4497 tmp = FLOAT_ONE;
4498 else
4499 tmp = FLOAT_ZERO;
4500
4501 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4502 if (err < 0)
4503 return err;
4504
4505 /* If it is enabled, make sure to set the crossover frequency. */
4506 if (tmp) {
4507 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4508 err = dspio_set_uint_param(codec, 0x96,
4509 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4510 if (err < 0)
4511 return err;
4512 }
4513
4514 return 0;
4515 }
4516
4517 /*
4518 * These are the commands needed to setup output on each of the different card
4519 * types.
4520 */
ca0132_alt_select_out_get_quirk_data(struct hda_codec * codec,const struct ca0132_alt_out_set_quirk_data ** quirk_data)4521 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4522 const struct ca0132_alt_out_set_quirk_data **quirk_data)
4523 {
4524 struct ca0132_spec *spec = codec->spec;
4525 int quirk = ca0132_quirk(spec);
4526 unsigned int i;
4527
4528 *quirk_data = NULL;
4529 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4530 if (quirk_out_set_data[i].quirk_id == quirk) {
4531 *quirk_data = &quirk_out_set_data[i];
4532 return;
4533 }
4534 }
4535 }
4536
ca0132_alt_select_out_quirk_set(struct hda_codec * codec)4537 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4538 {
4539 const struct ca0132_alt_out_set_quirk_data *quirk_data;
4540 const struct ca0132_alt_out_set_info *out_info;
4541 struct ca0132_spec *spec = codec->spec;
4542 unsigned int i, gpio_data;
4543 int err;
4544
4545 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4546 if (!quirk_data)
4547 return 0;
4548
4549 out_info = &quirk_data->out_set_info[spec->cur_out_type];
4550 if (quirk_data->is_ae_series)
4551 ae5_mmio_select_out(codec);
4552
4553 if (out_info->has_hda_gpio) {
4554 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4555 AC_VERB_GET_GPIO_DATA, 0);
4556
4557 if (out_info->hda_gpio_set)
4558 gpio_data |= (1 << out_info->hda_gpio_pin);
4559 else
4560 gpio_data &= ~(1 << out_info->hda_gpio_pin);
4561
4562 snd_hda_codec_write(codec, codec->core.afg, 0,
4563 AC_VERB_SET_GPIO_DATA, gpio_data);
4564 }
4565
4566 if (out_info->mmio_gpio_count) {
4567 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4568 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4569 out_info->mmio_gpio_set[i]);
4570 }
4571 }
4572
4573 if (out_info->scp_cmds_count) {
4574 for (i = 0; i < out_info->scp_cmds_count; i++) {
4575 err = dspio_set_uint_param(codec,
4576 out_info->scp_cmd_mid[i],
4577 out_info->scp_cmd_req[i],
4578 out_info->scp_cmd_val[i]);
4579 if (err < 0)
4580 return err;
4581 }
4582 }
4583
4584 chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4585
4586 if (out_info->has_chipio_write) {
4587 chipio_write(codec, out_info->chipio_write_addr,
4588 out_info->chipio_write_data);
4589 }
4590
4591 if (quirk_data->has_headphone_gain) {
4592 if (spec->cur_out_type != HEADPHONE_OUT) {
4593 if (quirk_data->is_ae_series)
4594 ae5_headphone_gain_set(codec, 2);
4595 else
4596 zxr_headphone_gain_set(codec, 0);
4597 } else {
4598 if (quirk_data->is_ae_series)
4599 ae5_headphone_gain_set(codec,
4600 spec->ae5_headphone_gain_val);
4601 else
4602 zxr_headphone_gain_set(codec,
4603 spec->zxr_gain_set);
4604 }
4605 }
4606
4607 return 0;
4608 }
4609
ca0132_set_out_node_pincfg(struct hda_codec * codec,hda_nid_t nid,bool out_enable,bool hp_enable)4610 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4611 bool out_enable, bool hp_enable)
4612 {
4613 unsigned int pin_ctl;
4614
4615 pin_ctl = snd_hda_codec_read(codec, nid, 0,
4616 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4617
4618 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
4619 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT;
4620 snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4621 }
4622
4623 /*
4624 * This function behaves similarly to the ca0132_select_out funciton above,
4625 * except with a few differences. It adds the ability to select the current
4626 * output with an enumerated control "output source" if the auto detect
4627 * mute switch is set to off. If the auto detect mute switch is enabled, it
4628 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4629 * It also adds the ability to auto-detect the front headphone port.
4630 */
ca0132_alt_select_out(struct hda_codec * codec)4631 static int ca0132_alt_select_out(struct hda_codec *codec)
4632 {
4633 struct ca0132_spec *spec = codec->spec;
4634 unsigned int tmp, outfx_set;
4635 int jack_present;
4636 int auto_jack;
4637 int err;
4638 /* Default Headphone is rear headphone */
4639 hda_nid_t headphone_nid = spec->out_pins[1];
4640
4641 codec_dbg(codec, "%s\n", __func__);
4642
4643 snd_hda_power_up_pm(codec);
4644
4645 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4646
4647 /*
4648 * If headphone rear or front is plugged in, set to headphone.
4649 * If neither is plugged in, set to rear line out. Only if
4650 * hp/speaker auto detect is enabled.
4651 */
4652 if (auto_jack) {
4653 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4654 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4655
4656 if (jack_present)
4657 spec->cur_out_type = HEADPHONE_OUT;
4658 else
4659 spec->cur_out_type = SPEAKER_OUT;
4660 } else
4661 spec->cur_out_type = spec->out_enum_val;
4662
4663 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4664
4665 /* Begin DSP output switch, mute DSP volume. */
4666 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4667 if (err < 0)
4668 goto exit;
4669
4670 if (ca0132_alt_select_out_quirk_set(codec) < 0)
4671 goto exit;
4672
4673 switch (spec->cur_out_type) {
4674 case SPEAKER_OUT:
4675 codec_dbg(codec, "%s speaker\n", __func__);
4676
4677 /* Enable EAPD */
4678 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4679 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4680
4681 /* Disable headphone node. */
4682 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4683 /* Set front L-R to output. */
4684 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4685 /* Set Center/LFE to output. */
4686 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4687 /* Set rear surround to output. */
4688 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4689
4690 /*
4691 * Without PlayEnhancement being enabled, if we've got a 2.0
4692 * setup, set it to floating point eight to disable any DSP
4693 * processing effects.
4694 */
4695 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4696 tmp = FLOAT_EIGHT;
4697 else
4698 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4699
4700 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4701 if (err < 0)
4702 goto exit;
4703
4704 break;
4705 case HEADPHONE_OUT:
4706 codec_dbg(codec, "%s hp\n", __func__);
4707 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4708 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4709
4710 /* Disable all speaker nodes. */
4711 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4712 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4713 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4714
4715 /* enable headphone, either front or rear */
4716 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4717 headphone_nid = spec->out_pins[2];
4718 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4719 headphone_nid = spec->out_pins[1];
4720
4721 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4722
4723 if (outfx_set)
4724 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4725 else
4726 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4727
4728 if (err < 0)
4729 goto exit;
4730 break;
4731 }
4732 /*
4733 * If output effects are enabled, set the X-Bass effect value again to
4734 * make sure that it's properly enabled/disabled for speaker
4735 * configurations with an LFE channel.
4736 */
4737 if (outfx_set)
4738 ca0132_effects_set(codec, X_BASS,
4739 spec->effects_switch[X_BASS - EFFECT_START_NID]);
4740
4741 /* Set speaker EQ bypass attenuation to 0. */
4742 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4743 if (err < 0)
4744 goto exit;
4745
4746 /*
4747 * Although unused on all cards but the AE series, this is always set
4748 * to zero when setting the output.
4749 */
4750 err = dspio_set_uint_param(codec, 0x96,
4751 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
4752 if (err < 0)
4753 goto exit;
4754
4755 if (spec->cur_out_type == SPEAKER_OUT)
4756 err = ca0132_alt_surround_set_bass_redirection(codec,
4757 spec->bass_redirection_val);
4758 else
4759 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4760
4761 /* Unmute DSP now that we're done with output selection. */
4762 err = dspio_set_uint_param(codec, 0x96,
4763 SPEAKER_TUNING_MUTE, FLOAT_ZERO);
4764 if (err < 0)
4765 goto exit;
4766
4767 if (spec->cur_out_type == SPEAKER_OUT) {
4768 err = ca0132_alt_set_full_range_speaker(codec);
4769 if (err < 0)
4770 goto exit;
4771 }
4772
4773 exit:
4774 snd_hda_power_down_pm(codec);
4775
4776 return err < 0 ? err : 0;
4777 }
4778
ca0132_unsol_hp_delayed(struct work_struct * work)4779 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4780 {
4781 struct ca0132_spec *spec = container_of(
4782 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4783 struct hda_jack_tbl *jack;
4784
4785 if (ca0132_use_alt_functions(spec))
4786 ca0132_alt_select_out(spec->codec);
4787 else
4788 ca0132_select_out(spec->codec);
4789
4790 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4791 if (jack) {
4792 jack->block_report = 0;
4793 snd_hda_jack_report_sync(spec->codec);
4794 }
4795 }
4796
4797 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4798 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4799 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4800 static int stop_mic1(struct hda_codec *codec);
4801 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4802 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4803
4804 /*
4805 * Select the active VIP source
4806 */
ca0132_set_vipsource(struct hda_codec * codec,int val)4807 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4808 {
4809 struct ca0132_spec *spec = codec->spec;
4810 unsigned int tmp;
4811
4812 if (spec->dsp_state != DSP_DOWNLOADED)
4813 return 0;
4814
4815 /* if CrystalVoice if off, vipsource should be 0 */
4816 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4817 (val == 0)) {
4818 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4819 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4820 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4821 if (spec->cur_mic_type == DIGITAL_MIC)
4822 tmp = FLOAT_TWO;
4823 else
4824 tmp = FLOAT_ONE;
4825 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4826 tmp = FLOAT_ZERO;
4827 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4828 } else {
4829 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4830 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4831 if (spec->cur_mic_type == DIGITAL_MIC)
4832 tmp = FLOAT_TWO;
4833 else
4834 tmp = FLOAT_ONE;
4835 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4836 tmp = FLOAT_ONE;
4837 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4838 msleep(20);
4839 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4840 }
4841
4842 return 1;
4843 }
4844
ca0132_alt_set_vipsource(struct hda_codec * codec,int val)4845 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4846 {
4847 struct ca0132_spec *spec = codec->spec;
4848 unsigned int tmp;
4849
4850 if (spec->dsp_state != DSP_DOWNLOADED)
4851 return 0;
4852
4853 codec_dbg(codec, "%s\n", __func__);
4854
4855 chipio_set_stream_control(codec, 0x03, 0);
4856 chipio_set_stream_control(codec, 0x04, 0);
4857
4858 /* if CrystalVoice is off, vipsource should be 0 */
4859 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4860 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4861 codec_dbg(codec, "%s: off.", __func__);
4862 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4863
4864 tmp = FLOAT_ZERO;
4865 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4866
4867 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4868 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4869 if (ca0132_quirk(spec) == QUIRK_R3DI)
4870 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4871
4872
4873 if (spec->in_enum_val == REAR_LINE_IN)
4874 tmp = FLOAT_ZERO;
4875 else {
4876 if (ca0132_quirk(spec) == QUIRK_SBZ)
4877 tmp = FLOAT_THREE;
4878 else
4879 tmp = FLOAT_ONE;
4880 }
4881
4882 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4883
4884 } else {
4885 codec_dbg(codec, "%s: on.", __func__);
4886 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4887 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4888 if (ca0132_quirk(spec) == QUIRK_R3DI)
4889 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4890
4891 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4892 tmp = FLOAT_TWO;
4893 else
4894 tmp = FLOAT_ONE;
4895 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4896
4897 tmp = FLOAT_ONE;
4898 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4899
4900 msleep(20);
4901 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4902 }
4903
4904 chipio_set_stream_control(codec, 0x03, 1);
4905 chipio_set_stream_control(codec, 0x04, 1);
4906
4907 return 1;
4908 }
4909
4910 /*
4911 * Select the active microphone.
4912 * If autodetect is enabled, mic will be selected based on jack detection.
4913 * If jack inserted, ext.mic will be selected, else built-in mic
4914 * If autodetect is disabled, mic will be selected based on selection.
4915 */
ca0132_select_mic(struct hda_codec * codec)4916 static int ca0132_select_mic(struct hda_codec *codec)
4917 {
4918 struct ca0132_spec *spec = codec->spec;
4919 int jack_present;
4920 int auto_jack;
4921
4922 codec_dbg(codec, "ca0132_select_mic\n");
4923
4924 snd_hda_power_up_pm(codec);
4925
4926 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4927
4928 if (auto_jack)
4929 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4930 else
4931 jack_present =
4932 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4933
4934 if (jack_present)
4935 spec->cur_mic_type = LINE_MIC_IN;
4936 else
4937 spec->cur_mic_type = DIGITAL_MIC;
4938
4939 if (spec->cur_mic_type == DIGITAL_MIC) {
4940 /* enable digital Mic */
4941 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4942 ca0132_set_dmic(codec, 1);
4943 ca0132_mic_boost_set(codec, 0);
4944 /* set voice focus */
4945 ca0132_effects_set(codec, VOICE_FOCUS,
4946 spec->effects_switch
4947 [VOICE_FOCUS - EFFECT_START_NID]);
4948 } else {
4949 /* disable digital Mic */
4950 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4951 ca0132_set_dmic(codec, 0);
4952 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4953 /* disable voice focus */
4954 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4955 }
4956
4957 snd_hda_power_down_pm(codec);
4958
4959 return 0;
4960 }
4961
4962 /*
4963 * Select the active input.
4964 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4965 * The front mic has no jack-detection, so the only way to switch to it
4966 * is to do it manually in alsamixer.
4967 */
ca0132_alt_select_in(struct hda_codec * codec)4968 static int ca0132_alt_select_in(struct hda_codec *codec)
4969 {
4970 struct ca0132_spec *spec = codec->spec;
4971 unsigned int tmp;
4972
4973 codec_dbg(codec, "%s\n", __func__);
4974
4975 snd_hda_power_up_pm(codec);
4976
4977 chipio_set_stream_control(codec, 0x03, 0);
4978 chipio_set_stream_control(codec, 0x04, 0);
4979
4980 spec->cur_mic_type = spec->in_enum_val;
4981
4982 switch (spec->cur_mic_type) {
4983 case REAR_MIC:
4984 switch (ca0132_quirk(spec)) {
4985 case QUIRK_SBZ:
4986 case QUIRK_R3D:
4987 ca0113_mmio_gpio_set(codec, 0, false);
4988 tmp = FLOAT_THREE;
4989 break;
4990 case QUIRK_ZXR:
4991 tmp = FLOAT_THREE;
4992 break;
4993 case QUIRK_R3DI:
4994 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4995 tmp = FLOAT_ONE;
4996 break;
4997 case QUIRK_AE5:
4998 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
4999 tmp = FLOAT_THREE;
5000 break;
5001 case QUIRK_AE7:
5002 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5003 tmp = FLOAT_THREE;
5004 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5005 SR_96_000);
5006 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5007 SR_96_000);
5008 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5009 break;
5010 default:
5011 tmp = FLOAT_ONE;
5012 break;
5013 }
5014
5015 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5016 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5017 if (ca0132_quirk(spec) == QUIRK_R3DI)
5018 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5019
5020 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5021
5022 chipio_set_stream_control(codec, 0x03, 1);
5023 chipio_set_stream_control(codec, 0x04, 1);
5024 switch (ca0132_quirk(spec)) {
5025 case QUIRK_SBZ:
5026 chipio_write(codec, 0x18B098, 0x0000000C);
5027 chipio_write(codec, 0x18B09C, 0x0000000C);
5028 break;
5029 case QUIRK_ZXR:
5030 chipio_write(codec, 0x18B098, 0x0000000C);
5031 chipio_write(codec, 0x18B09C, 0x000000CC);
5032 break;
5033 case QUIRK_AE5:
5034 chipio_write(codec, 0x18B098, 0x0000000C);
5035 chipio_write(codec, 0x18B09C, 0x0000004C);
5036 break;
5037 default:
5038 break;
5039 }
5040 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5041 break;
5042 case REAR_LINE_IN:
5043 ca0132_mic_boost_set(codec, 0);
5044 switch (ca0132_quirk(spec)) {
5045 case QUIRK_SBZ:
5046 case QUIRK_R3D:
5047 ca0113_mmio_gpio_set(codec, 0, false);
5048 break;
5049 case QUIRK_R3DI:
5050 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5051 break;
5052 case QUIRK_AE5:
5053 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5054 break;
5055 case QUIRK_AE7:
5056 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5057 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5058 SR_96_000);
5059 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5060 SR_96_000);
5061 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5062 break;
5063 default:
5064 break;
5065 }
5066
5067 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5068 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5069 if (ca0132_quirk(spec) == QUIRK_R3DI)
5070 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5071
5072 if (ca0132_quirk(spec) == QUIRK_AE7)
5073 tmp = FLOAT_THREE;
5074 else
5075 tmp = FLOAT_ZERO;
5076 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5077
5078 switch (ca0132_quirk(spec)) {
5079 case QUIRK_SBZ:
5080 case QUIRK_AE5:
5081 chipio_write(codec, 0x18B098, 0x00000000);
5082 chipio_write(codec, 0x18B09C, 0x00000000);
5083 break;
5084 default:
5085 break;
5086 }
5087 chipio_set_stream_control(codec, 0x03, 1);
5088 chipio_set_stream_control(codec, 0x04, 1);
5089 break;
5090 case FRONT_MIC:
5091 switch (ca0132_quirk(spec)) {
5092 case QUIRK_SBZ:
5093 case QUIRK_R3D:
5094 ca0113_mmio_gpio_set(codec, 0, true);
5095 ca0113_mmio_gpio_set(codec, 5, false);
5096 tmp = FLOAT_THREE;
5097 break;
5098 case QUIRK_R3DI:
5099 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5100 tmp = FLOAT_ONE;
5101 break;
5102 case QUIRK_AE5:
5103 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5104 tmp = FLOAT_THREE;
5105 break;
5106 default:
5107 tmp = FLOAT_ONE;
5108 break;
5109 }
5110
5111 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5112 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5113 if (ca0132_quirk(spec) == QUIRK_R3DI)
5114 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5115
5116 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5117
5118 chipio_set_stream_control(codec, 0x03, 1);
5119 chipio_set_stream_control(codec, 0x04, 1);
5120
5121 switch (ca0132_quirk(spec)) {
5122 case QUIRK_SBZ:
5123 chipio_write(codec, 0x18B098, 0x0000000C);
5124 chipio_write(codec, 0x18B09C, 0x000000CC);
5125 break;
5126 case QUIRK_AE5:
5127 chipio_write(codec, 0x18B098, 0x0000000C);
5128 chipio_write(codec, 0x18B09C, 0x0000004C);
5129 break;
5130 default:
5131 break;
5132 }
5133 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5134 break;
5135 }
5136 ca0132_cvoice_switch_set(codec);
5137
5138 snd_hda_power_down_pm(codec);
5139 return 0;
5140 }
5141
5142 /*
5143 * Check if VNODE settings take effect immediately.
5144 */
ca0132_is_vnode_effective(struct hda_codec * codec,hda_nid_t vnid,hda_nid_t * shared_nid)5145 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5146 hda_nid_t vnid,
5147 hda_nid_t *shared_nid)
5148 {
5149 struct ca0132_spec *spec = codec->spec;
5150 hda_nid_t nid;
5151
5152 switch (vnid) {
5153 case VNID_SPK:
5154 nid = spec->shared_out_nid;
5155 break;
5156 case VNID_MIC:
5157 nid = spec->shared_mic_nid;
5158 break;
5159 default:
5160 return false;
5161 }
5162
5163 if (shared_nid)
5164 *shared_nid = nid;
5165
5166 return true;
5167 }
5168
5169 /*
5170 * The following functions are control change helpers.
5171 * They return 0 if no changed. Return 1 if changed.
5172 */
ca0132_voicefx_set(struct hda_codec * codec,int enable)5173 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5174 {
5175 struct ca0132_spec *spec = codec->spec;
5176 unsigned int tmp;
5177
5178 /* based on CrystalVoice state to enable VoiceFX. */
5179 if (enable) {
5180 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5181 FLOAT_ONE : FLOAT_ZERO;
5182 } else {
5183 tmp = FLOAT_ZERO;
5184 }
5185
5186 dspio_set_uint_param(codec, ca0132_voicefx.mid,
5187 ca0132_voicefx.reqs[0], tmp);
5188
5189 return 1;
5190 }
5191
5192 /*
5193 * Set the effects parameters
5194 */
ca0132_effects_set(struct hda_codec * codec,hda_nid_t nid,long val)5195 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5196 {
5197 struct ca0132_spec *spec = codec->spec;
5198 unsigned int on, tmp, channel_cfg;
5199 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5200 int err = 0;
5201 int idx = nid - EFFECT_START_NID;
5202
5203 if ((idx < 0) || (idx >= num_fx))
5204 return 0; /* no changed */
5205
5206 /* for out effect, qualify with PE */
5207 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
5208 /* if PE if off, turn off out effects. */
5209 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5210 val = 0;
5211 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5212 channel_cfg = spec->channel_cfg_val;
5213 if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
5214 channel_cfg != SPEAKER_CHANNELS_4_0)
5215 val = 0;
5216 }
5217 }
5218
5219 /* for in effect, qualify with CrystalVoice */
5220 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
5221 /* if CrystalVoice if off, turn off in effects. */
5222 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5223 val = 0;
5224
5225 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5226 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5227 val = 0;
5228
5229 /* If Voice Focus on SBZ, set to two channel. */
5230 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
5231 && (spec->cur_mic_type != REAR_LINE_IN)) {
5232 if (spec->effects_switch[CRYSTAL_VOICE -
5233 EFFECT_START_NID]) {
5234
5235 if (spec->effects_switch[VOICE_FOCUS -
5236 EFFECT_START_NID]) {
5237 tmp = FLOAT_TWO;
5238 val = 1;
5239 } else
5240 tmp = FLOAT_ONE;
5241
5242 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5243 }
5244 }
5245 /*
5246 * For SBZ noise reduction, there's an extra command
5247 * to module ID 0x47. No clue why.
5248 */
5249 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
5250 && (spec->cur_mic_type != REAR_LINE_IN)) {
5251 if (spec->effects_switch[CRYSTAL_VOICE -
5252 EFFECT_START_NID]) {
5253 if (spec->effects_switch[NOISE_REDUCTION -
5254 EFFECT_START_NID])
5255 tmp = FLOAT_ONE;
5256 else
5257 tmp = FLOAT_ZERO;
5258 } else
5259 tmp = FLOAT_ZERO;
5260
5261 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5262 }
5263
5264 /* If rear line in disable effects. */
5265 if (ca0132_use_alt_functions(spec) &&
5266 spec->in_enum_val == REAR_LINE_IN)
5267 val = 0;
5268 }
5269
5270 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5271 nid, val);
5272
5273 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5274 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5275 ca0132_effects[idx].reqs[0], on);
5276
5277 if (err < 0)
5278 return 0; /* no changed */
5279
5280 return 1;
5281 }
5282
5283 /*
5284 * Turn on/off Playback Enhancements
5285 */
ca0132_pe_switch_set(struct hda_codec * codec)5286 static int ca0132_pe_switch_set(struct hda_codec *codec)
5287 {
5288 struct ca0132_spec *spec = codec->spec;
5289 hda_nid_t nid;
5290 int i, ret = 0;
5291
5292 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5293 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5294
5295 if (ca0132_use_alt_functions(spec))
5296 ca0132_alt_select_out(codec);
5297
5298 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5299 nid = OUT_EFFECT_START_NID;
5300 /* PE affects all out effects */
5301 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
5302 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5303
5304 return ret;
5305 }
5306
5307 /* Check if Mic1 is streaming, if so, stop streaming */
stop_mic1(struct hda_codec * codec)5308 static int stop_mic1(struct hda_codec *codec)
5309 {
5310 struct ca0132_spec *spec = codec->spec;
5311 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5312 AC_VERB_GET_CONV, 0);
5313 if (oldval != 0)
5314 snd_hda_codec_write(codec, spec->adcs[0], 0,
5315 AC_VERB_SET_CHANNEL_STREAMID,
5316 0);
5317 return oldval;
5318 }
5319
5320 /* Resume Mic1 streaming if it was stopped. */
resume_mic1(struct hda_codec * codec,unsigned int oldval)5321 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5322 {
5323 struct ca0132_spec *spec = codec->spec;
5324 /* Restore the previous stream and channel */
5325 if (oldval != 0)
5326 snd_hda_codec_write(codec, spec->adcs[0], 0,
5327 AC_VERB_SET_CHANNEL_STREAMID,
5328 oldval);
5329 }
5330
5331 /*
5332 * Turn on/off CrystalVoice
5333 */
ca0132_cvoice_switch_set(struct hda_codec * codec)5334 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5335 {
5336 struct ca0132_spec *spec = codec->spec;
5337 hda_nid_t nid;
5338 int i, ret = 0;
5339 unsigned int oldval;
5340
5341 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5342 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5343
5344 i = IN_EFFECT_START_NID - EFFECT_START_NID;
5345 nid = IN_EFFECT_START_NID;
5346 /* CrystalVoice affects all in effects */
5347 for (; nid < IN_EFFECT_END_NID; nid++, i++)
5348 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5349
5350 /* including VoiceFX */
5351 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5352
5353 /* set correct vipsource */
5354 oldval = stop_mic1(codec);
5355 if (ca0132_use_alt_functions(spec))
5356 ret |= ca0132_alt_set_vipsource(codec, 1);
5357 else
5358 ret |= ca0132_set_vipsource(codec, 1);
5359 resume_mic1(codec, oldval);
5360 return ret;
5361 }
5362
ca0132_mic_boost_set(struct hda_codec * codec,long val)5363 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5364 {
5365 struct ca0132_spec *spec = codec->spec;
5366 int ret = 0;
5367
5368 if (val) /* on */
5369 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5370 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5371 else /* off */
5372 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5373 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5374
5375 return ret;
5376 }
5377
ca0132_alt_mic_boost_set(struct hda_codec * codec,long val)5378 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5379 {
5380 struct ca0132_spec *spec = codec->spec;
5381 int ret = 0;
5382
5383 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5384 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5385 return ret;
5386 }
5387
ae5_headphone_gain_set(struct hda_codec * codec,long val)5388 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5389 {
5390 unsigned int i;
5391
5392 for (i = 0; i < 4; i++)
5393 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5394 ae5_headphone_gain_presets[val].vals[i]);
5395 return 0;
5396 }
5397
5398 /*
5399 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5400 * amplifier to handle a 600 ohm load.
5401 */
zxr_headphone_gain_set(struct hda_codec * codec,long val)5402 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5403 {
5404 ca0113_mmio_gpio_set(codec, 1, val);
5405
5406 return 0;
5407 }
5408
ca0132_vnode_switch_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5409 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5410 struct snd_ctl_elem_value *ucontrol)
5411 {
5412 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5413 hda_nid_t nid = get_amp_nid(kcontrol);
5414 hda_nid_t shared_nid = 0;
5415 bool effective;
5416 int ret = 0;
5417 struct ca0132_spec *spec = codec->spec;
5418 int auto_jack;
5419
5420 if (nid == VNID_HP_SEL) {
5421 auto_jack =
5422 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5423 if (!auto_jack) {
5424 if (ca0132_use_alt_functions(spec))
5425 ca0132_alt_select_out(codec);
5426 else
5427 ca0132_select_out(codec);
5428 }
5429 return 1;
5430 }
5431
5432 if (nid == VNID_AMIC1_SEL) {
5433 auto_jack =
5434 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5435 if (!auto_jack)
5436 ca0132_select_mic(codec);
5437 return 1;
5438 }
5439
5440 if (nid == VNID_HP_ASEL) {
5441 if (ca0132_use_alt_functions(spec))
5442 ca0132_alt_select_out(codec);
5443 else
5444 ca0132_select_out(codec);
5445 return 1;
5446 }
5447
5448 if (nid == VNID_AMIC1_ASEL) {
5449 ca0132_select_mic(codec);
5450 return 1;
5451 }
5452
5453 /* if effective conditions, then update hw immediately. */
5454 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5455 if (effective) {
5456 int dir = get_amp_direction(kcontrol);
5457 int ch = get_amp_channels(kcontrol);
5458 unsigned long pval;
5459
5460 mutex_lock(&codec->control_mutex);
5461 pval = kcontrol->private_value;
5462 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5463 0, dir);
5464 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5465 kcontrol->private_value = pval;
5466 mutex_unlock(&codec->control_mutex);
5467 }
5468
5469 return ret;
5470 }
5471 /* End of control change helpers. */
5472
ca0132_alt_bass_redirection_xover_set(struct hda_codec * codec,long idx)5473 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5474 long idx)
5475 {
5476 snd_hda_power_up(codec);
5477
5478 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5479 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
5480
5481 snd_hda_power_down(codec);
5482 }
5483
5484 /*
5485 * Below I've added controls to mess with the effect levels, I've only enabled
5486 * them on the Sound Blaster Z, but they would probably also work on the
5487 * Chromebook. I figured they were probably tuned specifically for it, and left
5488 * out for a reason.
5489 */
5490
5491 /* Sets DSP effect level from the sliders above the controls */
5492
ca0132_alt_slider_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)5493 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5494 const unsigned int *lookup, int idx)
5495 {
5496 int i = 0;
5497 unsigned int y;
5498 /*
5499 * For X_BASS, req 2 is actually crossover freq instead of
5500 * effect level
5501 */
5502 if (nid == X_BASS)
5503 y = 2;
5504 else
5505 y = 1;
5506
5507 snd_hda_power_up(codec);
5508 if (nid == XBASS_XOVER) {
5509 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5510 if (ca0132_effects[i].nid == X_BASS)
5511 break;
5512
5513 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5514 ca0132_effects[i].reqs[1],
5515 &(lookup[idx - 1]), sizeof(unsigned int));
5516 } else {
5517 /* Find the actual effect structure */
5518 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5519 if (nid == ca0132_effects[i].nid)
5520 break;
5521
5522 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5523 ca0132_effects[i].reqs[y],
5524 &(lookup[idx]), sizeof(unsigned int));
5525 }
5526
5527 snd_hda_power_down(codec);
5528
5529 return 0;
5530 }
5531
ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5532 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5533 struct snd_ctl_elem_value *ucontrol)
5534 {
5535 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5536 struct ca0132_spec *spec = codec->spec;
5537 long *valp = ucontrol->value.integer.value;
5538 hda_nid_t nid = get_amp_nid(kcontrol);
5539
5540 if (nid == BASS_REDIRECTION_XOVER)
5541 *valp = spec->bass_redirect_xover_freq;
5542 else
5543 *valp = spec->xbass_xover_freq;
5544
5545 return 0;
5546 }
5547
ca0132_alt_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5548 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5549 struct snd_ctl_elem_value *ucontrol)
5550 {
5551 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5552 struct ca0132_spec *spec = codec->spec;
5553 hda_nid_t nid = get_amp_nid(kcontrol);
5554 long *valp = ucontrol->value.integer.value;
5555 int idx = nid - OUT_EFFECT_START_NID;
5556
5557 *valp = spec->fx_ctl_val[idx];
5558 return 0;
5559 }
5560
5561 /*
5562 * The X-bass crossover starts at 10hz, so the min is 1. The
5563 * frequency is set in multiples of 10.
5564 */
ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5565 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5566 struct snd_ctl_elem_info *uinfo)
5567 {
5568 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5569 uinfo->count = 1;
5570 uinfo->value.integer.min = 1;
5571 uinfo->value.integer.max = 100;
5572 uinfo->value.integer.step = 1;
5573
5574 return 0;
5575 }
5576
ca0132_alt_effect_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5577 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5578 struct snd_ctl_elem_info *uinfo)
5579 {
5580 int chs = get_amp_channels(kcontrol);
5581
5582 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5583 uinfo->count = chs == 3 ? 2 : 1;
5584 uinfo->value.integer.min = 0;
5585 uinfo->value.integer.max = 100;
5586 uinfo->value.integer.step = 1;
5587
5588 return 0;
5589 }
5590
ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5591 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5592 struct snd_ctl_elem_value *ucontrol)
5593 {
5594 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5595 struct ca0132_spec *spec = codec->spec;
5596 hda_nid_t nid = get_amp_nid(kcontrol);
5597 long *valp = ucontrol->value.integer.value;
5598 long *cur_val;
5599 int idx;
5600
5601 if (nid == BASS_REDIRECTION_XOVER)
5602 cur_val = &spec->bass_redirect_xover_freq;
5603 else
5604 cur_val = &spec->xbass_xover_freq;
5605
5606 /* any change? */
5607 if (*cur_val == *valp)
5608 return 0;
5609
5610 *cur_val = *valp;
5611
5612 idx = *valp;
5613 if (nid == BASS_REDIRECTION_XOVER)
5614 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5615 else
5616 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5617
5618 return 0;
5619 }
5620
ca0132_alt_effect_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5621 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5622 struct snd_ctl_elem_value *ucontrol)
5623 {
5624 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5625 struct ca0132_spec *spec = codec->spec;
5626 hda_nid_t nid = get_amp_nid(kcontrol);
5627 long *valp = ucontrol->value.integer.value;
5628 int idx;
5629
5630 idx = nid - EFFECT_START_NID;
5631 /* any change? */
5632 if (spec->fx_ctl_val[idx] == *valp)
5633 return 0;
5634
5635 spec->fx_ctl_val[idx] = *valp;
5636
5637 idx = *valp;
5638 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5639
5640 return 0;
5641 }
5642
5643
5644 /*
5645 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5646 * only has off or full 30 dB, and didn't like making a volume slider that has
5647 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5648 */
5649 #define MIC_BOOST_NUM_OF_STEPS 4
5650 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5651
ca0132_alt_mic_boost_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5652 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5653 struct snd_ctl_elem_info *uinfo)
5654 {
5655 char *sfx = "dB";
5656 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5657
5658 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5659 uinfo->count = 1;
5660 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5661 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5662 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5663 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5664 strcpy(uinfo->value.enumerated.name, namestr);
5665 return 0;
5666 }
5667
ca0132_alt_mic_boost_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5668 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5669 struct snd_ctl_elem_value *ucontrol)
5670 {
5671 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5672 struct ca0132_spec *spec = codec->spec;
5673
5674 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5675 return 0;
5676 }
5677
ca0132_alt_mic_boost_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5678 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5679 struct snd_ctl_elem_value *ucontrol)
5680 {
5681 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5682 struct ca0132_spec *spec = codec->spec;
5683 int sel = ucontrol->value.enumerated.item[0];
5684 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5685
5686 if (sel >= items)
5687 return 0;
5688
5689 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5690 sel);
5691
5692 spec->mic_boost_enum_val = sel;
5693
5694 if (spec->in_enum_val != REAR_LINE_IN)
5695 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5696
5697 return 1;
5698 }
5699
5700 /*
5701 * Sound BlasterX AE-5 Headphone Gain Controls.
5702 */
5703 #define AE5_HEADPHONE_GAIN_MAX 3
ae5_headphone_gain_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5704 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5705 struct snd_ctl_elem_info *uinfo)
5706 {
5707 char *sfx = " Ohms)";
5708 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5709
5710 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5711 uinfo->count = 1;
5712 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5713 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5714 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5715 sprintf(namestr, "%s %s",
5716 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5717 sfx);
5718 strcpy(uinfo->value.enumerated.name, namestr);
5719 return 0;
5720 }
5721
ae5_headphone_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5722 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5723 struct snd_ctl_elem_value *ucontrol)
5724 {
5725 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5726 struct ca0132_spec *spec = codec->spec;
5727
5728 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5729 return 0;
5730 }
5731
ae5_headphone_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5732 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5733 struct snd_ctl_elem_value *ucontrol)
5734 {
5735 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5736 struct ca0132_spec *spec = codec->spec;
5737 int sel = ucontrol->value.enumerated.item[0];
5738 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5739
5740 if (sel >= items)
5741 return 0;
5742
5743 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5744 sel);
5745
5746 spec->ae5_headphone_gain_val = sel;
5747
5748 if (spec->out_enum_val == HEADPHONE_OUT)
5749 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5750
5751 return 1;
5752 }
5753
5754 /*
5755 * Sound BlasterX AE-5 sound filter enumerated control.
5756 */
5757 #define AE5_SOUND_FILTER_MAX 3
5758
ae5_sound_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5759 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5760 struct snd_ctl_elem_info *uinfo)
5761 {
5762 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5763
5764 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5765 uinfo->count = 1;
5766 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5767 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5768 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5769 sprintf(namestr, "%s",
5770 ae5_filter_presets[uinfo->value.enumerated.item].name);
5771 strcpy(uinfo->value.enumerated.name, namestr);
5772 return 0;
5773 }
5774
ae5_sound_filter_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5775 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5776 struct snd_ctl_elem_value *ucontrol)
5777 {
5778 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5779 struct ca0132_spec *spec = codec->spec;
5780
5781 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5782 return 0;
5783 }
5784
ae5_sound_filter_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5785 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5786 struct snd_ctl_elem_value *ucontrol)
5787 {
5788 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5789 struct ca0132_spec *spec = codec->spec;
5790 int sel = ucontrol->value.enumerated.item[0];
5791 unsigned int items = AE5_SOUND_FILTER_MAX;
5792
5793 if (sel >= items)
5794 return 0;
5795
5796 codec_dbg(codec, "ae5_sound_filter: %s\n",
5797 ae5_filter_presets[sel].name);
5798
5799 spec->ae5_filter_val = sel;
5800
5801 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5802 ae5_filter_presets[sel].val);
5803
5804 return 1;
5805 }
5806
5807 /*
5808 * Input Select Control for alternative ca0132 codecs. This exists because
5809 * front microphone has no auto-detect, and we need a way to set the rear
5810 * as line-in
5811 */
ca0132_alt_input_source_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5812 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5813 struct snd_ctl_elem_info *uinfo)
5814 {
5815 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5816 uinfo->count = 1;
5817 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5818 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5819 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5820 strcpy(uinfo->value.enumerated.name,
5821 in_src_str[uinfo->value.enumerated.item]);
5822 return 0;
5823 }
5824
ca0132_alt_input_source_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5825 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5826 struct snd_ctl_elem_value *ucontrol)
5827 {
5828 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5829 struct ca0132_spec *spec = codec->spec;
5830
5831 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5832 return 0;
5833 }
5834
ca0132_alt_input_source_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5835 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5836 struct snd_ctl_elem_value *ucontrol)
5837 {
5838 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5839 struct ca0132_spec *spec = codec->spec;
5840 int sel = ucontrol->value.enumerated.item[0];
5841 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5842
5843 /*
5844 * The AE-7 has no front microphone, so limit items to 2: rear mic and
5845 * line-in.
5846 */
5847 if (ca0132_quirk(spec) == QUIRK_AE7)
5848 items = 2;
5849
5850 if (sel >= items)
5851 return 0;
5852
5853 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5854 sel, in_src_str[sel]);
5855
5856 spec->in_enum_val = sel;
5857
5858 ca0132_alt_select_in(codec);
5859
5860 return 1;
5861 }
5862
5863 /* Sound Blaster Z Output Select Control */
ca0132_alt_output_select_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5864 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5865 struct snd_ctl_elem_info *uinfo)
5866 {
5867 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5868 uinfo->count = 1;
5869 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5870 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5871 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5872 strcpy(uinfo->value.enumerated.name,
5873 out_type_str[uinfo->value.enumerated.item]);
5874 return 0;
5875 }
5876
ca0132_alt_output_select_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5877 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5878 struct snd_ctl_elem_value *ucontrol)
5879 {
5880 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5881 struct ca0132_spec *spec = codec->spec;
5882
5883 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5884 return 0;
5885 }
5886
ca0132_alt_output_select_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5887 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5888 struct snd_ctl_elem_value *ucontrol)
5889 {
5890 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5891 struct ca0132_spec *spec = codec->spec;
5892 int sel = ucontrol->value.enumerated.item[0];
5893 unsigned int items = NUM_OF_OUTPUTS;
5894 unsigned int auto_jack;
5895
5896 if (sel >= items)
5897 return 0;
5898
5899 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5900 sel, out_type_str[sel]);
5901
5902 spec->out_enum_val = sel;
5903
5904 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5905
5906 if (!auto_jack)
5907 ca0132_alt_select_out(codec);
5908
5909 return 1;
5910 }
5911
5912 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5913 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
5914 struct snd_ctl_elem_info *uinfo)
5915 {
5916 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
5917
5918 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5919 uinfo->count = 1;
5920 uinfo->value.enumerated.items = items;
5921 if (uinfo->value.enumerated.item >= items)
5922 uinfo->value.enumerated.item = items - 1;
5923 strcpy(uinfo->value.enumerated.name,
5924 speaker_channel_cfgs[uinfo->value.enumerated.item].name);
5925 return 0;
5926 }
5927
ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5928 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
5929 struct snd_ctl_elem_value *ucontrol)
5930 {
5931 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5932 struct ca0132_spec *spec = codec->spec;
5933
5934 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
5935 return 0;
5936 }
5937
ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5938 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
5939 struct snd_ctl_elem_value *ucontrol)
5940 {
5941 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5942 struct ca0132_spec *spec = codec->spec;
5943 int sel = ucontrol->value.enumerated.item[0];
5944 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
5945
5946 if (sel >= items)
5947 return 0;
5948
5949 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
5950 sel, speaker_channel_cfgs[sel].name);
5951
5952 spec->channel_cfg_val = sel;
5953
5954 if (spec->out_enum_val == SPEAKER_OUT)
5955 ca0132_alt_select_out(codec);
5956
5957 return 1;
5958 }
5959
5960 /*
5961 * Smart Volume output setting control. Three different settings, Normal,
5962 * which takes the value from the smart volume slider. The two others, loud
5963 * and night, disregard the slider value and have uneditable values.
5964 */
5965 #define NUM_OF_SVM_SETTINGS 3
5966 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5967
ca0132_alt_svm_setting_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5968 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5969 struct snd_ctl_elem_info *uinfo)
5970 {
5971 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5972 uinfo->count = 1;
5973 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5974 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5975 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5976 strcpy(uinfo->value.enumerated.name,
5977 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5978 return 0;
5979 }
5980
ca0132_alt_svm_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5981 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5982 struct snd_ctl_elem_value *ucontrol)
5983 {
5984 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5985 struct ca0132_spec *spec = codec->spec;
5986
5987 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5988 return 0;
5989 }
5990
ca0132_alt_svm_setting_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5991 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5992 struct snd_ctl_elem_value *ucontrol)
5993 {
5994 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5995 struct ca0132_spec *spec = codec->spec;
5996 int sel = ucontrol->value.enumerated.item[0];
5997 unsigned int items = NUM_OF_SVM_SETTINGS;
5998 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5999 unsigned int tmp;
6000
6001 if (sel >= items)
6002 return 0;
6003
6004 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6005 sel, out_svm_set_enum_str[sel]);
6006
6007 spec->smart_volume_setting = sel;
6008
6009 switch (sel) {
6010 case 0:
6011 tmp = FLOAT_ZERO;
6012 break;
6013 case 1:
6014 tmp = FLOAT_ONE;
6015 break;
6016 case 2:
6017 tmp = FLOAT_TWO;
6018 break;
6019 default:
6020 tmp = FLOAT_ZERO;
6021 break;
6022 }
6023 /* Req 2 is the Smart Volume Setting req. */
6024 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6025 ca0132_effects[idx].reqs[2], tmp);
6026 return 1;
6027 }
6028
6029 /* Sound Blaster Z EQ preset controls */
ca0132_alt_eq_preset_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6030 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
6031 struct snd_ctl_elem_info *uinfo)
6032 {
6033 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6034
6035 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6036 uinfo->count = 1;
6037 uinfo->value.enumerated.items = items;
6038 if (uinfo->value.enumerated.item >= items)
6039 uinfo->value.enumerated.item = items - 1;
6040 strcpy(uinfo->value.enumerated.name,
6041 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6042 return 0;
6043 }
6044
ca0132_alt_eq_preset_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6045 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
6046 struct snd_ctl_elem_value *ucontrol)
6047 {
6048 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6049 struct ca0132_spec *spec = codec->spec;
6050
6051 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6052 return 0;
6053 }
6054
ca0132_alt_eq_preset_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6055 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
6056 struct snd_ctl_elem_value *ucontrol)
6057 {
6058 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6059 struct ca0132_spec *spec = codec->spec;
6060 int i, err = 0;
6061 int sel = ucontrol->value.enumerated.item[0];
6062 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6063
6064 if (sel >= items)
6065 return 0;
6066
6067 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6068 ca0132_alt_eq_presets[sel].name);
6069 /*
6070 * Idx 0 is default.
6071 * Default needs to qualify with CrystalVoice state.
6072 */
6073 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6074 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6075 ca0132_alt_eq_enum.reqs[i],
6076 ca0132_alt_eq_presets[sel].vals[i]);
6077 if (err < 0)
6078 break;
6079 }
6080
6081 if (err >= 0)
6082 spec->eq_preset_val = sel;
6083
6084 return 1;
6085 }
6086
ca0132_voicefx_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6087 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
6088 struct snd_ctl_elem_info *uinfo)
6089 {
6090 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
6091
6092 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6093 uinfo->count = 1;
6094 uinfo->value.enumerated.items = items;
6095 if (uinfo->value.enumerated.item >= items)
6096 uinfo->value.enumerated.item = items - 1;
6097 strcpy(uinfo->value.enumerated.name,
6098 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6099 return 0;
6100 }
6101
ca0132_voicefx_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6102 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
6103 struct snd_ctl_elem_value *ucontrol)
6104 {
6105 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6106 struct ca0132_spec *spec = codec->spec;
6107
6108 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6109 return 0;
6110 }
6111
ca0132_voicefx_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6112 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
6113 struct snd_ctl_elem_value *ucontrol)
6114 {
6115 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6116 struct ca0132_spec *spec = codec->spec;
6117 int i, err = 0;
6118 int sel = ucontrol->value.enumerated.item[0];
6119
6120 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
6121 return 0;
6122
6123 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6124 sel, ca0132_voicefx_presets[sel].name);
6125
6126 /*
6127 * Idx 0 is default.
6128 * Default needs to qualify with CrystalVoice state.
6129 */
6130 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6131 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6132 ca0132_voicefx.reqs[i],
6133 ca0132_voicefx_presets[sel].vals[i]);
6134 if (err < 0)
6135 break;
6136 }
6137
6138 if (err >= 0) {
6139 spec->voicefx_val = sel;
6140 /* enable voice fx */
6141 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6142 }
6143
6144 return 1;
6145 }
6146
ca0132_switch_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6147 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
6148 struct snd_ctl_elem_value *ucontrol)
6149 {
6150 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6151 struct ca0132_spec *spec = codec->spec;
6152 hda_nid_t nid = get_amp_nid(kcontrol);
6153 int ch = get_amp_channels(kcontrol);
6154 long *valp = ucontrol->value.integer.value;
6155
6156 /* vnode */
6157 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6158 if (ch & 1) {
6159 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6160 valp++;
6161 }
6162 if (ch & 2) {
6163 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6164 valp++;
6165 }
6166 return 0;
6167 }
6168
6169 /* effects, include PE and CrystalVoice */
6170 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
6171 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6172 return 0;
6173 }
6174
6175 /* mic boost */
6176 if (nid == spec->input_pins[0]) {
6177 *valp = spec->cur_mic_boost;
6178 return 0;
6179 }
6180
6181 if (nid == ZXR_HEADPHONE_GAIN) {
6182 *valp = spec->zxr_gain_set;
6183 return 0;
6184 }
6185
6186 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6187 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6188 return 0;
6189 }
6190
6191 if (nid == BASS_REDIRECTION) {
6192 *valp = spec->bass_redirection_val;
6193 return 0;
6194 }
6195
6196 return 0;
6197 }
6198
ca0132_switch_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6199 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
6200 struct snd_ctl_elem_value *ucontrol)
6201 {
6202 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6203 struct ca0132_spec *spec = codec->spec;
6204 hda_nid_t nid = get_amp_nid(kcontrol);
6205 int ch = get_amp_channels(kcontrol);
6206 long *valp = ucontrol->value.integer.value;
6207 int changed = 1;
6208
6209 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6210 nid, *valp);
6211
6212 snd_hda_power_up(codec);
6213 /* vnode */
6214 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6215 if (ch & 1) {
6216 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6217 valp++;
6218 }
6219 if (ch & 2) {
6220 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6221 valp++;
6222 }
6223 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
6224 goto exit;
6225 }
6226
6227 /* PE */
6228 if (nid == PLAY_ENHANCEMENT) {
6229 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6230 changed = ca0132_pe_switch_set(codec);
6231 goto exit;
6232 }
6233
6234 /* CrystalVoice */
6235 if (nid == CRYSTAL_VOICE) {
6236 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6237 changed = ca0132_cvoice_switch_set(codec);
6238 goto exit;
6239 }
6240
6241 /* out and in effects */
6242 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
6243 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
6244 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6245 changed = ca0132_effects_set(codec, nid, *valp);
6246 goto exit;
6247 }
6248
6249 /* mic boost */
6250 if (nid == spec->input_pins[0]) {
6251 spec->cur_mic_boost = *valp;
6252 if (ca0132_use_alt_functions(spec)) {
6253 if (spec->in_enum_val != REAR_LINE_IN)
6254 changed = ca0132_mic_boost_set(codec, *valp);
6255 } else {
6256 /* Mic boost does not apply to Digital Mic */
6257 if (spec->cur_mic_type != DIGITAL_MIC)
6258 changed = ca0132_mic_boost_set(codec, *valp);
6259 }
6260
6261 goto exit;
6262 }
6263
6264 if (nid == ZXR_HEADPHONE_GAIN) {
6265 spec->zxr_gain_set = *valp;
6266 if (spec->cur_out_type == HEADPHONE_OUT)
6267 changed = zxr_headphone_gain_set(codec, *valp);
6268 else
6269 changed = 0;
6270
6271 goto exit;
6272 }
6273
6274 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6275 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6276 if (spec->cur_out_type == SPEAKER_OUT)
6277 ca0132_alt_set_full_range_speaker(codec);
6278
6279 changed = 0;
6280 }
6281
6282 if (nid == BASS_REDIRECTION) {
6283 spec->bass_redirection_val = *valp;
6284 if (spec->cur_out_type == SPEAKER_OUT)
6285 ca0132_alt_surround_set_bass_redirection(codec, *valp);
6286
6287 changed = 0;
6288 }
6289
6290 exit:
6291 snd_hda_power_down(codec);
6292 return changed;
6293 }
6294
6295 /*
6296 * Volume related
6297 */
6298 /*
6299 * Sets the internal DSP decibel level to match the DAC for output, and the
6300 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
6301 * all alternative codecs set DSP playback volume.
6302 */
ca0132_alt_dsp_volume_put(struct hda_codec * codec,hda_nid_t nid)6303 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6304 {
6305 struct ca0132_spec *spec = codec->spec;
6306 unsigned int dsp_dir;
6307 unsigned int lookup_val;
6308
6309 if (nid == VNID_SPK)
6310 dsp_dir = DSP_VOL_OUT;
6311 else
6312 dsp_dir = DSP_VOL_IN;
6313
6314 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6315
6316 dspio_set_uint_param(codec,
6317 ca0132_alt_vol_ctls[dsp_dir].mid,
6318 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6319 float_vol_db_lookup[lookup_val]);
6320
6321 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6322
6323 dspio_set_uint_param(codec,
6324 ca0132_alt_vol_ctls[dsp_dir].mid,
6325 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6326 float_vol_db_lookup[lookup_val]);
6327
6328 dspio_set_uint_param(codec,
6329 ca0132_alt_vol_ctls[dsp_dir].mid,
6330 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
6331 }
6332
ca0132_volume_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6333 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
6334 struct snd_ctl_elem_info *uinfo)
6335 {
6336 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6337 struct ca0132_spec *spec = codec->spec;
6338 hda_nid_t nid = get_amp_nid(kcontrol);
6339 int ch = get_amp_channels(kcontrol);
6340 int dir = get_amp_direction(kcontrol);
6341 unsigned long pval;
6342 int err;
6343
6344 switch (nid) {
6345 case VNID_SPK:
6346 /* follow shared_out info */
6347 nid = spec->shared_out_nid;
6348 mutex_lock(&codec->control_mutex);
6349 pval = kcontrol->private_value;
6350 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6351 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6352 kcontrol->private_value = pval;
6353 mutex_unlock(&codec->control_mutex);
6354 break;
6355 case VNID_MIC:
6356 /* follow shared_mic info */
6357 nid = spec->shared_mic_nid;
6358 mutex_lock(&codec->control_mutex);
6359 pval = kcontrol->private_value;
6360 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6361 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6362 kcontrol->private_value = pval;
6363 mutex_unlock(&codec->control_mutex);
6364 break;
6365 default:
6366 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6367 }
6368 return err;
6369 }
6370
ca0132_volume_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6371 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
6372 struct snd_ctl_elem_value *ucontrol)
6373 {
6374 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6375 struct ca0132_spec *spec = codec->spec;
6376 hda_nid_t nid = get_amp_nid(kcontrol);
6377 int ch = get_amp_channels(kcontrol);
6378 long *valp = ucontrol->value.integer.value;
6379
6380 /* store the left and right volume */
6381 if (ch & 1) {
6382 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6383 valp++;
6384 }
6385 if (ch & 2) {
6386 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6387 valp++;
6388 }
6389 return 0;
6390 }
6391
ca0132_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6392 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
6393 struct snd_ctl_elem_value *ucontrol)
6394 {
6395 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6396 struct ca0132_spec *spec = codec->spec;
6397 hda_nid_t nid = get_amp_nid(kcontrol);
6398 int ch = get_amp_channels(kcontrol);
6399 long *valp = ucontrol->value.integer.value;
6400 hda_nid_t shared_nid = 0;
6401 bool effective;
6402 int changed = 1;
6403
6404 /* store the left and right volume */
6405 if (ch & 1) {
6406 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6407 valp++;
6408 }
6409 if (ch & 2) {
6410 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6411 valp++;
6412 }
6413
6414 /* if effective conditions, then update hw immediately. */
6415 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6416 if (effective) {
6417 int dir = get_amp_direction(kcontrol);
6418 unsigned long pval;
6419
6420 snd_hda_power_up(codec);
6421 mutex_lock(&codec->control_mutex);
6422 pval = kcontrol->private_value;
6423 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6424 0, dir);
6425 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6426 kcontrol->private_value = pval;
6427 mutex_unlock(&codec->control_mutex);
6428 snd_hda_power_down(codec);
6429 }
6430
6431 return changed;
6432 }
6433
6434 /*
6435 * This function is the same as the one above, because using an if statement
6436 * inside of the above volume control for the DSP volume would cause too much
6437 * lag. This is a lot more smooth.
6438 */
ca0132_alt_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6439 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6440 struct snd_ctl_elem_value *ucontrol)
6441 {
6442 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6443 struct ca0132_spec *spec = codec->spec;
6444 hda_nid_t nid = get_amp_nid(kcontrol);
6445 int ch = get_amp_channels(kcontrol);
6446 long *valp = ucontrol->value.integer.value;
6447 hda_nid_t vnid = 0;
6448 int changed;
6449
6450 switch (nid) {
6451 case 0x02:
6452 vnid = VNID_SPK;
6453 break;
6454 case 0x07:
6455 vnid = VNID_MIC;
6456 break;
6457 }
6458
6459 /* store the left and right volume */
6460 if (ch & 1) {
6461 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6462 valp++;
6463 }
6464 if (ch & 2) {
6465 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6466 valp++;
6467 }
6468
6469 snd_hda_power_up(codec);
6470 ca0132_alt_dsp_volume_put(codec, vnid);
6471 mutex_lock(&codec->control_mutex);
6472 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6473 mutex_unlock(&codec->control_mutex);
6474 snd_hda_power_down(codec);
6475
6476 return changed;
6477 }
6478
ca0132_volume_tlv(struct snd_kcontrol * kcontrol,int op_flag,unsigned int size,unsigned int __user * tlv)6479 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6480 unsigned int size, unsigned int __user *tlv)
6481 {
6482 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6483 struct ca0132_spec *spec = codec->spec;
6484 hda_nid_t nid = get_amp_nid(kcontrol);
6485 int ch = get_amp_channels(kcontrol);
6486 int dir = get_amp_direction(kcontrol);
6487 unsigned long pval;
6488 int err;
6489
6490 switch (nid) {
6491 case VNID_SPK:
6492 /* follow shared_out tlv */
6493 nid = spec->shared_out_nid;
6494 mutex_lock(&codec->control_mutex);
6495 pval = kcontrol->private_value;
6496 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6497 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6498 kcontrol->private_value = pval;
6499 mutex_unlock(&codec->control_mutex);
6500 break;
6501 case VNID_MIC:
6502 /* follow shared_mic tlv */
6503 nid = spec->shared_mic_nid;
6504 mutex_lock(&codec->control_mutex);
6505 pval = kcontrol->private_value;
6506 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6507 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6508 kcontrol->private_value = pval;
6509 mutex_unlock(&codec->control_mutex);
6510 break;
6511 default:
6512 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6513 }
6514 return err;
6515 }
6516
6517 /* Add volume slider control for effect level */
ca0132_alt_add_effect_slider(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6518 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6519 const char *pfx, int dir)
6520 {
6521 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6522 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6523 struct snd_kcontrol_new knew =
6524 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6525
6526 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6527
6528 knew.tlv.c = NULL;
6529
6530 switch (nid) {
6531 case XBASS_XOVER:
6532 knew.info = ca0132_alt_xbass_xover_slider_info;
6533 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6534 knew.put = ca0132_alt_xbass_xover_slider_put;
6535 break;
6536 default:
6537 knew.info = ca0132_alt_effect_slider_info;
6538 knew.get = ca0132_alt_slider_ctl_get;
6539 knew.put = ca0132_alt_effect_slider_put;
6540 knew.private_value =
6541 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6542 break;
6543 }
6544
6545 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6546 }
6547
6548 /*
6549 * Added FX: prefix for the alternative codecs, because otherwise the surround
6550 * effect would conflict with the Surround sound volume control. Also seems more
6551 * clear as to what the switches do. Left alone for others.
6552 */
add_fx_switch(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6553 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6554 const char *pfx, int dir)
6555 {
6556 struct ca0132_spec *spec = codec->spec;
6557 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6558 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6559 struct snd_kcontrol_new knew =
6560 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6561 /* If using alt_controls, add FX: prefix. But, don't add FX:
6562 * prefix to OutFX or InFX enable controls.
6563 */
6564 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6565 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6566 else
6567 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6568
6569 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6570 }
6571
add_voicefx(struct hda_codec * codec)6572 static int add_voicefx(struct hda_codec *codec)
6573 {
6574 struct snd_kcontrol_new knew =
6575 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6576 VOICEFX, 1, 0, HDA_INPUT);
6577 knew.info = ca0132_voicefx_info;
6578 knew.get = ca0132_voicefx_get;
6579 knew.put = ca0132_voicefx_put;
6580 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6581 }
6582
6583 /* Create the EQ Preset control */
add_ca0132_alt_eq_presets(struct hda_codec * codec)6584 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6585 {
6586 struct snd_kcontrol_new knew =
6587 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6588 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6589 knew.info = ca0132_alt_eq_preset_info;
6590 knew.get = ca0132_alt_eq_preset_get;
6591 knew.put = ca0132_alt_eq_preset_put;
6592 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6593 snd_ctl_new1(&knew, codec));
6594 }
6595
6596 /*
6597 * Add enumerated control for the three different settings of the smart volume
6598 * output effect. Normal just uses the slider value, and loud and night are
6599 * their own things that ignore that value.
6600 */
ca0132_alt_add_svm_enum(struct hda_codec * codec)6601 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6602 {
6603 struct snd_kcontrol_new knew =
6604 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6605 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6606 knew.info = ca0132_alt_svm_setting_info;
6607 knew.get = ca0132_alt_svm_setting_get;
6608 knew.put = ca0132_alt_svm_setting_put;
6609 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6610 snd_ctl_new1(&knew, codec));
6611
6612 }
6613
6614 /*
6615 * Create an Output Select enumerated control for codecs with surround
6616 * out capabilities.
6617 */
ca0132_alt_add_output_enum(struct hda_codec * codec)6618 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6619 {
6620 struct snd_kcontrol_new knew =
6621 HDA_CODEC_MUTE_MONO("Output Select",
6622 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6623 knew.info = ca0132_alt_output_select_get_info;
6624 knew.get = ca0132_alt_output_select_get;
6625 knew.put = ca0132_alt_output_select_put;
6626 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6627 snd_ctl_new1(&knew, codec));
6628 }
6629
6630 /*
6631 * Add a control for selecting channel count on speaker output. Setting this
6632 * allows the DSP to do bass redirection and channel upmixing on surround
6633 * configurations.
6634 */
ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec * codec)6635 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6636 {
6637 struct snd_kcontrol_new knew =
6638 HDA_CODEC_MUTE_MONO("Surround Channel Config",
6639 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6640 knew.info = ca0132_alt_speaker_channel_cfg_get_info;
6641 knew.get = ca0132_alt_speaker_channel_cfg_get;
6642 knew.put = ca0132_alt_speaker_channel_cfg_put;
6643 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6644 snd_ctl_new1(&knew, codec));
6645 }
6646
6647 /*
6648 * Full range front stereo and rear surround switches. When these are set to
6649 * full range, the lower frequencies from these channels are no longer
6650 * redirected to the LFE channel.
6651 */
ca0132_alt_add_front_full_range_switch(struct hda_codec * codec)6652 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6653 {
6654 struct snd_kcontrol_new knew =
6655 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6656 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6657
6658 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6659 snd_ctl_new1(&knew, codec));
6660 }
6661
ca0132_alt_add_rear_full_range_switch(struct hda_codec * codec)6662 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6663 {
6664 struct snd_kcontrol_new knew =
6665 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6666 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6667
6668 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6669 snd_ctl_new1(&knew, codec));
6670 }
6671
6672 /*
6673 * Bass redirection redirects audio below the crossover frequency to the LFE
6674 * channel on speakers that are set as not being full-range. On configurations
6675 * without an LFE channel, it does nothing. Bass redirection seems to be the
6676 * replacement for X-Bass on configurations with an LFE channel.
6677 */
ca0132_alt_add_bass_redirection_crossover(struct hda_codec * codec)6678 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6679 {
6680 const char *namestr = "Bass Redirection Crossover";
6681 struct snd_kcontrol_new knew =
6682 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6683 HDA_OUTPUT);
6684
6685 knew.tlv.c = NULL;
6686 knew.info = ca0132_alt_xbass_xover_slider_info;
6687 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6688 knew.put = ca0132_alt_xbass_xover_slider_put;
6689
6690 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6691 snd_ctl_new1(&knew, codec));
6692 }
6693
ca0132_alt_add_bass_redirection_switch(struct hda_codec * codec)6694 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6695 {
6696 const char *namestr = "Bass Redirection";
6697 struct snd_kcontrol_new knew =
6698 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6699 HDA_OUTPUT);
6700
6701 return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6702 snd_ctl_new1(&knew, codec));
6703 }
6704
6705 /*
6706 * Create an Input Source enumerated control for the alternate ca0132 codecs
6707 * because the front microphone has no auto-detect, and Line-in has to be set
6708 * somehow.
6709 */
ca0132_alt_add_input_enum(struct hda_codec * codec)6710 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6711 {
6712 struct snd_kcontrol_new knew =
6713 HDA_CODEC_MUTE_MONO("Input Source",
6714 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6715 knew.info = ca0132_alt_input_source_info;
6716 knew.get = ca0132_alt_input_source_get;
6717 knew.put = ca0132_alt_input_source_put;
6718 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6719 snd_ctl_new1(&knew, codec));
6720 }
6721
6722 /*
6723 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6724 * more control than the original mic boost, which is either full 30dB or off.
6725 */
ca0132_alt_add_mic_boost_enum(struct hda_codec * codec)6726 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6727 {
6728 struct snd_kcontrol_new knew =
6729 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6730 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6731 knew.info = ca0132_alt_mic_boost_info;
6732 knew.get = ca0132_alt_mic_boost_get;
6733 knew.put = ca0132_alt_mic_boost_put;
6734 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6735 snd_ctl_new1(&knew, codec));
6736
6737 }
6738
6739 /*
6740 * Add headphone gain enumerated control for the AE-5. This switches between
6741 * three modes, low, medium, and high. When non-headphone outputs are selected,
6742 * it is automatically set to high. This is the same behavior as Windows.
6743 */
ae5_add_headphone_gain_enum(struct hda_codec * codec)6744 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6745 {
6746 struct snd_kcontrol_new knew =
6747 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6748 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6749 knew.info = ae5_headphone_gain_info;
6750 knew.get = ae5_headphone_gain_get;
6751 knew.put = ae5_headphone_gain_put;
6752 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6753 snd_ctl_new1(&knew, codec));
6754 }
6755
6756 /*
6757 * Add sound filter enumerated control for the AE-5. This adds three different
6758 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6759 * read into it, it changes the DAC's interpolation filter.
6760 */
ae5_add_sound_filter_enum(struct hda_codec * codec)6761 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6762 {
6763 struct snd_kcontrol_new knew =
6764 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6765 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6766 knew.info = ae5_sound_filter_info;
6767 knew.get = ae5_sound_filter_get;
6768 knew.put = ae5_sound_filter_put;
6769 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6770 snd_ctl_new1(&knew, codec));
6771 }
6772
zxr_add_headphone_gain_switch(struct hda_codec * codec)6773 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6774 {
6775 struct snd_kcontrol_new knew =
6776 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6777 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6778
6779 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6780 snd_ctl_new1(&knew, codec));
6781 }
6782
6783 /*
6784 * Need to create follower controls for the alternate codecs that have surround
6785 * capabilities.
6786 */
6787 static const char * const ca0132_alt_follower_pfxs[] = {
6788 "Front", "Surround", "Center", "LFE", NULL,
6789 };
6790
6791 /*
6792 * Also need special channel map, because the default one is incorrect.
6793 * I think this has to do with the pin for rear surround being 0x11,
6794 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6795 */
6796 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6797 { .channels = 2,
6798 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6799 { .channels = 4,
6800 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6801 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6802 { .channels = 6,
6803 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6804 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6805 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6806 { }
6807 };
6808
6809 /* Add the correct chmap for streams with 6 channels. */
ca0132_alt_add_chmap_ctls(struct hda_codec * codec)6810 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6811 {
6812 int err = 0;
6813 struct hda_pcm *pcm;
6814
6815 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6816 struct hda_pcm_stream *hinfo =
6817 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6818 struct snd_pcm_chmap *chmap;
6819 const struct snd_pcm_chmap_elem *elem;
6820
6821 elem = ca0132_alt_chmaps;
6822 if (hinfo->channels_max == 6) {
6823 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6824 SNDRV_PCM_STREAM_PLAYBACK,
6825 elem, hinfo->channels_max, 0, &chmap);
6826 if (err < 0)
6827 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6828 }
6829 }
6830 }
6831
6832 /*
6833 * When changing Node IDs for Mixer Controls below, make sure to update
6834 * Node IDs in ca0132_config() as well.
6835 */
6836 static const struct snd_kcontrol_new ca0132_mixer[] = {
6837 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6838 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6839 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6840 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6841 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6842 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6843 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6844 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6845 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6846 0x12, 1, HDA_INPUT),
6847 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6848 VNID_HP_SEL, 1, HDA_OUTPUT),
6849 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6850 VNID_AMIC1_SEL, 1, HDA_INPUT),
6851 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6852 VNID_HP_ASEL, 1, HDA_OUTPUT),
6853 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6854 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6855 { } /* end */
6856 };
6857
6858 /*
6859 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6860 * surround controls. Also sets both the Front Playback and Capture Volume
6861 * controls to alt so they set the DSP's decibel level.
6862 */
6863 static const struct snd_kcontrol_new desktop_mixer[] = {
6864 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6865 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6866 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6867 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6868 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6869 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6870 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6871 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6872 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6873 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6874 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6875 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6876 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6877 VNID_HP_ASEL, 1, HDA_OUTPUT),
6878 { } /* end */
6879 };
6880
6881 /*
6882 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6883 * because it doesn't set decibel levels for the DSP for capture.
6884 */
6885 static const struct snd_kcontrol_new r3di_mixer[] = {
6886 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6887 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6888 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6889 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6890 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6891 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6892 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6893 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6894 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6895 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6896 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6897 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6898 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6899 VNID_HP_ASEL, 1, HDA_OUTPUT),
6900 { } /* end */
6901 };
6902
ca0132_build_controls(struct hda_codec * codec)6903 static int ca0132_build_controls(struct hda_codec *codec)
6904 {
6905 struct ca0132_spec *spec = codec->spec;
6906 int i, num_fx, num_sliders;
6907 int err = 0;
6908
6909 /* Add Mixer controls */
6910 for (i = 0; i < spec->num_mixers; i++) {
6911 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6912 if (err < 0)
6913 return err;
6914 }
6915 /* Setup vmaster with surround followers for desktop ca0132 devices */
6916 if (ca0132_use_alt_functions(spec)) {
6917 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6918 spec->tlv);
6919 snd_hda_add_vmaster(codec, "Master Playback Volume",
6920 spec->tlv, ca0132_alt_follower_pfxs,
6921 "Playback Volume");
6922 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6923 NULL, ca0132_alt_follower_pfxs,
6924 "Playback Switch",
6925 true, &spec->vmaster_mute.sw_kctl);
6926 if (err < 0)
6927 return err;
6928 }
6929
6930 /* Add in and out effects controls.
6931 * VoiceFX, PE and CrystalVoice are added separately.
6932 */
6933 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6934 for (i = 0; i < num_fx; i++) {
6935 /* Desktop cards break if Echo Cancellation is used. */
6936 if (ca0132_use_pci_mmio(spec)) {
6937 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6938 OUT_EFFECTS_COUNT))
6939 continue;
6940 }
6941
6942 err = add_fx_switch(codec, ca0132_effects[i].nid,
6943 ca0132_effects[i].name,
6944 ca0132_effects[i].direct);
6945 if (err < 0)
6946 return err;
6947 }
6948 /*
6949 * If codec has use_alt_controls set to true, add effect level sliders,
6950 * EQ presets, and Smart Volume presets. Also, change names to add FX
6951 * prefix, and change PlayEnhancement and CrystalVoice to match.
6952 */
6953 if (ca0132_use_alt_controls(spec)) {
6954 err = ca0132_alt_add_svm_enum(codec);
6955 if (err < 0)
6956 return err;
6957
6958 err = add_ca0132_alt_eq_presets(codec);
6959 if (err < 0)
6960 return err;
6961
6962 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6963 "Enable OutFX", 0);
6964 if (err < 0)
6965 return err;
6966
6967 err = add_fx_switch(codec, CRYSTAL_VOICE,
6968 "Enable InFX", 1);
6969 if (err < 0)
6970 return err;
6971
6972 num_sliders = OUT_EFFECTS_COUNT - 1;
6973 for (i = 0; i < num_sliders; i++) {
6974 err = ca0132_alt_add_effect_slider(codec,
6975 ca0132_effects[i].nid,
6976 ca0132_effects[i].name,
6977 ca0132_effects[i].direct);
6978 if (err < 0)
6979 return err;
6980 }
6981
6982 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6983 "X-Bass Crossover", EFX_DIR_OUT);
6984
6985 if (err < 0)
6986 return err;
6987 } else {
6988 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6989 "PlayEnhancement", 0);
6990 if (err < 0)
6991 return err;
6992
6993 err = add_fx_switch(codec, CRYSTAL_VOICE,
6994 "CrystalVoice", 1);
6995 if (err < 0)
6996 return err;
6997 }
6998 err = add_voicefx(codec);
6999 if (err < 0)
7000 return err;
7001
7002 /*
7003 * If the codec uses alt_functions, you need the enumerated controls
7004 * to select the new outputs and inputs, plus add the new mic boost
7005 * setting control.
7006 */
7007 if (ca0132_use_alt_functions(spec)) {
7008 err = ca0132_alt_add_output_enum(codec);
7009 if (err < 0)
7010 return err;
7011 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7012 if (err < 0)
7013 return err;
7014 err = ca0132_alt_add_front_full_range_switch(codec);
7015 if (err < 0)
7016 return err;
7017 err = ca0132_alt_add_rear_full_range_switch(codec);
7018 if (err < 0)
7019 return err;
7020 err = ca0132_alt_add_bass_redirection_crossover(codec);
7021 if (err < 0)
7022 return err;
7023 err = ca0132_alt_add_bass_redirection_switch(codec);
7024 if (err < 0)
7025 return err;
7026 err = ca0132_alt_add_mic_boost_enum(codec);
7027 if (err < 0)
7028 return err;
7029 /*
7030 * ZxR only has microphone input, there is no front panel
7031 * header on the card, and aux-in is handled by the DBPro board.
7032 */
7033 if (ca0132_quirk(spec) != QUIRK_ZXR) {
7034 err = ca0132_alt_add_input_enum(codec);
7035 if (err < 0)
7036 return err;
7037 }
7038 }
7039
7040 switch (ca0132_quirk(spec)) {
7041 case QUIRK_AE5:
7042 case QUIRK_AE7:
7043 err = ae5_add_headphone_gain_enum(codec);
7044 if (err < 0)
7045 return err;
7046 err = ae5_add_sound_filter_enum(codec);
7047 if (err < 0)
7048 return err;
7049 break;
7050 case QUIRK_ZXR:
7051 err = zxr_add_headphone_gain_switch(codec);
7052 if (err < 0)
7053 return err;
7054 break;
7055 default:
7056 break;
7057 }
7058
7059 #ifdef ENABLE_TUNING_CONTROLS
7060 add_tuning_ctls(codec);
7061 #endif
7062
7063 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7064 if (err < 0)
7065 return err;
7066
7067 if (spec->dig_out) {
7068 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7069 spec->dig_out);
7070 if (err < 0)
7071 return err;
7072 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7073 if (err < 0)
7074 return err;
7075 /* spec->multiout.share_spdif = 1; */
7076 }
7077
7078 if (spec->dig_in) {
7079 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7080 if (err < 0)
7081 return err;
7082 }
7083
7084 if (ca0132_use_alt_functions(spec))
7085 ca0132_alt_add_chmap_ctls(codec);
7086
7087 return 0;
7088 }
7089
dbpro_build_controls(struct hda_codec * codec)7090 static int dbpro_build_controls(struct hda_codec *codec)
7091 {
7092 struct ca0132_spec *spec = codec->spec;
7093 int err = 0;
7094
7095 if (spec->dig_out) {
7096 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7097 spec->dig_out);
7098 if (err < 0)
7099 return err;
7100 }
7101
7102 if (spec->dig_in) {
7103 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7104 if (err < 0)
7105 return err;
7106 }
7107
7108 return 0;
7109 }
7110
7111 /*
7112 * PCM
7113 */
7114 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
7115 .substreams = 1,
7116 .channels_min = 2,
7117 .channels_max = 6,
7118 .ops = {
7119 .prepare = ca0132_playback_pcm_prepare,
7120 .cleanup = ca0132_playback_pcm_cleanup,
7121 .get_delay = ca0132_playback_pcm_delay,
7122 },
7123 };
7124
7125 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
7126 .substreams = 1,
7127 .channels_min = 2,
7128 .channels_max = 2,
7129 .ops = {
7130 .prepare = ca0132_capture_pcm_prepare,
7131 .cleanup = ca0132_capture_pcm_cleanup,
7132 .get_delay = ca0132_capture_pcm_delay,
7133 },
7134 };
7135
7136 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
7137 .substreams = 1,
7138 .channels_min = 2,
7139 .channels_max = 2,
7140 .ops = {
7141 .open = ca0132_dig_playback_pcm_open,
7142 .close = ca0132_dig_playback_pcm_close,
7143 .prepare = ca0132_dig_playback_pcm_prepare,
7144 .cleanup = ca0132_dig_playback_pcm_cleanup
7145 },
7146 };
7147
7148 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
7149 .substreams = 1,
7150 .channels_min = 2,
7151 .channels_max = 2,
7152 };
7153
ca0132_build_pcms(struct hda_codec * codec)7154 static int ca0132_build_pcms(struct hda_codec *codec)
7155 {
7156 struct ca0132_spec *spec = codec->spec;
7157 struct hda_pcm *info;
7158
7159 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7160 if (!info)
7161 return -ENOMEM;
7162 if (ca0132_use_alt_functions(spec)) {
7163 info->own_chmap = true;
7164 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7165 = ca0132_alt_chmaps;
7166 }
7167 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7168 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7169 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7170 spec->multiout.max_channels;
7171 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7172 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7173 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7174
7175 /* With the DSP enabled, desktops don't use this ADC. */
7176 if (!ca0132_use_alt_functions(spec)) {
7177 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7178 if (!info)
7179 return -ENOMEM;
7180 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7181 ca0132_pcm_analog_capture;
7182 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7183 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7184 }
7185
7186 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7187 if (!info)
7188 return -ENOMEM;
7189 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7190 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7191 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7192
7193 if (!spec->dig_out && !spec->dig_in)
7194 return 0;
7195
7196 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7197 if (!info)
7198 return -ENOMEM;
7199 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7200 if (spec->dig_out) {
7201 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7202 ca0132_pcm_digital_playback;
7203 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7204 }
7205 if (spec->dig_in) {
7206 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7207 ca0132_pcm_digital_capture;
7208 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7209 }
7210
7211 return 0;
7212 }
7213
dbpro_build_pcms(struct hda_codec * codec)7214 static int dbpro_build_pcms(struct hda_codec *codec)
7215 {
7216 struct ca0132_spec *spec = codec->spec;
7217 struct hda_pcm *info;
7218
7219 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7220 if (!info)
7221 return -ENOMEM;
7222 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7223 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7224 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7225
7226
7227 if (!spec->dig_out && !spec->dig_in)
7228 return 0;
7229
7230 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7231 if (!info)
7232 return -ENOMEM;
7233 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7234 if (spec->dig_out) {
7235 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7236 ca0132_pcm_digital_playback;
7237 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7238 }
7239 if (spec->dig_in) {
7240 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7241 ca0132_pcm_digital_capture;
7242 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7243 }
7244
7245 return 0;
7246 }
7247
init_output(struct hda_codec * codec,hda_nid_t pin,hda_nid_t dac)7248 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7249 {
7250 if (pin) {
7251 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7252 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7253 snd_hda_codec_write(codec, pin, 0,
7254 AC_VERB_SET_AMP_GAIN_MUTE,
7255 AMP_OUT_UNMUTE);
7256 }
7257 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7258 snd_hda_codec_write(codec, dac, 0,
7259 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
7260 }
7261
init_input(struct hda_codec * codec,hda_nid_t pin,hda_nid_t adc)7262 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7263 {
7264 if (pin) {
7265 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7266 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7267 snd_hda_codec_write(codec, pin, 0,
7268 AC_VERB_SET_AMP_GAIN_MUTE,
7269 AMP_IN_UNMUTE(0));
7270 }
7271 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7272 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7273 AMP_IN_UNMUTE(0));
7274
7275 /* init to 0 dB and unmute. */
7276 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7277 HDA_AMP_VOLMASK, 0x5a);
7278 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7279 HDA_AMP_MUTE, 0);
7280 }
7281 }
7282
refresh_amp_caps(struct hda_codec * codec,hda_nid_t nid,int dir)7283 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7284 {
7285 unsigned int caps;
7286
7287 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7288 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
7289 snd_hda_override_amp_caps(codec, nid, dir, caps);
7290 }
7291
7292 /*
7293 * Switch between Digital built-in mic and analog mic.
7294 */
ca0132_set_dmic(struct hda_codec * codec,int enable)7295 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7296 {
7297 struct ca0132_spec *spec = codec->spec;
7298 unsigned int tmp;
7299 u8 val;
7300 unsigned int oldval;
7301
7302 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7303
7304 oldval = stop_mic1(codec);
7305 ca0132_set_vipsource(codec, 0);
7306 if (enable) {
7307 /* set DMic input as 2-ch */
7308 tmp = FLOAT_TWO;
7309 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7310
7311 val = spec->dmic_ctl;
7312 val |= 0x80;
7313 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7314 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7315
7316 if (!(spec->dmic_ctl & 0x20))
7317 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7318 } else {
7319 /* set AMic input as mono */
7320 tmp = FLOAT_ONE;
7321 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7322
7323 val = spec->dmic_ctl;
7324 /* clear bit7 and bit5 to disable dmic */
7325 val &= 0x5f;
7326 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7327 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7328
7329 if (!(spec->dmic_ctl & 0x20))
7330 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7331 }
7332 ca0132_set_vipsource(codec, 1);
7333 resume_mic1(codec, oldval);
7334 }
7335
7336 /*
7337 * Initialization for Digital Mic.
7338 */
ca0132_init_dmic(struct hda_codec * codec)7339 static void ca0132_init_dmic(struct hda_codec *codec)
7340 {
7341 struct ca0132_spec *spec = codec->spec;
7342 u8 val;
7343
7344 /* Setup Digital Mic here, but don't enable.
7345 * Enable based on jack detect.
7346 */
7347
7348 /* MCLK uses MPIO1, set to enable.
7349 * Bit 2-0: MPIO select
7350 * Bit 3: set to disable
7351 * Bit 7-4: reserved
7352 */
7353 val = 0x01;
7354 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7355 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
7356
7357 /* Data1 uses MPIO3. Data2 not use
7358 * Bit 2-0: Data1 MPIO select
7359 * Bit 3: set disable Data1
7360 * Bit 6-4: Data2 MPIO select
7361 * Bit 7: set disable Data2
7362 */
7363 val = 0x83;
7364 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7365 VENDOR_CHIPIO_DMIC_PIN_SET, val);
7366
7367 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7368 * Bit 3-0: Channel mask
7369 * Bit 4: set for 48KHz, clear for 32KHz
7370 * Bit 5: mode
7371 * Bit 6: set to select Data2, clear for Data1
7372 * Bit 7: set to enable DMic, clear for AMic
7373 */
7374 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
7375 val = 0x33;
7376 else
7377 val = 0x23;
7378 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
7379 spec->dmic_ctl = val;
7380 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7381 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7382 }
7383
7384 /*
7385 * Initialization for Analog Mic 2
7386 */
ca0132_init_analog_mic2(struct hda_codec * codec)7387 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7388 {
7389 struct ca0132_spec *spec = codec->spec;
7390
7391 mutex_lock(&spec->chipio_mutex);
7392 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7393 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7394 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7395 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7396 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7397 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7398 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7399 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
7400 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7401 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7402 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7403 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7404 mutex_unlock(&spec->chipio_mutex);
7405 }
7406
ca0132_refresh_widget_caps(struct hda_codec * codec)7407 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7408 {
7409 struct ca0132_spec *spec = codec->spec;
7410 int i;
7411
7412 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7413 snd_hda_codec_update_widgets(codec);
7414
7415 for (i = 0; i < spec->multiout.num_dacs; i++)
7416 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7417
7418 for (i = 0; i < spec->num_outputs; i++)
7419 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7420
7421 for (i = 0; i < spec->num_inputs; i++) {
7422 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7423 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7424 }
7425 }
7426
7427 /*
7428 * Default speaker tuning values setup for alternative codecs.
7429 */
7430 static const unsigned int sbz_default_delay_values[] = {
7431 /* Non-zero values are floating point 0.000198. */
7432 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7433 };
7434
7435 static const unsigned int zxr_default_delay_values[] = {
7436 /* Non-zero values are floating point 0.000220. */
7437 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7438 };
7439
7440 static const unsigned int ae5_default_delay_values[] = {
7441 /* Non-zero values are floating point 0.000100. */
7442 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7443 };
7444
7445 /*
7446 * If we never change these, probably only need them on initialization.
7447 */
ca0132_alt_init_speaker_tuning(struct hda_codec * codec)7448 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7449 {
7450 struct ca0132_spec *spec = codec->spec;
7451 unsigned int i, tmp, start_req, end_req;
7452 const unsigned int *values;
7453
7454 switch (ca0132_quirk(spec)) {
7455 case QUIRK_SBZ:
7456 values = sbz_default_delay_values;
7457 break;
7458 case QUIRK_ZXR:
7459 values = zxr_default_delay_values;
7460 break;
7461 case QUIRK_AE5:
7462 case QUIRK_AE7:
7463 values = ae5_default_delay_values;
7464 break;
7465 default:
7466 values = sbz_default_delay_values;
7467 break;
7468 }
7469
7470 tmp = FLOAT_ZERO;
7471 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7472
7473 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
7474 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
7475 for (i = start_req; i < end_req + 1; i++)
7476 dspio_set_uint_param(codec, 0x96, i, tmp);
7477
7478 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
7479 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
7480 for (i = start_req; i < end_req + 1; i++)
7481 dspio_set_uint_param(codec, 0x96, i, tmp);
7482
7483
7484 for (i = 0; i < 6; i++)
7485 dspio_set_uint_param(codec, 0x96,
7486 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
7487 }
7488
7489 /*
7490 * Creates a dummy stream to bind the output to. This seems to have to be done
7491 * after changing the main outputs source and destination streams.
7492 */
ca0132_alt_create_dummy_stream(struct hda_codec * codec)7493 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
7494 {
7495 struct ca0132_spec *spec = codec->spec;
7496 unsigned int stream_format;
7497
7498 stream_format = snd_hdac_calc_stream_format(48000, 2,
7499 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7500
7501 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
7502 0, stream_format);
7503
7504 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7505 }
7506
7507 /*
7508 * Initialize mic for non-chromebook ca0132 implementations.
7509 */
ca0132_alt_init_analog_mics(struct hda_codec * codec)7510 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7511 {
7512 struct ca0132_spec *spec = codec->spec;
7513 unsigned int tmp;
7514
7515 /* Mic 1 Setup */
7516 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7517 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7518 if (ca0132_quirk(spec) == QUIRK_R3DI) {
7519 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7520 tmp = FLOAT_ONE;
7521 } else
7522 tmp = FLOAT_THREE;
7523 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7524
7525 /* Mic 2 setup (not present on desktop cards) */
7526 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7527 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7528 if (ca0132_quirk(spec) == QUIRK_R3DI)
7529 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7530 tmp = FLOAT_ZERO;
7531 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7532 }
7533
7534 /*
7535 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7536 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7537 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
7538 * having an updated DAC, which changes the destination to that DAC.
7539 */
sbz_connect_streams(struct hda_codec * codec)7540 static void sbz_connect_streams(struct hda_codec *codec)
7541 {
7542 struct ca0132_spec *spec = codec->spec;
7543
7544 mutex_lock(&spec->chipio_mutex);
7545
7546 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7547
7548 chipio_set_stream_channels(codec, 0x0C, 6);
7549 chipio_set_stream_control(codec, 0x0C, 1);
7550
7551 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7552 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7553
7554 /* Setup stream 0x14 with it's source and destination points */
7555 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7556 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7557 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7558 chipio_set_stream_channels(codec, 0x14, 2);
7559 chipio_set_stream_control(codec, 0x14, 1);
7560
7561 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7562
7563 mutex_unlock(&spec->chipio_mutex);
7564 }
7565
7566 /*
7567 * Write data through ChipIO to setup proper stream destinations.
7568 * Not sure how it exactly works, but it seems to direct data
7569 * to different destinations. Example is f8 to c0, e0 to c0.
7570 * All I know is, if you don't set these, you get no sound.
7571 */
sbz_chipio_startup_data(struct hda_codec * codec)7572 static void sbz_chipio_startup_data(struct hda_codec *codec)
7573 {
7574 struct ca0132_spec *spec = codec->spec;
7575
7576 mutex_lock(&spec->chipio_mutex);
7577 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7578
7579 /* These control audio output */
7580 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
7581 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
7582 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
7583 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
7584 /* Signal to update I think */
7585 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7586
7587 chipio_set_stream_channels(codec, 0x0C, 6);
7588 chipio_set_stream_control(codec, 0x0C, 1);
7589 /* No clue what these control */
7590 if (ca0132_quirk(spec) == QUIRK_SBZ) {
7591 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
7592 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
7593 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
7594 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
7595 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
7596 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
7597 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
7598 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
7599 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
7600 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
7601 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
7602 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
7603 } else if (ca0132_quirk(spec) == QUIRK_ZXR) {
7604 chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
7605 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
7606 chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
7607 chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
7608 chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
7609 chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
7610 chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
7611 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
7612 }
7613 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7614
7615 codec_dbg(codec, "Startup Data exited, mutex released.\n");
7616 mutex_unlock(&spec->chipio_mutex);
7617 }
7618
7619 /*
7620 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
7621 * done after the DSP is loaded.
7622 */
ca0132_alt_dsp_scp_startup(struct hda_codec * codec)7623 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
7624 {
7625 struct ca0132_spec *spec = codec->spec;
7626 unsigned int tmp, i;
7627
7628 /*
7629 * Gotta run these twice, or else mic works inconsistently. Not clear
7630 * why this is, but multiple tests have confirmed it.
7631 */
7632 for (i = 0; i < 2; i++) {
7633 switch (ca0132_quirk(spec)) {
7634 case QUIRK_SBZ:
7635 case QUIRK_AE5:
7636 case QUIRK_AE7:
7637 tmp = 0x00000003;
7638 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7639 tmp = 0x00000000;
7640 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7641 tmp = 0x00000001;
7642 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7643 tmp = 0x00000004;
7644 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7645 tmp = 0x00000005;
7646 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7647 tmp = 0x00000000;
7648 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7649 break;
7650 case QUIRK_R3D:
7651 case QUIRK_R3DI:
7652 tmp = 0x00000000;
7653 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7654 tmp = 0x00000001;
7655 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7656 tmp = 0x00000004;
7657 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7658 tmp = 0x00000005;
7659 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7660 tmp = 0x00000000;
7661 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7662 break;
7663 default:
7664 break;
7665 }
7666 msleep(100);
7667 }
7668 }
7669
ca0132_alt_dsp_initial_mic_setup(struct hda_codec * codec)7670 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7671 {
7672 struct ca0132_spec *spec = codec->spec;
7673 unsigned int tmp;
7674
7675 chipio_set_stream_control(codec, 0x03, 0);
7676 chipio_set_stream_control(codec, 0x04, 0);
7677
7678 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7679 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7680
7681 tmp = FLOAT_THREE;
7682 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7683
7684 chipio_set_stream_control(codec, 0x03, 1);
7685 chipio_set_stream_control(codec, 0x04, 1);
7686
7687 switch (ca0132_quirk(spec)) {
7688 case QUIRK_SBZ:
7689 chipio_write(codec, 0x18b098, 0x0000000c);
7690 chipio_write(codec, 0x18b09C, 0x0000000c);
7691 break;
7692 case QUIRK_AE5:
7693 chipio_write(codec, 0x18b098, 0x0000000c);
7694 chipio_write(codec, 0x18b09c, 0x0000004c);
7695 break;
7696 default:
7697 break;
7698 }
7699 }
7700
ae5_post_dsp_register_set(struct hda_codec * codec)7701 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7702 {
7703 struct ca0132_spec *spec = codec->spec;
7704
7705 chipio_8051_write_direct(codec, 0x93, 0x10);
7706 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7707 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7708 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7709 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7710
7711 writeb(0xff, spec->mem_base + 0x304);
7712 writeb(0xff, spec->mem_base + 0x304);
7713 writeb(0xff, spec->mem_base + 0x304);
7714 writeb(0xff, spec->mem_base + 0x304);
7715 writeb(0x00, spec->mem_base + 0x100);
7716 writeb(0xff, spec->mem_base + 0x304);
7717 writeb(0x00, spec->mem_base + 0x100);
7718 writeb(0xff, spec->mem_base + 0x304);
7719 writeb(0x00, spec->mem_base + 0x100);
7720 writeb(0xff, spec->mem_base + 0x304);
7721 writeb(0x00, spec->mem_base + 0x100);
7722 writeb(0xff, spec->mem_base + 0x304);
7723
7724 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7725 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7726 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7727 }
7728
ae5_post_dsp_param_setup(struct hda_codec * codec)7729 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7730 {
7731 /*
7732 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7733 * which seems to be 'multichannel'. This is also mentioned in the
7734 * AE-5's registry values in Windows.
7735 */
7736 chipio_set_control_param(codec, 3, 0);
7737 /*
7738 * I believe ASI is 'audio serial interface' and that it's used to
7739 * change colors on the external LED strip connected to the AE-5.
7740 */
7741 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7742
7743 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7744 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7745
7746 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7747 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
7748 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7749 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
7750 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7751 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
7752 }
7753
ae5_post_dsp_pll_setup(struct hda_codec * codec)7754 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7755 {
7756 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7757 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
7758 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7759 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
7760
7761 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7762 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
7763 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7764 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
7765
7766 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7767 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
7768 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7769 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
7770
7771 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7772 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7773 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7774 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7775
7776 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7777 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
7778 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7779 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
7780 }
7781
ae5_post_dsp_stream_setup(struct hda_codec * codec)7782 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7783 {
7784 struct ca0132_spec *spec = codec->spec;
7785
7786 mutex_lock(&spec->chipio_mutex);
7787
7788 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7789
7790 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7791
7792 chipio_set_stream_channels(codec, 0x0C, 6);
7793 chipio_set_stream_control(codec, 0x0C, 1);
7794
7795 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7796
7797 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7798 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7799 chipio_set_stream_channels(codec, 0x18, 6);
7800 chipio_set_stream_control(codec, 0x18, 1);
7801
7802 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7803
7804 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7805 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7806 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7807 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7808
7809 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7810
7811 mutex_unlock(&spec->chipio_mutex);
7812 }
7813
ae5_post_dsp_startup_data(struct hda_codec * codec)7814 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7815 {
7816 struct ca0132_spec *spec = codec->spec;
7817
7818 mutex_lock(&spec->chipio_mutex);
7819
7820 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7821 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7822 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7823 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7824
7825 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7826 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7827 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7828 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7829 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7830 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7831 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7832 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7833 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7834 ca0113_mmio_gpio_set(codec, 0, true);
7835 ca0113_mmio_gpio_set(codec, 1, true);
7836 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7837
7838 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7839
7840 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7841 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7842
7843 mutex_unlock(&spec->chipio_mutex);
7844 }
7845
7846 static const unsigned int ae7_port_set_data[] = {
7847 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 0x0001e2c4, 0x0001e3c5,
7848 0x0001e8c6, 0x0001e9c7, 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb
7849 };
7850
ae7_post_dsp_setup_ports(struct hda_codec * codec)7851 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
7852 {
7853 struct ca0132_spec *spec = codec->spec;
7854 unsigned int i, count, addr;
7855
7856 mutex_lock(&spec->chipio_mutex);
7857
7858 chipio_set_stream_channels(codec, 0x0c, 6);
7859 chipio_set_stream_control(codec, 0x0c, 1);
7860
7861 count = ARRAY_SIZE(ae7_port_set_data);
7862 addr = 0x190030;
7863 for (i = 0; i < count; i++) {
7864 chipio_write_no_mutex(codec, addr, ae7_port_set_data[i]);
7865
7866 /* Addresses are incremented by 4-bytes. */
7867 addr += 0x04;
7868 }
7869
7870 /*
7871 * Port setting always ends with a write of 0x1 to address 0x19042c.
7872 */
7873 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7874
7875 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7876 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
7877 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
7878 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
7879 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
7880 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
7881 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
7882 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
7883
7884 mutex_unlock(&spec->chipio_mutex);
7885 }
7886
ae7_post_dsp_asi_stream_setup(struct hda_codec * codec)7887 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
7888 {
7889 struct ca0132_spec *spec = codec->spec;
7890
7891 mutex_lock(&spec->chipio_mutex);
7892
7893 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7894 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
7895
7896 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7897 chipio_set_stream_channels(codec, 0x0c, 6);
7898 chipio_set_stream_control(codec, 0x0c, 1);
7899
7900 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
7901 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
7902
7903 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7904 chipio_set_stream_channels(codec, 0x18, 6);
7905 chipio_set_stream_control(codec, 0x18, 1);
7906
7907 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7908
7909 mutex_unlock(&spec->chipio_mutex);
7910 }
7911
ae7_post_dsp_pll_setup(struct hda_codec * codec)7912 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
7913 {
7914 static const unsigned int addr[] = {
7915 0x41, 0x45, 0x40, 0x43, 0x51
7916 };
7917 static const unsigned int data[] = {
7918 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
7919 };
7920 unsigned int i;
7921
7922 for (i = 0; i < ARRAY_SIZE(addr); i++) {
7923 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7924 VENDOR_CHIPIO_8051_ADDRESS_LOW, addr[i]);
7925 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7926 VENDOR_CHIPIO_PLL_PMU_WRITE, data[i]);
7927 }
7928 }
7929
ae7_post_dsp_asi_setup_ports(struct hda_codec * codec)7930 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
7931 {
7932 struct ca0132_spec *spec = codec->spec;
7933 static const unsigned int target[] = {
7934 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
7935 };
7936 static const unsigned int data[] = {
7937 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
7938 };
7939 unsigned int i;
7940
7941 mutex_lock(&spec->chipio_mutex);
7942
7943 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7944 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7945 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7946 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7947
7948 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7949 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7950 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7951 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7952
7953 ae7_post_dsp_pll_setup(codec);
7954 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7955
7956 for (i = 0; i < ARRAY_SIZE(target); i++)
7957 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
7958
7959 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
7960 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7961 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7962
7963 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
7964 chipio_set_stream_channels(codec, 0x21, 2);
7965 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
7966
7967 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
7968 /*
7969 * In the 8051's memory, this param is referred to as 'n2sid', which I
7970 * believe is 'node to streamID'. It seems to be a way to assign a
7971 * stream to a given HDA node.
7972 */
7973 chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
7974
7975 chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
7976
7977 /*
7978 * Now, at this point on Windows, an actual stream is setup and
7979 * seemingly sends data to the HDA node 0x09, which is the digital
7980 * audio input node. This is left out here, because obviously I don't
7981 * know what data is being sent. Interestingly, the AE-5 seems to go
7982 * through the motions of getting here and never actually takes this
7983 * step, but the AE-7 does.
7984 */
7985
7986 ca0113_mmio_gpio_set(codec, 0, 1);
7987 ca0113_mmio_gpio_set(codec, 1, 1);
7988
7989 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
7990 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
7991 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7992 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7993
7994 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
7995 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
7996
7997 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7998 chipio_set_stream_channels(codec, 0x18, 6);
7999
8000 /*
8001 * Runs again, this has been repeated a few times, but I'm just
8002 * following what the Windows driver does.
8003 */
8004 ae7_post_dsp_pll_setup(codec);
8005 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8006
8007 mutex_unlock(&spec->chipio_mutex);
8008 }
8009
8010 /*
8011 * The Windows driver has commands that seem to setup ASI, which I believe to
8012 * be some sort of audio serial interface. My current speculation is that it's
8013 * related to communicating with the new DAC.
8014 */
ae7_post_dsp_asi_setup(struct hda_codec * codec)8015 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8016 {
8017 chipio_8051_write_direct(codec, 0x93, 0x10);
8018
8019 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8020 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
8021 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8022 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
8023
8024 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8025 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8026
8027 chipio_set_control_param(codec, 3, 3);
8028 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8029
8030 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8031 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8032 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8033
8034 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8035 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
8036 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8037 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
8038 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8039 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
8040
8041 ae7_post_dsp_pll_setup(codec);
8042 ae7_post_dsp_asi_stream_setup(codec);
8043
8044 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8045 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
8046 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8047 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
8048
8049 ae7_post_dsp_asi_setup_ports(codec);
8050 }
8051
8052 /*
8053 * Setup default parameters for DSP
8054 */
ca0132_setup_defaults(struct hda_codec * codec)8055 static void ca0132_setup_defaults(struct hda_codec *codec)
8056 {
8057 struct ca0132_spec *spec = codec->spec;
8058 unsigned int tmp;
8059 int num_fx;
8060 int idx, i;
8061
8062 if (spec->dsp_state != DSP_DOWNLOADED)
8063 return;
8064
8065 /* out, in effects + voicefx */
8066 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8067 for (idx = 0; idx < num_fx; idx++) {
8068 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8069 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8070 ca0132_effects[idx].reqs[i],
8071 ca0132_effects[idx].def_vals[i]);
8072 }
8073 }
8074
8075 /*remove DSP headroom*/
8076 tmp = FLOAT_ZERO;
8077 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8078
8079 /*set speaker EQ bypass attenuation*/
8080 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8081
8082 /* set AMic1 and AMic2 as mono mic */
8083 tmp = FLOAT_ONE;
8084 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8085 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8086
8087 /* set AMic1 as CrystalVoice input */
8088 tmp = FLOAT_ONE;
8089 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8090
8091 /* set WUH source */
8092 tmp = FLOAT_TWO;
8093 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8094 }
8095
8096 /*
8097 * Setup default parameters for Recon3D/Recon3Di DSP.
8098 */
8099
r3d_setup_defaults(struct hda_codec * codec)8100 static void r3d_setup_defaults(struct hda_codec *codec)
8101 {
8102 struct ca0132_spec *spec = codec->spec;
8103 unsigned int tmp;
8104 int num_fx;
8105 int idx, i;
8106
8107 if (spec->dsp_state != DSP_DOWNLOADED)
8108 return;
8109
8110 ca0132_alt_dsp_scp_startup(codec);
8111 ca0132_alt_init_analog_mics(codec);
8112
8113 /*remove DSP headroom*/
8114 tmp = FLOAT_ZERO;
8115 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8116
8117 /* set WUH source */
8118 tmp = FLOAT_TWO;
8119 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8120 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8121
8122 /* Set speaker source? */
8123 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8124
8125 if (ca0132_quirk(spec) == QUIRK_R3DI)
8126 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8127
8128 /* Disable mute on Center/LFE. */
8129 if (ca0132_quirk(spec) == QUIRK_R3D) {
8130 ca0113_mmio_gpio_set(codec, 2, false);
8131 ca0113_mmio_gpio_set(codec, 4, true);
8132 }
8133
8134 /* Setup effect defaults */
8135 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8136 for (idx = 0; idx < num_fx; idx++) {
8137 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8138 dspio_set_uint_param(codec,
8139 ca0132_effects[idx].mid,
8140 ca0132_effects[idx].reqs[i],
8141 ca0132_effects[idx].def_vals[i]);
8142 }
8143 }
8144 }
8145
8146 /*
8147 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
8148 * than the Chromebook setup.
8149 */
sbz_setup_defaults(struct hda_codec * codec)8150 static void sbz_setup_defaults(struct hda_codec *codec)
8151 {
8152 struct ca0132_spec *spec = codec->spec;
8153 unsigned int tmp;
8154 int num_fx;
8155 int idx, i;
8156
8157 if (spec->dsp_state != DSP_DOWNLOADED)
8158 return;
8159
8160 ca0132_alt_dsp_scp_startup(codec);
8161 ca0132_alt_init_analog_mics(codec);
8162 sbz_connect_streams(codec);
8163 sbz_chipio_startup_data(codec);
8164
8165 chipio_set_stream_control(codec, 0x03, 1);
8166 chipio_set_stream_control(codec, 0x04, 1);
8167
8168 /*
8169 * Sets internal input loopback to off, used to have a switch to
8170 * enable input loopback, but turned out to be way too buggy.
8171 */
8172 tmp = FLOAT_ONE;
8173 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8174 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8175
8176 /*remove DSP headroom*/
8177 tmp = FLOAT_ZERO;
8178 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8179
8180 /* set WUH source */
8181 tmp = FLOAT_TWO;
8182 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8183 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8184
8185 /* Set speaker source? */
8186 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8187
8188 ca0132_alt_dsp_initial_mic_setup(codec);
8189
8190 /* out, in effects + voicefx */
8191 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8192 for (idx = 0; idx < num_fx; idx++) {
8193 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8194 dspio_set_uint_param(codec,
8195 ca0132_effects[idx].mid,
8196 ca0132_effects[idx].reqs[i],
8197 ca0132_effects[idx].def_vals[i]);
8198 }
8199 }
8200
8201 ca0132_alt_init_speaker_tuning(codec);
8202
8203 ca0132_alt_create_dummy_stream(codec);
8204 }
8205
8206 /*
8207 * Setup default parameters for the Sound BlasterX AE-5 DSP.
8208 */
ae5_setup_defaults(struct hda_codec * codec)8209 static void ae5_setup_defaults(struct hda_codec *codec)
8210 {
8211 struct ca0132_spec *spec = codec->spec;
8212 unsigned int tmp;
8213 int num_fx;
8214 int idx, i;
8215
8216 if (spec->dsp_state != DSP_DOWNLOADED)
8217 return;
8218
8219 ca0132_alt_dsp_scp_startup(codec);
8220 ca0132_alt_init_analog_mics(codec);
8221 chipio_set_stream_control(codec, 0x03, 1);
8222 chipio_set_stream_control(codec, 0x04, 1);
8223
8224 /* New, unknown SCP req's */
8225 tmp = FLOAT_ZERO;
8226 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8227 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8228 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8229 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8230
8231 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8232 ca0113_mmio_gpio_set(codec, 0, false);
8233 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8234
8235 /* Internal loopback off */
8236 tmp = FLOAT_ONE;
8237 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8238 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8239
8240 /*remove DSP headroom*/
8241 tmp = FLOAT_ZERO;
8242 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8243
8244 /* set WUH source */
8245 tmp = FLOAT_TWO;
8246 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8247 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8248
8249 /* Set speaker source? */
8250 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8251
8252 ca0132_alt_dsp_initial_mic_setup(codec);
8253 ae5_post_dsp_register_set(codec);
8254 ae5_post_dsp_param_setup(codec);
8255 ae5_post_dsp_pll_setup(codec);
8256 ae5_post_dsp_stream_setup(codec);
8257 ae5_post_dsp_startup_data(codec);
8258
8259 /* out, in effects + voicefx */
8260 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8261 for (idx = 0; idx < num_fx; idx++) {
8262 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8263 dspio_set_uint_param(codec,
8264 ca0132_effects[idx].mid,
8265 ca0132_effects[idx].reqs[i],
8266 ca0132_effects[idx].def_vals[i]);
8267 }
8268 }
8269
8270 ca0132_alt_init_speaker_tuning(codec);
8271
8272 ca0132_alt_create_dummy_stream(codec);
8273 }
8274
8275 /*
8276 * Setup default parameters for the Sound Blaster AE-7 DSP.
8277 */
ae7_setup_defaults(struct hda_codec * codec)8278 static void ae7_setup_defaults(struct hda_codec *codec)
8279 {
8280 struct ca0132_spec *spec = codec->spec;
8281 unsigned int tmp;
8282 int num_fx;
8283 int idx, i;
8284
8285 if (spec->dsp_state != DSP_DOWNLOADED)
8286 return;
8287
8288 ca0132_alt_dsp_scp_startup(codec);
8289 ca0132_alt_init_analog_mics(codec);
8290 ae7_post_dsp_setup_ports(codec);
8291
8292 tmp = FLOAT_ZERO;
8293 dspio_set_uint_param(codec, 0x96,
8294 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
8295 dspio_set_uint_param(codec, 0x96,
8296 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
8297
8298 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8299
8300 /* New, unknown SCP req's */
8301 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8302 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8303
8304 ca0113_mmio_gpio_set(codec, 0, false);
8305
8306 /* Internal loopback off */
8307 tmp = FLOAT_ONE;
8308 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8309 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8310
8311 /*remove DSP headroom*/
8312 tmp = FLOAT_ZERO;
8313 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8314
8315 /* set WUH source */
8316 tmp = FLOAT_TWO;
8317 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8318 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8319
8320 /* Set speaker source? */
8321 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8322 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8323
8324 /*
8325 * This is the second time we've called this, but this is seemingly
8326 * what Windows does.
8327 */
8328 ca0132_alt_init_analog_mics(codec);
8329
8330 ae7_post_dsp_asi_setup(codec);
8331
8332 /*
8333 * Not sure why, but these are both set to 1. They're only set to 0
8334 * upon shutdown.
8335 */
8336 ca0113_mmio_gpio_set(codec, 0, true);
8337 ca0113_mmio_gpio_set(codec, 1, true);
8338
8339 /* Volume control related. */
8340 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8341 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8342 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8343
8344 /* out, in effects + voicefx */
8345 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8346 for (idx = 0; idx < num_fx; idx++) {
8347 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8348 dspio_set_uint_param(codec,
8349 ca0132_effects[idx].mid,
8350 ca0132_effects[idx].reqs[i],
8351 ca0132_effects[idx].def_vals[i]);
8352 }
8353 }
8354
8355 ca0132_alt_init_speaker_tuning(codec);
8356
8357 ca0132_alt_create_dummy_stream(codec);
8358 }
8359
8360 /*
8361 * Initialization of flags in chip
8362 */
ca0132_init_flags(struct hda_codec * codec)8363 static void ca0132_init_flags(struct hda_codec *codec)
8364 {
8365 struct ca0132_spec *spec = codec->spec;
8366
8367 if (ca0132_use_alt_functions(spec)) {
8368 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8369 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8370 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8371 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8372 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8373 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8374 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8375 chipio_set_control_flag(codec,
8376 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8377 chipio_set_control_flag(codec,
8378 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8379 } else {
8380 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8381 chipio_set_control_flag(codec,
8382 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8383 chipio_set_control_flag(codec,
8384 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8385 chipio_set_control_flag(codec,
8386 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8387 chipio_set_control_flag(codec,
8388 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8389 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8390 }
8391 }
8392
8393 /*
8394 * Initialization of parameters in chip
8395 */
ca0132_init_params(struct hda_codec * codec)8396 static void ca0132_init_params(struct hda_codec *codec)
8397 {
8398 struct ca0132_spec *spec = codec->spec;
8399
8400 if (ca0132_use_alt_functions(spec)) {
8401 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8402 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8403 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8404 chipio_set_control_param(codec, 0, 0);
8405 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8406 }
8407
8408 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8409 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8410 }
8411
ca0132_set_dsp_msr(struct hda_codec * codec,bool is96k)8412 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8413 {
8414 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8415 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8416 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8417 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8418 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8419 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8420
8421 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8422 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8423 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8424 }
8425
ca0132_download_dsp_images(struct hda_codec * codec)8426 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8427 {
8428 bool dsp_loaded = false;
8429 struct ca0132_spec *spec = codec->spec;
8430 const struct dsp_image_seg *dsp_os_image;
8431 const struct firmware *fw_entry = NULL;
8432 /*
8433 * Alternate firmwares for different variants. The Recon3Di apparently
8434 * can use the default firmware, but I'll leave the option in case
8435 * it needs it again.
8436 */
8437 switch (ca0132_quirk(spec)) {
8438 case QUIRK_SBZ:
8439 case QUIRK_R3D:
8440 case QUIRK_AE5:
8441 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8442 codec->card->dev) != 0)
8443 codec_dbg(codec, "Desktop firmware not found.");
8444 else
8445 codec_dbg(codec, "Desktop firmware selected.");
8446 break;
8447 case QUIRK_R3DI:
8448 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
8449 codec->card->dev) != 0)
8450 codec_dbg(codec, "Recon3Di alt firmware not detected.");
8451 else
8452 codec_dbg(codec, "Recon3Di firmware selected.");
8453 break;
8454 default:
8455 break;
8456 }
8457 /*
8458 * Use default ctefx.bin if no alt firmware is detected, or if none
8459 * exists for your particular codec.
8460 */
8461 if (!fw_entry) {
8462 codec_dbg(codec, "Default firmware selected.");
8463 if (request_firmware(&fw_entry, EFX_FILE,
8464 codec->card->dev) != 0)
8465 return false;
8466 }
8467
8468 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8469 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8470 codec_err(codec, "ca0132 DSP load image failed\n");
8471 goto exit_download;
8472 }
8473
8474 dsp_loaded = dspload_wait_loaded(codec);
8475
8476 exit_download:
8477 release_firmware(fw_entry);
8478
8479 return dsp_loaded;
8480 }
8481
ca0132_download_dsp(struct hda_codec * codec)8482 static void ca0132_download_dsp(struct hda_codec *codec)
8483 {
8484 struct ca0132_spec *spec = codec->spec;
8485
8486 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
8487 return; /* NOP */
8488 #endif
8489
8490 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8491 return; /* don't retry failures */
8492
8493 chipio_enable_clocks(codec);
8494 if (spec->dsp_state != DSP_DOWNLOADED) {
8495 spec->dsp_state = DSP_DOWNLOADING;
8496
8497 if (!ca0132_download_dsp_images(codec))
8498 spec->dsp_state = DSP_DOWNLOAD_FAILED;
8499 else
8500 spec->dsp_state = DSP_DOWNLOADED;
8501 }
8502
8503 /* For codecs using alt functions, this is already done earlier */
8504 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8505 ca0132_set_dsp_msr(codec, true);
8506 }
8507
ca0132_process_dsp_response(struct hda_codec * codec,struct hda_jack_callback * callback)8508 static void ca0132_process_dsp_response(struct hda_codec *codec,
8509 struct hda_jack_callback *callback)
8510 {
8511 struct ca0132_spec *spec = codec->spec;
8512
8513 codec_dbg(codec, "ca0132_process_dsp_response\n");
8514 snd_hda_power_up_pm(codec);
8515 if (spec->wait_scp) {
8516 if (dspio_get_response_data(codec) >= 0)
8517 spec->wait_scp = 0;
8518 }
8519
8520 dspio_clear_response_queue(codec);
8521 snd_hda_power_down_pm(codec);
8522 }
8523
hp_callback(struct hda_codec * codec,struct hda_jack_callback * cb)8524 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8525 {
8526 struct ca0132_spec *spec = codec->spec;
8527 struct hda_jack_tbl *tbl;
8528
8529 /* Delay enabling the HP amp, to let the mic-detection
8530 * state machine run.
8531 */
8532 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8533 if (tbl)
8534 tbl->block_report = 1;
8535 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8536 }
8537
amic_callback(struct hda_codec * codec,struct hda_jack_callback * cb)8538 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8539 {
8540 struct ca0132_spec *spec = codec->spec;
8541
8542 if (ca0132_use_alt_functions(spec))
8543 ca0132_alt_select_in(codec);
8544 else
8545 ca0132_select_mic(codec);
8546 }
8547
ca0132_init_unsol(struct hda_codec * codec)8548 static void ca0132_init_unsol(struct hda_codec *codec)
8549 {
8550 struct ca0132_spec *spec = codec->spec;
8551 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8552 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8553 amic_callback);
8554 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8555 ca0132_process_dsp_response);
8556 /* Front headphone jack detection */
8557 if (ca0132_use_alt_functions(spec))
8558 snd_hda_jack_detect_enable_callback(codec,
8559 spec->unsol_tag_front_hp, hp_callback);
8560 }
8561
8562 /*
8563 * Verbs tables.
8564 */
8565
8566 /* Sends before DSP download. */
8567 static const struct hda_verb ca0132_base_init_verbs[] = {
8568 /*enable ct extension*/
8569 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8570 {}
8571 };
8572
8573 /* Send at exit. */
8574 static const struct hda_verb ca0132_base_exit_verbs[] = {
8575 /*set afg to D3*/
8576 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8577 /*disable ct extension*/
8578 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8579 {}
8580 };
8581
8582 /* Other verbs tables. Sends after DSP download. */
8583
8584 static const struct hda_verb ca0132_init_verbs0[] = {
8585 /* chip init verbs */
8586 {0x15, 0x70D, 0xF0},
8587 {0x15, 0x70E, 0xFE},
8588 {0x15, 0x707, 0x75},
8589 {0x15, 0x707, 0xD3},
8590 {0x15, 0x707, 0x09},
8591 {0x15, 0x707, 0x53},
8592 {0x15, 0x707, 0xD4},
8593 {0x15, 0x707, 0xEF},
8594 {0x15, 0x707, 0x75},
8595 {0x15, 0x707, 0xD3},
8596 {0x15, 0x707, 0x09},
8597 {0x15, 0x707, 0x02},
8598 {0x15, 0x707, 0x37},
8599 {0x15, 0x707, 0x78},
8600 {0x15, 0x53C, 0xCE},
8601 {0x15, 0x575, 0xC9},
8602 {0x15, 0x53D, 0xCE},
8603 {0x15, 0x5B7, 0xC9},
8604 {0x15, 0x70D, 0xE8},
8605 {0x15, 0x70E, 0xFE},
8606 {0x15, 0x707, 0x02},
8607 {0x15, 0x707, 0x68},
8608 {0x15, 0x707, 0x62},
8609 {0x15, 0x53A, 0xCE},
8610 {0x15, 0x546, 0xC9},
8611 {0x15, 0x53B, 0xCE},
8612 {0x15, 0x5E8, 0xC9},
8613 {}
8614 };
8615
8616 /* Extra init verbs for desktop cards. */
8617 static const struct hda_verb ca0132_init_verbs1[] = {
8618 {0x15, 0x70D, 0x20},
8619 {0x15, 0x70E, 0x19},
8620 {0x15, 0x707, 0x00},
8621 {0x15, 0x539, 0xCE},
8622 {0x15, 0x546, 0xC9},
8623 {0x15, 0x70D, 0xB7},
8624 {0x15, 0x70E, 0x09},
8625 {0x15, 0x707, 0x10},
8626 {0x15, 0x70D, 0xAF},
8627 {0x15, 0x70E, 0x09},
8628 {0x15, 0x707, 0x01},
8629 {0x15, 0x707, 0x05},
8630 {0x15, 0x70D, 0x73},
8631 {0x15, 0x70E, 0x09},
8632 {0x15, 0x707, 0x14},
8633 {0x15, 0x6FF, 0xC4},
8634 {}
8635 };
8636
ca0132_init_chip(struct hda_codec * codec)8637 static void ca0132_init_chip(struct hda_codec *codec)
8638 {
8639 struct ca0132_spec *spec = codec->spec;
8640 int num_fx;
8641 int i;
8642 unsigned int on;
8643
8644 mutex_init(&spec->chipio_mutex);
8645
8646 spec->cur_out_type = SPEAKER_OUT;
8647 if (!ca0132_use_alt_functions(spec))
8648 spec->cur_mic_type = DIGITAL_MIC;
8649 else
8650 spec->cur_mic_type = REAR_MIC;
8651
8652 spec->cur_mic_boost = 0;
8653
8654 for (i = 0; i < VNODES_COUNT; i++) {
8655 spec->vnode_lvol[i] = 0x5a;
8656 spec->vnode_rvol[i] = 0x5a;
8657 spec->vnode_lswitch[i] = 0;
8658 spec->vnode_rswitch[i] = 0;
8659 }
8660
8661 /*
8662 * Default states for effects are in ca0132_effects[].
8663 */
8664 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
8665 for (i = 0; i < num_fx; i++) {
8666 on = (unsigned int)ca0132_effects[i].reqs[0];
8667 spec->effects_switch[i] = on ? 1 : 0;
8668 }
8669 /*
8670 * Sets defaults for the effect slider controls, only for alternative
8671 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8672 */
8673 if (ca0132_use_alt_controls(spec)) {
8674 /* Set speakers to default to full range. */
8675 spec->speaker_range_val[0] = 1;
8676 spec->speaker_range_val[1] = 1;
8677
8678 spec->xbass_xover_freq = 8;
8679 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8680 spec->fx_ctl_val[i] = effect_slider_defaults[i];
8681
8682 spec->bass_redirect_xover_freq = 8;
8683 }
8684
8685 spec->voicefx_val = 0;
8686 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8687 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8688
8689 /*
8690 * The ZxR doesn't have a front panel header, and it's line-in is on
8691 * the daughter board. So, there is no input enum control, and we need
8692 * to make sure that spec->in_enum_val is set properly.
8693 */
8694 if (ca0132_quirk(spec) == QUIRK_ZXR)
8695 spec->in_enum_val = REAR_MIC;
8696
8697 #ifdef ENABLE_TUNING_CONTROLS
8698 ca0132_init_tuning_defaults(codec);
8699 #endif
8700 }
8701
8702 /*
8703 * Recon3Di exit specific commands.
8704 */
8705 /* prevents popping noise on shutdown */
r3di_gpio_shutdown(struct hda_codec * codec)8706 static void r3di_gpio_shutdown(struct hda_codec *codec)
8707 {
8708 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8709 }
8710
8711 /*
8712 * Sound Blaster Z exit specific commands.
8713 */
sbz_region2_exit(struct hda_codec * codec)8714 static void sbz_region2_exit(struct hda_codec *codec)
8715 {
8716 struct ca0132_spec *spec = codec->spec;
8717 unsigned int i;
8718
8719 for (i = 0; i < 4; i++)
8720 writeb(0x0, spec->mem_base + 0x100);
8721 for (i = 0; i < 8; i++)
8722 writeb(0xb3, spec->mem_base + 0x304);
8723
8724 ca0113_mmio_gpio_set(codec, 0, false);
8725 ca0113_mmio_gpio_set(codec, 1, false);
8726 ca0113_mmio_gpio_set(codec, 4, true);
8727 ca0113_mmio_gpio_set(codec, 5, false);
8728 ca0113_mmio_gpio_set(codec, 7, false);
8729 }
8730
sbz_set_pin_ctl_default(struct hda_codec * codec)8731 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8732 {
8733 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8734 unsigned int i;
8735
8736 snd_hda_codec_write(codec, 0x11, 0,
8737 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8738
8739 for (i = 0; i < ARRAY_SIZE(pins); i++)
8740 snd_hda_codec_write(codec, pins[i], 0,
8741 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8742 }
8743
ca0132_clear_unsolicited(struct hda_codec * codec)8744 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8745 {
8746 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8747 unsigned int i;
8748
8749 for (i = 0; i < ARRAY_SIZE(pins); i++) {
8750 snd_hda_codec_write(codec, pins[i], 0,
8751 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8752 }
8753 }
8754
8755 /* On shutdown, sends commands in sets of three */
sbz_gpio_shutdown_commands(struct hda_codec * codec,int dir,int mask,int data)8756 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8757 int mask, int data)
8758 {
8759 if (dir >= 0)
8760 snd_hda_codec_write(codec, 0x01, 0,
8761 AC_VERB_SET_GPIO_DIRECTION, dir);
8762 if (mask >= 0)
8763 snd_hda_codec_write(codec, 0x01, 0,
8764 AC_VERB_SET_GPIO_MASK, mask);
8765
8766 if (data >= 0)
8767 snd_hda_codec_write(codec, 0x01, 0,
8768 AC_VERB_SET_GPIO_DATA, data);
8769 }
8770
zxr_dbpro_power_state_shutdown(struct hda_codec * codec)8771 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8772 {
8773 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8774 unsigned int i;
8775
8776 for (i = 0; i < ARRAY_SIZE(pins); i++)
8777 snd_hda_codec_write(codec, pins[i], 0,
8778 AC_VERB_SET_POWER_STATE, 0x03);
8779 }
8780
sbz_exit_chip(struct hda_codec * codec)8781 static void sbz_exit_chip(struct hda_codec *codec)
8782 {
8783 chipio_set_stream_control(codec, 0x03, 0);
8784 chipio_set_stream_control(codec, 0x04, 0);
8785
8786 /* Mess with GPIO */
8787 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8788 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8789 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8790
8791 chipio_set_stream_control(codec, 0x14, 0);
8792 chipio_set_stream_control(codec, 0x0C, 0);
8793
8794 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8795 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8796
8797 chipio_write(codec, 0x18a020, 0x00000083);
8798
8799 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8800 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8801 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8802
8803 chipio_set_stream_control(codec, 0x0C, 0);
8804
8805 chipio_set_control_param(codec, 0x0D, 0x24);
8806
8807 ca0132_clear_unsolicited(codec);
8808 sbz_set_pin_ctl_default(codec);
8809
8810 snd_hda_codec_write(codec, 0x0B, 0,
8811 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8812
8813 sbz_region2_exit(codec);
8814 }
8815
r3d_exit_chip(struct hda_codec * codec)8816 static void r3d_exit_chip(struct hda_codec *codec)
8817 {
8818 ca0132_clear_unsolicited(codec);
8819 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8820 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8821 }
8822
ae5_exit_chip(struct hda_codec * codec)8823 static void ae5_exit_chip(struct hda_codec *codec)
8824 {
8825 chipio_set_stream_control(codec, 0x03, 0);
8826 chipio_set_stream_control(codec, 0x04, 0);
8827
8828 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8829 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8830 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8831 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8832 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8833 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8834 ca0113_mmio_gpio_set(codec, 0, false);
8835 ca0113_mmio_gpio_set(codec, 1, false);
8836
8837 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8838 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8839
8840 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8841
8842 chipio_set_stream_control(codec, 0x18, 0);
8843 chipio_set_stream_control(codec, 0x0c, 0);
8844
8845 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
8846 }
8847
ae7_exit_chip(struct hda_codec * codec)8848 static void ae7_exit_chip(struct hda_codec *codec)
8849 {
8850 chipio_set_stream_control(codec, 0x18, 0);
8851 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
8852 chipio_set_stream_channels(codec, 0x21, 0);
8853 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
8854 chipio_set_control_param(codec, 0x20, 0x01);
8855
8856 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8857
8858 chipio_set_stream_control(codec, 0x18, 0);
8859 chipio_set_stream_control(codec, 0x0c, 0);
8860
8861 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8862 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
8863 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8864 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8865 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
8866 ca0113_mmio_gpio_set(codec, 0, false);
8867 ca0113_mmio_gpio_set(codec, 1, false);
8868 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8869
8870 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8871 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8872 }
8873
zxr_exit_chip(struct hda_codec * codec)8874 static void zxr_exit_chip(struct hda_codec *codec)
8875 {
8876 chipio_set_stream_control(codec, 0x03, 0);
8877 chipio_set_stream_control(codec, 0x04, 0);
8878 chipio_set_stream_control(codec, 0x14, 0);
8879 chipio_set_stream_control(codec, 0x0C, 0);
8880
8881 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8882 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8883
8884 chipio_write(codec, 0x18a020, 0x00000083);
8885
8886 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8887 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8888
8889 ca0132_clear_unsolicited(codec);
8890 sbz_set_pin_ctl_default(codec);
8891 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8892
8893 ca0113_mmio_gpio_set(codec, 5, false);
8894 ca0113_mmio_gpio_set(codec, 2, false);
8895 ca0113_mmio_gpio_set(codec, 3, false);
8896 ca0113_mmio_gpio_set(codec, 0, false);
8897 ca0113_mmio_gpio_set(codec, 4, true);
8898 ca0113_mmio_gpio_set(codec, 0, true);
8899 ca0113_mmio_gpio_set(codec, 5, true);
8900 ca0113_mmio_gpio_set(codec, 2, false);
8901 ca0113_mmio_gpio_set(codec, 3, false);
8902 }
8903
ca0132_exit_chip(struct hda_codec * codec)8904 static void ca0132_exit_chip(struct hda_codec *codec)
8905 {
8906 /* put any chip cleanup stuffs here. */
8907
8908 if (dspload_is_loaded(codec))
8909 dsp_reset(codec);
8910 }
8911
8912 /*
8913 * This fixes a problem that was hard to reproduce. Very rarely, I would
8914 * boot up, and there would be no sound, but the DSP indicated it had loaded
8915 * properly. I did a few memory dumps to see if anything was different, and
8916 * there were a few areas of memory uninitialized with a1a2a3a4. This function
8917 * checks if those areas are uninitialized, and if they are, it'll attempt to
8918 * reload the card 3 times. Usually it fixes by the second.
8919 */
sbz_dsp_startup_check(struct hda_codec * codec)8920 static void sbz_dsp_startup_check(struct hda_codec *codec)
8921 {
8922 struct ca0132_spec *spec = codec->spec;
8923 unsigned int dsp_data_check[4];
8924 unsigned int cur_address = 0x390;
8925 unsigned int i;
8926 unsigned int failure = 0;
8927 unsigned int reload = 3;
8928
8929 if (spec->startup_check_entered)
8930 return;
8931
8932 spec->startup_check_entered = true;
8933
8934 for (i = 0; i < 4; i++) {
8935 chipio_read(codec, cur_address, &dsp_data_check[i]);
8936 cur_address += 0x4;
8937 }
8938 for (i = 0; i < 4; i++) {
8939 if (dsp_data_check[i] == 0xa1a2a3a4)
8940 failure = 1;
8941 }
8942
8943 codec_dbg(codec, "Startup Check: %d ", failure);
8944 if (failure)
8945 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
8946 /*
8947 * While the failure condition is true, and we haven't reached our
8948 * three reload limit, continue trying to reload the driver and
8949 * fix the issue.
8950 */
8951 while (failure && (reload != 0)) {
8952 codec_info(codec, "Reloading... Tries left: %d", reload);
8953 sbz_exit_chip(codec);
8954 spec->dsp_state = DSP_DOWNLOAD_INIT;
8955 codec->patch_ops.init(codec);
8956 failure = 0;
8957 for (i = 0; i < 4; i++) {
8958 chipio_read(codec, cur_address, &dsp_data_check[i]);
8959 cur_address += 0x4;
8960 }
8961 for (i = 0; i < 4; i++) {
8962 if (dsp_data_check[i] == 0xa1a2a3a4)
8963 failure = 1;
8964 }
8965 reload--;
8966 }
8967
8968 if (!failure && reload < 3)
8969 codec_info(codec, "DSP fixed.");
8970
8971 if (!failure)
8972 return;
8973
8974 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
8975 }
8976
8977 /*
8978 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
8979 * extra precision for decibel values. If you had the dB value in floating point
8980 * you would take the value after the decimal point, multiply by 64, and divide
8981 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
8982 * implement fixed point or floating point dB volumes. For now, I'll set them
8983 * to 0 just incase a value has lingered from a boot into Windows.
8984 */
ca0132_alt_vol_setup(struct hda_codec * codec)8985 static void ca0132_alt_vol_setup(struct hda_codec *codec)
8986 {
8987 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
8988 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
8989 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
8990 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
8991 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
8992 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
8993 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
8994 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
8995 }
8996
8997 /*
8998 * Extra commands that don't really fit anywhere else.
8999 */
sbz_pre_dsp_setup(struct hda_codec * codec)9000 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9001 {
9002 struct ca0132_spec *spec = codec->spec;
9003
9004 writel(0x00820680, spec->mem_base + 0x01C);
9005 writel(0x00820680, spec->mem_base + 0x01C);
9006
9007 chipio_write(codec, 0x18b0a4, 0x000000c2);
9008
9009 snd_hda_codec_write(codec, 0x11, 0,
9010 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9011 }
9012
r3d_pre_dsp_setup(struct hda_codec * codec)9013 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9014 {
9015 chipio_write(codec, 0x18b0a4, 0x000000c2);
9016
9017 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9018 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
9019 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9020 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
9021 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9022 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
9023
9024 snd_hda_codec_write(codec, 0x11, 0,
9025 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9026 }
9027
r3di_pre_dsp_setup(struct hda_codec * codec)9028 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9029 {
9030 chipio_write(codec, 0x18b0a4, 0x000000c2);
9031
9032 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9033 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
9034 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9035 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
9036 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9037 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
9038
9039 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9040 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
9041 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9042 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
9043 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9044 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
9045 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9046 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
9047
9048 snd_hda_codec_write(codec, 0x11, 0,
9049 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9050 }
9051
9052 /*
9053 * These are sent before the DSP is downloaded. Not sure
9054 * what they do, or if they're necessary. Could possibly
9055 * be removed. Figure they're better to leave in.
9056 */
9057 static const unsigned int ca0113_mmio_init_address_sbz[] = {
9058 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9059 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9060 };
9061
9062 static const unsigned int ca0113_mmio_init_data_sbz[] = {
9063 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9064 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9065 0x000000c1, 0x00000080
9066 };
9067
9068 static const unsigned int ca0113_mmio_init_data_zxr[] = {
9069 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9070 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9071 0x000000c1, 0x00000080
9072 };
9073
9074 static const unsigned int ca0113_mmio_init_address_ae5[] = {
9075 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9076 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9077 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9078 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9079 };
9080
9081 static const unsigned int ca0113_mmio_init_data_ae5[] = {
9082 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9083 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9084 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9085 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9086 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9087 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9088 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9089 0x00000080, 0x00880680
9090 };
9091
ca0132_mmio_init_sbz(struct hda_codec * codec)9092 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9093 {
9094 struct ca0132_spec *spec = codec->spec;
9095 unsigned int tmp[2], i, count, cur_addr;
9096 const unsigned int *addr, *data;
9097
9098 addr = ca0113_mmio_init_address_sbz;
9099 for (i = 0; i < 3; i++)
9100 writel(0x00000000, spec->mem_base + addr[i]);
9101
9102 cur_addr = i;
9103 switch (ca0132_quirk(spec)) {
9104 case QUIRK_ZXR:
9105 tmp[0] = 0x00880480;
9106 tmp[1] = 0x00000080;
9107 break;
9108 case QUIRK_SBZ:
9109 tmp[0] = 0x00820680;
9110 tmp[1] = 0x00000083;
9111 break;
9112 case QUIRK_R3D:
9113 tmp[0] = 0x00880680;
9114 tmp[1] = 0x00000083;
9115 break;
9116 default:
9117 tmp[0] = 0x00000000;
9118 tmp[1] = 0x00000000;
9119 break;
9120 }
9121
9122 for (i = 0; i < 2; i++)
9123 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9124
9125 cur_addr += i;
9126
9127 switch (ca0132_quirk(spec)) {
9128 case QUIRK_ZXR:
9129 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
9130 data = ca0113_mmio_init_data_zxr;
9131 break;
9132 default:
9133 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
9134 data = ca0113_mmio_init_data_sbz;
9135 break;
9136 }
9137
9138 for (i = 0; i < count; i++)
9139 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9140 }
9141
ca0132_mmio_init_ae5(struct hda_codec * codec)9142 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9143 {
9144 struct ca0132_spec *spec = codec->spec;
9145 const unsigned int *addr, *data;
9146 unsigned int i, count;
9147
9148 addr = ca0113_mmio_init_address_ae5;
9149 data = ca0113_mmio_init_data_ae5;
9150 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
9151
9152 if (ca0132_quirk(spec) == QUIRK_AE7) {
9153 writel(0x00000680, spec->mem_base + 0x1c);
9154 writel(0x00880680, spec->mem_base + 0x1c);
9155 }
9156
9157 for (i = 0; i < count; i++) {
9158 /*
9159 * AE-7 shares all writes with the AE-5, except that it writes
9160 * a different value to 0x20c.
9161 */
9162 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
9163 writel(0x00800001, spec->mem_base + addr[i]);
9164 continue;
9165 }
9166
9167 writel(data[i], spec->mem_base + addr[i]);
9168 }
9169
9170 if (ca0132_quirk(spec) == QUIRK_AE5)
9171 writel(0x00880680, spec->mem_base + 0x1c);
9172 }
9173
ca0132_mmio_init(struct hda_codec * codec)9174 static void ca0132_mmio_init(struct hda_codec *codec)
9175 {
9176 struct ca0132_spec *spec = codec->spec;
9177
9178 switch (ca0132_quirk(spec)) {
9179 case QUIRK_R3D:
9180 case QUIRK_SBZ:
9181 case QUIRK_ZXR:
9182 ca0132_mmio_init_sbz(codec);
9183 break;
9184 case QUIRK_AE5:
9185 ca0132_mmio_init_ae5(codec);
9186 break;
9187 default:
9188 break;
9189 }
9190 }
9191
9192 static const unsigned int ca0132_ae5_register_set_addresses[] = {
9193 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9194 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9195 };
9196
9197 static const unsigned char ca0132_ae5_register_set_data[] = {
9198 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9199 0x01, 0x6b, 0x57
9200 };
9201
9202 /*
9203 * This function writes to some SFR's, does some region2 writes, and then
9204 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9205 * what it does.
9206 */
ae5_register_set(struct hda_codec * codec)9207 static void ae5_register_set(struct hda_codec *codec)
9208 {
9209 struct ca0132_spec *spec = codec->spec;
9210 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
9211 const unsigned int *addr = ca0132_ae5_register_set_addresses;
9212 const unsigned char *data = ca0132_ae5_register_set_data;
9213 unsigned int i, cur_addr;
9214 unsigned char tmp[3];
9215
9216 if (ca0132_quirk(spec) == QUIRK_AE7) {
9217 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9218 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
9219 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9220 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
9221 }
9222
9223 chipio_8051_write_direct(codec, 0x93, 0x10);
9224 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9225 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
9226 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9227 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
9228
9229 if (ca0132_quirk(spec) == QUIRK_AE7) {
9230 tmp[0] = 0x03;
9231 tmp[1] = 0x03;
9232 tmp[2] = 0x07;
9233 } else {
9234 tmp[0] = 0x0f;
9235 tmp[1] = 0x0f;
9236 tmp[2] = 0x0f;
9237 }
9238
9239 for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9240 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9241
9242 /*
9243 * First writes are in single bytes, final are in 4 bytes. So, we use
9244 * writeb, then writel.
9245 */
9246 for (i = 0; cur_addr < 12; i++, cur_addr++)
9247 writeb(data[i], spec->mem_base + addr[cur_addr]);
9248
9249 for (; cur_addr < count; i++, cur_addr++)
9250 writel(data[i], spec->mem_base + addr[cur_addr]);
9251
9252 writel(0x00800001, spec->mem_base + 0x20c);
9253
9254 if (ca0132_quirk(spec) == QUIRK_AE7) {
9255 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9256 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9257 } else {
9258 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9259 }
9260
9261 chipio_8051_write_direct(codec, 0x90, 0x00);
9262 chipio_8051_write_direct(codec, 0x90, 0x10);
9263
9264 if (ca0132_quirk(spec) == QUIRK_AE5)
9265 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9266
9267 chipio_write(codec, 0x18b0a4, 0x000000c2);
9268
9269 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
9270 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
9271 }
9272
9273 /*
9274 * Extra init functions for alternative ca0132 codecs. Done
9275 * here so they don't clutter up the main ca0132_init function
9276 * anymore than they have to.
9277 */
ca0132_alt_init(struct hda_codec * codec)9278 static void ca0132_alt_init(struct hda_codec *codec)
9279 {
9280 struct ca0132_spec *spec = codec->spec;
9281
9282 ca0132_alt_vol_setup(codec);
9283
9284 switch (ca0132_quirk(spec)) {
9285 case QUIRK_SBZ:
9286 codec_dbg(codec, "SBZ alt_init");
9287 ca0132_gpio_init(codec);
9288 sbz_pre_dsp_setup(codec);
9289 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9290 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9291 break;
9292 case QUIRK_R3DI:
9293 codec_dbg(codec, "R3DI alt_init");
9294 ca0132_gpio_init(codec);
9295 ca0132_gpio_setup(codec);
9296 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9297 r3di_pre_dsp_setup(codec);
9298 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9299 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9300 break;
9301 case QUIRK_R3D:
9302 r3d_pre_dsp_setup(codec);
9303 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9304 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9305 break;
9306 case QUIRK_AE5:
9307 ca0132_gpio_init(codec);
9308 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9309 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
9310 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9311 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
9312 chipio_write(codec, 0x18b030, 0x00000020);
9313 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9314 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9315 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9316 break;
9317 case QUIRK_AE7:
9318 ca0132_gpio_init(codec);
9319 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9320 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
9321 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9322 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
9323 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9324 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9325 chipio_write(codec, 0x18b008, 0x000000f8);
9326 chipio_write(codec, 0x18b008, 0x000000f0);
9327 chipio_write(codec, 0x18b030, 0x00000020);
9328 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9329 break;
9330 case QUIRK_ZXR:
9331 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9332 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9333 break;
9334 default:
9335 break;
9336 }
9337 }
9338
ca0132_init(struct hda_codec * codec)9339 static int ca0132_init(struct hda_codec *codec)
9340 {
9341 struct ca0132_spec *spec = codec->spec;
9342 struct auto_pin_cfg *cfg = &spec->autocfg;
9343 int i;
9344 bool dsp_loaded;
9345
9346 /*
9347 * If the DSP is already downloaded, and init has been entered again,
9348 * there's only two reasons for it. One, the codec has awaken from a
9349 * suspended state, and in that case dspload_is_loaded will return
9350 * false, and the init will be ran again. The other reason it gets
9351 * re entered is on startup for some reason it triggers a suspend and
9352 * resume state. In this case, it will check if the DSP is downloaded,
9353 * and not run the init function again. For codecs using alt_functions,
9354 * it will check if the DSP is loaded properly.
9355 */
9356 if (spec->dsp_state == DSP_DOWNLOADED) {
9357 dsp_loaded = dspload_is_loaded(codec);
9358 if (!dsp_loaded) {
9359 spec->dsp_reload = true;
9360 spec->dsp_state = DSP_DOWNLOAD_INIT;
9361 } else {
9362 if (ca0132_quirk(spec) == QUIRK_SBZ)
9363 sbz_dsp_startup_check(codec);
9364 return 0;
9365 }
9366 }
9367
9368 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9369 spec->dsp_state = DSP_DOWNLOAD_INIT;
9370 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9371
9372 if (ca0132_use_pci_mmio(spec))
9373 ca0132_mmio_init(codec);
9374
9375 snd_hda_power_up_pm(codec);
9376
9377 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7)
9378 ae5_register_set(codec);
9379
9380 ca0132_init_unsol(codec);
9381 ca0132_init_params(codec);
9382 ca0132_init_flags(codec);
9383
9384 snd_hda_sequence_write(codec, spec->base_init_verbs);
9385
9386 if (ca0132_use_alt_functions(spec))
9387 ca0132_alt_init(codec);
9388
9389 ca0132_download_dsp(codec);
9390
9391 ca0132_refresh_widget_caps(codec);
9392
9393 switch (ca0132_quirk(spec)) {
9394 case QUIRK_R3DI:
9395 case QUIRK_R3D:
9396 r3d_setup_defaults(codec);
9397 break;
9398 case QUIRK_SBZ:
9399 case QUIRK_ZXR:
9400 sbz_setup_defaults(codec);
9401 break;
9402 case QUIRK_AE5:
9403 ae5_setup_defaults(codec);
9404 break;
9405 case QUIRK_AE7:
9406 ae7_setup_defaults(codec);
9407 break;
9408 default:
9409 ca0132_setup_defaults(codec);
9410 ca0132_init_analog_mic2(codec);
9411 ca0132_init_dmic(codec);
9412 break;
9413 }
9414
9415 for (i = 0; i < spec->num_outputs; i++)
9416 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9417
9418 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9419
9420 for (i = 0; i < spec->num_inputs; i++)
9421 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9422
9423 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9424
9425 if (!ca0132_use_alt_functions(spec)) {
9426 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9427 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9428 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9429 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9430 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9431 }
9432
9433 if (ca0132_quirk(spec) == QUIRK_SBZ)
9434 ca0132_gpio_setup(codec);
9435
9436 snd_hda_sequence_write(codec, spec->spec_init_verbs);
9437 if (ca0132_use_alt_functions(spec)) {
9438 ca0132_alt_select_out(codec);
9439 ca0132_alt_select_in(codec);
9440 } else {
9441 ca0132_select_out(codec);
9442 ca0132_select_mic(codec);
9443 }
9444
9445 snd_hda_jack_report_sync(codec);
9446
9447 /*
9448 * Re set the PlayEnhancement switch on a resume event, because the
9449 * controls will not be reloaded.
9450 */
9451 if (spec->dsp_reload) {
9452 spec->dsp_reload = false;
9453 ca0132_pe_switch_set(codec);
9454 }
9455
9456 snd_hda_power_down_pm(codec);
9457
9458 return 0;
9459 }
9460
dbpro_init(struct hda_codec * codec)9461 static int dbpro_init(struct hda_codec *codec)
9462 {
9463 struct ca0132_spec *spec = codec->spec;
9464 struct auto_pin_cfg *cfg = &spec->autocfg;
9465 unsigned int i;
9466
9467 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9468 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9469
9470 for (i = 0; i < spec->num_inputs; i++)
9471 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9472
9473 return 0;
9474 }
9475
ca0132_free(struct hda_codec * codec)9476 static void ca0132_free(struct hda_codec *codec)
9477 {
9478 struct ca0132_spec *spec = codec->spec;
9479
9480 cancel_delayed_work_sync(&spec->unsol_hp_work);
9481 snd_hda_power_up(codec);
9482 switch (ca0132_quirk(spec)) {
9483 case QUIRK_SBZ:
9484 sbz_exit_chip(codec);
9485 break;
9486 case QUIRK_ZXR:
9487 zxr_exit_chip(codec);
9488 break;
9489 case QUIRK_R3D:
9490 r3d_exit_chip(codec);
9491 break;
9492 case QUIRK_AE5:
9493 ae5_exit_chip(codec);
9494 break;
9495 case QUIRK_AE7:
9496 ae7_exit_chip(codec);
9497 break;
9498 case QUIRK_R3DI:
9499 r3di_gpio_shutdown(codec);
9500 break;
9501 default:
9502 break;
9503 }
9504
9505 snd_hda_sequence_write(codec, spec->base_exit_verbs);
9506 ca0132_exit_chip(codec);
9507
9508 snd_hda_power_down(codec);
9509 #ifdef CONFIG_PCI
9510 if (spec->mem_base)
9511 pci_iounmap(codec->bus->pci, spec->mem_base);
9512 #endif
9513 kfree(spec->spec_init_verbs);
9514 kfree(codec->spec);
9515 }
9516
dbpro_free(struct hda_codec * codec)9517 static void dbpro_free(struct hda_codec *codec)
9518 {
9519 struct ca0132_spec *spec = codec->spec;
9520
9521 zxr_dbpro_power_state_shutdown(codec);
9522
9523 kfree(spec->spec_init_verbs);
9524 kfree(codec->spec);
9525 }
9526
ca0132_reboot_notify(struct hda_codec * codec)9527 static void ca0132_reboot_notify(struct hda_codec *codec)
9528 {
9529 codec->patch_ops.free(codec);
9530 }
9531
9532 #ifdef CONFIG_PM
ca0132_suspend(struct hda_codec * codec)9533 static int ca0132_suspend(struct hda_codec *codec)
9534 {
9535 struct ca0132_spec *spec = codec->spec;
9536
9537 cancel_delayed_work_sync(&spec->unsol_hp_work);
9538 return 0;
9539 }
9540 #endif
9541
9542 static const struct hda_codec_ops ca0132_patch_ops = {
9543 .build_controls = ca0132_build_controls,
9544 .build_pcms = ca0132_build_pcms,
9545 .init = ca0132_init,
9546 .free = ca0132_free,
9547 .unsol_event = snd_hda_jack_unsol_event,
9548 #ifdef CONFIG_PM
9549 .suspend = ca0132_suspend,
9550 #endif
9551 .reboot_notify = ca0132_reboot_notify,
9552 };
9553
9554 static const struct hda_codec_ops dbpro_patch_ops = {
9555 .build_controls = dbpro_build_controls,
9556 .build_pcms = dbpro_build_pcms,
9557 .init = dbpro_init,
9558 .free = dbpro_free,
9559 };
9560
ca0132_config(struct hda_codec * codec)9561 static void ca0132_config(struct hda_codec *codec)
9562 {
9563 struct ca0132_spec *spec = codec->spec;
9564
9565 spec->dacs[0] = 0x2;
9566 spec->dacs[1] = 0x3;
9567 spec->dacs[2] = 0x4;
9568
9569 spec->multiout.dac_nids = spec->dacs;
9570 spec->multiout.num_dacs = 3;
9571
9572 if (!ca0132_use_alt_functions(spec))
9573 spec->multiout.max_channels = 2;
9574 else
9575 spec->multiout.max_channels = 6;
9576
9577 switch (ca0132_quirk(spec)) {
9578 case QUIRK_ALIENWARE:
9579 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9580 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9581 break;
9582 case QUIRK_SBZ:
9583 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9584 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9585 break;
9586 case QUIRK_ZXR:
9587 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9588 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9589 break;
9590 case QUIRK_R3D:
9591 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9592 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9593 break;
9594 case QUIRK_R3DI:
9595 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9596 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9597 break;
9598 case QUIRK_AE5:
9599 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9600 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9601 break;
9602 case QUIRK_AE7:
9603 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9604 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9605 break;
9606 default:
9607 break;
9608 }
9609
9610 switch (ca0132_quirk(spec)) {
9611 case QUIRK_ALIENWARE:
9612 spec->num_outputs = 2;
9613 spec->out_pins[0] = 0x0b; /* speaker out */
9614 spec->out_pins[1] = 0x0f;
9615 spec->shared_out_nid = 0x2;
9616 spec->unsol_tag_hp = 0x0f;
9617
9618 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9619 spec->adcs[1] = 0x8; /* analog mic2 */
9620 spec->adcs[2] = 0xa; /* what u hear */
9621
9622 spec->num_inputs = 3;
9623 spec->input_pins[0] = 0x12;
9624 spec->input_pins[1] = 0x11;
9625 spec->input_pins[2] = 0x13;
9626 spec->shared_mic_nid = 0x7;
9627 spec->unsol_tag_amic1 = 0x11;
9628 break;
9629 case QUIRK_SBZ:
9630 case QUIRK_R3D:
9631 spec->num_outputs = 2;
9632 spec->out_pins[0] = 0x0B; /* Line out */
9633 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9634 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9635 spec->out_pins[3] = 0x11; /* Rear surround */
9636 spec->shared_out_nid = 0x2;
9637 spec->unsol_tag_hp = spec->out_pins[1];
9638 spec->unsol_tag_front_hp = spec->out_pins[2];
9639
9640 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9641 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9642 spec->adcs[2] = 0xa; /* what u hear */
9643
9644 spec->num_inputs = 2;
9645 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9646 spec->input_pins[1] = 0x13; /* What U Hear */
9647 spec->shared_mic_nid = 0x7;
9648 spec->unsol_tag_amic1 = spec->input_pins[0];
9649
9650 /* SPDIF I/O */
9651 spec->dig_out = 0x05;
9652 spec->multiout.dig_out_nid = spec->dig_out;
9653 spec->dig_in = 0x09;
9654 break;
9655 case QUIRK_ZXR:
9656 spec->num_outputs = 2;
9657 spec->out_pins[0] = 0x0B; /* Line out */
9658 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9659 spec->out_pins[2] = 0x10; /* Center/LFE */
9660 spec->out_pins[3] = 0x11; /* Rear surround */
9661 spec->shared_out_nid = 0x2;
9662 spec->unsol_tag_hp = spec->out_pins[1];
9663 spec->unsol_tag_front_hp = spec->out_pins[2];
9664
9665 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9666 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9667 spec->adcs[2] = 0xa; /* what u hear */
9668
9669 spec->num_inputs = 2;
9670 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9671 spec->input_pins[1] = 0x13; /* What U Hear */
9672 spec->shared_mic_nid = 0x7;
9673 spec->unsol_tag_amic1 = spec->input_pins[0];
9674 break;
9675 case QUIRK_ZXR_DBPRO:
9676 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9677
9678 spec->num_inputs = 1;
9679 spec->input_pins[0] = 0x11; /* RCA Line-in */
9680
9681 spec->dig_out = 0x05;
9682 spec->multiout.dig_out_nid = spec->dig_out;
9683
9684 spec->dig_in = 0x09;
9685 break;
9686 case QUIRK_AE5:
9687 case QUIRK_AE7:
9688 spec->num_outputs = 2;
9689 spec->out_pins[0] = 0x0B; /* Line out */
9690 spec->out_pins[1] = 0x11; /* Rear headphone out */
9691 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9692 spec->out_pins[3] = 0x0F; /* Rear surround */
9693 spec->shared_out_nid = 0x2;
9694 spec->unsol_tag_hp = spec->out_pins[1];
9695 spec->unsol_tag_front_hp = spec->out_pins[2];
9696
9697 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9698 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9699 spec->adcs[2] = 0xa; /* what u hear */
9700
9701 spec->num_inputs = 2;
9702 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9703 spec->input_pins[1] = 0x13; /* What U Hear */
9704 spec->shared_mic_nid = 0x7;
9705 spec->unsol_tag_amic1 = spec->input_pins[0];
9706
9707 /* SPDIF I/O */
9708 spec->dig_out = 0x05;
9709 spec->multiout.dig_out_nid = spec->dig_out;
9710 break;
9711 case QUIRK_R3DI:
9712 spec->num_outputs = 2;
9713 spec->out_pins[0] = 0x0B; /* Line out */
9714 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9715 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9716 spec->out_pins[3] = 0x11; /* Rear surround */
9717 spec->shared_out_nid = 0x2;
9718 spec->unsol_tag_hp = spec->out_pins[1];
9719 spec->unsol_tag_front_hp = spec->out_pins[2];
9720
9721 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9722 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9723 spec->adcs[2] = 0x0a; /* what u hear */
9724
9725 spec->num_inputs = 2;
9726 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9727 spec->input_pins[1] = 0x13; /* What U Hear */
9728 spec->shared_mic_nid = 0x7;
9729 spec->unsol_tag_amic1 = spec->input_pins[0];
9730
9731 /* SPDIF I/O */
9732 spec->dig_out = 0x05;
9733 spec->multiout.dig_out_nid = spec->dig_out;
9734 break;
9735 default:
9736 spec->num_outputs = 2;
9737 spec->out_pins[0] = 0x0b; /* speaker out */
9738 spec->out_pins[1] = 0x10; /* headphone out */
9739 spec->shared_out_nid = 0x2;
9740 spec->unsol_tag_hp = spec->out_pins[1];
9741
9742 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9743 spec->adcs[1] = 0x8; /* analog mic2 */
9744 spec->adcs[2] = 0xa; /* what u hear */
9745
9746 spec->num_inputs = 3;
9747 spec->input_pins[0] = 0x12;
9748 spec->input_pins[1] = 0x11;
9749 spec->input_pins[2] = 0x13;
9750 spec->shared_mic_nid = 0x7;
9751 spec->unsol_tag_amic1 = spec->input_pins[0];
9752
9753 /* SPDIF I/O */
9754 spec->dig_out = 0x05;
9755 spec->multiout.dig_out_nid = spec->dig_out;
9756 spec->dig_in = 0x09;
9757 break;
9758 }
9759 }
9760
ca0132_prepare_verbs(struct hda_codec * codec)9761 static int ca0132_prepare_verbs(struct hda_codec *codec)
9762 {
9763 /* Verbs + terminator (an empty element) */
9764 #define NUM_SPEC_VERBS 2
9765 struct ca0132_spec *spec = codec->spec;
9766
9767 spec->chip_init_verbs = ca0132_init_verbs0;
9768 /*
9769 * Since desktop cards use pci_mmio, this can be used to determine
9770 * whether or not to use these verbs instead of a separate bool.
9771 */
9772 if (ca0132_use_pci_mmio(spec))
9773 spec->desktop_init_verbs = ca0132_init_verbs1;
9774 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9775 sizeof(struct hda_verb),
9776 GFP_KERNEL);
9777 if (!spec->spec_init_verbs)
9778 return -ENOMEM;
9779
9780 /* config EAPD */
9781 spec->spec_init_verbs[0].nid = 0x0b;
9782 spec->spec_init_verbs[0].param = 0x78D;
9783 spec->spec_init_verbs[0].verb = 0x00;
9784
9785 /* Previously commented configuration */
9786 /*
9787 spec->spec_init_verbs[2].nid = 0x0b;
9788 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9789 spec->spec_init_verbs[2].verb = 0x02;
9790
9791 spec->spec_init_verbs[3].nid = 0x10;
9792 spec->spec_init_verbs[3].param = 0x78D;
9793 spec->spec_init_verbs[3].verb = 0x02;
9794
9795 spec->spec_init_verbs[4].nid = 0x10;
9796 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9797 spec->spec_init_verbs[4].verb = 0x02;
9798 */
9799
9800 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9801 return 0;
9802 }
9803
9804 /*
9805 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
9806 * Sound Blaster Z cards. However, they have different HDA codec subsystem
9807 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
9808 * daughter boards ID.
9809 */
sbz_detect_quirk(struct hda_codec * codec)9810 static void sbz_detect_quirk(struct hda_codec *codec)
9811 {
9812 struct ca0132_spec *spec = codec->spec;
9813
9814 switch (codec->core.subsystem_id) {
9815 case 0x11020033:
9816 spec->quirk = QUIRK_ZXR;
9817 break;
9818 case 0x1102003f:
9819 spec->quirk = QUIRK_ZXR_DBPRO;
9820 break;
9821 default:
9822 spec->quirk = QUIRK_SBZ;
9823 break;
9824 }
9825 }
9826
patch_ca0132(struct hda_codec * codec)9827 static int patch_ca0132(struct hda_codec *codec)
9828 {
9829 struct ca0132_spec *spec;
9830 int err;
9831 const struct snd_pci_quirk *quirk;
9832
9833 codec_dbg(codec, "patch_ca0132\n");
9834
9835 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
9836 if (!spec)
9837 return -ENOMEM;
9838 codec->spec = spec;
9839 spec->codec = codec;
9840
9841 /* Detect codec quirk */
9842 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
9843 if (quirk)
9844 spec->quirk = quirk->value;
9845 else
9846 spec->quirk = QUIRK_NONE;
9847 if (ca0132_quirk(spec) == QUIRK_SBZ)
9848 sbz_detect_quirk(codec);
9849
9850 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
9851 codec->patch_ops = dbpro_patch_ops;
9852 else
9853 codec->patch_ops = ca0132_patch_ops;
9854
9855 codec->pcm_format_first = 1;
9856 codec->no_sticky_stream = 1;
9857
9858
9859 spec->dsp_state = DSP_DOWNLOAD_INIT;
9860 spec->num_mixers = 1;
9861
9862 /* Set which mixers each quirk uses. */
9863 switch (ca0132_quirk(spec)) {
9864 case QUIRK_SBZ:
9865 spec->mixers[0] = desktop_mixer;
9866 snd_hda_codec_set_name(codec, "Sound Blaster Z");
9867 break;
9868 case QUIRK_ZXR:
9869 spec->mixers[0] = desktop_mixer;
9870 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
9871 break;
9872 case QUIRK_ZXR_DBPRO:
9873 break;
9874 case QUIRK_R3D:
9875 spec->mixers[0] = desktop_mixer;
9876 snd_hda_codec_set_name(codec, "Recon3D");
9877 break;
9878 case QUIRK_R3DI:
9879 spec->mixers[0] = r3di_mixer;
9880 snd_hda_codec_set_name(codec, "Recon3Di");
9881 break;
9882 case QUIRK_AE5:
9883 spec->mixers[0] = desktop_mixer;
9884 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
9885 break;
9886 case QUIRK_AE7:
9887 spec->mixers[0] = desktop_mixer;
9888 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
9889 break;
9890 default:
9891 spec->mixers[0] = ca0132_mixer;
9892 break;
9893 }
9894
9895 /* Setup whether or not to use alt functions/controls/pci_mmio */
9896 switch (ca0132_quirk(spec)) {
9897 case QUIRK_SBZ:
9898 case QUIRK_R3D:
9899 case QUIRK_AE5:
9900 case QUIRK_AE7:
9901 case QUIRK_ZXR:
9902 spec->use_alt_controls = true;
9903 spec->use_alt_functions = true;
9904 spec->use_pci_mmio = true;
9905 break;
9906 case QUIRK_R3DI:
9907 spec->use_alt_controls = true;
9908 spec->use_alt_functions = true;
9909 spec->use_pci_mmio = false;
9910 break;
9911 default:
9912 spec->use_alt_controls = false;
9913 spec->use_alt_functions = false;
9914 spec->use_pci_mmio = false;
9915 break;
9916 }
9917
9918 #ifdef CONFIG_PCI
9919 if (spec->use_pci_mmio) {
9920 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
9921 if (spec->mem_base == NULL) {
9922 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
9923 spec->quirk = QUIRK_NONE;
9924 }
9925 }
9926 #endif
9927
9928 spec->base_init_verbs = ca0132_base_init_verbs;
9929 spec->base_exit_verbs = ca0132_base_exit_verbs;
9930
9931 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
9932
9933 ca0132_init_chip(codec);
9934
9935 ca0132_config(codec);
9936
9937 err = ca0132_prepare_verbs(codec);
9938 if (err < 0)
9939 goto error;
9940
9941 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
9942 if (err < 0)
9943 goto error;
9944
9945 return 0;
9946
9947 error:
9948 ca0132_free(codec);
9949 return err;
9950 }
9951
9952 /*
9953 * patch entries
9954 */
9955 static const struct hda_device_id snd_hda_id_ca0132[] = {
9956 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
9957 {} /* terminator */
9958 };
9959 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
9960
9961 MODULE_LICENSE("GPL");
9962 MODULE_DESCRIPTION("Creative Sound Core3D codec");
9963
9964 static struct hda_codec_driver ca0132_driver = {
9965 .id = snd_hda_id_ca0132,
9966 };
9967
9968 module_hda_codec_driver(ca0132_driver);
9969