1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/module.h>
25
26 #include <drm/drm_drv.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_ras.h"
30 #include "vi.h"
31 #include "soc15.h"
32 #include "nv.h"
33
34 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \
35 do { \
36 vf2pf_info->ucode_info[ucode].id = ucode; \
37 vf2pf_info->ucode_info[ucode].version = ver; \
38 } while (0)
39
amdgpu_virt_mmio_blocked(struct amdgpu_device * adev)40 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
41 {
42 /* By now all MMIO pages except mailbox are blocked */
43 /* if blocking is enabled in hypervisor. Choose the */
44 /* SCRATCH_REG0 to test. */
45 return RREG32_NO_KIQ(0xc040) == 0xffffffff;
46 }
47
amdgpu_virt_init_setting(struct amdgpu_device * adev)48 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
49 {
50 /* enable virtual display */
51 if (adev->mode_info.num_crtc == 0)
52 adev->mode_info.num_crtc = 1;
53 adev->enable_virtual_display = true;
54 adev_to_drm(adev)->driver->driver_features &= ~DRIVER_ATOMIC;
55 adev->cg_flags = 0;
56 adev->pg_flags = 0;
57 }
58
amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device * adev,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)59 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
60 uint32_t reg0, uint32_t reg1,
61 uint32_t ref, uint32_t mask)
62 {
63 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
64 struct amdgpu_ring *ring = &kiq->ring;
65 signed long r, cnt = 0;
66 unsigned long flags;
67 uint32_t seq;
68
69 spin_lock_irqsave(&kiq->ring_lock, flags);
70 amdgpu_ring_alloc(ring, 32);
71 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
72 ref, mask);
73 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
74 if (r)
75 goto failed_undo;
76
77 amdgpu_ring_commit(ring);
78 spin_unlock_irqrestore(&kiq->ring_lock, flags);
79
80 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
81
82 /* don't wait anymore for IRQ context */
83 if (r < 1 && in_interrupt())
84 goto failed_kiq;
85
86 might_sleep();
87 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
88
89 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
90 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
91 }
92
93 if (cnt > MAX_KIQ_REG_TRY)
94 goto failed_kiq;
95
96 return;
97
98 failed_undo:
99 amdgpu_ring_undo(ring);
100 spin_unlock_irqrestore(&kiq->ring_lock, flags);
101 failed_kiq:
102 dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1);
103 }
104
105 /**
106 * amdgpu_virt_request_full_gpu() - request full gpu access
107 * @amdgpu: amdgpu device.
108 * @init: is driver init time.
109 * When start to init/fini driver, first need to request full gpu access.
110 * Return: Zero if request success, otherwise will return error.
111 */
amdgpu_virt_request_full_gpu(struct amdgpu_device * adev,bool init)112 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
113 {
114 struct amdgpu_virt *virt = &adev->virt;
115 int r;
116
117 if (virt->ops && virt->ops->req_full_gpu) {
118 r = virt->ops->req_full_gpu(adev, init);
119 if (r)
120 return r;
121
122 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
123 }
124
125 return 0;
126 }
127
128 /**
129 * amdgpu_virt_release_full_gpu() - release full gpu access
130 * @amdgpu: amdgpu device.
131 * @init: is driver init time.
132 * When finishing driver init/fini, need to release full gpu access.
133 * Return: Zero if release success, otherwise will returen error.
134 */
amdgpu_virt_release_full_gpu(struct amdgpu_device * adev,bool init)135 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
136 {
137 struct amdgpu_virt *virt = &adev->virt;
138 int r;
139
140 if (virt->ops && virt->ops->rel_full_gpu) {
141 r = virt->ops->rel_full_gpu(adev, init);
142 if (r)
143 return r;
144
145 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
146 }
147 return 0;
148 }
149
150 /**
151 * amdgpu_virt_reset_gpu() - reset gpu
152 * @amdgpu: amdgpu device.
153 * Send reset command to GPU hypervisor to reset GPU that VM is using
154 * Return: Zero if reset success, otherwise will return error.
155 */
amdgpu_virt_reset_gpu(struct amdgpu_device * adev)156 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
157 {
158 struct amdgpu_virt *virt = &adev->virt;
159 int r;
160
161 if (virt->ops && virt->ops->reset_gpu) {
162 r = virt->ops->reset_gpu(adev);
163 if (r)
164 return r;
165
166 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
167 }
168
169 return 0;
170 }
171
amdgpu_virt_request_init_data(struct amdgpu_device * adev)172 void amdgpu_virt_request_init_data(struct amdgpu_device *adev)
173 {
174 struct amdgpu_virt *virt = &adev->virt;
175
176 if (virt->ops && virt->ops->req_init_data)
177 virt->ops->req_init_data(adev);
178
179 if (adev->virt.req_init_data_ver > 0)
180 DRM_INFO("host supports REQ_INIT_DATA handshake\n");
181 else
182 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n");
183 }
184
185 /**
186 * amdgpu_virt_wait_reset() - wait for reset gpu completed
187 * @amdgpu: amdgpu device.
188 * Wait for GPU reset completed.
189 * Return: Zero if reset success, otherwise will return error.
190 */
amdgpu_virt_wait_reset(struct amdgpu_device * adev)191 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
192 {
193 struct amdgpu_virt *virt = &adev->virt;
194
195 if (!virt->ops || !virt->ops->wait_reset)
196 return -EINVAL;
197
198 return virt->ops->wait_reset(adev);
199 }
200
201 /**
202 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
203 * @amdgpu: amdgpu device.
204 * MM table is used by UVD and VCE for its initialization
205 * Return: Zero if allocate success.
206 */
amdgpu_virt_alloc_mm_table(struct amdgpu_device * adev)207 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
208 {
209 int r;
210
211 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
212 return 0;
213
214 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
215 AMDGPU_GEM_DOMAIN_VRAM,
216 &adev->virt.mm_table.bo,
217 &adev->virt.mm_table.gpu_addr,
218 (void *)&adev->virt.mm_table.cpu_addr);
219 if (r) {
220 DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
221 return r;
222 }
223
224 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
225 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
226 adev->virt.mm_table.gpu_addr,
227 adev->virt.mm_table.cpu_addr);
228 return 0;
229 }
230
231 /**
232 * amdgpu_virt_free_mm_table() - free mm table memory
233 * @amdgpu: amdgpu device.
234 * Free MM table memory
235 */
amdgpu_virt_free_mm_table(struct amdgpu_device * adev)236 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
237 {
238 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
239 return;
240
241 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
242 &adev->virt.mm_table.gpu_addr,
243 (void *)&adev->virt.mm_table.cpu_addr);
244 adev->virt.mm_table.gpu_addr = 0;
245 }
246
247
amd_sriov_msg_checksum(void * obj,unsigned long obj_size,unsigned int key,unsigned int checksum)248 unsigned int amd_sriov_msg_checksum(void *obj,
249 unsigned long obj_size,
250 unsigned int key,
251 unsigned int checksum)
252 {
253 unsigned int ret = key;
254 unsigned long i = 0;
255 unsigned char *pos;
256
257 pos = (char *)obj;
258 /* calculate checksum */
259 for (i = 0; i < obj_size; ++i)
260 ret += *(pos + i);
261 /* minus the checksum itself */
262 pos = (char *)&checksum;
263 for (i = 0; i < sizeof(checksum); ++i)
264 ret -= *(pos + i);
265 return ret;
266 }
267
amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device * adev)268 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)
269 {
270 struct amdgpu_virt *virt = &adev->virt;
271 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data;
272 /* GPU will be marked bad on host if bp count more then 10,
273 * so alloc 512 is enough.
274 */
275 unsigned int align_space = 512;
276 void *bps = NULL;
277 struct amdgpu_bo **bps_bo = NULL;
278
279 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL);
280 if (!*data)
281 return -ENOMEM;
282
283 bps = kmalloc(align_space * sizeof((*data)->bps), GFP_KERNEL);
284 bps_bo = kmalloc(align_space * sizeof((*data)->bps_bo), GFP_KERNEL);
285
286 if (!bps || !bps_bo) {
287 kfree(bps);
288 kfree(bps_bo);
289 kfree(*data);
290 return -ENOMEM;
291 }
292
293 (*data)->bps = bps;
294 (*data)->bps_bo = bps_bo;
295 (*data)->count = 0;
296 (*data)->last_reserved = 0;
297
298 virt->ras_init_done = true;
299
300 return 0;
301 }
302
amdgpu_virt_ras_release_bp(struct amdgpu_device * adev)303 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)
304 {
305 struct amdgpu_virt *virt = &adev->virt;
306 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
307 struct amdgpu_bo *bo;
308 int i;
309
310 if (!data)
311 return;
312
313 for (i = data->last_reserved - 1; i >= 0; i--) {
314 bo = data->bps_bo[i];
315 amdgpu_bo_free_kernel(&bo, NULL, NULL);
316 data->bps_bo[i] = bo;
317 data->last_reserved = i;
318 }
319 }
320
amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device * adev)321 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)
322 {
323 struct amdgpu_virt *virt = &adev->virt;
324 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
325
326 virt->ras_init_done = false;
327
328 if (!data)
329 return;
330
331 amdgpu_virt_ras_release_bp(adev);
332
333 kfree(data->bps);
334 kfree(data->bps_bo);
335 kfree(data);
336 virt->virt_eh_data = NULL;
337 }
338
amdgpu_virt_ras_add_bps(struct amdgpu_device * adev,struct eeprom_table_record * bps,int pages)339 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,
340 struct eeprom_table_record *bps, int pages)
341 {
342 struct amdgpu_virt *virt = &adev->virt;
343 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
344
345 if (!data)
346 return;
347
348 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
349 data->count += pages;
350 }
351
amdgpu_virt_ras_reserve_bps(struct amdgpu_device * adev)352 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)
353 {
354 struct amdgpu_virt *virt = &adev->virt;
355 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
356 struct amdgpu_bo *bo = NULL;
357 uint64_t bp;
358 int i;
359
360 if (!data)
361 return;
362
363 for (i = data->last_reserved; i < data->count; i++) {
364 bp = data->bps[i].retired_page;
365
366 /* There are two cases of reserve error should be ignored:
367 * 1) a ras bad page has been allocated (used by someone);
368 * 2) a ras bad page has been reserved (duplicate error injection
369 * for one page);
370 */
371 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
372 AMDGPU_GPU_PAGE_SIZE,
373 AMDGPU_GEM_DOMAIN_VRAM,
374 &bo, NULL))
375 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp);
376
377 data->bps_bo[i] = bo;
378 data->last_reserved = i + 1;
379 bo = NULL;
380 }
381 }
382
amdgpu_virt_ras_check_bad_page(struct amdgpu_device * adev,uint64_t retired_page)383 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,
384 uint64_t retired_page)
385 {
386 struct amdgpu_virt *virt = &adev->virt;
387 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
388 int i;
389
390 if (!data)
391 return true;
392
393 for (i = 0; i < data->count; i++)
394 if (retired_page == data->bps[i].retired_page)
395 return true;
396
397 return false;
398 }
399
amdgpu_virt_add_bad_page(struct amdgpu_device * adev,uint64_t bp_block_offset,uint32_t bp_block_size)400 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,
401 uint64_t bp_block_offset, uint32_t bp_block_size)
402 {
403 struct eeprom_table_record bp;
404 uint64_t retired_page;
405 uint32_t bp_idx, bp_cnt;
406
407 if (bp_block_size) {
408 bp_cnt = bp_block_size / sizeof(uint64_t);
409 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
410 retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va +
411 bp_block_offset + bp_idx * sizeof(uint64_t));
412 bp.retired_page = retired_page;
413
414 if (amdgpu_virt_ras_check_bad_page(adev, retired_page))
415 continue;
416
417 amdgpu_virt_ras_add_bps(adev, &bp, 1);
418
419 amdgpu_virt_ras_reserve_bps(adev);
420 }
421 }
422 }
423
amdgpu_virt_read_pf2vf_data(struct amdgpu_device * adev)424 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
425 {
426 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf;
427 uint32_t checksum;
428 uint32_t checkval;
429
430 if (adev->virt.fw_reserve.p_pf2vf == NULL)
431 return -EINVAL;
432
433 if (pf2vf_info->size > 1024) {
434 DRM_ERROR("invalid pf2vf message size\n");
435 return -EINVAL;
436 }
437
438 switch (pf2vf_info->version) {
439 case 1:
440 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum;
441 checkval = amd_sriov_msg_checksum(
442 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
443 adev->virt.fw_reserve.checksum_key, checksum);
444 if (checksum != checkval) {
445 DRM_ERROR("invalid pf2vf message\n");
446 return -EINVAL;
447 }
448
449 adev->virt.gim_feature =
450 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags;
451 break;
452 case 2:
453 /* TODO: missing key, need to add it later */
454 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum;
455 checkval = amd_sriov_msg_checksum(
456 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
457 0, checksum);
458 if (checksum != checkval) {
459 DRM_ERROR("invalid pf2vf message\n");
460 return -EINVAL;
461 }
462
463 adev->virt.vf2pf_update_interval_ms =
464 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms;
465 adev->virt.gim_feature =
466 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all;
467
468 break;
469 default:
470 DRM_ERROR("invalid pf2vf version\n");
471 return -EINVAL;
472 }
473
474 /* correct too large or too little interval value */
475 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000)
476 adev->virt.vf2pf_update_interval_ms = 2000;
477
478 return 0;
479 }
480
amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device * adev)481 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)
482 {
483 struct amd_sriov_msg_vf2pf_info *vf2pf_info;
484 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
485
486 if (adev->virt.fw_reserve.p_vf2pf == NULL)
487 return;
488
489 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version);
490 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version);
491 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version);
492 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version);
493 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version);
494 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version);
495 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version);
496 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);
497 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);
498 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);
499 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version);
500 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version);
501 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos_fw_version);
502 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, adev->psp.asd_fw_version);
503 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, adev->psp.ta_ras_ucode_version);
504 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, adev->psp.ta_xgmi_ucode_version);
505 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version);
506 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version);
507 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version);
508 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version);
509 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version);
510 }
511
amdgpu_virt_write_vf2pf_data(struct amdgpu_device * adev)512 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)
513 {
514 struct amd_sriov_msg_vf2pf_info *vf2pf_info;
515 struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
516
517 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
518
519 if (adev->virt.fw_reserve.p_vf2pf == NULL)
520 return -EINVAL;
521
522 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info));
523
524 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info);
525 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER;
526
527 #ifdef MODULE
528 if (THIS_MODULE->version != NULL)
529 strcpy(vf2pf_info->driver_version, THIS_MODULE->version);
530 else
531 #endif
532 strcpy(vf2pf_info->driver_version, "N/A");
533
534 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all
535 vf2pf_info->driver_cert = 0;
536 vf2pf_info->os_info.all = 0;
537
538 vf2pf_info->fb_usage = amdgpu_vram_mgr_usage(vram_man) >> 20;
539 vf2pf_info->fb_vis_usage = amdgpu_vram_mgr_vis_usage(vram_man) >> 20;
540 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;
541 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20;
542
543 amdgpu_virt_populate_vf2pf_ucode_info(adev);
544
545 /* TODO: read dynamic info */
546 vf2pf_info->gfx_usage = 0;
547 vf2pf_info->compute_usage = 0;
548 vf2pf_info->encode_usage = 0;
549 vf2pf_info->decode_usage = 0;
550
551 vf2pf_info->checksum =
552 amd_sriov_msg_checksum(
553 vf2pf_info, vf2pf_info->header.size, 0, 0);
554
555 return 0;
556 }
557
amdgpu_virt_update_vf2pf_work_item(struct work_struct * work)558 void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
559 {
560 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work);
561 int ret;
562
563 ret = amdgpu_virt_read_pf2vf_data(adev);
564 if (ret)
565 goto out;
566 amdgpu_virt_write_vf2pf_data(adev);
567
568 out:
569 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
570 }
571
amdgpu_virt_fini_data_exchange(struct amdgpu_device * adev)572 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)
573 {
574 if (adev->virt.vf2pf_update_interval_ms != 0) {
575 DRM_INFO("clean up the vf2pf work item\n");
576 flush_delayed_work(&adev->virt.vf2pf_work);
577 cancel_delayed_work_sync(&adev->virt.vf2pf_work);
578 }
579 }
580
amdgpu_virt_init_data_exchange(struct amdgpu_device * adev)581 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
582 {
583 uint64_t bp_block_offset = 0;
584 uint32_t bp_block_size = 0;
585 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
586
587 adev->virt.fw_reserve.p_pf2vf = NULL;
588 adev->virt.fw_reserve.p_vf2pf = NULL;
589 adev->virt.vf2pf_update_interval_ms = 0;
590
591 if (adev->mman.fw_vram_usage_va != NULL) {
592 adev->virt.vf2pf_update_interval_ms = 2000;
593
594 adev->virt.fw_reserve.p_pf2vf =
595 (struct amd_sriov_msg_pf2vf_info_header *)
596 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
597 adev->virt.fw_reserve.p_vf2pf =
598 (struct amd_sriov_msg_vf2pf_info_header *)
599 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
600
601 amdgpu_virt_read_pf2vf_data(adev);
602 amdgpu_virt_write_vf2pf_data(adev);
603
604 /* bad page handling for version 2 */
605 if (adev->virt.fw_reserve.p_pf2vf->version == 2) {
606 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;
607
608 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) |
609 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000);
610 bp_block_size = pf2vf_v2->bp_block_size;
611
612 if (bp_block_size && !adev->virt.ras_init_done)
613 amdgpu_virt_init_ras_err_handler_data(adev);
614
615 if (adev->virt.ras_init_done)
616 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
617 }
618 }
619
620 if (adev->virt.vf2pf_update_interval_ms != 0) {
621 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
622 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
623 }
624 }
625
amdgpu_detect_virtualization(struct amdgpu_device * adev)626 void amdgpu_detect_virtualization(struct amdgpu_device *adev)
627 {
628 uint32_t reg;
629
630 switch (adev->asic_type) {
631 case CHIP_TONGA:
632 case CHIP_FIJI:
633 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
634 break;
635 case CHIP_VEGA10:
636 case CHIP_VEGA20:
637 case CHIP_NAVI10:
638 case CHIP_NAVI12:
639 case CHIP_SIENNA_CICHLID:
640 case CHIP_ARCTURUS:
641 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
642 break;
643 default: /* other chip doesn't support SRIOV */
644 reg = 0;
645 break;
646 }
647
648 if (reg & 1)
649 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
650
651 if (reg & 0x80000000)
652 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
653
654 if (!reg) {
655 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
656 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
657 }
658
659 /* we have the ability to check now */
660 if (amdgpu_sriov_vf(adev)) {
661 switch (adev->asic_type) {
662 case CHIP_TONGA:
663 case CHIP_FIJI:
664 vi_set_virt_ops(adev);
665 break;
666 case CHIP_VEGA10:
667 case CHIP_VEGA20:
668 case CHIP_ARCTURUS:
669 soc15_set_virt_ops(adev);
670 break;
671 case CHIP_NAVI10:
672 case CHIP_NAVI12:
673 case CHIP_SIENNA_CICHLID:
674 nv_set_virt_ops(adev);
675 /* try send GPU_INIT_DATA request to host */
676 amdgpu_virt_request_init_data(adev);
677 break;
678 default: /* other chip doesn't support SRIOV */
679 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type);
680 break;
681 }
682 }
683 }
684
amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device * adev)685 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
686 {
687 return amdgpu_sriov_is_debug(adev) ? true : false;
688 }
689
amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device * adev)690 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
691 {
692 return amdgpu_sriov_is_normal(adev) ? true : false;
693 }
694
amdgpu_virt_enable_access_debugfs(struct amdgpu_device * adev)695 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)
696 {
697 if (!amdgpu_sriov_vf(adev) ||
698 amdgpu_virt_access_debugfs_is_kiq(adev))
699 return 0;
700
701 if (amdgpu_virt_access_debugfs_is_mmio(adev))
702 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
703 else
704 return -EPERM;
705
706 return 0;
707 }
708
amdgpu_virt_disable_access_debugfs(struct amdgpu_device * adev)709 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)
710 {
711 if (amdgpu_sriov_vf(adev))
712 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
713 }
714
amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device * adev)715 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)
716 {
717 enum amdgpu_sriov_vf_mode mode;
718
719 if (amdgpu_sriov_vf(adev)) {
720 if (amdgpu_sriov_is_pp_one_vf(adev))
721 mode = SRIOV_VF_MODE_ONE_VF;
722 else
723 mode = SRIOV_VF_MODE_MULTI_VF;
724 } else {
725 mode = SRIOV_VF_MODE_BARE_METAL;
726 }
727
728 return mode;
729 }
730