1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
11 *
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
21 *
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
28 *
29 * Some implementation details worth remembering:
30 *
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
33 *
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
37 *
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
42 *
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
45 *
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49 *
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
55 * details.
56 *
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
60 * KVM guests.
61 */
62
63 #define pr_fmt(fmt) "CPU features: " fmt
64
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/percpu.h>
69 #include <linux/sort.h>
70 #include <linux/stop_machine.h>
71 #include <linux/types.h>
72 #include <linux/mm.h>
73 #include <linux/cpu.h>
74
75 #include <asm/cpu.h>
76 #include <asm/cpufeature.h>
77 #include <asm/cpu_ops.h>
78 #include <asm/fpsimd.h>
79 #include <asm/mmu_context.h>
80 #include <asm/mte.h>
81 #include <asm/processor.h>
82 #include <asm/sysreg.h>
83 #include <asm/traps.h>
84 #include <asm/vectors.h>
85 #include <asm/virt.h>
86
87 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
88 static unsigned long elf_hwcap __read_mostly;
89
90 #ifdef CONFIG_COMPAT
91 #define COMPAT_ELF_HWCAP_DEFAULT \
92 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
93 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
94 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
95 COMPAT_HWCAP_LPAE)
96 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
97 unsigned int compat_elf_hwcap2 __read_mostly;
98 #endif
99
100 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
101 EXPORT_SYMBOL(cpu_hwcaps);
102 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
103
104 /* Need also bit for ARM64_CB_PATCH */
105 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
106
107 bool arm64_use_ng_mappings = false;
108 EXPORT_SYMBOL(arm64_use_ng_mappings);
109
110 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
111
112 /*
113 * Flag to indicate if we have computed the system wide
114 * capabilities based on the boot time active CPUs. This
115 * will be used to determine if a new booting CPU should
116 * go through the verification process to make sure that it
117 * supports the system capabilities, without using a hotplug
118 * notifier. This is also used to decide if we could use
119 * the fast path for checking constant CPU caps.
120 */
121 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
122 EXPORT_SYMBOL(arm64_const_caps_ready);
finalize_system_capabilities(void)123 static inline void finalize_system_capabilities(void)
124 {
125 static_branch_enable(&arm64_const_caps_ready);
126 }
127
dump_cpu_features(void)128 void dump_cpu_features(void)
129 {
130 /* file-wide pr_fmt adds "CPU features: " prefix */
131 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
132 }
133
134 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
135 EXPORT_SYMBOL(cpu_hwcap_keys);
136
137 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
138 { \
139 .sign = SIGNED, \
140 .visible = VISIBLE, \
141 .strict = STRICT, \
142 .type = TYPE, \
143 .shift = SHIFT, \
144 .width = WIDTH, \
145 .safe_val = SAFE_VAL, \
146 }
147
148 /* Define a feature with unsigned values */
149 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
150 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
151
152 /* Define a feature with a signed value */
153 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
154 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
155
156 #define ARM64_FTR_END \
157 { \
158 .width = 0, \
159 }
160
161 /* meta feature for alternatives */
162 static bool __maybe_unused
163 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
164
165 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
166
167 static bool __system_matches_cap(unsigned int n);
168
169 /*
170 * NOTE: Any changes to the visibility of features should be kept in
171 * sync with the documentation of the CPU feature register ABI.
172 */
173 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
174 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
175 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
182 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
188 ARM64_FTR_END,
189 };
190
191 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
199 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
201 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
206 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
208 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
210 ARM64_FTR_END,
211 };
212
213 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
215 ARM64_FTR_END,
216 };
217
218 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
226 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
229 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
230 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
235 ARM64_FTR_END,
236 };
237
238 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
242 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
246 ARM64_FTR_END,
247 };
248
249 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
256 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
257 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
258 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
259 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
261 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
268 ARM64_FTR_END,
269 };
270
271 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
272 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
275 /*
276 * Page size not being supported at Stage-2 is not fatal. You
277 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
278 * your favourite nesting hypervisor.
279 *
280 * There is a small corner case where the hypervisor explicitly
281 * advertises a given granule size at Stage-2 (value 2) on some
282 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
283 * vCPUs. Although this is not forbidden by the architecture, it
284 * indicates that the hypervisor is being silly (or buggy).
285 *
286 * We make no effort to cope with this and pretend that if these
287 * fields are inconsistent across vCPUs, then it isn't worth
288 * trying to bring KVM up.
289 */
290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
293 /*
294 * We already refuse to boot CPUs that don't support our configured
295 * page size, so we can only detect mismatches for a page size other
296 * than the one we're currently using. Unfortunately, SoCs like this
297 * exist in the wild so, even though we don't like it, we'll have to go
298 * along with it and treat them as non-strict.
299 */
300 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
301 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
303
304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
305 /* Linux shouldn't care about secure memory */
306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
309 /*
310 * Differing PARange is fine as long as all peripherals and memory are mapped
311 * within the minimum PARange of all CPUs
312 */
313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
314 ARM64_FTR_END,
315 };
316
317 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
328 ARM64_FTR_END,
329 };
330
331 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
338 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
347 ARM64_FTR_END,
348 };
349
350 static const struct arm64_ftr_bits ftr_ctr[] = {
351 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
352 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
353 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
354 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
355 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
356 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
357 /*
358 * Linux can handle differing I-cache policies. Userspace JITs will
359 * make use of *minLine.
360 * If we have differing I-cache policies, report it as the weakest - VIPT.
361 */
362 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
363 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
364 ARM64_FTR_END,
365 };
366
367 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
368 .name = "SYS_CTR_EL0",
369 .ftr_bits = ftr_ctr
370 };
371
372 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
373 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
378 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
381 ARM64_FTR_END,
382 };
383
384 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
385 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
390 /*
391 * We can instantiate multiple PMU instances with different levels
392 * of support.
393 */
394 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
395 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
396 ARM64_FTR_END,
397 };
398
399 static const struct arm64_ftr_bits ftr_mvfr2[] = {
400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
402 ARM64_FTR_END,
403 };
404
405 static const struct arm64_ftr_bits ftr_dczid[] = {
406 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
407 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
408 ARM64_FTR_END,
409 };
410
411 static const struct arm64_ftr_bits ftr_id_isar0[] = {
412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
419 ARM64_FTR_END,
420 };
421
422 static const struct arm64_ftr_bits ftr_id_isar5[] = {
423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
429 ARM64_FTR_END,
430 };
431
432 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
440
441 /*
442 * SpecSEI = 1 indicates that the PE might generate an SError on an
443 * external abort on speculative read. It is safe to assume that an
444 * SError might be generated than it will not be. Hence it has been
445 * classified as FTR_HIGHER_SAFE.
446 */
447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
448 ARM64_FTR_END,
449 };
450
451 static const struct arm64_ftr_bits ftr_id_isar4[] = {
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
460 ARM64_FTR_END,
461 };
462
463 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
465 ARM64_FTR_END,
466 };
467
468 static const struct arm64_ftr_bits ftr_id_isar6[] = {
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
476 ARM64_FTR_END,
477 };
478
479 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
486 ARM64_FTR_END,
487 };
488
489 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
498 ARM64_FTR_END,
499 };
500
501 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
504 ARM64_FTR_END,
505 };
506
507 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
508 /* [31:28] TraceFilt */
509 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf),
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
516 ARM64_FTR_END,
517 };
518
519 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
520 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
521 ARM64_FTR_END,
522 };
523
524 static const struct arm64_ftr_bits ftr_zcr[] = {
525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
526 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
527 ARM64_FTR_END,
528 };
529
530 /*
531 * Common ftr bits for a 32bit register with all hidden, strict
532 * attributes, with 4bit feature fields and a default safe value of
533 * 0. Covers the following 32bit registers:
534 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
535 */
536 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
545 ARM64_FTR_END,
546 };
547
548 /* Table for a single 32bit feature value */
549 static const struct arm64_ftr_bits ftr_single32[] = {
550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
551 ARM64_FTR_END,
552 };
553
554 static const struct arm64_ftr_bits ftr_raz[] = {
555 ARM64_FTR_END,
556 };
557
558 #define ARM64_FTR_REG(id, table) { \
559 .sys_id = id, \
560 .reg = &(struct arm64_ftr_reg){ \
561 .name = #id, \
562 .ftr_bits = &((table)[0]), \
563 }}
564
565 static const struct __ftr_reg_entry {
566 u32 sys_id;
567 struct arm64_ftr_reg *reg;
568 } arm64_ftr_regs[] = {
569
570 /* Op1 = 0, CRn = 0, CRm = 1 */
571 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
572 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
573 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
574 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
575 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
576 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
577 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
578
579 /* Op1 = 0, CRn = 0, CRm = 2 */
580 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
581 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
582 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
583 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
584 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
585 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
586 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
587 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
588
589 /* Op1 = 0, CRn = 0, CRm = 3 */
590 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
591 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
592 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
593 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
594 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
595 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
596
597 /* Op1 = 0, CRn = 0, CRm = 4 */
598 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
599 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
600 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
601
602 /* Op1 = 0, CRn = 0, CRm = 5 */
603 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
604 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
605
606 /* Op1 = 0, CRn = 0, CRm = 6 */
607 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
608 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
609 ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
610
611 /* Op1 = 0, CRn = 0, CRm = 7 */
612 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
613 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
614 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
615
616 /* Op1 = 0, CRn = 1, CRm = 2 */
617 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
618
619 /* Op1 = 3, CRn = 0, CRm = 0 */
620 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
621 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
622
623 /* Op1 = 3, CRn = 14, CRm = 0 */
624 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
625 };
626
search_cmp_ftr_reg(const void * id,const void * regp)627 static int search_cmp_ftr_reg(const void *id, const void *regp)
628 {
629 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
630 }
631
632 /*
633 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
634 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
635 * ascending order of sys_id, we use binary search to find a matching
636 * entry.
637 *
638 * returns - Upon success, matching ftr_reg entry for id.
639 * - NULL on failure. It is upto the caller to decide
640 * the impact of a failure.
641 */
get_arm64_ftr_reg_nowarn(u32 sys_id)642 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
643 {
644 const struct __ftr_reg_entry *ret;
645
646 ret = bsearch((const void *)(unsigned long)sys_id,
647 arm64_ftr_regs,
648 ARRAY_SIZE(arm64_ftr_regs),
649 sizeof(arm64_ftr_regs[0]),
650 search_cmp_ftr_reg);
651 if (ret)
652 return ret->reg;
653 return NULL;
654 }
655
656 /*
657 * get_arm64_ftr_reg - Looks up a feature register entry using
658 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
659 *
660 * returns - Upon success, matching ftr_reg entry for id.
661 * - NULL on failure but with an WARN_ON().
662 */
get_arm64_ftr_reg(u32 sys_id)663 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
664 {
665 struct arm64_ftr_reg *reg;
666
667 reg = get_arm64_ftr_reg_nowarn(sys_id);
668
669 /*
670 * Requesting a non-existent register search is an error. Warn
671 * and let the caller handle it.
672 */
673 WARN_ON(!reg);
674 return reg;
675 }
676
arm64_ftr_set_value(const struct arm64_ftr_bits * ftrp,s64 reg,s64 ftr_val)677 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
678 s64 ftr_val)
679 {
680 u64 mask = arm64_ftr_mask(ftrp);
681
682 reg &= ~mask;
683 reg |= (ftr_val << ftrp->shift) & mask;
684 return reg;
685 }
686
arm64_ftr_safe_value(const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)687 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
688 s64 cur)
689 {
690 s64 ret = 0;
691
692 switch (ftrp->type) {
693 case FTR_EXACT:
694 ret = ftrp->safe_val;
695 break;
696 case FTR_LOWER_SAFE:
697 ret = new < cur ? new : cur;
698 break;
699 case FTR_HIGHER_OR_ZERO_SAFE:
700 if (!cur || !new)
701 break;
702 fallthrough;
703 case FTR_HIGHER_SAFE:
704 ret = new > cur ? new : cur;
705 break;
706 default:
707 BUG();
708 }
709
710 return ret;
711 }
712
sort_ftr_regs(void)713 static void __init sort_ftr_regs(void)
714 {
715 unsigned int i;
716
717 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
718 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
719 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
720 unsigned int j = 0;
721
722 /*
723 * Features here must be sorted in descending order with respect
724 * to their shift values and should not overlap with each other.
725 */
726 for (; ftr_bits->width != 0; ftr_bits++, j++) {
727 unsigned int width = ftr_reg->ftr_bits[j].width;
728 unsigned int shift = ftr_reg->ftr_bits[j].shift;
729 unsigned int prev_shift;
730
731 WARN((shift + width) > 64,
732 "%s has invalid feature at shift %d\n",
733 ftr_reg->name, shift);
734
735 /*
736 * Skip the first feature. There is nothing to
737 * compare against for now.
738 */
739 if (j == 0)
740 continue;
741
742 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
743 WARN((shift + width) > prev_shift,
744 "%s has feature overlap at shift %d\n",
745 ftr_reg->name, shift);
746 }
747
748 /*
749 * Skip the first register. There is nothing to
750 * compare against for now.
751 */
752 if (i == 0)
753 continue;
754 /*
755 * Registers here must be sorted in ascending order with respect
756 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
757 * to work correctly.
758 */
759 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
760 }
761 }
762
763 /*
764 * Initialise the CPU feature register from Boot CPU values.
765 * Also initiliases the strict_mask for the register.
766 * Any bits that are not covered by an arm64_ftr_bits entry are considered
767 * RES0 for the system-wide value, and must strictly match.
768 */
init_cpu_ftr_reg(u32 sys_reg,u64 new)769 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
770 {
771 u64 val = 0;
772 u64 strict_mask = ~0x0ULL;
773 u64 user_mask = 0;
774 u64 valid_mask = 0;
775
776 const struct arm64_ftr_bits *ftrp;
777 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
778
779 if (!reg)
780 return;
781
782 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
783 u64 ftr_mask = arm64_ftr_mask(ftrp);
784 s64 ftr_new = arm64_ftr_value(ftrp, new);
785
786 val = arm64_ftr_set_value(ftrp, val, ftr_new);
787
788 valid_mask |= ftr_mask;
789 if (!ftrp->strict)
790 strict_mask &= ~ftr_mask;
791 if (ftrp->visible)
792 user_mask |= ftr_mask;
793 else
794 reg->user_val = arm64_ftr_set_value(ftrp,
795 reg->user_val,
796 ftrp->safe_val);
797 }
798
799 val &= valid_mask;
800
801 reg->sys_val = val;
802 reg->strict_mask = strict_mask;
803 reg->user_mask = user_mask;
804 }
805
806 extern const struct arm64_cpu_capabilities arm64_errata[];
807 static const struct arm64_cpu_capabilities arm64_features[];
808
809 static void __init
init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities * caps)810 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
811 {
812 for (; caps->matches; caps++) {
813 if (WARN(caps->capability >= ARM64_NCAPS,
814 "Invalid capability %d\n", caps->capability))
815 continue;
816 if (WARN(cpu_hwcaps_ptrs[caps->capability],
817 "Duplicate entry for capability %d\n",
818 caps->capability))
819 continue;
820 cpu_hwcaps_ptrs[caps->capability] = caps;
821 }
822 }
823
init_cpu_hwcaps_indirect_list(void)824 static void __init init_cpu_hwcaps_indirect_list(void)
825 {
826 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
827 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
828 }
829
830 static void __init setup_boot_cpu_capabilities(void);
831
init_cpu_features(struct cpuinfo_arm64 * info)832 void __init init_cpu_features(struct cpuinfo_arm64 *info)
833 {
834 /* Before we start using the tables, make sure it is sorted */
835 sort_ftr_regs();
836
837 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
838 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
839 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
840 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
841 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
842 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
843 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
844 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
845 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
846 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
847 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
848 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
849 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
850 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
851
852 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
853 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
854 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
855 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
856 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
857 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
858 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
859 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
860 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
861 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
862 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
863 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
864 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
865 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
866 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
867 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
868 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
869 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
870 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
871 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
872 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
873 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
874 }
875
876 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
877 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
878 sve_init_vq_map();
879 }
880
881 /*
882 * Initialize the indirect array of CPU hwcaps capabilities pointers
883 * before we handle the boot CPU below.
884 */
885 init_cpu_hwcaps_indirect_list();
886
887 /*
888 * Detect and enable early CPU capabilities based on the boot CPU,
889 * after we have initialised the CPU feature infrastructure.
890 */
891 setup_boot_cpu_capabilities();
892 }
893
update_cpu_ftr_reg(struct arm64_ftr_reg * reg,u64 new)894 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
895 {
896 const struct arm64_ftr_bits *ftrp;
897
898 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
899 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
900 s64 ftr_new = arm64_ftr_value(ftrp, new);
901
902 if (ftr_cur == ftr_new)
903 continue;
904 /* Find a safe value */
905 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
906 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
907 }
908
909 }
910
check_update_ftr_reg(u32 sys_id,int cpu,u64 val,u64 boot)911 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
912 {
913 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
914
915 if (!regp)
916 return 0;
917
918 update_cpu_ftr_reg(regp, val);
919 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
920 return 0;
921 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
922 regp->name, boot, cpu, val);
923 return 1;
924 }
925
relax_cpu_ftr_reg(u32 sys_id,int field)926 static void relax_cpu_ftr_reg(u32 sys_id, int field)
927 {
928 const struct arm64_ftr_bits *ftrp;
929 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
930
931 if (!regp)
932 return;
933
934 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
935 if (ftrp->shift == field) {
936 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
937 break;
938 }
939 }
940
941 /* Bogus field? */
942 WARN_ON(!ftrp->width);
943 }
944
update_32bit_cpu_features(int cpu,struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)945 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
946 struct cpuinfo_arm64 *boot)
947 {
948 int taint = 0;
949 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
950
951 /*
952 * If we don't have AArch32 at all then skip the checks entirely
953 * as the register values may be UNKNOWN and we're not going to be
954 * using them for anything.
955 */
956 if (!id_aa64pfr0_32bit_el0(pfr0))
957 return taint;
958
959 /*
960 * If we don't have AArch32 at EL1, then relax the strictness of
961 * EL1-dependent register fields to avoid spurious sanity check fails.
962 */
963 if (!id_aa64pfr0_32bit_el1(pfr0)) {
964 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
965 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
966 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
967 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
968 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
969 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
970 }
971
972 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
973 info->reg_id_dfr0, boot->reg_id_dfr0);
974 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
975 info->reg_id_dfr1, boot->reg_id_dfr1);
976 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
977 info->reg_id_isar0, boot->reg_id_isar0);
978 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
979 info->reg_id_isar1, boot->reg_id_isar1);
980 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
981 info->reg_id_isar2, boot->reg_id_isar2);
982 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
983 info->reg_id_isar3, boot->reg_id_isar3);
984 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
985 info->reg_id_isar4, boot->reg_id_isar4);
986 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
987 info->reg_id_isar5, boot->reg_id_isar5);
988 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
989 info->reg_id_isar6, boot->reg_id_isar6);
990
991 /*
992 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
993 * ACTLR formats could differ across CPUs and therefore would have to
994 * be trapped for virtualization anyway.
995 */
996 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
997 info->reg_id_mmfr0, boot->reg_id_mmfr0);
998 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
999 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1000 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1001 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1002 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1003 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1004 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1005 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1006 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1007 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1008 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1009 info->reg_id_pfr0, boot->reg_id_pfr0);
1010 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1011 info->reg_id_pfr1, boot->reg_id_pfr1);
1012 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1013 info->reg_id_pfr2, boot->reg_id_pfr2);
1014 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1015 info->reg_mvfr0, boot->reg_mvfr0);
1016 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1017 info->reg_mvfr1, boot->reg_mvfr1);
1018 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1019 info->reg_mvfr2, boot->reg_mvfr2);
1020
1021 return taint;
1022 }
1023
1024 /*
1025 * Update system wide CPU feature registers with the values from a
1026 * non-boot CPU. Also performs SANITY checks to make sure that there
1027 * aren't any insane variations from that of the boot CPU.
1028 */
update_cpu_features(int cpu,struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)1029 void update_cpu_features(int cpu,
1030 struct cpuinfo_arm64 *info,
1031 struct cpuinfo_arm64 *boot)
1032 {
1033 int taint = 0;
1034
1035 /*
1036 * The kernel can handle differing I-cache policies, but otherwise
1037 * caches should look identical. Userspace JITs will make use of
1038 * *minLine.
1039 */
1040 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1041 info->reg_ctr, boot->reg_ctr);
1042
1043 /*
1044 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1045 * could result in too much or too little memory being zeroed if a
1046 * process is preempted and migrated between CPUs.
1047 */
1048 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1049 info->reg_dczid, boot->reg_dczid);
1050
1051 /* If different, timekeeping will be broken (especially with KVM) */
1052 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1053 info->reg_cntfrq, boot->reg_cntfrq);
1054
1055 /*
1056 * The kernel uses self-hosted debug features and expects CPUs to
1057 * support identical debug features. We presently need CTX_CMPs, WRPs,
1058 * and BRPs to be identical.
1059 * ID_AA64DFR1 is currently RES0.
1060 */
1061 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1062 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1063 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1064 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1065 /*
1066 * Even in big.LITTLE, processors should be identical instruction-set
1067 * wise.
1068 */
1069 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1070 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1071 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1072 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1073 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1074 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1075
1076 /*
1077 * Differing PARange support is fine as long as all peripherals and
1078 * memory are mapped within the minimum PARange of all CPUs.
1079 * Linux should not care about secure memory.
1080 */
1081 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1082 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1083 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1084 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1085 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1086 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1087
1088 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1089 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1090 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1091 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1092
1093 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1094 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1095
1096 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1097 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1098 info->reg_zcr, boot->reg_zcr);
1099
1100 /* Probe vector lengths, unless we already gave up on SVE */
1101 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1102 !system_capabilities_finalized())
1103 sve_update_vq_map();
1104 }
1105
1106 /*
1107 * This relies on a sanitised view of the AArch64 ID registers
1108 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1109 */
1110 taint |= update_32bit_cpu_features(cpu, info, boot);
1111
1112 /*
1113 * Mismatched CPU features are a recipe for disaster. Don't even
1114 * pretend to support them.
1115 */
1116 if (taint) {
1117 pr_warn_once("Unsupported CPU feature variation detected.\n");
1118 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1119 }
1120 }
1121
read_sanitised_ftr_reg(u32 id)1122 u64 read_sanitised_ftr_reg(u32 id)
1123 {
1124 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1125
1126 if (!regp)
1127 return 0;
1128 return regp->sys_val;
1129 }
1130 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1131
1132 #define read_sysreg_case(r) \
1133 case r: return read_sysreg_s(r)
1134
1135 /*
1136 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1137 * Read the system register on the current CPU
1138 */
__read_sysreg_by_encoding(u32 sys_id)1139 static u64 __read_sysreg_by_encoding(u32 sys_id)
1140 {
1141 switch (sys_id) {
1142 read_sysreg_case(SYS_ID_PFR0_EL1);
1143 read_sysreg_case(SYS_ID_PFR1_EL1);
1144 read_sysreg_case(SYS_ID_PFR2_EL1);
1145 read_sysreg_case(SYS_ID_DFR0_EL1);
1146 read_sysreg_case(SYS_ID_DFR1_EL1);
1147 read_sysreg_case(SYS_ID_MMFR0_EL1);
1148 read_sysreg_case(SYS_ID_MMFR1_EL1);
1149 read_sysreg_case(SYS_ID_MMFR2_EL1);
1150 read_sysreg_case(SYS_ID_MMFR3_EL1);
1151 read_sysreg_case(SYS_ID_MMFR4_EL1);
1152 read_sysreg_case(SYS_ID_MMFR5_EL1);
1153 read_sysreg_case(SYS_ID_ISAR0_EL1);
1154 read_sysreg_case(SYS_ID_ISAR1_EL1);
1155 read_sysreg_case(SYS_ID_ISAR2_EL1);
1156 read_sysreg_case(SYS_ID_ISAR3_EL1);
1157 read_sysreg_case(SYS_ID_ISAR4_EL1);
1158 read_sysreg_case(SYS_ID_ISAR5_EL1);
1159 read_sysreg_case(SYS_ID_ISAR6_EL1);
1160 read_sysreg_case(SYS_MVFR0_EL1);
1161 read_sysreg_case(SYS_MVFR1_EL1);
1162 read_sysreg_case(SYS_MVFR2_EL1);
1163
1164 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1165 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1166 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1167 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1168 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1169 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1170 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1171 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1172 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1173 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1174 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1175
1176 read_sysreg_case(SYS_CNTFRQ_EL0);
1177 read_sysreg_case(SYS_CTR_EL0);
1178 read_sysreg_case(SYS_DCZID_EL0);
1179
1180 default:
1181 BUG();
1182 return 0;
1183 }
1184 }
1185
1186 #include <linux/irqchip/arm-gic-v3.h>
1187
1188 static bool
feature_matches(u64 reg,const struct arm64_cpu_capabilities * entry)1189 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1190 {
1191 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1192
1193 return val >= entry->min_field_value;
1194 }
1195
1196 static bool
has_cpuid_feature(const struct arm64_cpu_capabilities * entry,int scope)1197 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1198 {
1199 u64 val;
1200
1201 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1202 if (scope == SCOPE_SYSTEM)
1203 val = read_sanitised_ftr_reg(entry->sys_reg);
1204 else
1205 val = __read_sysreg_by_encoding(entry->sys_reg);
1206
1207 return feature_matches(val, entry);
1208 }
1209
has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities * entry,int scope)1210 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1211 {
1212 bool has_sre;
1213
1214 if (!has_cpuid_feature(entry, scope))
1215 return false;
1216
1217 has_sre = gic_enable_sre();
1218 if (!has_sre)
1219 pr_warn_once("%s present but disabled by higher exception level\n",
1220 entry->desc);
1221
1222 return has_sre;
1223 }
1224
has_no_hw_prefetch(const struct arm64_cpu_capabilities * entry,int __unused)1225 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1226 {
1227 u32 midr = read_cpuid_id();
1228
1229 /* Cavium ThunderX pass 1.x and 2.x */
1230 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1231 MIDR_CPU_VAR_REV(0, 0),
1232 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1233 }
1234
has_no_fpsimd(const struct arm64_cpu_capabilities * entry,int __unused)1235 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1236 {
1237 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1238
1239 return cpuid_feature_extract_signed_field(pfr0,
1240 ID_AA64PFR0_FP_SHIFT) < 0;
1241 }
1242
has_cache_idc(const struct arm64_cpu_capabilities * entry,int scope)1243 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1244 int scope)
1245 {
1246 u64 ctr;
1247
1248 if (scope == SCOPE_SYSTEM)
1249 ctr = arm64_ftr_reg_ctrel0.sys_val;
1250 else
1251 ctr = read_cpuid_effective_cachetype();
1252
1253 return ctr & BIT(CTR_IDC_SHIFT);
1254 }
1255
cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities * __unused)1256 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1257 {
1258 /*
1259 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1260 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1261 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1262 * value.
1263 */
1264 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1265 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1266 }
1267
has_cache_dic(const struct arm64_cpu_capabilities * entry,int scope)1268 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1269 int scope)
1270 {
1271 u64 ctr;
1272
1273 if (scope == SCOPE_SYSTEM)
1274 ctr = arm64_ftr_reg_ctrel0.sys_val;
1275 else
1276 ctr = read_cpuid_cachetype();
1277
1278 return ctr & BIT(CTR_DIC_SHIFT);
1279 }
1280
1281 static bool __maybe_unused
has_useable_cnp(const struct arm64_cpu_capabilities * entry,int scope)1282 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1283 {
1284 /*
1285 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1286 * may share TLB entries with a CPU stuck in the crashed
1287 * kernel.
1288 */
1289 if (is_kdump_kernel())
1290 return false;
1291
1292 return has_cpuid_feature(entry, scope);
1293 }
1294
1295 /*
1296 * This check is triggered during the early boot before the cpufeature
1297 * is initialised. Checking the status on the local CPU allows the boot
1298 * CPU to detect the need for non-global mappings and thus avoiding a
1299 * pagetable re-write after all the CPUs are booted. This check will be
1300 * anyway run on individual CPUs, allowing us to get the consistent
1301 * state once the SMP CPUs are up and thus make the switch to non-global
1302 * mappings if required.
1303 */
kaslr_requires_kpti(void)1304 bool kaslr_requires_kpti(void)
1305 {
1306 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1307 return false;
1308
1309 /*
1310 * E0PD does a similar job to KPTI so can be used instead
1311 * where available.
1312 */
1313 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1314 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1315 if (cpuid_feature_extract_unsigned_field(mmfr2,
1316 ID_AA64MMFR2_E0PD_SHIFT))
1317 return false;
1318 }
1319
1320 /*
1321 * Systems affected by Cavium erratum 24756 are incompatible
1322 * with KPTI.
1323 */
1324 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1325 extern const struct midr_range cavium_erratum_27456_cpus[];
1326
1327 if (is_midr_in_range_list(read_cpuid_id(),
1328 cavium_erratum_27456_cpus))
1329 return false;
1330 }
1331
1332 return kaslr_offset() > 0;
1333 }
1334
1335 static bool __meltdown_safe = true;
1336 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1337
unmap_kernel_at_el0(const struct arm64_cpu_capabilities * entry,int scope)1338 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1339 int scope)
1340 {
1341 /* List of CPUs that are not vulnerable and don't need KPTI */
1342 static const struct midr_range kpti_safe_list[] = {
1343 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1344 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1345 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1346 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1347 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1348 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1349 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1350 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1351 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1352 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1353 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1354 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1355 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1356 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1357 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1358 { /* sentinel */ }
1359 };
1360 char const *str = "kpti command line option";
1361 bool meltdown_safe;
1362
1363 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1364
1365 /* Defer to CPU feature registers */
1366 if (has_cpuid_feature(entry, scope))
1367 meltdown_safe = true;
1368
1369 if (!meltdown_safe)
1370 __meltdown_safe = false;
1371
1372 /*
1373 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1374 * ThunderX leads to apparent I-cache corruption of kernel text, which
1375 * ends as well as you might imagine. Don't even try.
1376 */
1377 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1378 str = "ARM64_WORKAROUND_CAVIUM_27456";
1379 __kpti_forced = -1;
1380 }
1381
1382 /* Useful for KASLR robustness */
1383 if (kaslr_requires_kpti()) {
1384 if (!__kpti_forced) {
1385 str = "KASLR";
1386 __kpti_forced = 1;
1387 }
1388 }
1389
1390 if (cpu_mitigations_off() && !__kpti_forced) {
1391 str = "mitigations=off";
1392 __kpti_forced = -1;
1393 }
1394
1395 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1396 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1397 return false;
1398 }
1399
1400 /* Forced? */
1401 if (__kpti_forced) {
1402 pr_info_once("kernel page table isolation forced %s by %s\n",
1403 __kpti_forced > 0 ? "ON" : "OFF", str);
1404 return __kpti_forced > 0;
1405 }
1406
1407 return !meltdown_safe;
1408 }
1409
1410 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1411 static void __nocfi
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1412 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1413 {
1414 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1415 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1416 kpti_remap_fn *remap_fn;
1417
1418 int cpu = smp_processor_id();
1419
1420 if (__this_cpu_read(this_cpu_vector) == vectors) {
1421 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1422
1423 __this_cpu_write(this_cpu_vector, v);
1424 }
1425
1426 /*
1427 * We don't need to rewrite the page-tables if either we've done
1428 * it already or we have KASLR enabled and therefore have not
1429 * created any global mappings at all.
1430 */
1431 if (arm64_use_ng_mappings)
1432 return;
1433
1434 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1435
1436 cpu_install_idmap();
1437 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1438 cpu_uninstall_idmap();
1439
1440 if (!cpu)
1441 arm64_use_ng_mappings = true;
1442
1443 return;
1444 }
1445 #else
1446 static void
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1447 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1448 {
1449 }
1450 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1451
parse_kpti(char * str)1452 static int __init parse_kpti(char *str)
1453 {
1454 bool enabled;
1455 int ret = strtobool(str, &enabled);
1456
1457 if (ret)
1458 return ret;
1459
1460 __kpti_forced = enabled ? 1 : -1;
1461 return 0;
1462 }
1463 early_param("kpti", parse_kpti);
1464
1465 #ifdef CONFIG_ARM64_HW_AFDBM
__cpu_enable_hw_dbm(void)1466 static inline void __cpu_enable_hw_dbm(void)
1467 {
1468 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1469
1470 write_sysreg(tcr, tcr_el1);
1471 isb();
1472 local_flush_tlb_all();
1473 }
1474
cpu_has_broken_dbm(void)1475 static bool cpu_has_broken_dbm(void)
1476 {
1477 /* List of CPUs which have broken DBM support. */
1478 static const struct midr_range cpus[] = {
1479 #ifdef CONFIG_ARM64_ERRATUM_1024718
1480 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1481 /* Kryo4xx Silver (rdpe => r1p0) */
1482 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1483 #endif
1484 {},
1485 };
1486
1487 return is_midr_in_range_list(read_cpuid_id(), cpus);
1488 }
1489
cpu_can_use_dbm(const struct arm64_cpu_capabilities * cap)1490 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1491 {
1492 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1493 !cpu_has_broken_dbm();
1494 }
1495
cpu_enable_hw_dbm(struct arm64_cpu_capabilities const * cap)1496 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1497 {
1498 if (cpu_can_use_dbm(cap))
1499 __cpu_enable_hw_dbm();
1500 }
1501
has_hw_dbm(const struct arm64_cpu_capabilities * cap,int __unused)1502 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1503 int __unused)
1504 {
1505 static bool detected = false;
1506 /*
1507 * DBM is a non-conflicting feature. i.e, the kernel can safely
1508 * run a mix of CPUs with and without the feature. So, we
1509 * unconditionally enable the capability to allow any late CPU
1510 * to use the feature. We only enable the control bits on the
1511 * CPU, if it actually supports.
1512 *
1513 * We have to make sure we print the "feature" detection only
1514 * when at least one CPU actually uses it. So check if this CPU
1515 * can actually use it and print the message exactly once.
1516 *
1517 * This is safe as all CPUs (including secondary CPUs - due to the
1518 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1519 * goes through the "matches" check exactly once. Also if a CPU
1520 * matches the criteria, it is guaranteed that the CPU will turn
1521 * the DBM on, as the capability is unconditionally enabled.
1522 */
1523 if (!detected && cpu_can_use_dbm(cap)) {
1524 detected = true;
1525 pr_info("detected: Hardware dirty bit management\n");
1526 }
1527
1528 return true;
1529 }
1530
1531 #endif
1532
1533 #ifdef CONFIG_ARM64_AMU_EXTN
1534
1535 /*
1536 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1537 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1538 * information regarding all the events that it supports. When a CPU bit is
1539 * set in the cpumask, the user of this feature can only rely on the presence
1540 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1541 * counters are enabled or access to these counters is enabled by code
1542 * executed at higher exception levels (firmware).
1543 */
1544 static struct cpumask amu_cpus __read_mostly;
1545
cpu_has_amu_feat(int cpu)1546 bool cpu_has_amu_feat(int cpu)
1547 {
1548 return cpumask_test_cpu(cpu, &amu_cpus);
1549 }
1550
1551 /* Initialize the use of AMU counters for frequency invariance */
1552 extern void init_cpu_freq_invariance_counters(void);
1553
cpu_amu_enable(struct arm64_cpu_capabilities const * cap)1554 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1555 {
1556 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1557 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1558 smp_processor_id());
1559 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1560 init_cpu_freq_invariance_counters();
1561 }
1562 }
1563
has_amu(const struct arm64_cpu_capabilities * cap,int __unused)1564 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1565 int __unused)
1566 {
1567 /*
1568 * The AMU extension is a non-conflicting feature: the kernel can
1569 * safely run a mix of CPUs with and without support for the
1570 * activity monitors extension. Therefore, unconditionally enable
1571 * the capability to allow any late CPU to use the feature.
1572 *
1573 * With this feature unconditionally enabled, the cpu_enable
1574 * function will be called for all CPUs that match the criteria,
1575 * including secondary and hotplugged, marking this feature as
1576 * present on that respective CPU. The enable function will also
1577 * print a detection message.
1578 */
1579
1580 return true;
1581 }
1582 #endif
1583
1584 #ifdef CONFIG_ARM64_VHE
runs_at_el2(const struct arm64_cpu_capabilities * entry,int __unused)1585 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1586 {
1587 return is_kernel_in_hyp_mode();
1588 }
1589
cpu_copy_el2regs(const struct arm64_cpu_capabilities * __unused)1590 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1591 {
1592 /*
1593 * Copy register values that aren't redirected by hardware.
1594 *
1595 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1596 * this value to tpidr_el2 before we patch the code. Once we've done
1597 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1598 * do anything here.
1599 */
1600 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1601 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1602 }
1603 #endif
1604
cpu_has_fwb(const struct arm64_cpu_capabilities * __unused)1605 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1606 {
1607 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1608
1609 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1610 WARN_ON(val & (7 << 27 | 7 << 21));
1611 }
1612
1613 #ifdef CONFIG_ARM64_PAN
cpu_enable_pan(const struct arm64_cpu_capabilities * __unused)1614 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1615 {
1616 /*
1617 * We modify PSTATE. This won't work from irq context as the PSTATE
1618 * is discarded once we return from the exception.
1619 */
1620 WARN_ON_ONCE(in_interrupt());
1621
1622 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1623 asm(SET_PSTATE_PAN(1));
1624 }
1625 #endif /* CONFIG_ARM64_PAN */
1626
1627 #ifdef CONFIG_ARM64_RAS_EXTN
cpu_clear_disr(const struct arm64_cpu_capabilities * __unused)1628 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1629 {
1630 /* Firmware may have left a deferred SError in this register. */
1631 write_sysreg_s(0, SYS_DISR_EL1);
1632 }
1633 #endif /* CONFIG_ARM64_RAS_EXTN */
1634
1635 #ifdef CONFIG_ARM64_PTR_AUTH
has_address_auth_cpucap(const struct arm64_cpu_capabilities * entry,int scope)1636 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1637 {
1638 int boot_val, sec_val;
1639
1640 /* We don't expect to be called with SCOPE_SYSTEM */
1641 WARN_ON(scope == SCOPE_SYSTEM);
1642 /*
1643 * The ptr-auth feature levels are not intercompatible with lower
1644 * levels. Hence we must match ptr-auth feature level of the secondary
1645 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1646 * from the sanitised register whereas direct register read is done for
1647 * the secondary CPUs.
1648 * The sanitised feature state is guaranteed to match that of the
1649 * boot CPU as a mismatched secondary CPU is parked before it gets
1650 * a chance to update the state, with the capability.
1651 */
1652 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1653 entry->field_pos, entry->sign);
1654 if (scope & SCOPE_BOOT_CPU)
1655 return boot_val >= entry->min_field_value;
1656 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
1657 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1658 entry->field_pos, entry->sign);
1659 return sec_val == boot_val;
1660 }
1661
has_address_auth_metacap(const struct arm64_cpu_capabilities * entry,int scope)1662 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1663 int scope)
1664 {
1665 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) ||
1666 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1667 }
1668
has_generic_auth(const struct arm64_cpu_capabilities * entry,int __unused)1669 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1670 int __unused)
1671 {
1672 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1673 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1674 }
1675 #endif /* CONFIG_ARM64_PTR_AUTH */
1676
1677 #ifdef CONFIG_ARM64_E0PD
cpu_enable_e0pd(struct arm64_cpu_capabilities const * cap)1678 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1679 {
1680 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1681 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1682 }
1683 #endif /* CONFIG_ARM64_E0PD */
1684
1685 #ifdef CONFIG_ARM64_PSEUDO_NMI
1686 static bool enable_pseudo_nmi;
1687
early_enable_pseudo_nmi(char * p)1688 static int __init early_enable_pseudo_nmi(char *p)
1689 {
1690 return strtobool(p, &enable_pseudo_nmi);
1691 }
1692 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1693
can_use_gic_priorities(const struct arm64_cpu_capabilities * entry,int scope)1694 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1695 int scope)
1696 {
1697 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1698 }
1699 #endif
1700
1701 #ifdef CONFIG_ARM64_BTI
bti_enable(const struct arm64_cpu_capabilities * __unused)1702 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1703 {
1704 /*
1705 * Use of X16/X17 for tail-calls and trampolines that jump to
1706 * function entry points using BR is a requirement for
1707 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
1708 * So, be strict and forbid other BRs using other registers to
1709 * jump onto a PACIxSP instruction:
1710 */
1711 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1712 isb();
1713 }
1714 #endif /* CONFIG_ARM64_BTI */
1715
1716 #ifdef CONFIG_ARM64_MTE
cpu_enable_mte(struct arm64_cpu_capabilities const * cap)1717 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
1718 {
1719 /*
1720 * Clear the tags in the zero page. This needs to be done via the
1721 * linear map which has the Tagged attribute.
1722 */
1723 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
1724 mte_clear_page_tags(lm_alias(empty_zero_page));
1725 }
1726 #endif /* CONFIG_ARM64_MTE */
1727
1728 /* Internal helper functions to match cpu capability type */
1729 static bool
cpucap_late_cpu_optional(const struct arm64_cpu_capabilities * cap)1730 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1731 {
1732 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1733 }
1734
1735 static bool
cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities * cap)1736 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1737 {
1738 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1739 }
1740
1741 static bool
cpucap_panic_on_conflict(const struct arm64_cpu_capabilities * cap)1742 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1743 {
1744 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1745 }
1746
1747 static const struct arm64_cpu_capabilities arm64_features[] = {
1748 {
1749 .desc = "GIC system register CPU interface",
1750 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1751 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1752 .matches = has_useable_gicv3_cpuif,
1753 .sys_reg = SYS_ID_AA64PFR0_EL1,
1754 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1755 .sign = FTR_UNSIGNED,
1756 .min_field_value = 1,
1757 },
1758 #ifdef CONFIG_ARM64_PAN
1759 {
1760 .desc = "Privileged Access Never",
1761 .capability = ARM64_HAS_PAN,
1762 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1763 .matches = has_cpuid_feature,
1764 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1765 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1766 .sign = FTR_UNSIGNED,
1767 .min_field_value = 1,
1768 .cpu_enable = cpu_enable_pan,
1769 },
1770 #endif /* CONFIG_ARM64_PAN */
1771 #ifdef CONFIG_ARM64_LSE_ATOMICS
1772 {
1773 .desc = "LSE atomic instructions",
1774 .capability = ARM64_HAS_LSE_ATOMICS,
1775 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1776 .matches = has_cpuid_feature,
1777 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1778 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1779 .sign = FTR_UNSIGNED,
1780 .min_field_value = 2,
1781 },
1782 #endif /* CONFIG_ARM64_LSE_ATOMICS */
1783 {
1784 .desc = "Software prefetching using PRFM",
1785 .capability = ARM64_HAS_NO_HW_PREFETCH,
1786 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1787 .matches = has_no_hw_prefetch,
1788 },
1789 #ifdef CONFIG_ARM64_UAO
1790 {
1791 .desc = "User Access Override",
1792 .capability = ARM64_HAS_UAO,
1793 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1794 .matches = has_cpuid_feature,
1795 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1796 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1797 .min_field_value = 1,
1798 /*
1799 * We rely on stop_machine() calling uao_thread_switch() to set
1800 * UAO immediately after patching.
1801 */
1802 },
1803 #endif /* CONFIG_ARM64_UAO */
1804 #ifdef CONFIG_ARM64_PAN
1805 {
1806 .capability = ARM64_ALT_PAN_NOT_UAO,
1807 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1808 .matches = cpufeature_pan_not_uao,
1809 },
1810 #endif /* CONFIG_ARM64_PAN */
1811 #ifdef CONFIG_ARM64_VHE
1812 {
1813 .desc = "Virtualization Host Extensions",
1814 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1815 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1816 .matches = runs_at_el2,
1817 .cpu_enable = cpu_copy_el2regs,
1818 },
1819 #endif /* CONFIG_ARM64_VHE */
1820 {
1821 .desc = "32-bit EL0 Support",
1822 .capability = ARM64_HAS_32BIT_EL0,
1823 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1824 .matches = has_cpuid_feature,
1825 .sys_reg = SYS_ID_AA64PFR0_EL1,
1826 .sign = FTR_UNSIGNED,
1827 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1828 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1829 },
1830 #ifdef CONFIG_KVM
1831 {
1832 .desc = "32-bit EL1 Support",
1833 .capability = ARM64_HAS_32BIT_EL1,
1834 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1835 .matches = has_cpuid_feature,
1836 .sys_reg = SYS_ID_AA64PFR0_EL1,
1837 .sign = FTR_UNSIGNED,
1838 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1839 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1840 },
1841 #endif
1842 {
1843 .desc = "Kernel page table isolation (KPTI)",
1844 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1845 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1846 /*
1847 * The ID feature fields below are used to indicate that
1848 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1849 * more details.
1850 */
1851 .sys_reg = SYS_ID_AA64PFR0_EL1,
1852 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1853 .min_field_value = 1,
1854 .matches = unmap_kernel_at_el0,
1855 .cpu_enable = kpti_install_ng_mappings,
1856 },
1857 {
1858 /* FP/SIMD is not implemented */
1859 .capability = ARM64_HAS_NO_FPSIMD,
1860 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1861 .min_field_value = 0,
1862 .matches = has_no_fpsimd,
1863 },
1864 #ifdef CONFIG_ARM64_PMEM
1865 {
1866 .desc = "Data cache clean to Point of Persistence",
1867 .capability = ARM64_HAS_DCPOP,
1868 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1869 .matches = has_cpuid_feature,
1870 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1871 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1872 .min_field_value = 1,
1873 },
1874 {
1875 .desc = "Data cache clean to Point of Deep Persistence",
1876 .capability = ARM64_HAS_DCPODP,
1877 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1878 .matches = has_cpuid_feature,
1879 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1880 .sign = FTR_UNSIGNED,
1881 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1882 .min_field_value = 2,
1883 },
1884 #endif
1885 #ifdef CONFIG_ARM64_SVE
1886 {
1887 .desc = "Scalable Vector Extension",
1888 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1889 .capability = ARM64_SVE,
1890 .sys_reg = SYS_ID_AA64PFR0_EL1,
1891 .sign = FTR_UNSIGNED,
1892 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1893 .min_field_value = ID_AA64PFR0_SVE,
1894 .matches = has_cpuid_feature,
1895 .cpu_enable = sve_kernel_enable,
1896 },
1897 #endif /* CONFIG_ARM64_SVE */
1898 #ifdef CONFIG_ARM64_RAS_EXTN
1899 {
1900 .desc = "RAS Extension Support",
1901 .capability = ARM64_HAS_RAS_EXTN,
1902 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1903 .matches = has_cpuid_feature,
1904 .sys_reg = SYS_ID_AA64PFR0_EL1,
1905 .sign = FTR_UNSIGNED,
1906 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1907 .min_field_value = ID_AA64PFR0_RAS_V1,
1908 .cpu_enable = cpu_clear_disr,
1909 },
1910 #endif /* CONFIG_ARM64_RAS_EXTN */
1911 #ifdef CONFIG_ARM64_AMU_EXTN
1912 {
1913 /*
1914 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1915 * Therefore, don't provide .desc as we don't want the detection
1916 * message to be shown until at least one CPU is detected to
1917 * support the feature.
1918 */
1919 .capability = ARM64_HAS_AMU_EXTN,
1920 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1921 .matches = has_amu,
1922 .sys_reg = SYS_ID_AA64PFR0_EL1,
1923 .sign = FTR_UNSIGNED,
1924 .field_pos = ID_AA64PFR0_AMU_SHIFT,
1925 .min_field_value = ID_AA64PFR0_AMU,
1926 .cpu_enable = cpu_amu_enable,
1927 },
1928 #endif /* CONFIG_ARM64_AMU_EXTN */
1929 {
1930 .desc = "Data cache clean to the PoU not required for I/D coherence",
1931 .capability = ARM64_HAS_CACHE_IDC,
1932 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1933 .matches = has_cache_idc,
1934 .cpu_enable = cpu_emulate_effective_ctr,
1935 },
1936 {
1937 .desc = "Instruction cache invalidation not required for I/D coherence",
1938 .capability = ARM64_HAS_CACHE_DIC,
1939 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1940 .matches = has_cache_dic,
1941 },
1942 {
1943 .desc = "Stage-2 Force Write-Back",
1944 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1945 .capability = ARM64_HAS_STAGE2_FWB,
1946 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1947 .sign = FTR_UNSIGNED,
1948 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1949 .min_field_value = 1,
1950 .matches = has_cpuid_feature,
1951 .cpu_enable = cpu_has_fwb,
1952 },
1953 {
1954 .desc = "ARMv8.4 Translation Table Level",
1955 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1956 .capability = ARM64_HAS_ARMv8_4_TTL,
1957 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1958 .sign = FTR_UNSIGNED,
1959 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
1960 .min_field_value = 1,
1961 .matches = has_cpuid_feature,
1962 },
1963 {
1964 .desc = "TLB range maintenance instructions",
1965 .capability = ARM64_HAS_TLB_RANGE,
1966 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1967 .matches = has_cpuid_feature,
1968 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1969 .field_pos = ID_AA64ISAR0_TLB_SHIFT,
1970 .sign = FTR_UNSIGNED,
1971 .min_field_value = ID_AA64ISAR0_TLB_RANGE,
1972 },
1973 #ifdef CONFIG_ARM64_HW_AFDBM
1974 {
1975 /*
1976 * Since we turn this on always, we don't want the user to
1977 * think that the feature is available when it may not be.
1978 * So hide the description.
1979 *
1980 * .desc = "Hardware pagetable Dirty Bit Management",
1981 *
1982 */
1983 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1984 .capability = ARM64_HW_DBM,
1985 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1986 .sign = FTR_UNSIGNED,
1987 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1988 .min_field_value = 2,
1989 .matches = has_hw_dbm,
1990 .cpu_enable = cpu_enable_hw_dbm,
1991 },
1992 #endif
1993 {
1994 .desc = "CRC32 instructions",
1995 .capability = ARM64_HAS_CRC32,
1996 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1997 .matches = has_cpuid_feature,
1998 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1999 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
2000 .min_field_value = 1,
2001 },
2002 {
2003 .desc = "Speculative Store Bypassing Safe (SSBS)",
2004 .capability = ARM64_SSBS,
2005 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2006 .matches = has_cpuid_feature,
2007 .sys_reg = SYS_ID_AA64PFR1_EL1,
2008 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2009 .sign = FTR_UNSIGNED,
2010 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2011 },
2012 #ifdef CONFIG_ARM64_CNP
2013 {
2014 .desc = "Common not Private translations",
2015 .capability = ARM64_HAS_CNP,
2016 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2017 .matches = has_useable_cnp,
2018 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2019 .sign = FTR_UNSIGNED,
2020 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2021 .min_field_value = 1,
2022 .cpu_enable = cpu_enable_cnp,
2023 },
2024 #endif
2025 {
2026 .desc = "Speculation barrier (SB)",
2027 .capability = ARM64_HAS_SB,
2028 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2029 .matches = has_cpuid_feature,
2030 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2031 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2032 .sign = FTR_UNSIGNED,
2033 .min_field_value = 1,
2034 },
2035 #ifdef CONFIG_ARM64_PTR_AUTH
2036 {
2037 .desc = "Address authentication (architected algorithm)",
2038 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
2039 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2040 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2041 .sign = FTR_UNSIGNED,
2042 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2043 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2044 .matches = has_address_auth_cpucap,
2045 },
2046 {
2047 .desc = "Address authentication (IMP DEF algorithm)",
2048 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2049 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2050 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2051 .sign = FTR_UNSIGNED,
2052 .field_pos = ID_AA64ISAR1_API_SHIFT,
2053 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2054 .matches = has_address_auth_cpucap,
2055 },
2056 {
2057 .capability = ARM64_HAS_ADDRESS_AUTH,
2058 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2059 .matches = has_address_auth_metacap,
2060 },
2061 {
2062 .desc = "Generic authentication (architected algorithm)",
2063 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
2064 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2065 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2066 .sign = FTR_UNSIGNED,
2067 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2068 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2069 .matches = has_cpuid_feature,
2070 },
2071 {
2072 .desc = "Generic authentication (IMP DEF algorithm)",
2073 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2074 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2075 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2076 .sign = FTR_UNSIGNED,
2077 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2078 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2079 .matches = has_cpuid_feature,
2080 },
2081 {
2082 .capability = ARM64_HAS_GENERIC_AUTH,
2083 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2084 .matches = has_generic_auth,
2085 },
2086 #endif /* CONFIG_ARM64_PTR_AUTH */
2087 #ifdef CONFIG_ARM64_PSEUDO_NMI
2088 {
2089 /*
2090 * Depends on having GICv3
2091 */
2092 .desc = "IRQ priority masking",
2093 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2094 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2095 .matches = can_use_gic_priorities,
2096 .sys_reg = SYS_ID_AA64PFR0_EL1,
2097 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2098 .sign = FTR_UNSIGNED,
2099 .min_field_value = 1,
2100 },
2101 #endif
2102 #ifdef CONFIG_ARM64_E0PD
2103 {
2104 .desc = "E0PD",
2105 .capability = ARM64_HAS_E0PD,
2106 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2107 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2108 .sign = FTR_UNSIGNED,
2109 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2110 .matches = has_cpuid_feature,
2111 .min_field_value = 1,
2112 .cpu_enable = cpu_enable_e0pd,
2113 },
2114 #endif
2115 #ifdef CONFIG_ARCH_RANDOM
2116 {
2117 .desc = "Random Number Generator",
2118 .capability = ARM64_HAS_RNG,
2119 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2120 .matches = has_cpuid_feature,
2121 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2122 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
2123 .sign = FTR_UNSIGNED,
2124 .min_field_value = 1,
2125 },
2126 #endif
2127 #ifdef CONFIG_ARM64_BTI
2128 {
2129 .desc = "Branch Target Identification",
2130 .capability = ARM64_BTI,
2131 #ifdef CONFIG_ARM64_BTI_KERNEL
2132 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2133 #else
2134 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2135 #endif
2136 .matches = has_cpuid_feature,
2137 .cpu_enable = bti_enable,
2138 .sys_reg = SYS_ID_AA64PFR1_EL1,
2139 .field_pos = ID_AA64PFR1_BT_SHIFT,
2140 .min_field_value = ID_AA64PFR1_BT_BTI,
2141 .sign = FTR_UNSIGNED,
2142 },
2143 #endif
2144 #ifdef CONFIG_ARM64_MTE
2145 {
2146 .desc = "Memory Tagging Extension",
2147 .capability = ARM64_MTE,
2148 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2149 .matches = has_cpuid_feature,
2150 .sys_reg = SYS_ID_AA64PFR1_EL1,
2151 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2152 .min_field_value = ID_AA64PFR1_MTE,
2153 .sign = FTR_UNSIGNED,
2154 .cpu_enable = cpu_enable_mte,
2155 },
2156 #endif /* CONFIG_ARM64_MTE */
2157 {},
2158 };
2159
2160 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2161 .matches = has_cpuid_feature, \
2162 .sys_reg = reg, \
2163 .field_pos = field, \
2164 .sign = s, \
2165 .min_field_value = min_value,
2166
2167 #define __HWCAP_CAP(name, cap_type, cap) \
2168 .desc = name, \
2169 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2170 .hwcap_type = cap_type, \
2171 .hwcap = cap, \
2172
2173 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
2174 { \
2175 __HWCAP_CAP(#cap, cap_type, cap) \
2176 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2177 }
2178
2179 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2180 { \
2181 __HWCAP_CAP(#cap, cap_type, cap) \
2182 .matches = cpucap_multi_entry_cap_matches, \
2183 .match_list = list, \
2184 }
2185
2186 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2187 { \
2188 __HWCAP_CAP(#cap, cap_type, cap) \
2189 .matches = match, \
2190 }
2191
2192 #ifdef CONFIG_ARM64_PTR_AUTH
2193 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2194 {
2195 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2196 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2197 },
2198 {
2199 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2200 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2201 },
2202 {},
2203 };
2204
2205 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2206 {
2207 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2208 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2209 },
2210 {
2211 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2212 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2213 },
2214 {},
2215 };
2216 #endif
2217
2218 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2219 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2220 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2221 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2222 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2223 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2224 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2225 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2226 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2227 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2228 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2229 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2230 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2231 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2232 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2233 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2234 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2235 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2236 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2237 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2238 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2239 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2240 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2241 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2242 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2243 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2244 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2245 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2246 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2247 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2248 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2249 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2250 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2251 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2252 #ifdef CONFIG_ARM64_SVE
2253 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2254 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2255 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2256 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2257 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2258 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2259 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2260 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2261 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2262 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2263 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2264 #endif
2265 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2266 #ifdef CONFIG_ARM64_BTI
2267 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2268 #endif
2269 #ifdef CONFIG_ARM64_PTR_AUTH
2270 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2271 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2272 #endif
2273 #ifdef CONFIG_ARM64_MTE
2274 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2275 #endif /* CONFIG_ARM64_MTE */
2276 {},
2277 };
2278
2279 #ifdef CONFIG_COMPAT
compat_has_neon(const struct arm64_cpu_capabilities * cap,int scope)2280 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2281 {
2282 /*
2283 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2284 * in line with that of arm32 as in vfp_init(). We make sure that the
2285 * check is future proof, by making sure value is non-zero.
2286 */
2287 u32 mvfr1;
2288
2289 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2290 if (scope == SCOPE_SYSTEM)
2291 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2292 else
2293 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2294
2295 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2296 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2297 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2298 }
2299 #endif
2300
2301 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2302 #ifdef CONFIG_COMPAT
2303 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2304 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2305 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2306 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2307 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2308 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2309 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2310 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2311 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2312 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2313 #endif
2314 {},
2315 };
2316
cap_set_elf_hwcap(const struct arm64_cpu_capabilities * cap)2317 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2318 {
2319 switch (cap->hwcap_type) {
2320 case CAP_HWCAP:
2321 cpu_set_feature(cap->hwcap);
2322 break;
2323 #ifdef CONFIG_COMPAT
2324 case CAP_COMPAT_HWCAP:
2325 compat_elf_hwcap |= (u32)cap->hwcap;
2326 break;
2327 case CAP_COMPAT_HWCAP2:
2328 compat_elf_hwcap2 |= (u32)cap->hwcap;
2329 break;
2330 #endif
2331 default:
2332 WARN_ON(1);
2333 break;
2334 }
2335 }
2336
2337 /* Check if we have a particular HWCAP enabled */
cpus_have_elf_hwcap(const struct arm64_cpu_capabilities * cap)2338 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2339 {
2340 bool rc;
2341
2342 switch (cap->hwcap_type) {
2343 case CAP_HWCAP:
2344 rc = cpu_have_feature(cap->hwcap);
2345 break;
2346 #ifdef CONFIG_COMPAT
2347 case CAP_COMPAT_HWCAP:
2348 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2349 break;
2350 case CAP_COMPAT_HWCAP2:
2351 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2352 break;
2353 #endif
2354 default:
2355 WARN_ON(1);
2356 rc = false;
2357 }
2358
2359 return rc;
2360 }
2361
setup_elf_hwcaps(const struct arm64_cpu_capabilities * hwcaps)2362 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2363 {
2364 /* We support emulation of accesses to CPU ID feature registers */
2365 cpu_set_named_feature(CPUID);
2366 for (; hwcaps->matches; hwcaps++)
2367 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2368 cap_set_elf_hwcap(hwcaps);
2369 }
2370
update_cpu_capabilities(u16 scope_mask)2371 static void update_cpu_capabilities(u16 scope_mask)
2372 {
2373 int i;
2374 const struct arm64_cpu_capabilities *caps;
2375
2376 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2377 for (i = 0; i < ARM64_NCAPS; i++) {
2378 caps = cpu_hwcaps_ptrs[i];
2379 if (!caps || !(caps->type & scope_mask) ||
2380 cpus_have_cap(caps->capability) ||
2381 !caps->matches(caps, cpucap_default_scope(caps)))
2382 continue;
2383
2384 if (caps->desc)
2385 pr_info("detected: %s\n", caps->desc);
2386 cpus_set_cap(caps->capability);
2387
2388 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2389 set_bit(caps->capability, boot_capabilities);
2390 }
2391 }
2392
2393 /*
2394 * Enable all the available capabilities on this CPU. The capabilities
2395 * with BOOT_CPU scope are handled separately and hence skipped here.
2396 */
cpu_enable_non_boot_scope_capabilities(void * __unused)2397 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2398 {
2399 int i;
2400 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2401
2402 for_each_available_cap(i) {
2403 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2404
2405 if (WARN_ON(!cap))
2406 continue;
2407
2408 if (!(cap->type & non_boot_scope))
2409 continue;
2410
2411 if (cap->cpu_enable)
2412 cap->cpu_enable(cap);
2413 }
2414 return 0;
2415 }
2416
2417 /*
2418 * Run through the enabled capabilities and enable() it on all active
2419 * CPUs
2420 */
enable_cpu_capabilities(u16 scope_mask)2421 static void __init enable_cpu_capabilities(u16 scope_mask)
2422 {
2423 int i;
2424 const struct arm64_cpu_capabilities *caps;
2425 bool boot_scope;
2426
2427 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2428 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2429
2430 for (i = 0; i < ARM64_NCAPS; i++) {
2431 unsigned int num;
2432
2433 caps = cpu_hwcaps_ptrs[i];
2434 if (!caps || !(caps->type & scope_mask))
2435 continue;
2436 num = caps->capability;
2437 if (!cpus_have_cap(num))
2438 continue;
2439
2440 /* Ensure cpus_have_const_cap(num) works */
2441 static_branch_enable(&cpu_hwcap_keys[num]);
2442
2443 if (boot_scope && caps->cpu_enable)
2444 /*
2445 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2446 * before any secondary CPU boots. Thus, each secondary
2447 * will enable the capability as appropriate via
2448 * check_local_cpu_capabilities(). The only exception is
2449 * the boot CPU, for which the capability must be
2450 * enabled here. This approach avoids costly
2451 * stop_machine() calls for this case.
2452 */
2453 caps->cpu_enable(caps);
2454 }
2455
2456 /*
2457 * For all non-boot scope capabilities, use stop_machine()
2458 * as it schedules the work allowing us to modify PSTATE,
2459 * instead of on_each_cpu() which uses an IPI, giving us a
2460 * PSTATE that disappears when we return.
2461 */
2462 if (!boot_scope)
2463 stop_machine(cpu_enable_non_boot_scope_capabilities,
2464 NULL, cpu_online_mask);
2465 }
2466
2467 /*
2468 * Run through the list of capabilities to check for conflicts.
2469 * If the system has already detected a capability, take necessary
2470 * action on this CPU.
2471 */
verify_local_cpu_caps(u16 scope_mask)2472 static void verify_local_cpu_caps(u16 scope_mask)
2473 {
2474 int i;
2475 bool cpu_has_cap, system_has_cap;
2476 const struct arm64_cpu_capabilities *caps;
2477
2478 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2479
2480 for (i = 0; i < ARM64_NCAPS; i++) {
2481 caps = cpu_hwcaps_ptrs[i];
2482 if (!caps || !(caps->type & scope_mask))
2483 continue;
2484
2485 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2486 system_has_cap = cpus_have_cap(caps->capability);
2487
2488 if (system_has_cap) {
2489 /*
2490 * Check if the new CPU misses an advertised feature,
2491 * which is not safe to miss.
2492 */
2493 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2494 break;
2495 /*
2496 * We have to issue cpu_enable() irrespective of
2497 * whether the CPU has it or not, as it is enabeld
2498 * system wide. It is upto the call back to take
2499 * appropriate action on this CPU.
2500 */
2501 if (caps->cpu_enable)
2502 caps->cpu_enable(caps);
2503 } else {
2504 /*
2505 * Check if the CPU has this capability if it isn't
2506 * safe to have when the system doesn't.
2507 */
2508 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2509 break;
2510 }
2511 }
2512
2513 if (i < ARM64_NCAPS) {
2514 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2515 smp_processor_id(), caps->capability,
2516 caps->desc, system_has_cap, cpu_has_cap);
2517
2518 if (cpucap_panic_on_conflict(caps))
2519 cpu_panic_kernel();
2520 else
2521 cpu_die_early();
2522 }
2523 }
2524
2525 /*
2526 * Check for CPU features that are used in early boot
2527 * based on the Boot CPU value.
2528 */
check_early_cpu_features(void)2529 static void check_early_cpu_features(void)
2530 {
2531 verify_cpu_asid_bits();
2532
2533 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2534 }
2535
2536 static void
verify_local_elf_hwcaps(const struct arm64_cpu_capabilities * caps)2537 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2538 {
2539
2540 for (; caps->matches; caps++)
2541 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2542 pr_crit("CPU%d: missing HWCAP: %s\n",
2543 smp_processor_id(), caps->desc);
2544 cpu_die_early();
2545 }
2546 }
2547
verify_sve_features(void)2548 static void verify_sve_features(void)
2549 {
2550 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2551 u64 zcr = read_zcr_features();
2552
2553 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2554 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2555
2556 if (len < safe_len || sve_verify_vq_map()) {
2557 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2558 smp_processor_id());
2559 cpu_die_early();
2560 }
2561
2562 /* Add checks on other ZCR bits here if necessary */
2563 }
2564
verify_hyp_capabilities(void)2565 static void verify_hyp_capabilities(void)
2566 {
2567 u64 safe_mmfr1, mmfr0, mmfr1;
2568 int parange, ipa_max;
2569 unsigned int safe_vmid_bits, vmid_bits;
2570
2571 if (!IS_ENABLED(CONFIG_KVM))
2572 return;
2573
2574 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2575 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2576 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2577
2578 /* Verify VMID bits */
2579 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2580 vmid_bits = get_vmid_bits(mmfr1);
2581 if (vmid_bits < safe_vmid_bits) {
2582 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2583 cpu_die_early();
2584 }
2585
2586 /* Verify IPA range */
2587 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2588 ID_AA64MMFR0_PARANGE_SHIFT);
2589 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2590 if (ipa_max < get_kvm_ipa_limit()) {
2591 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2592 cpu_die_early();
2593 }
2594 }
2595
2596 /*
2597 * Run through the enabled system capabilities and enable() it on this CPU.
2598 * The capabilities were decided based on the available CPUs at the boot time.
2599 * Any new CPU should match the system wide status of the capability. If the
2600 * new CPU doesn't have a capability which the system now has enabled, we
2601 * cannot do anything to fix it up and could cause unexpected failures. So
2602 * we park the CPU.
2603 */
verify_local_cpu_capabilities(void)2604 static void verify_local_cpu_capabilities(void)
2605 {
2606 /*
2607 * The capabilities with SCOPE_BOOT_CPU are checked from
2608 * check_early_cpu_features(), as they need to be verified
2609 * on all secondary CPUs.
2610 */
2611 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2612
2613 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2614
2615 if (system_supports_32bit_el0())
2616 verify_local_elf_hwcaps(compat_elf_hwcaps);
2617
2618 if (system_supports_sve())
2619 verify_sve_features();
2620
2621 if (is_hyp_mode_available())
2622 verify_hyp_capabilities();
2623 }
2624
check_local_cpu_capabilities(void)2625 void check_local_cpu_capabilities(void)
2626 {
2627 /*
2628 * All secondary CPUs should conform to the early CPU features
2629 * in use by the kernel based on boot CPU.
2630 */
2631 check_early_cpu_features();
2632
2633 /*
2634 * If we haven't finalised the system capabilities, this CPU gets
2635 * a chance to update the errata work arounds and local features.
2636 * Otherwise, this CPU should verify that it has all the system
2637 * advertised capabilities.
2638 */
2639 if (!system_capabilities_finalized())
2640 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2641 else
2642 verify_local_cpu_capabilities();
2643 }
2644
setup_boot_cpu_capabilities(void)2645 static void __init setup_boot_cpu_capabilities(void)
2646 {
2647 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2648 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2649 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2650 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2651 }
2652
this_cpu_has_cap(unsigned int n)2653 bool this_cpu_has_cap(unsigned int n)
2654 {
2655 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2656 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2657
2658 if (cap)
2659 return cap->matches(cap, SCOPE_LOCAL_CPU);
2660 }
2661
2662 return false;
2663 }
2664
2665 /*
2666 * This helper function is used in a narrow window when,
2667 * - The system wide safe registers are set with all the SMP CPUs and,
2668 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2669 * In all other cases cpus_have_{const_}cap() should be used.
2670 */
__system_matches_cap(unsigned int n)2671 static bool __system_matches_cap(unsigned int n)
2672 {
2673 if (n < ARM64_NCAPS) {
2674 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2675
2676 if (cap)
2677 return cap->matches(cap, SCOPE_SYSTEM);
2678 }
2679 return false;
2680 }
2681
cpu_set_feature(unsigned int num)2682 void cpu_set_feature(unsigned int num)
2683 {
2684 WARN_ON(num >= MAX_CPU_FEATURES);
2685 elf_hwcap |= BIT(num);
2686 }
2687 EXPORT_SYMBOL_GPL(cpu_set_feature);
2688
cpu_have_feature(unsigned int num)2689 bool cpu_have_feature(unsigned int num)
2690 {
2691 WARN_ON(num >= MAX_CPU_FEATURES);
2692 return elf_hwcap & BIT(num);
2693 }
2694 EXPORT_SYMBOL_GPL(cpu_have_feature);
2695
cpu_get_elf_hwcap(void)2696 unsigned long cpu_get_elf_hwcap(void)
2697 {
2698 /*
2699 * We currently only populate the first 32 bits of AT_HWCAP. Please
2700 * note that for userspace compatibility we guarantee that bits 62
2701 * and 63 will always be returned as 0.
2702 */
2703 return lower_32_bits(elf_hwcap);
2704 }
2705
cpu_get_elf_hwcap2(void)2706 unsigned long cpu_get_elf_hwcap2(void)
2707 {
2708 return upper_32_bits(elf_hwcap);
2709 }
2710
setup_system_capabilities(void)2711 static void __init setup_system_capabilities(void)
2712 {
2713 /*
2714 * We have finalised the system-wide safe feature
2715 * registers, finalise the capabilities that depend
2716 * on it. Also enable all the available capabilities,
2717 * that are not enabled already.
2718 */
2719 update_cpu_capabilities(SCOPE_SYSTEM);
2720 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2721 }
2722
setup_cpu_features(void)2723 void __init setup_cpu_features(void)
2724 {
2725 u32 cwg;
2726
2727 setup_system_capabilities();
2728 setup_elf_hwcaps(arm64_elf_hwcaps);
2729
2730 if (system_supports_32bit_el0())
2731 setup_elf_hwcaps(compat_elf_hwcaps);
2732
2733 if (system_uses_ttbr0_pan())
2734 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2735
2736 sve_setup();
2737 minsigstksz_setup();
2738
2739 /* Advertise that we have computed the system capabilities */
2740 finalize_system_capabilities();
2741
2742 /*
2743 * Check for sane CTR_EL0.CWG value.
2744 */
2745 cwg = cache_type_cwg();
2746 if (!cwg)
2747 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2748 ARCH_DMA_MINALIGN);
2749 }
2750
2751 static bool __maybe_unused
cpufeature_pan_not_uao(const struct arm64_cpu_capabilities * entry,int __unused)2752 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2753 {
2754 return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO));
2755 }
2756
cpu_enable_cnp(struct arm64_cpu_capabilities const * cap)2757 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2758 {
2759 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2760 }
2761
2762 /*
2763 * We emulate only the following system register space.
2764 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2765 * See Table C5-6 System instruction encodings for System register accesses,
2766 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2767 */
is_emulated(u32 id)2768 static inline bool __attribute_const__ is_emulated(u32 id)
2769 {
2770 return (sys_reg_Op0(id) == 0x3 &&
2771 sys_reg_CRn(id) == 0x0 &&
2772 sys_reg_Op1(id) == 0x0 &&
2773 (sys_reg_CRm(id) == 0 ||
2774 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2775 }
2776
2777 /*
2778 * With CRm == 0, reg should be one of :
2779 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2780 */
emulate_id_reg(u32 id,u64 * valp)2781 static inline int emulate_id_reg(u32 id, u64 *valp)
2782 {
2783 switch (id) {
2784 case SYS_MIDR_EL1:
2785 *valp = read_cpuid_id();
2786 break;
2787 case SYS_MPIDR_EL1:
2788 *valp = SYS_MPIDR_SAFE_VAL;
2789 break;
2790 case SYS_REVIDR_EL1:
2791 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2792 *valp = 0;
2793 break;
2794 default:
2795 return -EINVAL;
2796 }
2797
2798 return 0;
2799 }
2800
emulate_sys_reg(u32 id,u64 * valp)2801 static int emulate_sys_reg(u32 id, u64 *valp)
2802 {
2803 struct arm64_ftr_reg *regp;
2804
2805 if (!is_emulated(id))
2806 return -EINVAL;
2807
2808 if (sys_reg_CRm(id) == 0)
2809 return emulate_id_reg(id, valp);
2810
2811 regp = get_arm64_ftr_reg_nowarn(id);
2812 if (regp)
2813 *valp = arm64_ftr_reg_user_value(regp);
2814 else
2815 /*
2816 * The untracked registers are either IMPLEMENTATION DEFINED
2817 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2818 */
2819 *valp = 0;
2820 return 0;
2821 }
2822
do_emulate_mrs(struct pt_regs * regs,u32 sys_reg,u32 rt)2823 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2824 {
2825 int rc;
2826 u64 val;
2827
2828 rc = emulate_sys_reg(sys_reg, &val);
2829 if (!rc) {
2830 pt_regs_write_reg(regs, rt, val);
2831 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2832 }
2833 return rc;
2834 }
2835
emulate_mrs(struct pt_regs * regs,u32 insn)2836 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2837 {
2838 u32 sys_reg, rt;
2839
2840 /*
2841 * sys_reg values are defined as used in mrs/msr instruction.
2842 * shift the imm value to get the encoding.
2843 */
2844 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2845 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2846 return do_emulate_mrs(regs, sys_reg, rt);
2847 }
2848
2849 static struct undef_hook mrs_hook = {
2850 .instr_mask = 0xfff00000,
2851 .instr_val = 0xd5300000,
2852 .pstate_mask = PSR_AA32_MODE_MASK,
2853 .pstate_val = PSR_MODE_EL0t,
2854 .fn = emulate_mrs,
2855 };
2856
enable_mrs_emulation(void)2857 static int __init enable_mrs_emulation(void)
2858 {
2859 register_undef_hook(&mrs_hook);
2860 return 0;
2861 }
2862
2863 core_initcall(enable_mrs_emulation);
2864
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)2865 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2866 char *buf)
2867 {
2868 if (__meltdown_safe)
2869 return sprintf(buf, "Not affected\n");
2870
2871 if (arm64_kernel_unmapped_at_el0())
2872 return sprintf(buf, "Mitigation: PTI\n");
2873
2874 return sprintf(buf, "Vulnerable\n");
2875 }
2876