1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "core_types.h"
28 #include "dc_dmub_srv.h"
29 #include "panel_cntl.h"
30 #include "dce_panel_cntl.h"
31 #include "atom.h"
32
33 #define TO_DCE_PANEL_CNTL(panel_cntl)\
34 container_of(panel_cntl, struct dce_panel_cntl, base)
35
36 #define CTX \
37 dce_panel_cntl->base.ctx
38
39 #define DC_LOGGER \
40 dce_panel_cntl->base.ctx->logger
41
42 #define REG(reg)\
43 dce_panel_cntl->regs->reg
44
45 #undef FN
46 #define FN(reg_name, field_name) \
47 dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name
48
dce_get_16_bit_backlight_from_pwm(struct panel_cntl * panel_cntl)49 static unsigned int dce_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
50 {
51 uint64_t current_backlight;
52 uint32_t round_result;
53 uint32_t pwm_period_cntl, bl_period, bl_int_count;
54 uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
55 uint32_t bl_period_mask, bl_pwm_mask;
56 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
57
58 pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
59 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
60 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
61
62 bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
63 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
64 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
65
66 if (bl_int_count == 0)
67 bl_int_count = 16;
68
69 bl_period_mask = (1 << bl_int_count) - 1;
70 bl_period &= bl_period_mask;
71
72 bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
73
74 if (fractional_duty_cycle_en == 0)
75 bl_pwm &= bl_pwm_mask;
76 else
77 bl_pwm &= 0xFFFF;
78
79 current_backlight = (uint64_t)bl_pwm << (1 + bl_int_count);
80
81 if (bl_period == 0)
82 bl_period = 0xFFFF;
83
84 current_backlight = div_u64(current_backlight, bl_period);
85 current_backlight = (current_backlight + 1) >> 1;
86
87 current_backlight = (uint64_t)(current_backlight) * bl_period;
88
89 round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
90
91 round_result = (round_result >> (bl_int_count-1)) & 1;
92
93 current_backlight >>= bl_int_count;
94 current_backlight += round_result;
95
96 return (uint32_t)(current_backlight);
97 }
98
dce_panel_cntl_hw_init(struct panel_cntl * panel_cntl)99 static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
100 {
101 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
102 uint32_t value;
103 uint32_t current_backlight;
104
105 /* It must not be 0, so we have to restore them
106 * Bios bug w/a - period resets to zero,
107 * restoring to cache values which is always correct
108 */
109 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
110
111 if (value == 0 || value == 1) {
112 if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) {
113 REG_WRITE(BL_PWM_CNTL,
114 panel_cntl->stored_backlight_registers.BL_PWM_CNTL);
115 REG_WRITE(BL_PWM_CNTL2,
116 panel_cntl->stored_backlight_registers.BL_PWM_CNTL2);
117 REG_WRITE(BL_PWM_PERIOD_CNTL,
118 panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
119 REG_UPDATE(PWRSEQ_REF_DIV,
120 BL_PWM_REF_DIV,
121 panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
122 } else {
123 /* TODO: Note: This should not really happen since VBIOS
124 * should have initialized PWM registers on boot.
125 */
126 REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
127 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
128 }
129 } else {
130 panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
131 REG_READ(BL_PWM_CNTL);
132 panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
133 REG_READ(BL_PWM_CNTL2);
134 panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
135 REG_READ(BL_PWM_PERIOD_CNTL);
136
137 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
138 &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
139 }
140
141 // Have driver take backlight control
142 // TakeBacklightControl(true)
143 value = REG_READ(BIOS_SCRATCH_2);
144 value |= ATOM_S2_VRI_BRIGHT_ENABLE;
145 REG_WRITE(BIOS_SCRATCH_2, value);
146
147 // Enable the backlight output
148 REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
149
150 // Unlock group 2 backlight registers
151 REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
152 BL_PWM_GRP1_REG_LOCK, 0);
153
154 current_backlight = dce_get_16_bit_backlight_from_pwm(panel_cntl);
155
156 return current_backlight;
157 }
158
dce_is_panel_backlight_on(struct panel_cntl * panel_cntl)159 static bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl)
160 {
161 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
162 uint32_t blon, blon_ovrd, pwrseq_target_state;
163
164 REG_GET_2(PWRSEQ_CNTL, LVTMA_BLON, &blon, LVTMA_BLON_OVRD, &blon_ovrd);
165 REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state);
166
167 if (blon_ovrd)
168 return blon;
169 else
170 return pwrseq_target_state;
171 }
172
dce_is_panel_powered_on(struct panel_cntl * panel_cntl)173 static bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl)
174 {
175 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
176 uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
177
178 REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
179
180 REG_GET_2(PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
181
182 return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
183 }
184
dce_store_backlight_level(struct panel_cntl * panel_cntl)185 static void dce_store_backlight_level(struct panel_cntl *panel_cntl)
186 {
187 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
188
189 panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
190 REG_READ(BL_PWM_CNTL);
191 panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
192 REG_READ(BL_PWM_CNTL2);
193 panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
194 REG_READ(BL_PWM_PERIOD_CNTL);
195
196 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
197 &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
198 }
199
dce_driver_set_backlight(struct panel_cntl * panel_cntl,uint32_t backlight_pwm_u16_16)200 static void dce_driver_set_backlight(struct panel_cntl *panel_cntl,
201 uint32_t backlight_pwm_u16_16)
202 {
203 uint32_t backlight_16bit;
204 uint32_t masked_pwm_period;
205 uint8_t bit_count;
206 uint64_t active_duty_cycle;
207 uint32_t pwm_period_bitcnt;
208 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
209
210 /*
211 * 1. Find 16 bit backlight active duty cycle, where 0 <= backlight
212 * active duty cycle <= backlight period
213 */
214
215 /* 1.1 Apply bitmask for backlight period value based on value of BITCNT
216 */
217 REG_GET_2(BL_PWM_PERIOD_CNTL,
218 BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,
219 BL_PWM_PERIOD, &masked_pwm_period);
220
221 if (pwm_period_bitcnt == 0)
222 bit_count = 16;
223 else
224 bit_count = pwm_period_bitcnt;
225
226 /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
227 masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
228
229 /* 1.2 Calculate integer active duty cycle required upper 16 bits
230 * contain integer component, lower 16 bits contain fractional component
231 * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
232 */
233 active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period;
234
235 /* 1.3 Calculate 16 bit active duty cycle from integer and fractional
236 * components shift by bitCount then mask 16 bits and add rounding bit
237 * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
238 */
239 backlight_16bit = active_duty_cycle >> bit_count;
240 backlight_16bit &= 0xFFFF;
241 backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
242
243 /*
244 * 2. Program register with updated value
245 */
246
247 /* 2.1 Lock group 2 backlight registers */
248
249 REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
250 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,
251 BL_PWM_GRP1_REG_LOCK, 1);
252
253 // 2.2 Write new active duty cycle
254 REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
255
256 /* 2.3 Unlock group 2 backlight registers */
257 REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
258 BL_PWM_GRP1_REG_LOCK, 0);
259
260 /* 3 Wait for pending bit to be cleared */
261 REG_WAIT(BL_PWM_GRP1_REG_LOCK,
262 BL_PWM_GRP1_REG_UPDATE_PENDING, 0,
263 1, 10000);
264 }
265
dce_panel_cntl_destroy(struct panel_cntl ** panel_cntl)266 static void dce_panel_cntl_destroy(struct panel_cntl **panel_cntl)
267 {
268 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(*panel_cntl);
269
270 kfree(dce_panel_cntl);
271 *panel_cntl = NULL;
272 }
273
274 static const struct panel_cntl_funcs dce_link_panel_cntl_funcs = {
275 .destroy = dce_panel_cntl_destroy,
276 .hw_init = dce_panel_cntl_hw_init,
277 .is_panel_backlight_on = dce_is_panel_backlight_on,
278 .is_panel_powered_on = dce_is_panel_powered_on,
279 .store_backlight_level = dce_store_backlight_level,
280 .driver_set_backlight = dce_driver_set_backlight,
281 .get_current_backlight = dce_get_16_bit_backlight_from_pwm,
282 };
283
dce_panel_cntl_construct(struct dce_panel_cntl * dce_panel_cntl,const struct panel_cntl_init_data * init_data,const struct dce_panel_cntl_registers * regs,const struct dce_panel_cntl_shift * shift,const struct dce_panel_cntl_mask * mask)284 void dce_panel_cntl_construct(
285 struct dce_panel_cntl *dce_panel_cntl,
286 const struct panel_cntl_init_data *init_data,
287 const struct dce_panel_cntl_registers *regs,
288 const struct dce_panel_cntl_shift *shift,
289 const struct dce_panel_cntl_mask *mask)
290 {
291 struct panel_cntl *base = &dce_panel_cntl->base;
292
293 base->stored_backlight_registers.BL_PWM_CNTL = 0;
294 base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
295 base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
296 base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0;
297
298 dce_panel_cntl->regs = regs;
299 dce_panel_cntl->shift = shift;
300 dce_panel_cntl->mask = mask;
301
302 dce_panel_cntl->base.funcs = &dce_link_panel_cntl_funcs;
303 dce_panel_cntl->base.ctx = init_data->ctx;
304 dce_panel_cntl->base.inst = init_data->inst;
305 }
306