1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
34
35 #include "core.h"
36 #include "gadget.h"
37 #include "io.h"
38
39 #include "debug.h"
40
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43 /**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
dwc3_get_dr_mode(struct dwc3 * dwc)47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
48 {
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103 }
104
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
106 {
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113
114 dwc->current_dr_role = mode;
115 }
116
117 static int dwc3_core_soft_reset(struct dwc3 *dwc);
118
__dwc3_set_mode(struct work_struct * work)119 static void __dwc3_set_mode(struct work_struct *work)
120 {
121 struct dwc3 *dwc = work_to_dwc(work);
122 unsigned long flags;
123 int ret;
124 u32 reg;
125
126 mutex_lock(&dwc->mutex);
127
128 pm_runtime_get_sync(dwc->dev);
129
130 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
131 dwc3_otg_update(dwc, 0);
132
133 if (!dwc->desired_dr_role)
134 goto out;
135
136 if (dwc->desired_dr_role == dwc->current_dr_role)
137 goto out;
138
139 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
140 goto out;
141
142 switch (dwc->current_dr_role) {
143 case DWC3_GCTL_PRTCAP_HOST:
144 dwc3_host_exit(dwc);
145 break;
146 case DWC3_GCTL_PRTCAP_DEVICE:
147 dwc3_gadget_exit(dwc);
148 dwc3_event_buffers_cleanup(dwc);
149 break;
150 case DWC3_GCTL_PRTCAP_OTG:
151 dwc3_otg_exit(dwc);
152 spin_lock_irqsave(&dwc->lock, flags);
153 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
154 spin_unlock_irqrestore(&dwc->lock, flags);
155 dwc3_otg_update(dwc, 1);
156 break;
157 default:
158 break;
159 }
160
161 /* For DRD host or device mode only */
162 if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) {
163 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
164 reg |= DWC3_GCTL_CORESOFTRESET;
165 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
166
167 /*
168 * Wait for internal clocks to synchronized. DWC_usb31 and
169 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
170 * keep it consistent across different IPs, let's wait up to
171 * 100ms before clearing GCTL.CORESOFTRESET.
172 */
173 msleep(100);
174
175 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
176 reg &= ~DWC3_GCTL_CORESOFTRESET;
177 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
178 }
179
180 spin_lock_irqsave(&dwc->lock, flags);
181
182 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
183
184 spin_unlock_irqrestore(&dwc->lock, flags);
185
186 switch (dwc->desired_dr_role) {
187 case DWC3_GCTL_PRTCAP_HOST:
188 ret = dwc3_host_init(dwc);
189 if (ret) {
190 dev_err(dwc->dev, "failed to initialize host\n");
191 } else {
192 if (dwc->usb2_phy)
193 otg_set_vbus(dwc->usb2_phy->otg, true);
194 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
195 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
196 if (dwc->dis_split_quirk) {
197 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
198 reg |= DWC3_GUCTL3_SPLITDISABLE;
199 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
200 }
201 }
202 break;
203 case DWC3_GCTL_PRTCAP_DEVICE:
204 dwc3_core_soft_reset(dwc);
205
206 dwc3_event_buffers_setup(dwc);
207
208 if (dwc->usb2_phy)
209 otg_set_vbus(dwc->usb2_phy->otg, false);
210 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
211 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
212
213 ret = dwc3_gadget_init(dwc);
214 if (ret)
215 dev_err(dwc->dev, "failed to initialize peripheral\n");
216 break;
217 case DWC3_GCTL_PRTCAP_OTG:
218 dwc3_otg_init(dwc);
219 dwc3_otg_update(dwc, 0);
220 break;
221 default:
222 break;
223 }
224
225 out:
226 pm_runtime_mark_last_busy(dwc->dev);
227 pm_runtime_put_autosuspend(dwc->dev);
228 mutex_unlock(&dwc->mutex);
229 }
230
dwc3_set_mode(struct dwc3 * dwc,u32 mode)231 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
232 {
233 unsigned long flags;
234
235 if (dwc->dr_mode != USB_DR_MODE_OTG)
236 return;
237
238 spin_lock_irqsave(&dwc->lock, flags);
239 dwc->desired_dr_role = mode;
240 spin_unlock_irqrestore(&dwc->lock, flags);
241
242 queue_work(system_freezable_wq, &dwc->drd_work);
243 }
244
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)245 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
246 {
247 struct dwc3 *dwc = dep->dwc;
248 u32 reg;
249
250 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
251 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
252 DWC3_GDBGFIFOSPACE_TYPE(type));
253
254 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
255
256 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
257 }
258
259 /**
260 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
261 * @dwc: pointer to our context structure
262 */
dwc3_core_soft_reset(struct dwc3 * dwc)263 static int dwc3_core_soft_reset(struct dwc3 *dwc)
264 {
265 u32 reg;
266 int retries = 1000;
267
268 /*
269 * We're resetting only the device side because, if we're in host mode,
270 * XHCI driver will reset the host block. If dwc3 was configured for
271 * host-only mode, then we can return early.
272 */
273 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
274 return 0;
275
276 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
277 reg |= DWC3_DCTL_CSFTRST;
278 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
279
280 /*
281 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
282 * is cleared only after all the clocks are synchronized. This can
283 * take a little more than 50ms. Set the polling rate at 20ms
284 * for 10 times instead.
285 */
286 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
287 retries = 10;
288
289 do {
290 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
291 if (!(reg & DWC3_DCTL_CSFTRST))
292 goto done;
293
294 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
295 msleep(20);
296 else
297 udelay(1);
298 } while (--retries);
299
300 return -ETIMEDOUT;
301
302 done:
303 /*
304 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
305 * is cleared, we must wait at least 50ms before accessing the PHY
306 * domain (synchronization delay).
307 */
308 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
309 msleep(50);
310
311 return 0;
312 }
313
314 /*
315 * dwc3_frame_length_adjustment - Adjusts frame length if required
316 * @dwc3: Pointer to our controller context structure
317 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)318 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
319 {
320 u32 reg;
321 u32 dft;
322
323 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
324 return;
325
326 if (dwc->fladj == 0)
327 return;
328
329 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
330 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
331 if (dft != dwc->fladj) {
332 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
333 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
334 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
335 }
336 }
337
338 /**
339 * dwc3_free_one_event_buffer - Frees one event buffer
340 * @dwc: Pointer to our controller context structure
341 * @evt: Pointer to event buffer to be freed
342 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)343 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
344 struct dwc3_event_buffer *evt)
345 {
346 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
347 }
348
349 /**
350 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
351 * @dwc: Pointer to our controller context structure
352 * @length: size of the event buffer
353 *
354 * Returns a pointer to the allocated event buffer structure on success
355 * otherwise ERR_PTR(errno).
356 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)357 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
358 unsigned length)
359 {
360 struct dwc3_event_buffer *evt;
361
362 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
363 if (!evt)
364 return ERR_PTR(-ENOMEM);
365
366 evt->dwc = dwc;
367 evt->length = length;
368 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
369 if (!evt->cache)
370 return ERR_PTR(-ENOMEM);
371
372 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
373 &evt->dma, GFP_KERNEL);
374 if (!evt->buf)
375 return ERR_PTR(-ENOMEM);
376
377 return evt;
378 }
379
380 /**
381 * dwc3_free_event_buffers - frees all allocated event buffers
382 * @dwc: Pointer to our controller context structure
383 */
dwc3_free_event_buffers(struct dwc3 * dwc)384 static void dwc3_free_event_buffers(struct dwc3 *dwc)
385 {
386 struct dwc3_event_buffer *evt;
387
388 evt = dwc->ev_buf;
389 if (evt)
390 dwc3_free_one_event_buffer(dwc, evt);
391 }
392
393 /**
394 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
395 * @dwc: pointer to our controller context structure
396 * @length: size of event buffer
397 *
398 * Returns 0 on success otherwise negative errno. In the error case, dwc
399 * may contain some buffers allocated but not all which were requested.
400 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)401 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
402 {
403 struct dwc3_event_buffer *evt;
404
405 evt = dwc3_alloc_one_event_buffer(dwc, length);
406 if (IS_ERR(evt)) {
407 dev_err(dwc->dev, "can't allocate event buffer\n");
408 return PTR_ERR(evt);
409 }
410 dwc->ev_buf = evt;
411
412 return 0;
413 }
414
415 /**
416 * dwc3_event_buffers_setup - setup our allocated event buffers
417 * @dwc: pointer to our controller context structure
418 *
419 * Returns 0 on success otherwise negative errno.
420 */
dwc3_event_buffers_setup(struct dwc3 * dwc)421 int dwc3_event_buffers_setup(struct dwc3 *dwc)
422 {
423 struct dwc3_event_buffer *evt;
424
425 evt = dwc->ev_buf;
426 evt->lpos = 0;
427 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
428 lower_32_bits(evt->dma));
429 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
430 upper_32_bits(evt->dma));
431 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
432 DWC3_GEVNTSIZ_SIZE(evt->length));
433 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
434
435 return 0;
436 }
437
dwc3_event_buffers_cleanup(struct dwc3 * dwc)438 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
439 {
440 struct dwc3_event_buffer *evt;
441
442 evt = dwc->ev_buf;
443
444 evt->lpos = 0;
445
446 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
447 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
448 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
449 | DWC3_GEVNTSIZ_SIZE(0));
450 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
451 }
452
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)453 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
454 {
455 if (!dwc->has_hibernation)
456 return 0;
457
458 if (!dwc->nr_scratch)
459 return 0;
460
461 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
462 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
463 if (!dwc->scratchbuf)
464 return -ENOMEM;
465
466 return 0;
467 }
468
dwc3_setup_scratch_buffers(struct dwc3 * dwc)469 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
470 {
471 dma_addr_t scratch_addr;
472 u32 param;
473 int ret;
474
475 if (!dwc->has_hibernation)
476 return 0;
477
478 if (!dwc->nr_scratch)
479 return 0;
480
481 /* should never fall here */
482 if (!WARN_ON(dwc->scratchbuf))
483 return 0;
484
485 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
486 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
487 DMA_BIDIRECTIONAL);
488 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
489 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
490 ret = -EFAULT;
491 goto err0;
492 }
493
494 dwc->scratch_addr = scratch_addr;
495
496 param = lower_32_bits(scratch_addr);
497
498 ret = dwc3_send_gadget_generic_command(dwc,
499 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
500 if (ret < 0)
501 goto err1;
502
503 param = upper_32_bits(scratch_addr);
504
505 ret = dwc3_send_gadget_generic_command(dwc,
506 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
507 if (ret < 0)
508 goto err1;
509
510 return 0;
511
512 err1:
513 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
514 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
515
516 err0:
517 return ret;
518 }
519
dwc3_free_scratch_buffers(struct dwc3 * dwc)520 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
521 {
522 if (!dwc->has_hibernation)
523 return;
524
525 if (!dwc->nr_scratch)
526 return;
527
528 /* should never fall here */
529 if (!WARN_ON(dwc->scratchbuf))
530 return;
531
532 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
533 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
534 kfree(dwc->scratchbuf);
535 }
536
dwc3_core_num_eps(struct dwc3 * dwc)537 static void dwc3_core_num_eps(struct dwc3 *dwc)
538 {
539 struct dwc3_hwparams *parms = &dwc->hwparams;
540
541 dwc->num_eps = DWC3_NUM_EPS(parms);
542 }
543
dwc3_cache_hwparams(struct dwc3 * dwc)544 static void dwc3_cache_hwparams(struct dwc3 *dwc)
545 {
546 struct dwc3_hwparams *parms = &dwc->hwparams;
547
548 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
549 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
550 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
551 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
552 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
553 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
554 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
555 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
556 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
557 }
558
dwc3_core_ulpi_init(struct dwc3 * dwc)559 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
560 {
561 int intf;
562 int ret = 0;
563
564 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
565
566 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
567 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
568 dwc->hsphy_interface &&
569 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
570 ret = dwc3_ulpi_init(dwc);
571
572 return ret;
573 }
574
575 /**
576 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
577 * @dwc: Pointer to our controller context structure
578 *
579 * Returns 0 on success. The USB PHY interfaces are configured but not
580 * initialized. The PHY interfaces and the PHYs get initialized together with
581 * the core in dwc3_core_init.
582 */
dwc3_phy_setup(struct dwc3 * dwc)583 static int dwc3_phy_setup(struct dwc3 *dwc)
584 {
585 unsigned int hw_mode;
586 u32 reg;
587
588 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
589
590 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
591
592 /*
593 * Make sure UX_EXIT_PX is cleared as that causes issues with some
594 * PHYs. Also, this bit is not supposed to be used in normal operation.
595 */
596 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
597
598 /*
599 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
600 * to '0' during coreConsultant configuration. So default value
601 * will be '0' when the core is reset. Application needs to set it
602 * to '1' after the core initialization is completed.
603 */
604 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
605 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
606
607 /*
608 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
609 * power-on reset, and it can be set after core initialization, which is
610 * after device soft-reset during initialization.
611 */
612 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
613 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
614
615 if (dwc->u2ss_inp3_quirk)
616 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
617
618 if (dwc->dis_rxdet_inp3_quirk)
619 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
620
621 if (dwc->req_p1p2p3_quirk)
622 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
623
624 if (dwc->del_p1p2p3_quirk)
625 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
626
627 if (dwc->del_phy_power_chg_quirk)
628 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
629
630 if (dwc->lfps_filter_quirk)
631 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
632
633 if (dwc->rx_detect_poll_quirk)
634 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
635
636 if (dwc->tx_de_emphasis_quirk)
637 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
638
639 if (dwc->dis_u3_susphy_quirk)
640 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
641
642 if (dwc->dis_del_phy_power_chg_quirk)
643 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
644
645 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
646
647 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
648
649 /* Select the HS PHY interface */
650 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
651 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
652 if (dwc->hsphy_interface &&
653 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
654 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
655 break;
656 } else if (dwc->hsphy_interface &&
657 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
658 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
659 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
660 } else {
661 /* Relying on default value. */
662 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
663 break;
664 }
665 fallthrough;
666 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
667 default:
668 break;
669 }
670
671 switch (dwc->hsphy_mode) {
672 case USBPHY_INTERFACE_MODE_UTMI:
673 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
674 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
675 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
676 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
677 break;
678 case USBPHY_INTERFACE_MODE_UTMIW:
679 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
680 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
681 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
682 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
683 break;
684 default:
685 break;
686 }
687
688 /*
689 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
690 * '0' during coreConsultant configuration. So default value will
691 * be '0' when the core is reset. Application needs to set it to
692 * '1' after the core initialization is completed.
693 */
694 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
695 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
696
697 /*
698 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
699 * power-on reset, and it can be set after core initialization, which is
700 * after device soft-reset during initialization.
701 */
702 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
703 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
704
705 if (dwc->dis_u2_susphy_quirk)
706 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
707
708 if (dwc->dis_enblslpm_quirk)
709 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
710 else
711 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
712
713 if (dwc->dis_u2_freeclk_exists_quirk)
714 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
715
716 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
717
718 return 0;
719 }
720
dwc3_core_exit(struct dwc3 * dwc)721 static void dwc3_core_exit(struct dwc3 *dwc)
722 {
723 dwc3_event_buffers_cleanup(dwc);
724
725 usb_phy_shutdown(dwc->usb2_phy);
726 usb_phy_shutdown(dwc->usb3_phy);
727 phy_exit(dwc->usb2_generic_phy);
728 phy_exit(dwc->usb3_generic_phy);
729
730 usb_phy_set_suspend(dwc->usb2_phy, 1);
731 usb_phy_set_suspend(dwc->usb3_phy, 1);
732 phy_power_off(dwc->usb2_generic_phy);
733 phy_power_off(dwc->usb3_generic_phy);
734 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
735 reset_control_assert(dwc->reset);
736 }
737
dwc3_core_is_valid(struct dwc3 * dwc)738 static bool dwc3_core_is_valid(struct dwc3 *dwc)
739 {
740 u32 reg;
741
742 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
743 dwc->ip = DWC3_GSNPS_ID(reg);
744
745 /* This should read as U3 followed by revision number */
746 if (DWC3_IP_IS(DWC3)) {
747 dwc->revision = reg;
748 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
749 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
750 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
751 } else {
752 return false;
753 }
754
755 return true;
756 }
757
dwc3_core_setup_global_control(struct dwc3 * dwc)758 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
759 {
760 u32 hwparams4 = dwc->hwparams.hwparams4;
761 u32 reg;
762
763 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
764 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
765
766 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
767 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
768 /**
769 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
770 * issue which would cause xHCI compliance tests to fail.
771 *
772 * Because of that we cannot enable clock gating on such
773 * configurations.
774 *
775 * Refers to:
776 *
777 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
778 * SOF/ITP Mode Used
779 */
780 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
781 dwc->dr_mode == USB_DR_MODE_OTG) &&
782 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
783 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
784 else
785 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
786 break;
787 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
788 /* enable hibernation here */
789 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
790
791 /*
792 * REVISIT Enabling this bit so that host-mode hibernation
793 * will work. Device-mode hibernation is not yet implemented.
794 */
795 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
796 break;
797 default:
798 /* nothing */
799 break;
800 }
801
802 /* check if current dwc3 is on simulation board */
803 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
804 dev_info(dwc->dev, "Running with FPGA optimizations\n");
805 dwc->is_fpga = true;
806 }
807
808 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
809 "disable_scramble cannot be used on non-FPGA builds\n");
810
811 if (dwc->disable_scramble_quirk && dwc->is_fpga)
812 reg |= DWC3_GCTL_DISSCRAMBLE;
813 else
814 reg &= ~DWC3_GCTL_DISSCRAMBLE;
815
816 if (dwc->u2exit_lfps_quirk)
817 reg |= DWC3_GCTL_U2EXIT_LFPS;
818
819 /*
820 * WORKAROUND: DWC3 revisions <1.90a have a bug
821 * where the device can fail to connect at SuperSpeed
822 * and falls back to high-speed mode which causes
823 * the device to enter a Connect/Disconnect loop
824 */
825 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
826 reg |= DWC3_GCTL_U2RSTECN;
827
828 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
829 }
830
831 static int dwc3_core_get_phy(struct dwc3 *dwc);
832 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
833
834 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)835 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
836 {
837 struct device *dev = dwc->dev;
838 /* incrx_mode : for INCR burst type. */
839 bool incrx_mode;
840 /* incrx_size : for size of INCRX burst. */
841 u32 incrx_size;
842 u32 *vals;
843 u32 cfg;
844 int ntype;
845 int ret;
846 int i;
847
848 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
849
850 /*
851 * Handle property "snps,incr-burst-type-adjustment".
852 * Get the number of value from this property:
853 * result <= 0, means this property is not supported.
854 * result = 1, means INCRx burst mode supported.
855 * result > 1, means undefined length burst mode supported.
856 */
857 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
858 if (ntype <= 0)
859 return;
860
861 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
862 if (!vals) {
863 dev_err(dev, "Error to get memory\n");
864 return;
865 }
866
867 /* Get INCR burst type, and parse it */
868 ret = device_property_read_u32_array(dev,
869 "snps,incr-burst-type-adjustment", vals, ntype);
870 if (ret) {
871 kfree(vals);
872 dev_err(dev, "Error to get property\n");
873 return;
874 }
875
876 incrx_size = *vals;
877
878 if (ntype > 1) {
879 /* INCRX (undefined length) burst mode */
880 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
881 for (i = 1; i < ntype; i++) {
882 if (vals[i] > incrx_size)
883 incrx_size = vals[i];
884 }
885 } else {
886 /* INCRX burst mode */
887 incrx_mode = INCRX_BURST_MODE;
888 }
889
890 kfree(vals);
891
892 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
893 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
894 if (incrx_mode)
895 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
896 switch (incrx_size) {
897 case 256:
898 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
899 break;
900 case 128:
901 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
902 break;
903 case 64:
904 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
905 break;
906 case 32:
907 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
908 break;
909 case 16:
910 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
911 break;
912 case 8:
913 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
914 break;
915 case 4:
916 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
917 break;
918 case 1:
919 break;
920 default:
921 dev_err(dev, "Invalid property\n");
922 break;
923 }
924
925 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
926 }
927
928 /**
929 * dwc3_core_init - Low-level initialization of DWC3 Core
930 * @dwc: Pointer to our controller context structure
931 *
932 * Returns 0 on success otherwise negative errno.
933 */
dwc3_core_init(struct dwc3 * dwc)934 static int dwc3_core_init(struct dwc3 *dwc)
935 {
936 unsigned int hw_mode;
937 u32 reg;
938 int ret;
939
940 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
941
942 /*
943 * Write Linux Version Code to our GUID register so it's easy to figure
944 * out which kernel version a bug was found.
945 */
946 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
947
948 ret = dwc3_phy_setup(dwc);
949 if (ret)
950 goto err0;
951
952 if (!dwc->ulpi_ready) {
953 ret = dwc3_core_ulpi_init(dwc);
954 if (ret)
955 goto err0;
956 dwc->ulpi_ready = true;
957 }
958
959 if (!dwc->phys_ready) {
960 ret = dwc3_core_get_phy(dwc);
961 if (ret)
962 goto err0a;
963 dwc->phys_ready = true;
964 }
965
966 usb_phy_init(dwc->usb2_phy);
967 usb_phy_init(dwc->usb3_phy);
968 ret = phy_init(dwc->usb2_generic_phy);
969 if (ret < 0)
970 goto err0a;
971
972 ret = phy_init(dwc->usb3_generic_phy);
973 if (ret < 0) {
974 phy_exit(dwc->usb2_generic_phy);
975 goto err0a;
976 }
977
978 ret = dwc3_core_soft_reset(dwc);
979 if (ret)
980 goto err1;
981
982 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
983 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
984 if (!dwc->dis_u3_susphy_quirk) {
985 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
986 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
987 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
988 }
989
990 if (!dwc->dis_u2_susphy_quirk) {
991 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
992 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
993 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
994 }
995 }
996
997 dwc3_core_setup_global_control(dwc);
998 dwc3_core_num_eps(dwc);
999
1000 ret = dwc3_setup_scratch_buffers(dwc);
1001 if (ret)
1002 goto err1;
1003
1004 /* Adjust Frame Length */
1005 dwc3_frame_length_adjustment(dwc);
1006
1007 dwc3_set_incr_burst_type(dwc);
1008
1009 usb_phy_set_suspend(dwc->usb2_phy, 0);
1010 usb_phy_set_suspend(dwc->usb3_phy, 0);
1011 ret = phy_power_on(dwc->usb2_generic_phy);
1012 if (ret < 0)
1013 goto err2;
1014
1015 ret = phy_power_on(dwc->usb3_generic_phy);
1016 if (ret < 0)
1017 goto err3;
1018
1019 ret = dwc3_event_buffers_setup(dwc);
1020 if (ret) {
1021 dev_err(dwc->dev, "failed to setup event buffers\n");
1022 goto err4;
1023 }
1024
1025 /*
1026 * ENDXFER polling is available on version 3.10a and later of
1027 * the DWC_usb3 controller. It is NOT available in the
1028 * DWC_usb31 controller.
1029 */
1030 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1031 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1032 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1033 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1034 }
1035
1036 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1037 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1038
1039 /*
1040 * Enable hardware control of sending remote wakeup
1041 * in HS when the device is in the L1 state.
1042 */
1043 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1044 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1045
1046 if (dwc->dis_tx_ipgap_linecheck_quirk)
1047 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1048
1049 if (dwc->parkmode_disable_ss_quirk)
1050 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1051
1052 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1053 }
1054
1055 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1056 dwc->dr_mode == USB_DR_MODE_OTG) {
1057 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1058
1059 /*
1060 * Enable Auto retry Feature to make the controller operating in
1061 * Host mode on seeing transaction errors(CRC errors or internal
1062 * overrun scenerios) on IN transfers to reply to the device
1063 * with a non-terminating retry ACK (i.e, an ACK transcation
1064 * packet with Retry=1 & Nump != 0)
1065 */
1066 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1067
1068 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1069 }
1070
1071 /*
1072 * Must config both number of packets and max burst settings to enable
1073 * RX and/or TX threshold.
1074 */
1075 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1076 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1077 u8 rx_maxburst = dwc->rx_max_burst_prd;
1078 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1079 u8 tx_maxburst = dwc->tx_max_burst_prd;
1080
1081 if (rx_thr_num && rx_maxburst) {
1082 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1083 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1084
1085 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1086 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1087
1088 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1089 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1090
1091 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1092 }
1093
1094 if (tx_thr_num && tx_maxburst) {
1095 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1096 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1097
1098 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1099 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1100
1101 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1102 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1103
1104 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1105 }
1106 }
1107
1108 return 0;
1109
1110 err4:
1111 phy_power_off(dwc->usb3_generic_phy);
1112
1113 err3:
1114 phy_power_off(dwc->usb2_generic_phy);
1115
1116 err2:
1117 usb_phy_set_suspend(dwc->usb2_phy, 1);
1118 usb_phy_set_suspend(dwc->usb3_phy, 1);
1119
1120 err1:
1121 usb_phy_shutdown(dwc->usb2_phy);
1122 usb_phy_shutdown(dwc->usb3_phy);
1123 phy_exit(dwc->usb2_generic_phy);
1124 phy_exit(dwc->usb3_generic_phy);
1125
1126 err0a:
1127 dwc3_ulpi_exit(dwc);
1128
1129 err0:
1130 return ret;
1131 }
1132
dwc3_core_get_phy(struct dwc3 * dwc)1133 static int dwc3_core_get_phy(struct dwc3 *dwc)
1134 {
1135 struct device *dev = dwc->dev;
1136 struct device_node *node = dev->of_node;
1137 int ret;
1138
1139 if (node) {
1140 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1141 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1142 } else {
1143 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1144 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1145 }
1146
1147 if (IS_ERR(dwc->usb2_phy)) {
1148 ret = PTR_ERR(dwc->usb2_phy);
1149 if (ret == -ENXIO || ret == -ENODEV) {
1150 dwc->usb2_phy = NULL;
1151 } else if (ret == -EPROBE_DEFER) {
1152 return ret;
1153 } else {
1154 dev_err(dev, "no usb2 phy configured\n");
1155 return ret;
1156 }
1157 }
1158
1159 if (IS_ERR(dwc->usb3_phy)) {
1160 ret = PTR_ERR(dwc->usb3_phy);
1161 if (ret == -ENXIO || ret == -ENODEV) {
1162 dwc->usb3_phy = NULL;
1163 } else if (ret == -EPROBE_DEFER) {
1164 return ret;
1165 } else {
1166 dev_err(dev, "no usb3 phy configured\n");
1167 return ret;
1168 }
1169 }
1170
1171 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1172 if (IS_ERR(dwc->usb2_generic_phy)) {
1173 ret = PTR_ERR(dwc->usb2_generic_phy);
1174 if (ret == -ENOSYS || ret == -ENODEV) {
1175 dwc->usb2_generic_phy = NULL;
1176 } else if (ret == -EPROBE_DEFER) {
1177 return ret;
1178 } else {
1179 dev_err(dev, "no usb2 phy configured\n");
1180 return ret;
1181 }
1182 }
1183
1184 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1185 if (IS_ERR(dwc->usb3_generic_phy)) {
1186 ret = PTR_ERR(dwc->usb3_generic_phy);
1187 if (ret == -ENOSYS || ret == -ENODEV) {
1188 dwc->usb3_generic_phy = NULL;
1189 } else if (ret == -EPROBE_DEFER) {
1190 return ret;
1191 } else {
1192 dev_err(dev, "no usb3 phy configured\n");
1193 return ret;
1194 }
1195 }
1196
1197 return 0;
1198 }
1199
dwc3_core_init_mode(struct dwc3 * dwc)1200 static int dwc3_core_init_mode(struct dwc3 *dwc)
1201 {
1202 struct device *dev = dwc->dev;
1203 int ret;
1204
1205 switch (dwc->dr_mode) {
1206 case USB_DR_MODE_PERIPHERAL:
1207 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1208
1209 if (dwc->usb2_phy)
1210 otg_set_vbus(dwc->usb2_phy->otg, false);
1211 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1212 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1213
1214 ret = dwc3_gadget_init(dwc);
1215 if (ret) {
1216 if (ret != -EPROBE_DEFER)
1217 dev_err(dev, "failed to initialize gadget\n");
1218 return ret;
1219 }
1220 break;
1221 case USB_DR_MODE_HOST:
1222 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1223
1224 if (dwc->usb2_phy)
1225 otg_set_vbus(dwc->usb2_phy->otg, true);
1226 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1227 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1228
1229 ret = dwc3_host_init(dwc);
1230 if (ret) {
1231 if (ret != -EPROBE_DEFER)
1232 dev_err(dev, "failed to initialize host\n");
1233 return ret;
1234 }
1235 break;
1236 case USB_DR_MODE_OTG:
1237 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1238 ret = dwc3_drd_init(dwc);
1239 if (ret) {
1240 if (ret != -EPROBE_DEFER)
1241 dev_err(dev, "failed to initialize dual-role\n");
1242 return ret;
1243 }
1244 break;
1245 default:
1246 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1247 return -EINVAL;
1248 }
1249
1250 return 0;
1251 }
1252
dwc3_core_exit_mode(struct dwc3 * dwc)1253 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1254 {
1255 switch (dwc->dr_mode) {
1256 case USB_DR_MODE_PERIPHERAL:
1257 dwc3_gadget_exit(dwc);
1258 break;
1259 case USB_DR_MODE_HOST:
1260 dwc3_host_exit(dwc);
1261 break;
1262 case USB_DR_MODE_OTG:
1263 dwc3_drd_exit(dwc);
1264 break;
1265 default:
1266 /* do nothing */
1267 break;
1268 }
1269
1270 /* de-assert DRVVBUS for HOST and OTG mode */
1271 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1272 }
1273
dwc3_get_properties(struct dwc3 * dwc)1274 static void dwc3_get_properties(struct dwc3 *dwc)
1275 {
1276 struct device *dev = dwc->dev;
1277 u8 lpm_nyet_threshold;
1278 u8 tx_de_emphasis;
1279 u8 hird_threshold;
1280 u8 rx_thr_num_pkt_prd;
1281 u8 rx_max_burst_prd;
1282 u8 tx_thr_num_pkt_prd;
1283 u8 tx_max_burst_prd;
1284
1285 /* default to highest possible threshold */
1286 lpm_nyet_threshold = 0xf;
1287
1288 /* default to -3.5dB de-emphasis */
1289 tx_de_emphasis = 1;
1290
1291 /*
1292 * default to assert utmi_sleep_n and use maximum allowed HIRD
1293 * threshold value of 0b1100
1294 */
1295 hird_threshold = 12;
1296
1297 dwc->maximum_speed = usb_get_maximum_speed(dev);
1298 dwc->dr_mode = usb_get_dr_mode(dev);
1299 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1300
1301 dwc->sysdev_is_parent = device_property_read_bool(dev,
1302 "linux,sysdev_is_parent");
1303 if (dwc->sysdev_is_parent)
1304 dwc->sysdev = dwc->dev->parent;
1305 else
1306 dwc->sysdev = dwc->dev;
1307
1308 dwc->has_lpm_erratum = device_property_read_bool(dev,
1309 "snps,has-lpm-erratum");
1310 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1311 &lpm_nyet_threshold);
1312 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1313 "snps,is-utmi-l1-suspend");
1314 device_property_read_u8(dev, "snps,hird-threshold",
1315 &hird_threshold);
1316 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1317 "snps,dis-start-transfer-quirk");
1318 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1319 "snps,usb3_lpm_capable");
1320 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1321 "snps,usb2-lpm-disable");
1322 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1323 "snps,usb2-gadget-lpm-disable");
1324 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1325 &rx_thr_num_pkt_prd);
1326 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1327 &rx_max_burst_prd);
1328 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1329 &tx_thr_num_pkt_prd);
1330 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1331 &tx_max_burst_prd);
1332
1333 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1334 "snps,disable_scramble_quirk");
1335 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1336 "snps,u2exit_lfps_quirk");
1337 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1338 "snps,u2ss_inp3_quirk");
1339 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1340 "snps,req_p1p2p3_quirk");
1341 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1342 "snps,del_p1p2p3_quirk");
1343 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1344 "snps,del_phy_power_chg_quirk");
1345 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1346 "snps,lfps_filter_quirk");
1347 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1348 "snps,rx_detect_poll_quirk");
1349 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1350 "snps,dis_u3_susphy_quirk");
1351 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1352 "snps,dis_u2_susphy_quirk");
1353 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1354 "snps,dis_enblslpm_quirk");
1355 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1356 "snps,dis-u1-entry-quirk");
1357 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1358 "snps,dis-u2-entry-quirk");
1359 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1360 "snps,dis_rxdet_inp3_quirk");
1361 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1362 "snps,dis-u2-freeclk-exists-quirk");
1363 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1364 "snps,dis-del-phy-power-chg-quirk");
1365 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1366 "snps,dis-tx-ipgap-linecheck-quirk");
1367 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1368 "snps,parkmode-disable-ss-quirk");
1369
1370 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1371 "snps,tx_de_emphasis_quirk");
1372 device_property_read_u8(dev, "snps,tx_de_emphasis",
1373 &tx_de_emphasis);
1374 device_property_read_string(dev, "snps,hsphy_interface",
1375 &dwc->hsphy_interface);
1376 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1377 &dwc->fladj);
1378
1379 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1380 "snps,dis_metastability_quirk");
1381
1382 dwc->dis_split_quirk = device_property_read_bool(dev,
1383 "snps,dis-split-quirk");
1384
1385 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1386 dwc->tx_de_emphasis = tx_de_emphasis;
1387
1388 dwc->hird_threshold = hird_threshold;
1389
1390 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1391 dwc->rx_max_burst_prd = rx_max_burst_prd;
1392
1393 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1394 dwc->tx_max_burst_prd = tx_max_burst_prd;
1395
1396 dwc->imod_interval = 0;
1397 }
1398
1399 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1400 bool dwc3_has_imod(struct dwc3 *dwc)
1401 {
1402 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1403 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1404 DWC3_IP_IS(DWC32);
1405 }
1406
dwc3_check_params(struct dwc3 * dwc)1407 static void dwc3_check_params(struct dwc3 *dwc)
1408 {
1409 struct device *dev = dwc->dev;
1410 unsigned int hwparam_gen =
1411 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1412
1413 /* Check for proper value of imod_interval */
1414 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1415 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1416 dwc->imod_interval = 0;
1417 }
1418
1419 /*
1420 * Workaround for STAR 9000961433 which affects only version
1421 * 3.00a of the DWC_usb3 core. This prevents the controller
1422 * interrupt from being masked while handling events. IMOD
1423 * allows us to work around this issue. Enable it for the
1424 * affected version.
1425 */
1426 if (!dwc->imod_interval &&
1427 DWC3_VER_IS(DWC3, 300A))
1428 dwc->imod_interval = 1;
1429
1430 /* Check the maximum_speed parameter */
1431 switch (dwc->maximum_speed) {
1432 case USB_SPEED_LOW:
1433 case USB_SPEED_FULL:
1434 case USB_SPEED_HIGH:
1435 break;
1436 case USB_SPEED_SUPER:
1437 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1438 dev_warn(dev, "UDC doesn't support Gen 1\n");
1439 break;
1440 case USB_SPEED_SUPER_PLUS:
1441 if ((DWC3_IP_IS(DWC32) &&
1442 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1443 (!DWC3_IP_IS(DWC32) &&
1444 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1445 dev_warn(dev, "UDC doesn't support SSP\n");
1446 break;
1447 default:
1448 dev_err(dev, "invalid maximum_speed parameter %d\n",
1449 dwc->maximum_speed);
1450 fallthrough;
1451 case USB_SPEED_UNKNOWN:
1452 switch (hwparam_gen) {
1453 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1454 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1455 break;
1456 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1457 if (DWC3_IP_IS(DWC32))
1458 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1459 else
1460 dwc->maximum_speed = USB_SPEED_SUPER;
1461 break;
1462 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1463 dwc->maximum_speed = USB_SPEED_HIGH;
1464 break;
1465 default:
1466 dwc->maximum_speed = USB_SPEED_SUPER;
1467 break;
1468 }
1469 break;
1470 }
1471 }
1472
dwc3_probe(struct platform_device * pdev)1473 static int dwc3_probe(struct platform_device *pdev)
1474 {
1475 struct device *dev = &pdev->dev;
1476 struct resource *res, dwc_res;
1477 struct dwc3 *dwc;
1478
1479 int ret;
1480
1481 void __iomem *regs;
1482
1483 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1484 if (!dwc)
1485 return -ENOMEM;
1486
1487 dwc->dev = dev;
1488
1489 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1490 if (!res) {
1491 dev_err(dev, "missing memory resource\n");
1492 return -ENODEV;
1493 }
1494
1495 dwc->xhci_resources[0].start = res->start;
1496 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1497 DWC3_XHCI_REGS_END;
1498 dwc->xhci_resources[0].flags = res->flags;
1499 dwc->xhci_resources[0].name = res->name;
1500
1501 /*
1502 * Request memory region but exclude xHCI regs,
1503 * since it will be requested by the xhci-plat driver.
1504 */
1505 dwc_res = *res;
1506 dwc_res.start += DWC3_GLOBALS_REGS_START;
1507
1508 regs = devm_ioremap_resource(dev, &dwc_res);
1509 if (IS_ERR(regs))
1510 return PTR_ERR(regs);
1511
1512 dwc->regs = regs;
1513 dwc->regs_size = resource_size(&dwc_res);
1514
1515 dwc3_get_properties(dwc);
1516
1517 dwc->reset = devm_reset_control_array_get(dev, true, true);
1518 if (IS_ERR(dwc->reset))
1519 return PTR_ERR(dwc->reset);
1520
1521 if (dev->of_node) {
1522 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1523 if (ret == -EPROBE_DEFER)
1524 return ret;
1525 /*
1526 * Clocks are optional, but new DT platforms should support all
1527 * clocks as required by the DT-binding.
1528 */
1529 if (ret < 0)
1530 dwc->num_clks = 0;
1531 else
1532 dwc->num_clks = ret;
1533
1534 }
1535
1536 ret = reset_control_deassert(dwc->reset);
1537 if (ret)
1538 return ret;
1539
1540 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1541 if (ret)
1542 goto assert_reset;
1543
1544 if (!dwc3_core_is_valid(dwc)) {
1545 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1546 ret = -ENODEV;
1547 goto disable_clks;
1548 }
1549
1550 platform_set_drvdata(pdev, dwc);
1551 dwc3_cache_hwparams(dwc);
1552
1553 spin_lock_init(&dwc->lock);
1554 mutex_init(&dwc->mutex);
1555
1556 pm_runtime_set_active(dev);
1557 pm_runtime_use_autosuspend(dev);
1558 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1559 pm_runtime_enable(dev);
1560 ret = pm_runtime_get_sync(dev);
1561 if (ret < 0)
1562 goto err1;
1563
1564 pm_runtime_forbid(dev);
1565
1566 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1567 if (ret) {
1568 dev_err(dwc->dev, "failed to allocate event buffers\n");
1569 ret = -ENOMEM;
1570 goto err2;
1571 }
1572
1573 ret = dwc3_get_dr_mode(dwc);
1574 if (ret)
1575 goto err3;
1576
1577 ret = dwc3_alloc_scratch_buffers(dwc);
1578 if (ret)
1579 goto err3;
1580
1581 ret = dwc3_core_init(dwc);
1582 if (ret) {
1583 if (ret != -EPROBE_DEFER)
1584 dev_err(dev, "failed to initialize core: %d\n", ret);
1585 goto err4;
1586 }
1587
1588 dwc3_check_params(dwc);
1589 dwc3_debugfs_init(dwc);
1590
1591 ret = dwc3_core_init_mode(dwc);
1592 if (ret)
1593 goto err5;
1594
1595 pm_runtime_put(dev);
1596
1597 return 0;
1598
1599 err5:
1600 dwc3_debugfs_exit(dwc);
1601 dwc3_event_buffers_cleanup(dwc);
1602
1603 usb_phy_shutdown(dwc->usb2_phy);
1604 usb_phy_shutdown(dwc->usb3_phy);
1605 phy_exit(dwc->usb2_generic_phy);
1606 phy_exit(dwc->usb3_generic_phy);
1607
1608 usb_phy_set_suspend(dwc->usb2_phy, 1);
1609 usb_phy_set_suspend(dwc->usb3_phy, 1);
1610 phy_power_off(dwc->usb2_generic_phy);
1611 phy_power_off(dwc->usb3_generic_phy);
1612
1613 dwc3_ulpi_exit(dwc);
1614
1615 err4:
1616 dwc3_free_scratch_buffers(dwc);
1617
1618 err3:
1619 dwc3_free_event_buffers(dwc);
1620
1621 err2:
1622 pm_runtime_allow(&pdev->dev);
1623
1624 err1:
1625 pm_runtime_put_sync(&pdev->dev);
1626 pm_runtime_disable(&pdev->dev);
1627
1628 disable_clks:
1629 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1630 assert_reset:
1631 reset_control_assert(dwc->reset);
1632
1633 return ret;
1634 }
1635
dwc3_remove(struct platform_device * pdev)1636 static int dwc3_remove(struct platform_device *pdev)
1637 {
1638 struct dwc3 *dwc = platform_get_drvdata(pdev);
1639
1640 pm_runtime_get_sync(&pdev->dev);
1641
1642 dwc3_core_exit_mode(dwc);
1643 dwc3_debugfs_exit(dwc);
1644
1645 dwc3_core_exit(dwc);
1646 dwc3_ulpi_exit(dwc);
1647
1648 pm_runtime_disable(&pdev->dev);
1649 pm_runtime_put_noidle(&pdev->dev);
1650 pm_runtime_set_suspended(&pdev->dev);
1651
1652 dwc3_free_event_buffers(dwc);
1653 dwc3_free_scratch_buffers(dwc);
1654
1655 return 0;
1656 }
1657
1658 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)1659 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1660 {
1661 int ret;
1662
1663 ret = reset_control_deassert(dwc->reset);
1664 if (ret)
1665 return ret;
1666
1667 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1668 if (ret)
1669 goto assert_reset;
1670
1671 ret = dwc3_core_init(dwc);
1672 if (ret)
1673 goto disable_clks;
1674
1675 return 0;
1676
1677 disable_clks:
1678 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1679 assert_reset:
1680 reset_control_assert(dwc->reset);
1681
1682 return ret;
1683 }
1684
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)1685 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1686 {
1687 unsigned long flags;
1688 u32 reg;
1689
1690 switch (dwc->current_dr_role) {
1691 case DWC3_GCTL_PRTCAP_DEVICE:
1692 if (pm_runtime_suspended(dwc->dev))
1693 break;
1694 spin_lock_irqsave(&dwc->lock, flags);
1695 dwc3_gadget_suspend(dwc);
1696 spin_unlock_irqrestore(&dwc->lock, flags);
1697 synchronize_irq(dwc->irq_gadget);
1698 dwc3_core_exit(dwc);
1699 break;
1700 case DWC3_GCTL_PRTCAP_HOST:
1701 if (!PMSG_IS_AUTO(msg)) {
1702 dwc3_core_exit(dwc);
1703 break;
1704 }
1705
1706 /* Let controller to suspend HSPHY before PHY driver suspends */
1707 if (dwc->dis_u2_susphy_quirk ||
1708 dwc->dis_enblslpm_quirk) {
1709 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1710 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1711 DWC3_GUSB2PHYCFG_SUSPHY;
1712 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1713
1714 /* Give some time for USB2 PHY to suspend */
1715 usleep_range(5000, 6000);
1716 }
1717
1718 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1719 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1720 break;
1721 case DWC3_GCTL_PRTCAP_OTG:
1722 /* do nothing during runtime_suspend */
1723 if (PMSG_IS_AUTO(msg))
1724 break;
1725
1726 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1727 spin_lock_irqsave(&dwc->lock, flags);
1728 dwc3_gadget_suspend(dwc);
1729 spin_unlock_irqrestore(&dwc->lock, flags);
1730 synchronize_irq(dwc->irq_gadget);
1731 }
1732
1733 dwc3_otg_exit(dwc);
1734 dwc3_core_exit(dwc);
1735 break;
1736 default:
1737 /* do nothing */
1738 break;
1739 }
1740
1741 return 0;
1742 }
1743
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)1744 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1745 {
1746 unsigned long flags;
1747 int ret;
1748 u32 reg;
1749
1750 switch (dwc->current_dr_role) {
1751 case DWC3_GCTL_PRTCAP_DEVICE:
1752 ret = dwc3_core_init_for_resume(dwc);
1753 if (ret)
1754 return ret;
1755
1756 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1757 spin_lock_irqsave(&dwc->lock, flags);
1758 dwc3_gadget_resume(dwc);
1759 spin_unlock_irqrestore(&dwc->lock, flags);
1760 break;
1761 case DWC3_GCTL_PRTCAP_HOST:
1762 if (!PMSG_IS_AUTO(msg)) {
1763 ret = dwc3_core_init_for_resume(dwc);
1764 if (ret)
1765 return ret;
1766 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1767 break;
1768 }
1769 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1770 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1771 if (dwc->dis_u2_susphy_quirk)
1772 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1773
1774 if (dwc->dis_enblslpm_quirk)
1775 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1776
1777 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1778
1779 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1780 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1781 break;
1782 case DWC3_GCTL_PRTCAP_OTG:
1783 /* nothing to do on runtime_resume */
1784 if (PMSG_IS_AUTO(msg))
1785 break;
1786
1787 ret = dwc3_core_init_for_resume(dwc);
1788 if (ret)
1789 return ret;
1790
1791 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1792
1793 dwc3_otg_init(dwc);
1794 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1795 dwc3_otg_host_init(dwc);
1796 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1797 spin_lock_irqsave(&dwc->lock, flags);
1798 dwc3_gadget_resume(dwc);
1799 spin_unlock_irqrestore(&dwc->lock, flags);
1800 }
1801
1802 break;
1803 default:
1804 /* do nothing */
1805 break;
1806 }
1807
1808 return 0;
1809 }
1810
dwc3_runtime_checks(struct dwc3 * dwc)1811 static int dwc3_runtime_checks(struct dwc3 *dwc)
1812 {
1813 switch (dwc->current_dr_role) {
1814 case DWC3_GCTL_PRTCAP_DEVICE:
1815 if (dwc->connected)
1816 return -EBUSY;
1817 break;
1818 case DWC3_GCTL_PRTCAP_HOST:
1819 default:
1820 /* do nothing */
1821 break;
1822 }
1823
1824 return 0;
1825 }
1826
dwc3_runtime_suspend(struct device * dev)1827 static int dwc3_runtime_suspend(struct device *dev)
1828 {
1829 struct dwc3 *dwc = dev_get_drvdata(dev);
1830 int ret;
1831
1832 if (dwc3_runtime_checks(dwc))
1833 return -EBUSY;
1834
1835 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1836 if (ret)
1837 return ret;
1838
1839 device_init_wakeup(dev, true);
1840
1841 return 0;
1842 }
1843
dwc3_runtime_resume(struct device * dev)1844 static int dwc3_runtime_resume(struct device *dev)
1845 {
1846 struct dwc3 *dwc = dev_get_drvdata(dev);
1847 int ret;
1848
1849 device_init_wakeup(dev, false);
1850
1851 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1852 if (ret)
1853 return ret;
1854
1855 switch (dwc->current_dr_role) {
1856 case DWC3_GCTL_PRTCAP_DEVICE:
1857 dwc3_gadget_process_pending_events(dwc);
1858 break;
1859 case DWC3_GCTL_PRTCAP_HOST:
1860 default:
1861 /* do nothing */
1862 break;
1863 }
1864
1865 pm_runtime_mark_last_busy(dev);
1866
1867 return 0;
1868 }
1869
dwc3_runtime_idle(struct device * dev)1870 static int dwc3_runtime_idle(struct device *dev)
1871 {
1872 struct dwc3 *dwc = dev_get_drvdata(dev);
1873
1874 switch (dwc->current_dr_role) {
1875 case DWC3_GCTL_PRTCAP_DEVICE:
1876 if (dwc3_runtime_checks(dwc))
1877 return -EBUSY;
1878 break;
1879 case DWC3_GCTL_PRTCAP_HOST:
1880 default:
1881 /* do nothing */
1882 break;
1883 }
1884
1885 pm_runtime_mark_last_busy(dev);
1886 pm_runtime_autosuspend(dev);
1887
1888 return 0;
1889 }
1890 #endif /* CONFIG_PM */
1891
1892 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)1893 static int dwc3_suspend(struct device *dev)
1894 {
1895 struct dwc3 *dwc = dev_get_drvdata(dev);
1896 int ret;
1897
1898 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1899 if (ret)
1900 return ret;
1901
1902 pinctrl_pm_select_sleep_state(dev);
1903
1904 return 0;
1905 }
1906
dwc3_resume(struct device * dev)1907 static int dwc3_resume(struct device *dev)
1908 {
1909 struct dwc3 *dwc = dev_get_drvdata(dev);
1910 int ret;
1911
1912 pinctrl_pm_select_default_state(dev);
1913
1914 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1915 if (ret)
1916 return ret;
1917
1918 pm_runtime_disable(dev);
1919 pm_runtime_set_active(dev);
1920 pm_runtime_enable(dev);
1921
1922 return 0;
1923 }
1924
dwc3_complete(struct device * dev)1925 static void dwc3_complete(struct device *dev)
1926 {
1927 struct dwc3 *dwc = dev_get_drvdata(dev);
1928 u32 reg;
1929
1930 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1931 dwc->dis_split_quirk) {
1932 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1933 reg |= DWC3_GUCTL3_SPLITDISABLE;
1934 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1935 }
1936 }
1937 #else
1938 #define dwc3_complete NULL
1939 #endif /* CONFIG_PM_SLEEP */
1940
1941 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1942 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1943 .complete = dwc3_complete,
1944 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1945 dwc3_runtime_idle)
1946 };
1947
1948 #ifdef CONFIG_OF
1949 static const struct of_device_id of_dwc3_match[] = {
1950 {
1951 .compatible = "snps,dwc3"
1952 },
1953 {
1954 .compatible = "synopsys,dwc3"
1955 },
1956 { },
1957 };
1958 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1959 #endif
1960
1961 #ifdef CONFIG_ACPI
1962
1963 #define ACPI_ID_INTEL_BSW "808622B7"
1964
1965 static const struct acpi_device_id dwc3_acpi_match[] = {
1966 { ACPI_ID_INTEL_BSW, 0 },
1967 { },
1968 };
1969 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1970 #endif
1971
1972 static struct platform_driver dwc3_driver = {
1973 .probe = dwc3_probe,
1974 .remove = dwc3_remove,
1975 .driver = {
1976 .name = "dwc3",
1977 .of_match_table = of_match_ptr(of_dwc3_match),
1978 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1979 .pm = &dwc3_dev_pm_ops,
1980 },
1981 };
1982
1983 module_platform_driver(dwc3_driver);
1984
1985 MODULE_ALIAS("platform:dwc3");
1986 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1987 MODULE_LICENSE("GPL v2");
1988 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1989