1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation, incorporated herein by reference.
10 */
11
12 #include "ef100_nic.h"
13 #include "efx_common.h"
14 #include "efx_channels.h"
15 #include "io.h"
16 #include "selftest.h"
17 #include "ef100_regs.h"
18 #include "mcdi.h"
19 #include "mcdi_pcol.h"
20 #include "mcdi_port_common.h"
21 #include "mcdi_functions.h"
22 #include "mcdi_filters.h"
23 #include "ef100_rx.h"
24 #include "ef100_tx.h"
25 #include "ef100_netdev.h"
26
27 #define EF100_MAX_VIS 4096
28 #define EF100_NUM_MCDI_BUFFERS 1
29 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
30
31 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT)
32
33 /* MCDI
34 */
ef100_mcdi_buf(struct efx_nic * efx,u8 bufid,dma_addr_t * dma_addr)35 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr)
36 {
37 struct ef100_nic_data *nic_data = efx->nic_data;
38
39 if (dma_addr)
40 *dma_addr = nic_data->mcdi_buf.dma_addr +
41 bufid * ALIGN(MCDI_BUF_LEN, 256);
42 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
43 }
44
ef100_get_warm_boot_count(struct efx_nic * efx)45 static int ef100_get_warm_boot_count(struct efx_nic *efx)
46 {
47 efx_dword_t reg;
48
49 efx_readd(efx, ®, efx_reg(efx, ER_GZ_MC_SFT_STATUS));
50
51 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
52 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
53 efx->state = STATE_DISABLED;
54 return -ENETDOWN;
55 } else {
56 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
57 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
58 }
59 }
60
ef100_mcdi_request(struct efx_nic * efx,const efx_dword_t * hdr,size_t hdr_len,const efx_dword_t * sdu,size_t sdu_len)61 static void ef100_mcdi_request(struct efx_nic *efx,
62 const efx_dword_t *hdr, size_t hdr_len,
63 const efx_dword_t *sdu, size_t sdu_len)
64 {
65 dma_addr_t dma_addr;
66 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr);
67
68 memcpy(pdu, hdr, hdr_len);
69 memcpy(pdu + hdr_len, sdu, sdu_len);
70 wmb();
71
72 /* The hardware provides 'low' and 'high' (doorbell) registers
73 * for passing the 64-bit address of an MCDI request to
74 * firmware. However the dwords are swapped by firmware. The
75 * least significant bits of the doorbell are then 0 for all
76 * MCDI requests due to alignment.
77 */
78 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD));
79 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD));
80 }
81
ef100_mcdi_poll_response(struct efx_nic * efx)82 static bool ef100_mcdi_poll_response(struct efx_nic *efx)
83 {
84 const efx_dword_t hdr =
85 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL));
86
87 rmb();
88 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
89 }
90
ef100_mcdi_read_response(struct efx_nic * efx,efx_dword_t * outbuf,size_t offset,size_t outlen)91 static void ef100_mcdi_read_response(struct efx_nic *efx,
92 efx_dword_t *outbuf, size_t offset,
93 size_t outlen)
94 {
95 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL);
96
97 memcpy(outbuf, pdu + offset, outlen);
98 }
99
ef100_mcdi_poll_reboot(struct efx_nic * efx)100 static int ef100_mcdi_poll_reboot(struct efx_nic *efx)
101 {
102 struct ef100_nic_data *nic_data = efx->nic_data;
103 int rc;
104
105 rc = ef100_get_warm_boot_count(efx);
106 if (rc < 0) {
107 /* The firmware is presumably in the process of
108 * rebooting. However, we are supposed to report each
109 * reboot just once, so we must only do that once we
110 * can read and store the updated warm boot count.
111 */
112 return 0;
113 }
114
115 if (rc == nic_data->warm_boot_count)
116 return 0;
117
118 nic_data->warm_boot_count = rc;
119
120 return -EIO;
121 }
122
ef100_mcdi_reboot_detected(struct efx_nic * efx)123 static void ef100_mcdi_reboot_detected(struct efx_nic *efx)
124 {
125 }
126
127 /* MCDI calls
128 */
ef100_get_mac_address(struct efx_nic * efx,u8 * mac_address)129 static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address)
130 {
131 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
132 size_t outlen;
133 int rc;
134
135 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
136
137 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
138 outbuf, sizeof(outbuf), &outlen);
139 if (rc)
140 return rc;
141 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
142 return -EIO;
143
144 ether_addr_copy(mac_address,
145 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
146 return 0;
147 }
148
efx_ef100_init_datapath_caps(struct efx_nic * efx)149 static int efx_ef100_init_datapath_caps(struct efx_nic *efx)
150 {
151 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
152 struct ef100_nic_data *nic_data = efx->nic_data;
153 u8 vi_window_mode;
154 size_t outlen;
155 int rc;
156
157 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
158
159 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
160 outbuf, sizeof(outbuf), &outlen);
161 if (rc)
162 return rc;
163 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
164 netif_err(efx, drv, efx->net_dev,
165 "unable to read datapath firmware capabilities\n");
166 return -EIO;
167 }
168
169 nic_data->datapath_caps = MCDI_DWORD(outbuf,
170 GET_CAPABILITIES_OUT_FLAGS1);
171 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
172 GET_CAPABILITIES_V2_OUT_FLAGS2);
173 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
174 nic_data->datapath_caps3 = 0;
175 else
176 nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
177 GET_CAPABILITIES_V7_OUT_FLAGS3);
178
179 vi_window_mode = MCDI_BYTE(outbuf,
180 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
181 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
182 if (rc)
183 return rc;
184
185 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3))
186 efx->net_dev->features |= NETIF_F_TSO | NETIF_F_TSO6;
187 efx->num_mac_stats = MCDI_WORD(outbuf,
188 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
189 netif_dbg(efx, probe, efx->net_dev,
190 "firmware reports num_mac_stats = %u\n",
191 efx->num_mac_stats);
192 return 0;
193 }
194
195 /* Event handling
196 */
ef100_ev_probe(struct efx_channel * channel)197 static int ef100_ev_probe(struct efx_channel *channel)
198 {
199 /* Allocate an extra descriptor for the QMDA status completion entry */
200 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
201 (channel->eventq_mask + 2) *
202 sizeof(efx_qword_t),
203 GFP_KERNEL);
204 }
205
ef100_ev_init(struct efx_channel * channel)206 static int ef100_ev_init(struct efx_channel *channel)
207 {
208 struct ef100_nic_data *nic_data = channel->efx->nic_data;
209
210 /* initial phase is 0 */
211 clear_bit(channel->channel, nic_data->evq_phases);
212
213 return efx_mcdi_ev_init(channel, false, false);
214 }
215
ef100_ev_read_ack(struct efx_channel * channel)216 static void ef100_ev_read_ack(struct efx_channel *channel)
217 {
218 efx_dword_t evq_prime;
219
220 EFX_POPULATE_DWORD_2(evq_prime,
221 ERF_GZ_EVQ_ID, channel->channel,
222 ERF_GZ_IDX, channel->eventq_read_ptr &
223 channel->eventq_mask);
224
225 efx_writed(channel->efx, &evq_prime,
226 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME));
227 }
228
ef100_ev_process(struct efx_channel * channel,int quota)229 static int ef100_ev_process(struct efx_channel *channel, int quota)
230 {
231 struct efx_nic *efx = channel->efx;
232 struct ef100_nic_data *nic_data;
233 bool evq_phase, old_evq_phase;
234 unsigned int read_ptr;
235 efx_qword_t *p_event;
236 int spent = 0;
237 bool ev_phase;
238 int ev_type;
239
240 if (unlikely(!channel->enabled))
241 return 0;
242
243 nic_data = efx->nic_data;
244 evq_phase = test_bit(channel->channel, nic_data->evq_phases);
245 old_evq_phase = evq_phase;
246 read_ptr = channel->eventq_read_ptr;
247 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN);
248
249 while (spent < quota) {
250 p_event = efx_event(channel, read_ptr);
251
252 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE);
253 if (ev_phase != evq_phase)
254 break;
255
256 netif_vdbg(efx, drv, efx->net_dev,
257 "processing event on %d " EFX_QWORD_FMT "\n",
258 channel->channel, EFX_QWORD_VAL(*p_event));
259
260 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE);
261
262 switch (ev_type) {
263 case ESE_GZ_EF100_EV_RX_PKTS:
264 efx_ef100_ev_rx(channel, p_event);
265 ++spent;
266 break;
267 case ESE_GZ_EF100_EV_MCDI:
268 efx_mcdi_process_event(channel, p_event);
269 break;
270 case ESE_GZ_EF100_EV_TX_COMPLETION:
271 ef100_ev_tx(channel, p_event);
272 break;
273 case ESE_GZ_EF100_EV_DRIVER:
274 netif_info(efx, drv, efx->net_dev,
275 "Driver initiated event " EFX_QWORD_FMT "\n",
276 EFX_QWORD_VAL(*p_event));
277 break;
278 default:
279 netif_info(efx, drv, efx->net_dev,
280 "Unhandled event " EFX_QWORD_FMT "\n",
281 EFX_QWORD_VAL(*p_event));
282 }
283
284 ++read_ptr;
285 if ((read_ptr & channel->eventq_mask) == 0)
286 evq_phase = !evq_phase;
287 }
288
289 channel->eventq_read_ptr = read_ptr;
290 if (evq_phase != old_evq_phase)
291 change_bit(channel->channel, nic_data->evq_phases);
292
293 return spent;
294 }
295
ef100_msi_interrupt(int irq,void * dev_id)296 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id)
297 {
298 struct efx_msi_context *context = dev_id;
299 struct efx_nic *efx = context->efx;
300
301 netif_vdbg(efx, intr, efx->net_dev,
302 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
303
304 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
305 /* Note test interrupts */
306 if (context->index == efx->irq_level)
307 efx->last_irq_cpu = raw_smp_processor_id();
308
309 /* Schedule processing of the channel */
310 efx_schedule_channel_irq(efx->channel[context->index]);
311 }
312
313 return IRQ_HANDLED;
314 }
315
ef100_phy_probe(struct efx_nic * efx)316 static int ef100_phy_probe(struct efx_nic *efx)
317 {
318 struct efx_mcdi_phy_data *phy_data;
319 int rc;
320
321 /* Probe for the PHY */
322 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL);
323 if (!efx->phy_data)
324 return -ENOMEM;
325
326 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data);
327 if (rc)
328 return rc;
329
330 /* Populate driver and ethtool settings */
331 phy_data = efx->phy_data;
332 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap,
333 efx->link_advertising);
334 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap,
335 false);
336
337 /* Default to Autonegotiated flow control if the PHY supports it */
338 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
339 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
340 efx->wanted_fc |= EFX_FC_AUTO;
341 efx_link_set_wanted_fc(efx, efx->wanted_fc);
342
343 /* Push settings to the PHY. Failure is not fatal, the user can try to
344 * fix it using ethtool.
345 */
346 rc = efx_mcdi_port_reconfigure(efx);
347 if (rc && rc != -EPERM)
348 netif_warn(efx, drv, efx->net_dev,
349 "could not initialise PHY settings\n");
350
351 return 0;
352 }
353
ef100_filter_table_probe(struct efx_nic * efx)354 static int ef100_filter_table_probe(struct efx_nic *efx)
355 {
356 return efx_mcdi_filter_table_probe(efx, true);
357 }
358
ef100_filter_table_up(struct efx_nic * efx)359 static int ef100_filter_table_up(struct efx_nic *efx)
360 {
361 int rc;
362
363 rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
364 if (rc) {
365 efx_mcdi_filter_table_down(efx);
366 return rc;
367 }
368
369 rc = efx_mcdi_filter_add_vlan(efx, 0);
370 if (rc) {
371 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
372 efx_mcdi_filter_table_down(efx);
373 }
374
375 return rc;
376 }
377
ef100_filter_table_down(struct efx_nic * efx)378 static void ef100_filter_table_down(struct efx_nic *efx)
379 {
380 efx_mcdi_filter_del_vlan(efx, 0);
381 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
382 efx_mcdi_filter_table_down(efx);
383 }
384
385 /* Other
386 */
ef100_reconfigure_mac(struct efx_nic * efx,bool mtu_only)387 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only)
388 {
389 WARN_ON(!mutex_is_locked(&efx->mac_lock));
390
391 efx_mcdi_filter_sync_rx_mode(efx);
392
393 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
394 return efx_mcdi_set_mtu(efx);
395 return efx_mcdi_set_mac(efx);
396 }
397
ef100_map_reset_reason(enum reset_type reason)398 static enum reset_type ef100_map_reset_reason(enum reset_type reason)
399 {
400 if (reason == RESET_TYPE_TX_WATCHDOG)
401 return reason;
402 return RESET_TYPE_DISABLE;
403 }
404
ef100_map_reset_flags(u32 * flags)405 static int ef100_map_reset_flags(u32 *flags)
406 {
407 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */
408 if ((*flags & EF100_RESET_PORT)) {
409 *flags &= ~EF100_RESET_PORT;
410 return RESET_TYPE_ALL;
411 }
412 if (*flags & ETH_RESET_MGMT) {
413 *flags &= ~ETH_RESET_MGMT;
414 return RESET_TYPE_DISABLE;
415 }
416
417 return -EINVAL;
418 }
419
ef100_reset(struct efx_nic * efx,enum reset_type reset_type)420 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type)
421 {
422 int rc;
423
424 dev_close(efx->net_dev);
425
426 if (reset_type == RESET_TYPE_TX_WATCHDOG) {
427 netif_device_attach(efx->net_dev);
428 __clear_bit(reset_type, &efx->reset_pending);
429 rc = dev_open(efx->net_dev, NULL);
430 } else if (reset_type == RESET_TYPE_ALL) {
431 rc = efx_mcdi_reset(efx, reset_type);
432 if (rc)
433 return rc;
434
435 netif_device_attach(efx->net_dev);
436
437 rc = dev_open(efx->net_dev, NULL);
438 } else {
439 rc = 1; /* Leave the device closed */
440 }
441 return rc;
442 }
443
ef100_common_stat_mask(unsigned long * mask)444 static void ef100_common_stat_mask(unsigned long *mask)
445 {
446 __set_bit(EF100_STAT_port_rx_packets, mask);
447 __set_bit(EF100_STAT_port_tx_packets, mask);
448 __set_bit(EF100_STAT_port_rx_bytes, mask);
449 __set_bit(EF100_STAT_port_tx_bytes, mask);
450 __set_bit(EF100_STAT_port_rx_multicast, mask);
451 __set_bit(EF100_STAT_port_rx_bad, mask);
452 __set_bit(EF100_STAT_port_rx_align_error, mask);
453 __set_bit(EF100_STAT_port_rx_overflow, mask);
454 }
455
ef100_ethtool_stat_mask(unsigned long * mask)456 static void ef100_ethtool_stat_mask(unsigned long *mask)
457 {
458 __set_bit(EF100_STAT_port_tx_pause, mask);
459 __set_bit(EF100_STAT_port_tx_unicast, mask);
460 __set_bit(EF100_STAT_port_tx_multicast, mask);
461 __set_bit(EF100_STAT_port_tx_broadcast, mask);
462 __set_bit(EF100_STAT_port_tx_lt64, mask);
463 __set_bit(EF100_STAT_port_tx_64, mask);
464 __set_bit(EF100_STAT_port_tx_65_to_127, mask);
465 __set_bit(EF100_STAT_port_tx_128_to_255, mask);
466 __set_bit(EF100_STAT_port_tx_256_to_511, mask);
467 __set_bit(EF100_STAT_port_tx_512_to_1023, mask);
468 __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask);
469 __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask);
470 __set_bit(EF100_STAT_port_rx_good, mask);
471 __set_bit(EF100_STAT_port_rx_pause, mask);
472 __set_bit(EF100_STAT_port_rx_unicast, mask);
473 __set_bit(EF100_STAT_port_rx_broadcast, mask);
474 __set_bit(EF100_STAT_port_rx_lt64, mask);
475 __set_bit(EF100_STAT_port_rx_64, mask);
476 __set_bit(EF100_STAT_port_rx_65_to_127, mask);
477 __set_bit(EF100_STAT_port_rx_128_to_255, mask);
478 __set_bit(EF100_STAT_port_rx_256_to_511, mask);
479 __set_bit(EF100_STAT_port_rx_512_to_1023, mask);
480 __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask);
481 __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask);
482 __set_bit(EF100_STAT_port_rx_gtjumbo, mask);
483 __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask);
484 __set_bit(EF100_STAT_port_rx_length_error, mask);
485 __set_bit(EF100_STAT_port_rx_nodesc_drops, mask);
486 __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask);
487 __set_bit(GENERIC_STAT_rx_noskb_drops, mask);
488 }
489
490 #define EF100_DMA_STAT(ext_name, mcdi_name) \
491 [EF100_STAT_ ## ext_name] = \
492 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
493
494 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = {
495 EF100_DMA_STAT(port_tx_bytes, TX_BYTES),
496 EF100_DMA_STAT(port_tx_packets, TX_PKTS),
497 EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
498 EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
499 EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
500 EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
501 EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
502 EF100_DMA_STAT(port_tx_64, TX_64_PKTS),
503 EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
504 EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
505 EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
506 EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
507 EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
508 EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
509 EF100_DMA_STAT(port_rx_bytes, RX_BYTES),
510 EF100_DMA_STAT(port_rx_packets, RX_PKTS),
511 EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
512 EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
513 EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
514 EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
515 EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
516 EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
517 EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
518 EF100_DMA_STAT(port_rx_64, RX_64_PKTS),
519 EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
520 EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
521 EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
522 EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
523 EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
524 EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
525 EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
526 EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
527 EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
528 EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
529 EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
530 EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
531 EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
532 EFX_GENERIC_SW_STAT(rx_noskb_drops),
533 };
534
ef100_describe_stats(struct efx_nic * efx,u8 * names)535 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names)
536 {
537 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
538
539 ef100_ethtool_stat_mask(mask);
540 return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT,
541 mask, names);
542 }
543
ef100_update_stats_common(struct efx_nic * efx,u64 * full_stats,struct rtnl_link_stats64 * core_stats)544 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats,
545 struct rtnl_link_stats64 *core_stats)
546 {
547 struct ef100_nic_data *nic_data = efx->nic_data;
548 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
549 size_t stats_count = 0, index;
550 u64 *stats = nic_data->stats;
551
552 ef100_ethtool_stat_mask(mask);
553
554 if (full_stats) {
555 for_each_set_bit(index, mask, EF100_STAT_COUNT) {
556 if (ef100_stat_desc[index].name) {
557 *full_stats++ = stats[index];
558 ++stats_count;
559 }
560 }
561 }
562
563 if (!core_stats)
564 return stats_count;
565
566 core_stats->rx_packets = stats[EF100_STAT_port_rx_packets];
567 core_stats->tx_packets = stats[EF100_STAT_port_tx_packets];
568 core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes];
569 core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes];
570 core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] +
571 stats[GENERIC_STAT_rx_nodesc_trunc] +
572 stats[GENERIC_STAT_rx_noskb_drops];
573 core_stats->multicast = stats[EF100_STAT_port_rx_multicast];
574 core_stats->rx_length_errors =
575 stats[EF100_STAT_port_rx_gtjumbo] +
576 stats[EF100_STAT_port_rx_length_error];
577 core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad];
578 core_stats->rx_frame_errors =
579 stats[EF100_STAT_port_rx_align_error];
580 core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow];
581 core_stats->rx_errors = (core_stats->rx_length_errors +
582 core_stats->rx_crc_errors +
583 core_stats->rx_frame_errors);
584
585 return stats_count;
586 }
587
ef100_update_stats(struct efx_nic * efx,u64 * full_stats,struct rtnl_link_stats64 * core_stats)588 static size_t ef100_update_stats(struct efx_nic *efx,
589 u64 *full_stats,
590 struct rtnl_link_stats64 *core_stats)
591 {
592 __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC);
593 struct ef100_nic_data *nic_data = efx->nic_data;
594 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
595 u64 *stats = nic_data->stats;
596
597 ef100_common_stat_mask(mask);
598 ef100_ethtool_stat_mask(mask);
599
600 if (!mc_stats)
601 return 0;
602
603 efx_nic_copy_stats(efx, mc_stats);
604 efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask,
605 stats, mc_stats, false);
606
607 kfree(mc_stats);
608
609 return ef100_update_stats_common(efx, full_stats, core_stats);
610 }
611
efx_ef100_get_phys_port_id(struct efx_nic * efx,struct netdev_phys_item_id * ppid)612 static int efx_ef100_get_phys_port_id(struct efx_nic *efx,
613 struct netdev_phys_item_id *ppid)
614 {
615 struct ef100_nic_data *nic_data = efx->nic_data;
616
617 if (!is_valid_ether_addr(nic_data->port_id))
618 return -EOPNOTSUPP;
619
620 ppid->id_len = ETH_ALEN;
621 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
622
623 return 0;
624 }
625
efx_ef100_irq_test_generate(struct efx_nic * efx)626 static int efx_ef100_irq_test_generate(struct efx_nic *efx)
627 {
628 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
629
630 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
631
632 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
633 return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT,
634 inbuf, sizeof(inbuf), NULL, 0, NULL);
635 }
636
637 #define EFX_EF100_TEST 1
638
efx_ef100_ev_test_generate(struct efx_channel * channel)639 static void efx_ef100_ev_test_generate(struct efx_channel *channel)
640 {
641 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
642 struct efx_nic *efx = channel->efx;
643 efx_qword_t event;
644 int rc;
645
646 EFX_POPULATE_QWORD_2(event,
647 ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER,
648 ESF_GZ_DRIVER_DATA, EFX_EF100_TEST);
649
650 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
651
652 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
653 * already swapped the data to little-endian order.
654 */
655 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
656 sizeof(efx_qword_t));
657
658 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
659 NULL, 0, NULL);
660 if (rc && (rc != -ENETDOWN))
661 goto fail;
662
663 return;
664
665 fail:
666 WARN_ON(true);
667 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
668 }
669
ef100_check_caps(const struct efx_nic * efx,u8 flag,u32 offset)670 static unsigned int ef100_check_caps(const struct efx_nic *efx,
671 u8 flag, u32 offset)
672 {
673 const struct ef100_nic_data *nic_data = efx->nic_data;
674
675 switch (offset) {
676 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST:
677 return nic_data->datapath_caps & BIT_ULL(flag);
678 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST:
679 return nic_data->datapath_caps2 & BIT_ULL(flag);
680 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST:
681 return nic_data->datapath_caps3 & BIT_ULL(flag);
682 default:
683 return 0;
684 }
685 }
686
687 /* NIC level access functions
688 */
689 #define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \
690 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \
691 NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \
692 NETIF_F_TSO_MANGLEID | NETIF_F_HW_VLAN_CTAG_TX)
693
694 const struct efx_nic_type ef100_pf_nic_type = {
695 .revision = EFX_REV_EF100,
696 .is_vf = false,
697 .probe = ef100_probe_pf,
698 .offload_features = EF100_OFFLOAD_FEATURES,
699 .mcdi_max_ver = 2,
700 .mcdi_request = ef100_mcdi_request,
701 .mcdi_poll_response = ef100_mcdi_poll_response,
702 .mcdi_read_response = ef100_mcdi_read_response,
703 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
704 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
705 .irq_enable_master = efx_port_dummy_op_void,
706 .irq_test_generate = efx_ef100_irq_test_generate,
707 .irq_disable_non_ev = efx_port_dummy_op_void,
708 .push_irq_moderation = efx_channel_dummy_op_void,
709 .min_interrupt_mode = EFX_INT_MODE_MSIX,
710 .map_reset_reason = ef100_map_reset_reason,
711 .map_reset_flags = ef100_map_reset_flags,
712 .reset = ef100_reset,
713
714 .check_caps = ef100_check_caps,
715
716 .ev_probe = ef100_ev_probe,
717 .ev_init = ef100_ev_init,
718 .ev_fini = efx_mcdi_ev_fini,
719 .ev_remove = efx_mcdi_ev_remove,
720 .irq_handle_msi = ef100_msi_interrupt,
721 .ev_process = ef100_ev_process,
722 .ev_read_ack = ef100_ev_read_ack,
723 .ev_test_generate = efx_ef100_ev_test_generate,
724 .tx_probe = ef100_tx_probe,
725 .tx_init = ef100_tx_init,
726 .tx_write = ef100_tx_write,
727 .tx_enqueue = ef100_enqueue_skb,
728 .rx_probe = efx_mcdi_rx_probe,
729 .rx_init = efx_mcdi_rx_init,
730 .rx_remove = efx_mcdi_rx_remove,
731 .rx_write = ef100_rx_write,
732 .rx_packet = __ef100_rx_packet,
733 .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
734 .fini_dmaq = efx_fini_dmaq,
735 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
736 .filter_table_probe = ef100_filter_table_up,
737 .filter_table_restore = efx_mcdi_filter_table_restore,
738 .filter_table_remove = ef100_filter_table_down,
739 .filter_insert = efx_mcdi_filter_insert,
740 .filter_remove_safe = efx_mcdi_filter_remove_safe,
741 .filter_get_safe = efx_mcdi_filter_get_safe,
742 .filter_clear_rx = efx_mcdi_filter_clear_rx,
743 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
744 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
745 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
746 #ifdef CONFIG_RFS_ACCEL
747 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
748 #endif
749
750 .get_phys_port_id = efx_ef100_get_phys_port_id,
751
752 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
753 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
754 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
755 .rx_hash_key_size = 40,
756 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
757 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
758 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
759 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
760 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
761
762 .reconfigure_mac = ef100_reconfigure_mac,
763 .reconfigure_port = efx_mcdi_port_reconfigure,
764 .test_nvram = efx_new_mcdi_nvram_test_all,
765 .describe_stats = ef100_describe_stats,
766 .start_stats = efx_mcdi_mac_start_stats,
767 .update_stats = ef100_update_stats,
768 .pull_stats = efx_mcdi_mac_pull_stats,
769 .stop_stats = efx_mcdi_mac_stop_stats,
770
771 /* Per-type bar/size configuration not used on ef100. Location of
772 * registers is defined by extended capabilities.
773 */
774 .mem_bar = NULL,
775 .mem_map_size = NULL,
776
777 };
778
779 const struct efx_nic_type ef100_vf_nic_type = {
780 .revision = EFX_REV_EF100,
781 .is_vf = true,
782 .probe = ef100_probe_vf,
783 .offload_features = EF100_OFFLOAD_FEATURES,
784 .mcdi_max_ver = 2,
785 .mcdi_request = ef100_mcdi_request,
786 .mcdi_poll_response = ef100_mcdi_poll_response,
787 .mcdi_read_response = ef100_mcdi_read_response,
788 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
789 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
790 .irq_enable_master = efx_port_dummy_op_void,
791 .irq_test_generate = efx_ef100_irq_test_generate,
792 .irq_disable_non_ev = efx_port_dummy_op_void,
793 .push_irq_moderation = efx_channel_dummy_op_void,
794 .min_interrupt_mode = EFX_INT_MODE_MSIX,
795 .map_reset_reason = ef100_map_reset_reason,
796 .map_reset_flags = ef100_map_reset_flags,
797 .reset = ef100_reset,
798 .check_caps = ef100_check_caps,
799 .ev_probe = ef100_ev_probe,
800 .ev_init = ef100_ev_init,
801 .ev_fini = efx_mcdi_ev_fini,
802 .ev_remove = efx_mcdi_ev_remove,
803 .irq_handle_msi = ef100_msi_interrupt,
804 .ev_process = ef100_ev_process,
805 .ev_read_ack = ef100_ev_read_ack,
806 .ev_test_generate = efx_ef100_ev_test_generate,
807 .tx_probe = ef100_tx_probe,
808 .tx_init = ef100_tx_init,
809 .tx_write = ef100_tx_write,
810 .tx_enqueue = ef100_enqueue_skb,
811 .rx_probe = efx_mcdi_rx_probe,
812 .rx_init = efx_mcdi_rx_init,
813 .rx_remove = efx_mcdi_rx_remove,
814 .rx_write = ef100_rx_write,
815 .rx_packet = __ef100_rx_packet,
816 .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
817 .fini_dmaq = efx_fini_dmaq,
818 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
819 .filter_table_probe = ef100_filter_table_up,
820 .filter_table_restore = efx_mcdi_filter_table_restore,
821 .filter_table_remove = ef100_filter_table_down,
822 .filter_insert = efx_mcdi_filter_insert,
823 .filter_remove_safe = efx_mcdi_filter_remove_safe,
824 .filter_get_safe = efx_mcdi_filter_get_safe,
825 .filter_clear_rx = efx_mcdi_filter_clear_rx,
826 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
827 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
828 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
829 #ifdef CONFIG_RFS_ACCEL
830 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
831 #endif
832
833 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
834 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
835 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
836 .rx_hash_key_size = 40,
837 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
838 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
839 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
840
841 .reconfigure_mac = ef100_reconfigure_mac,
842 .test_nvram = efx_new_mcdi_nvram_test_all,
843 .describe_stats = ef100_describe_stats,
844 .start_stats = efx_mcdi_mac_start_stats,
845 .update_stats = ef100_update_stats,
846 .pull_stats = efx_mcdi_mac_pull_stats,
847 .stop_stats = efx_mcdi_mac_stop_stats,
848
849 .mem_bar = NULL,
850 .mem_map_size = NULL,
851
852 };
853
compare_versions(const char * a,const char * b)854 static int compare_versions(const char *a, const char *b)
855 {
856 int a_major, a_minor, a_point, a_patch;
857 int b_major, b_minor, b_point, b_patch;
858 int a_matched, b_matched;
859
860 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch);
861 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch);
862
863 if (a_matched == 4 && b_matched != 4)
864 return +1;
865
866 if (a_matched != 4 && b_matched == 4)
867 return -1;
868
869 if (a_matched != 4 && b_matched != 4)
870 return 0;
871
872 if (a_major != b_major)
873 return a_major - b_major;
874
875 if (a_minor != b_minor)
876 return a_minor - b_minor;
877
878 if (a_point != b_point)
879 return a_point - b_point;
880
881 return a_patch - b_patch;
882 }
883
884 enum ef100_tlv_state_machine {
885 EF100_TLV_TYPE,
886 EF100_TLV_TYPE_CONT,
887 EF100_TLV_LENGTH,
888 EF100_TLV_VALUE
889 };
890
891 struct ef100_tlv_state {
892 enum ef100_tlv_state_machine state;
893 u64 value;
894 u32 value_offset;
895 u16 type;
896 u8 len;
897 };
898
ef100_tlv_feed(struct ef100_tlv_state * state,u8 byte)899 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte)
900 {
901 switch (state->state) {
902 case EF100_TLV_TYPE:
903 state->type = byte & 0x7f;
904 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT
905 : EF100_TLV_LENGTH;
906 /* Clear ready to read in a new entry */
907 state->value = 0;
908 state->value_offset = 0;
909 return 0;
910 case EF100_TLV_TYPE_CONT:
911 state->type |= byte << 7;
912 state->state = EF100_TLV_LENGTH;
913 return 0;
914 case EF100_TLV_LENGTH:
915 state->len = byte;
916 /* We only handle TLVs that fit in a u64 */
917 if (state->len > sizeof(state->value))
918 return -EOPNOTSUPP;
919 /* len may be zero, implying a value of zero */
920 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE;
921 return 0;
922 case EF100_TLV_VALUE:
923 state->value |= ((u64)byte) << (state->value_offset * 8);
924 state->value_offset++;
925 if (state->value_offset >= state->len)
926 state->state = EF100_TLV_TYPE;
927 return 0;
928 default: /* state machine error, can't happen */
929 WARN_ON_ONCE(1);
930 return -EIO;
931 }
932 }
933
ef100_process_design_param(struct efx_nic * efx,const struct ef100_tlv_state * reader)934 static int ef100_process_design_param(struct efx_nic *efx,
935 const struct ef100_tlv_state *reader)
936 {
937 struct ef100_nic_data *nic_data = efx->nic_data;
938
939 switch (reader->type) {
940 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */
941 return 0;
942 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS:
943 /* Driver doesn't support timestamping yet, so we don't care */
944 return 0;
945 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS:
946 /* Driver doesn't support unsolicited-event credits yet, so
947 * we don't care
948 */
949 return 0;
950 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE:
951 /* Driver doesn't manage the NMMU (so we don't care) */
952 return 0;
953 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS:
954 /* Driver uses CHECKSUM_COMPLETE, so we don't care about
955 * protocol checksum validation
956 */
957 return 0;
958 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN:
959 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff);
960 return 0;
961 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS:
962 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */
963 if (!reader->value) {
964 netif_err(efx, probe, efx->net_dev,
965 "TSO_MAX_HDR_NUM_SEGS < 1\n");
966 return -EOPNOTSUPP;
967 }
968 return 0;
969 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY:
970 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY:
971 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by
972 * EFX_MIN_DMAQ_SIZE, so we just need to check that
973 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY.
974 * This is very unlikely to fail.
975 */
976 if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE ||
977 EFX_MIN_DMAQ_SIZE % (u32)reader->value) {
978 netif_err(efx, probe, efx->net_dev,
979 "%s size granularity is %llu, can't guarantee safety\n",
980 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ",
981 reader->value);
982 return -EOPNOTSUPP;
983 }
984 return 0;
985 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN:
986 nic_data->tso_max_payload_len = min_t(u64, reader->value, GSO_MAX_SIZE);
987 efx->net_dev->gso_max_size = nic_data->tso_max_payload_len;
988 return 0;
989 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS:
990 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff);
991 efx->net_dev->gso_max_segs = nic_data->tso_max_payload_num_segs;
992 return 0;
993 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES:
994 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff);
995 return 0;
996 case ESE_EF100_DP_GZ_COMPAT:
997 if (reader->value) {
998 netif_err(efx, probe, efx->net_dev,
999 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n",
1000 reader->value);
1001 return -EOPNOTSUPP;
1002 }
1003 return 0;
1004 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN:
1005 /* Driver doesn't use mem2mem transfers */
1006 return 0;
1007 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS:
1008 /* Driver doesn't currently use EVQ_TIMER */
1009 return 0;
1010 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES:
1011 /* Driver doesn't manage the NMMU (so we don't care) */
1012 return 0;
1013 case ESE_EF100_DP_GZ_VI_STRIDES:
1014 /* We never try to set the VI stride, and we don't rely on
1015 * being able to find VIs past VI 0 until after we've learned
1016 * the current stride from MC_CMD_GET_CAPABILITIES.
1017 * So the value of this shouldn't matter.
1018 */
1019 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT)
1020 netif_dbg(efx, probe, efx->net_dev,
1021 "NIC has other than default VI_STRIDES (mask "
1022 "%#llx), early probing might use wrong one\n",
1023 reader->value);
1024 return 0;
1025 case ESE_EF100_DP_GZ_RX_MAX_RUNT:
1026 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't
1027 * care whether it indicates runt or overlength for any given
1028 * packet, so we don't care about this parameter.
1029 */
1030 return 0;
1031 default:
1032 /* Host interface says "Drivers should ignore design parameters
1033 * that they do not recognise."
1034 */
1035 netif_dbg(efx, probe, efx->net_dev,
1036 "Ignoring unrecognised design parameter %u\n",
1037 reader->type);
1038 return 0;
1039 }
1040 }
1041
ef100_check_design_params(struct efx_nic * efx)1042 static int ef100_check_design_params(struct efx_nic *efx)
1043 {
1044 struct ef100_tlv_state reader = {};
1045 u32 total_len, offset = 0;
1046 efx_dword_t reg;
1047 int rc = 0, i;
1048 u32 data;
1049
1050 efx_readd(efx, ®, ER_GZ_PARAMS_TLV_LEN);
1051 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
1052 netif_dbg(efx, probe, efx->net_dev, "%u bytes of design parameters\n",
1053 total_len);
1054 while (offset < total_len) {
1055 efx_readd(efx, ®, ER_GZ_PARAMS_TLV + offset);
1056 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
1057 for (i = 0; i < sizeof(data); i++) {
1058 rc = ef100_tlv_feed(&reader, data);
1059 /* Got a complete value? */
1060 if (!rc && reader.state == EF100_TLV_TYPE)
1061 rc = ef100_process_design_param(efx, &reader);
1062 if (rc)
1063 goto out;
1064 data >>= 8;
1065 offset++;
1066 }
1067 }
1068 /* Check we didn't end halfway through a TLV entry, which could either
1069 * mean that the TLV stream is truncated or just that it's corrupted
1070 * and our state machine is out of sync.
1071 */
1072 if (reader.state != EF100_TLV_TYPE) {
1073 if (reader.state == EF100_TLV_TYPE_CONT)
1074 netif_err(efx, probe, efx->net_dev,
1075 "truncated design parameter (incomplete type %u)\n",
1076 reader.type);
1077 else
1078 netif_err(efx, probe, efx->net_dev,
1079 "truncated design parameter %u\n",
1080 reader.type);
1081 rc = -EIO;
1082 }
1083 out:
1084 return rc;
1085 }
1086
1087 /* NIC probe and remove
1088 */
ef100_probe_main(struct efx_nic * efx)1089 static int ef100_probe_main(struct efx_nic *efx)
1090 {
1091 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]);
1092 struct net_device *net_dev = efx->net_dev;
1093 struct ef100_nic_data *nic_data;
1094 char fw_version[32];
1095 int i, rc;
1096
1097 if (WARN_ON(bar_size == 0))
1098 return -EIO;
1099
1100 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1101 if (!nic_data)
1102 return -ENOMEM;
1103 efx->nic_data = nic_data;
1104 nic_data->efx = efx;
1105 net_dev->features |= efx->type->offload_features;
1106 net_dev->hw_features |= efx->type->offload_features;
1107
1108 /* Populate design-parameter defaults */
1109 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
1110 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
1111 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
1112 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
1113 net_dev->gso_max_segs = ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT;
1114 /* Read design parameters */
1115 rc = ef100_check_design_params(efx);
1116 if (rc) {
1117 netif_err(efx, probe, efx->net_dev,
1118 "Unsupported design parameters\n");
1119 goto fail;
1120 }
1121
1122 /* we assume later that we can copy from this buffer in dwords */
1123 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
1124
1125 /* MCDI buffers must be 256 byte aligned. */
1126 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN,
1127 GFP_KERNEL);
1128 if (rc)
1129 goto fail;
1130
1131 /* Get the MC's warm boot count. In case it's rebooting right
1132 * now, be prepared to retry.
1133 */
1134 i = 0;
1135 for (;;) {
1136 rc = ef100_get_warm_boot_count(efx);
1137 if (rc >= 0)
1138 break;
1139 if (++i == 5)
1140 goto fail;
1141 ssleep(1);
1142 }
1143 nic_data->warm_boot_count = rc;
1144
1145 /* In case we're recovering from a crash (kexec), we want to
1146 * cancel any outstanding request by the previous user of this
1147 * function. We send a special message using the least
1148 * significant bits of the 'high' (doorbell) register.
1149 */
1150 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD));
1151
1152 /* Post-IO section. */
1153
1154 rc = efx_mcdi_init(efx);
1155 if (!rc && efx->mcdi->fn_flags &
1156 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT)) {
1157 netif_info(efx, probe, efx->net_dev,
1158 "No network port on this PCI function");
1159 rc = -ENODEV;
1160 }
1161 if (rc)
1162 goto fail;
1163 /* Reset (most) configuration for this function */
1164 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
1165 if (rc)
1166 goto fail;
1167 /* Enable event logging */
1168 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
1169 if (rc)
1170 goto fail;
1171
1172 rc = efx_get_pf_index(efx, &nic_data->pf_index);
1173 if (rc)
1174 goto fail;
1175
1176 rc = efx_ef100_init_datapath_caps(efx);
1177 if (rc < 0)
1178 goto fail;
1179
1180 efx->max_vis = EF100_MAX_VIS;
1181
1182 rc = efx_mcdi_port_get_number(efx);
1183 if (rc < 0)
1184 goto fail;
1185 efx->port_num = rc;
1186
1187 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version));
1188 netif_dbg(efx, drv, efx->net_dev, "Firmware version %s\n", fw_version);
1189
1190 if (compare_versions(fw_version, "1.1.0.1000") < 0) {
1191 netif_info(efx, drv, efx->net_dev, "Firmware uses old event descriptors\n");
1192 rc = -EINVAL;
1193 goto fail;
1194 }
1195
1196 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) {
1197 netif_info(efx, drv, efx->net_dev, "Firmware uses unsolicited-event credits\n");
1198 rc = -EINVAL;
1199 goto fail;
1200 }
1201
1202 rc = ef100_phy_probe(efx);
1203 if (rc)
1204 goto fail;
1205
1206 down_write(&efx->filter_sem);
1207 rc = ef100_filter_table_probe(efx);
1208 up_write(&efx->filter_sem);
1209 if (rc)
1210 goto fail;
1211
1212 netdev_rss_key_fill(efx->rss_context.rx_hash_key,
1213 sizeof(efx->rss_context.rx_hash_key));
1214
1215 /* Don't fail init if RSS setup doesn't work. */
1216 efx_mcdi_push_default_indir_table(efx, efx->n_rx_channels);
1217
1218 rc = ef100_register_netdev(efx);
1219 if (rc)
1220 goto fail;
1221
1222 return 0;
1223 fail:
1224 return rc;
1225 }
1226
ef100_probe_pf(struct efx_nic * efx)1227 int ef100_probe_pf(struct efx_nic *efx)
1228 {
1229 struct net_device *net_dev = efx->net_dev;
1230 struct ef100_nic_data *nic_data;
1231 int rc = ef100_probe_main(efx);
1232
1233 if (rc)
1234 goto fail;
1235
1236 nic_data = efx->nic_data;
1237 rc = ef100_get_mac_address(efx, net_dev->perm_addr);
1238 if (rc)
1239 goto fail;
1240 /* Assign MAC address */
1241 memcpy(net_dev->dev_addr, net_dev->perm_addr, ETH_ALEN);
1242 memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN);
1243
1244 return 0;
1245
1246 fail:
1247 return rc;
1248 }
1249
ef100_probe_vf(struct efx_nic * efx)1250 int ef100_probe_vf(struct efx_nic *efx)
1251 {
1252 return ef100_probe_main(efx);
1253 }
1254
ef100_remove(struct efx_nic * efx)1255 void ef100_remove(struct efx_nic *efx)
1256 {
1257 struct ef100_nic_data *nic_data = efx->nic_data;
1258
1259 ef100_unregister_netdev(efx);
1260
1261 down_write(&efx->filter_sem);
1262 efx_mcdi_filter_table_remove(efx);
1263 up_write(&efx->filter_sem);
1264 efx_fini_channels(efx);
1265 kfree(efx->phy_data);
1266 efx->phy_data = NULL;
1267 efx_mcdi_detach(efx);
1268 efx_mcdi_fini(efx);
1269 if (nic_data)
1270 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1271 kfree(nic_data);
1272 efx->nic_data = NULL;
1273 }
1274