1 /*
2 * Copyright 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdint.h>
25
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
28
29 static uint64_t
__gen_combine_address(void * data,void * loc,uint64_t addr,uint32_t delta)30 __gen_combine_address(__attribute__((unused)) void *data,
31 __attribute__((unused)) void *loc, uint64_t addr,
32 uint32_t delta)
33 {
34 return addr + delta;
35 }
36
37 #include "genxml/gen_macros.h"
38 #include "genxml/genX_pack.h"
39
40 #include "isl_priv.h"
41
42 static const uint32_t isl_encode_ds_surftype[] = {
43 #if GFX_VER >= 9
44 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
45 *
46 * "If depth/stencil is enabled with 1D render target, depth/stencil
47 * surface type needs to be set to 2D surface type and height set to 1.
48 * Depth will use (legacy) TileY and stencil will use TileW. For this
49 * case only, the Surface Type of the depth buffer can be 2D while the
50 * Surface Type of the render target(s) are 1D, representing an
51 * exception to a programming note above.
52 */
53 [ISL_SURF_DIM_1D] = SURFTYPE_2D,
54 #else
55 [ISL_SURF_DIM_1D] = SURFTYPE_1D,
56 #endif
57 [ISL_SURF_DIM_2D] = SURFTYPE_2D,
58 [ISL_SURF_DIM_3D] = SURFTYPE_3D,
59 };
60
61 #if GFX_VERx10 >= 125
62 static const uint8_t isl_encode_tiling[] = {
63 [ISL_TILING_4] = TILE4,
64 [ISL_TILING_64] = TILE64,
65 };
66 #endif
67
68 void
isl_genX(emit_depth_stencil_hiz_s)69 isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
70 const struct isl_depth_stencil_hiz_emit_info *restrict info)
71 {
72 struct GENX(3DSTATE_DEPTH_BUFFER) db = {
73 GENX(3DSTATE_DEPTH_BUFFER_header),
74 };
75
76 if (info->depth_surf) {
77 db.SurfaceType = isl_encode_ds_surftype[info->depth_surf->dim];
78 db.SurfaceFormat = isl_surf_get_depth_format(dev, info->depth_surf);
79 db.Width = info->depth_surf->logical_level0_px.width - 1;
80 db.Height = info->depth_surf->logical_level0_px.height - 1;
81 if (db.SurfaceType == SURFTYPE_3D)
82 db.Depth = info->depth_surf->logical_level0_px.depth - 1;
83 } else if (info->stencil_surf) {
84 db.SurfaceType = isl_encode_ds_surftype[info->stencil_surf->dim];
85 db.SurfaceFormat = D32_FLOAT;
86 db.Width = info->stencil_surf->logical_level0_px.width - 1;
87 db.Height = info->stencil_surf->logical_level0_px.height - 1;
88 if (db.SurfaceType == SURFTYPE_3D)
89 db.Depth = info->stencil_surf->logical_level0_px.depth - 1;
90 } else {
91 db.SurfaceType = SURFTYPE_NULL;
92 db.SurfaceFormat = D32_FLOAT;
93 }
94
95 if (info->depth_surf || info->stencil_surf) {
96 /* These are based entirely on the view */
97 db.RenderTargetViewExtent = info->view->array_len - 1;
98 db.LOD = info->view->base_level;
99 db.MinimumArrayElement = info->view->base_array_layer;
100
101 /* From the Haswell PRM docs for 3DSTATE_DEPTH_BUFFER::Depth
102 *
103 * "This field specifies the total number of levels for a volume
104 * texture or the number of array elements allowed to be accessed
105 * starting at the Minimum Array Element for arrayed surfaces. If the
106 * volume texture is MIP-mapped, this field specifies the depth of
107 * the base MIP level."
108 *
109 * For 3D surfaces, we set it to the correct depth above. For non-3D
110 * surfaces, this is the same as RenderTargetViewExtent.
111 */
112 if (db.SurfaceType != SURFTYPE_3D)
113 db.Depth = db.RenderTargetViewExtent;
114 }
115
116 if (info->depth_surf) {
117 #if GFX_VER >= 7
118 db.DepthWriteEnable = true;
119 #endif
120 db.SurfaceBaseAddress = info->depth_address;
121 #if GFX_VER >= 6
122 db.MOCS = info->mocs;
123 #endif
124
125 #if GFX_VERx10 >= 125
126 db.TiledMode = isl_encode_tiling[info->depth_surf->tiling];
127 db.MipTailStartLOD = 15;
128 db.CompressionMode = isl_aux_usage_has_ccs(info->hiz_usage);
129 db.RenderCompressionFormat =
130 isl_get_render_compression_format(info->depth_surf->format);
131 #elif GFX_VER <= 6
132 db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR;
133 db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
134 TILEWALK_XMAJOR;
135 db.MIPMapLayoutMode = MIPLAYOUT_BELOW;
136 #endif
137
138 db.SurfacePitch = info->depth_surf->row_pitch_B - 1;
139 #if GFX_VER >= 8
140 db.SurfaceQPitch =
141 isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
142 #endif
143
144 #if GFX_VER >= 12
145 db.ControlSurfaceEnable = db.DepthBufferCompressionEnable =
146 isl_aux_usage_has_ccs(info->hiz_usage);
147 #endif
148 }
149
150 #if GFX_VER == 5 || GFX_VER == 6
151 const bool separate_stencil =
152 info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT;
153 if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
154 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
155 db.SeparateStencilBufferEnable = true;
156 db.HierarchicalDepthBufferEnable = true;
157 }
158 #endif
159
160 #if GFX_VER >= 6
161 struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
162 GENX(3DSTATE_STENCIL_BUFFER_header),
163 };
164 #else
165 # define sb db
166 #endif
167
168 if (info->stencil_surf) {
169 #if GFX_VER >= 7 && GFX_VER < 12
170 db.StencilWriteEnable = true;
171 #endif
172 #if GFX_VERx10 >= 125
173 sb.TiledMode = isl_encode_tiling[info->stencil_surf->tiling];
174 sb.MipTailStartLOD = 15;
175 sb.CompressionMode = isl_aux_usage_has_ccs(info->stencil_aux_usage);
176 sb.RenderCompressionFormat =
177 isl_get_render_compression_format(info->stencil_surf->format);
178 #endif
179 #if GFX_VER >= 12
180 sb.StencilWriteEnable = true;
181 sb.SurfaceType = SURFTYPE_2D;
182 sb.Width = info->stencil_surf->logical_level0_px.width - 1;
183 sb.Height = info->stencil_surf->logical_level0_px.height - 1;
184 sb.Depth = sb.RenderTargetViewExtent = info->view->array_len - 1;
185 sb.SurfLOD = info->view->base_level;
186 sb.MinimumArrayElement = info->view->base_array_layer;
187 assert(info->stencil_aux_usage == ISL_AUX_USAGE_NONE ||
188 info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS);
189 sb.StencilCompressionEnable =
190 info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
191 sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
192 #elif GFX_VERx10 >= 75
193 sb.StencilBufferEnable = true;
194 #endif
195 sb.SurfaceBaseAddress = info->stencil_address;
196 #if GFX_VER >= 6
197 sb.MOCS = info->mocs;
198 #endif
199 sb.SurfacePitch = info->stencil_surf->row_pitch_B - 1;
200 #if GFX_VER >= 8
201 sb.SurfaceQPitch =
202 isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2;
203 #endif
204 } else {
205 #if GFX_VER >= 12
206 sb.SurfaceType = SURFTYPE_NULL;
207
208 /* The docs seem to indicate that if surf-type is null, then we may need
209 * to match the depth-buffer value for `Depth`. It may be a
210 * documentation bug, since the other fields don't require this.
211 *
212 * TODO: Confirm documentation and remove seeting of `Depth` if not
213 * required.
214 */
215 sb.Depth = db.Depth;
216 #endif
217 }
218
219 #if GFX_VER >= 6
220 struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = {
221 GENX(3DSTATE_HIER_DEPTH_BUFFER_header),
222 };
223 struct GENX(3DSTATE_CLEAR_PARAMS) clear = {
224 GENX(3DSTATE_CLEAR_PARAMS_header),
225 };
226
227 assert(info->hiz_usage == ISL_AUX_USAGE_NONE ||
228 isl_aux_usage_has_hiz(info->hiz_usage));
229 if (isl_aux_usage_has_hiz(info->hiz_usage)) {
230 assert(GFX_VER >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ);
231 db.HierarchicalDepthBufferEnable = true;
232
233 hiz.SurfaceBaseAddress = info->hiz_address;
234 hiz.MOCS = info->mocs;
235 hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
236
237 #if GFX_VERx10 >= 125
238 hiz.TiledMode = isl_encode_tiling[info->hiz_surf->tiling];
239 #endif
240
241 #if GFX_VER >= 12
242 hiz.HierarchicalDepthBufferWriteThruEnable =
243 info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT;
244
245 /* The bspec docs for this bit are fairly unclear about exactly what is
246 * and isn't supported with HiZ write-through. It's fairly clear that
247 * you can't sample from a multisampled depth buffer with CCS. This
248 * limitation isn't called out explicitly but the docs for the CCS_E
249 * value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode say:
250 *
251 * "If Number of multisamples > 1, programming this value means MSAA
252 * compression is enabled for that surface. Auxillary surface is MSC
253 * with tile y."
254 *
255 * Since this interpretation ignores whether the surface is
256 * depth/stencil or not and since multisampled depth buffers use
257 * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
258 * compression, this means that we can't even specify MSAA depth CCS in
259 * RENDER_SURFACE_STATE::AuxiliarySurfaceMode. The BSpec also says, for
260 * 3DSTATE_HIER_DEPTH_BUFFER::HierarchicalDepthBufferWriteThruEnable,
261 *
262 * "This bit must NOT be set for >1x MSAA modes, since sampler
263 * doesn't support sampling from >1x MSAA depth buffer."
264 *
265 * Again, this is all focused around what the sampler can do and not
266 * what the depth hardware can do.
267 *
268 * Reading even more internal docs which can't be quoted here makes it
269 * pretty clear that, even if it's not currently called out in the
270 * BSpec, HiZ+CCS write-through isn't intended to work with MSAA and we
271 * shouldn't try to use it. Treat it as if it's disallowed even if the
272 * BSpec doesn't explicitly document that.
273 */
274 if (hiz.HierarchicalDepthBufferWriteThruEnable)
275 assert(info->depth_surf->samples == 1);
276 #endif
277
278 #if GFX_VER >= 8
279 /* From the SKL PRM Vol2a:
280 *
281 * The interpretation of this field is dependent on Surface Type
282 * as follows:
283 * - SURFTYPE_1D: distance in pixels between array slices
284 * - SURFTYPE_2D/CUBE: distance in rows between array slices
285 * - SURFTYPE_3D: distance in rows between R - slices
286 *
287 * Unfortunately, the docs aren't 100% accurate here. They fail to
288 * mention that the 1-D rule only applies to linear 1-D images.
289 * Since depth and HiZ buffers are always tiled, they are treated as
290 * 2-D images. Prior to Sky Lake, this field is always in rows.
291 */
292 hiz.SurfaceQPitch =
293 isl_surf_get_array_pitch_sa_rows(info->hiz_surf) >> 2;
294 #endif
295
296 clear.DepthClearValueValid = true;
297 #if GFX_VER >= 8
298 clear.DepthClearValue = info->depth_clear_value;
299 #else
300 switch (info->depth_surf->format) {
301 case ISL_FORMAT_R32_FLOAT: {
302 union { float f; uint32_t u; } fu;
303 fu.f = info->depth_clear_value;
304 clear.DepthClearValue = fu.u;
305 break;
306 }
307 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
308 clear.DepthClearValue = info->depth_clear_value * ((1u << 24) - 1);
309 break;
310 case ISL_FORMAT_R16_UNORM:
311 clear.DepthClearValue = info->depth_clear_value * ((1u << 16) - 1);
312 break;
313 default:
314 unreachable("Invalid depth type");
315 }
316 #endif
317 }
318 #endif /* GFX_VER >= 6 */
319
320 /* Pack everything into the batch */
321 uint32_t *dw = batch;
322 GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db);
323 dw += GENX(3DSTATE_DEPTH_BUFFER_length);
324
325 #if GFX_VER >= 6
326 GENX(3DSTATE_STENCIL_BUFFER_pack)(NULL, dw, &sb);
327 dw += GENX(3DSTATE_STENCIL_BUFFER_length);
328
329 GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
330 dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
331
332 GENX(3DSTATE_CLEAR_PARAMS_pack)(NULL, dw, &clear);
333 dw += GENX(3DSTATE_CLEAR_PARAMS_length);
334 #endif
335 }
336