1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
4
5 #include <linux/kvm_host.h>
6
7 #include <asm/kvm.h>
8 #include <asm/intel_pt.h>
9
10 #include "capabilities.h"
11 #include "kvm_cache_regs.h"
12 #include "posted_intr.h"
13 #include "vmcs.h"
14 #include "vmx_ops.h"
15 #include "cpuid.h"
16 #include "run_flags.h"
17
18 extern const u32 vmx_msr_index[];
19
20 #define MSR_TYPE_R 1
21 #define MSR_TYPE_W 2
22 #define MSR_TYPE_RW 3
23
24 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
25
26 #ifdef CONFIG_X86_64
27 #define MAX_NR_USER_RETURN_MSRS 7
28 #else
29 #define MAX_NR_USER_RETURN_MSRS 4
30 #endif
31
32 #define MAX_NR_LOADSTORE_MSRS 8
33
34 struct vmx_msrs {
35 unsigned int nr;
36 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
37 };
38
39 struct vmx_uret_msr {
40 unsigned int slot; /* The MSR's slot in kvm_user_return_msrs. */
41 u64 data;
42 u64 mask;
43 };
44
45 enum segment_cache_field {
46 SEG_FIELD_SEL = 0,
47 SEG_FIELD_BASE = 1,
48 SEG_FIELD_LIMIT = 2,
49 SEG_FIELD_AR = 3,
50
51 SEG_FIELD_NR = 4
52 };
53
54 #define RTIT_ADDR_RANGE 4
55
56 struct pt_ctx {
57 u64 ctl;
58 u64 status;
59 u64 output_base;
60 u64 output_mask;
61 u64 cr3_match;
62 u64 addr_a[RTIT_ADDR_RANGE];
63 u64 addr_b[RTIT_ADDR_RANGE];
64 };
65
66 struct pt_desc {
67 u64 ctl_bitmask;
68 u32 addr_range;
69 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
70 struct pt_ctx host;
71 struct pt_ctx guest;
72 };
73
74 union vmx_exit_reason {
75 struct {
76 u32 basic : 16;
77 u32 reserved16 : 1;
78 u32 reserved17 : 1;
79 u32 reserved18 : 1;
80 u32 reserved19 : 1;
81 u32 reserved20 : 1;
82 u32 reserved21 : 1;
83 u32 reserved22 : 1;
84 u32 reserved23 : 1;
85 u32 reserved24 : 1;
86 u32 reserved25 : 1;
87 u32 reserved26 : 1;
88 u32 enclave_mode : 1;
89 u32 smi_pending_mtf : 1;
90 u32 smi_from_vmx_root : 1;
91 u32 reserved30 : 1;
92 u32 failed_vmentry : 1;
93 };
94 u32 full;
95 };
96
97 /*
98 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
99 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
100 */
101 struct nested_vmx {
102 /* Has the level1 guest done vmxon? */
103 bool vmxon;
104 gpa_t vmxon_ptr;
105 bool pml_full;
106
107 /* The guest-physical address of the current VMCS L1 keeps for L2 */
108 gpa_t current_vmptr;
109 /*
110 * Cache of the guest's VMCS, existing outside of guest memory.
111 * Loaded from guest memory during VMPTRLD. Flushed to guest
112 * memory during VMCLEAR and VMPTRLD.
113 */
114 struct vmcs12 *cached_vmcs12;
115 /*
116 * Cache of the guest's shadow VMCS, existing outside of guest
117 * memory. Loaded from guest memory during VM entry. Flushed
118 * to guest memory during VM exit.
119 */
120 struct vmcs12 *cached_shadow_vmcs12;
121
122 /*
123 * Indicates if the shadow vmcs or enlightened vmcs must be updated
124 * with the data held by struct vmcs12.
125 */
126 bool need_vmcs12_to_shadow_sync;
127 bool dirty_vmcs12;
128
129 /*
130 * Indicates lazily loaded guest state has not yet been decached from
131 * vmcs02.
132 */
133 bool need_sync_vmcs02_to_vmcs12_rare;
134
135 /*
136 * vmcs02 has been initialized, i.e. state that is constant for
137 * vmcs02 has been written to the backing VMCS. Initialization
138 * is delayed until L1 actually attempts to run a nested VM.
139 */
140 bool vmcs02_initialized;
141
142 bool change_vmcs01_virtual_apic_mode;
143 bool reload_vmcs01_apic_access_page;
144
145 /*
146 * Enlightened VMCS has been enabled. It does not mean that L1 has to
147 * use it. However, VMX features available to L1 will be limited based
148 * on what the enlightened VMCS supports.
149 */
150 bool enlightened_vmcs_enabled;
151
152 /* L2 must run next, and mustn't decide to exit to L1. */
153 bool nested_run_pending;
154
155 /* Pending MTF VM-exit into L1. */
156 bool mtf_pending;
157
158 struct loaded_vmcs vmcs02;
159
160 /*
161 * Guest pages referred to in the vmcs02 with host-physical
162 * pointers, so we must keep them pinned while L2 runs.
163 */
164 struct page *apic_access_page;
165 struct kvm_host_map virtual_apic_map;
166 struct kvm_host_map pi_desc_map;
167
168 struct kvm_host_map msr_bitmap_map;
169
170 struct pi_desc *pi_desc;
171 bool pi_pending;
172 u16 posted_intr_nv;
173
174 struct hrtimer preemption_timer;
175 u64 preemption_timer_deadline;
176 bool has_preemption_timer_deadline;
177 bool preemption_timer_expired;
178
179 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
180 u64 vmcs01_debugctl;
181 u64 vmcs01_guest_bndcfgs;
182
183 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
184 int l1_tpr_threshold;
185
186 u16 vpid02;
187 u16 last_vpid;
188
189 struct nested_vmx_msrs msrs;
190
191 /* SMM related state */
192 struct {
193 /* in VMX operation on SMM entry? */
194 bool vmxon;
195 /* in guest mode on SMM entry? */
196 bool guest_mode;
197 } smm;
198
199 gpa_t hv_evmcs_vmptr;
200 struct kvm_host_map hv_evmcs_map;
201 struct hv_enlightened_vmcs *hv_evmcs;
202 };
203
204 struct vcpu_vmx {
205 struct kvm_vcpu vcpu;
206 u8 fail;
207 u8 msr_bitmap_mode;
208
209 /*
210 * If true, host state has been stored in vmx->loaded_vmcs for
211 * the CPU registers that only need to be switched when transitioning
212 * to/from the kernel, and the registers have been loaded with guest
213 * values. If false, host state is loaded in the CPU registers
214 * and vmx->loaded_vmcs->host_state is invalid.
215 */
216 bool guest_state_loaded;
217
218 unsigned long exit_qualification;
219 u32 exit_intr_info;
220 u32 idt_vectoring_info;
221 ulong rflags;
222
223 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
224 int nr_uret_msrs;
225 int nr_active_uret_msrs;
226 bool guest_uret_msrs_loaded;
227 #ifdef CONFIG_X86_64
228 u64 msr_host_kernel_gs_base;
229 u64 msr_guest_kernel_gs_base;
230 #endif
231
232 u64 spec_ctrl;
233 u32 msr_ia32_umwait_control;
234
235 u32 secondary_exec_control;
236
237 /*
238 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
239 * non-nested (L1) guest, it always points to vmcs01. For a nested
240 * guest (L2), it points to a different VMCS.
241 */
242 struct loaded_vmcs vmcs01;
243 struct loaded_vmcs *loaded_vmcs;
244
245 struct msr_autoload {
246 struct vmx_msrs guest;
247 struct vmx_msrs host;
248 } msr_autoload;
249
250 struct msr_autostore {
251 struct vmx_msrs guest;
252 } msr_autostore;
253
254 struct {
255 int vm86_active;
256 ulong save_rflags;
257 struct kvm_segment segs[8];
258 } rmode;
259 struct {
260 u32 bitmask; /* 4 bits per segment (1 bit per field) */
261 struct kvm_save_segment {
262 u16 selector;
263 unsigned long base;
264 u32 limit;
265 u32 ar;
266 } seg[8];
267 } segment_cache;
268 int vpid;
269 bool emulation_required;
270
271 union vmx_exit_reason exit_reason;
272
273 /* Posted interrupt descriptor */
274 struct pi_desc pi_desc;
275
276 /* Support for a guest hypervisor (nested VMX) */
277 struct nested_vmx nested;
278
279 /* Dynamic PLE window. */
280 unsigned int ple_window;
281 bool ple_window_dirty;
282
283 bool req_immediate_exit;
284
285 /* Support for PML */
286 #define PML_ENTITY_NUM 512
287 struct page *pml_pg;
288
289 /* apic deadline value in host tsc */
290 u64 hv_deadline_tsc;
291
292 u64 current_tsc_ratio;
293
294 unsigned long host_debugctlmsr;
295
296 /*
297 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
298 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
299 * in msr_ia32_feature_control_valid_bits.
300 */
301 u64 msr_ia32_feature_control;
302 u64 msr_ia32_feature_control_valid_bits;
303 u64 ept_pointer;
304 u64 msr_ia32_mcu_opt_ctrl;
305 bool disable_fb_clear;
306
307 struct pt_desc pt_desc;
308
309 /* Save desired MSR intercept (read: pass-through) state */
310 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 13
311 struct {
312 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
313 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
314 } shadow_msr_intercept;
315 };
316
317 enum ept_pointers_status {
318 EPT_POINTERS_CHECK = 0,
319 EPT_POINTERS_MATCH = 1,
320 EPT_POINTERS_MISMATCH = 2
321 };
322
323 struct kvm_vmx {
324 struct kvm kvm;
325
326 unsigned int tss_addr;
327 bool ept_identity_pagetable_done;
328 gpa_t ept_identity_map_addr;
329
330 enum ept_pointers_status ept_pointers_match;
331 spinlock_t ept_pointer_lock;
332 };
333
334 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
335 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
336 struct loaded_vmcs *buddy);
337 int allocate_vpid(void);
338 void free_vpid(int vpid);
339 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
340 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
341 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
342 unsigned long fs_base, unsigned long gs_base);
343 int vmx_get_cpl(struct kvm_vcpu *vcpu);
344 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
345 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
346 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
347 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
348 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
349 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
350 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
351 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
352 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
353 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
354 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
355 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa,
356 int root_level);
357
358 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
359 void update_exception_bitmap(struct kvm_vcpu *vcpu);
360 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
361 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
362 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
363 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
364 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
365 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
366 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
367 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
368 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
369 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags);
370 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx);
371 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs,
372 unsigned int flags);
373 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
374 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
375
vmx_get_rvi(void)376 static inline u8 vmx_get_rvi(void)
377 {
378 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
379 }
380
381 #define BUILD_CONTROLS_SHADOW(lname, uname) \
382 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
383 { \
384 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
385 vmcs_write32(uname, val); \
386 vmx->loaded_vmcs->controls_shadow.lname = val; \
387 } \
388 } \
389 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
390 { \
391 return vmx->loaded_vmcs->controls_shadow.lname; \
392 } \
393 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
394 { \
395 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
396 } \
397 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
398 { \
399 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
400 }
BUILD_CONTROLS_SHADOW(vm_entry,VM_ENTRY_CONTROLS)401 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
402 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
403 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
404 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
405 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
406
407 static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu)
408 {
409 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
410 | (1 << VCPU_EXREG_RFLAGS)
411 | (1 << VCPU_EXREG_PDPTR)
412 | (1 << VCPU_EXREG_SEGMENTS)
413 | (1 << VCPU_EXREG_CR0)
414 | (1 << VCPU_EXREG_CR3)
415 | (1 << VCPU_EXREG_CR4)
416 | (1 << VCPU_EXREG_EXIT_INFO_1)
417 | (1 << VCPU_EXREG_EXIT_INFO_2));
418 vcpu->arch.regs_dirty = 0;
419 }
420
vmx_vmentry_ctrl(void)421 static inline u32 vmx_vmentry_ctrl(void)
422 {
423 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
424 if (vmx_pt_mode_is_system())
425 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
426 VM_ENTRY_LOAD_IA32_RTIT_CTL);
427 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
428 return vmentry_ctrl &
429 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
430 }
431
vmx_vmexit_ctrl(void)432 static inline u32 vmx_vmexit_ctrl(void)
433 {
434 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
435 if (vmx_pt_mode_is_system())
436 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
437 VM_EXIT_CLEAR_IA32_RTIT_CTL);
438 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
439 return vmexit_ctrl &
440 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
441 }
442
443 u32 vmx_exec_control(struct vcpu_vmx *vmx);
444 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
445
to_kvm_vmx(struct kvm * kvm)446 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
447 {
448 return container_of(kvm, struct kvm_vmx, kvm);
449 }
450
to_vmx(struct kvm_vcpu * vcpu)451 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
452 {
453 return container_of(vcpu, struct vcpu_vmx, vcpu);
454 }
455
vmx_get_exit_qual(struct kvm_vcpu * vcpu)456 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
457 {
458 struct vcpu_vmx *vmx = to_vmx(vcpu);
459
460 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
461 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
462 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
463 }
464 return vmx->exit_qualification;
465 }
466
vmx_get_intr_info(struct kvm_vcpu * vcpu)467 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
468 {
469 struct vcpu_vmx *vmx = to_vmx(vcpu);
470
471 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
472 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
473 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
474 }
475 return vmx->exit_intr_info;
476 }
477
478 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
479 void free_vmcs(struct vmcs *vmcs);
480 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
481 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
482 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
483
alloc_vmcs(bool shadow)484 static inline struct vmcs *alloc_vmcs(bool shadow)
485 {
486 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
487 GFP_KERNEL_ACCOUNT);
488 }
489
decache_tsc_multiplier(struct vcpu_vmx * vmx)490 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
491 {
492 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
493 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
494 }
495
vmx_has_waitpkg(struct vcpu_vmx * vmx)496 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
497 {
498 return secondary_exec_controls_get(vmx) &
499 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
500 }
501
vmx_need_pf_intercept(struct kvm_vcpu * vcpu)502 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
503 {
504 if (!enable_ept)
505 return true;
506
507 return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
508 }
509
is_unrestricted_guest(struct kvm_vcpu * vcpu)510 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
511 {
512 return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
513 (secondary_exec_controls_get(to_vmx(vcpu)) &
514 SECONDARY_EXEC_UNRESTRICTED_GUEST));
515 }
516
517 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
vmx_guest_state_valid(struct kvm_vcpu * vcpu)518 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
519 {
520 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
521 }
522
523 void dump_vmcs(void);
524
525 #endif /* __KVM_X86_VMX_H */
526