1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/format/u_format.h"
29 #include "util/u_helpers.h"
30 #include "util/u_memory.h"
31 #include "util/u_string.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_query_hw.h"
35 #include "freedreno_resource.h"
36
37 #include "fd4_blend.h"
38 #include "fd4_context.h"
39 #include "fd4_emit.h"
40 #include "fd4_format.h"
41 #include "fd4_program.h"
42 #include "fd4_rasterizer.h"
43 #include "fd4_texture.h"
44 #include "fd4_zsa.h"
45
46 #define emit_const_user fd4_emit_const_user
47 #define emit_const_bo fd4_emit_const_bo
48 #include "ir3_const.h"
49
50 /* regid: base const register
51 * prsc or dwords: buffer containing constant values
52 * sizedwords: size of const value buffer
53 */
54 static void
fd4_emit_const_user(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t sizedwords,const uint32_t * dwords)55 fd4_emit_const_user(struct fd_ringbuffer *ring,
56 const struct ir3_shader_variant *v, uint32_t regid,
57 uint32_t sizedwords, const uint32_t *dwords)
58 {
59 emit_const_asserts(ring, v, regid, sizedwords);
60
61 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sizedwords);
62 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) |
63 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
64 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) |
65 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords / 4));
66 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
67 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
68 for (int i = 0; i < sizedwords; i++)
69 OUT_RING(ring, dwords[i]);
70 }
71
72 static void
fd4_emit_const_bo(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t offset,uint32_t sizedwords,struct fd_bo * bo)73 fd4_emit_const_bo(struct fd_ringbuffer *ring,
74 const struct ir3_shader_variant *v, uint32_t regid,
75 uint32_t offset, uint32_t sizedwords, struct fd_bo *bo)
76 {
77 uint32_t dst_off = regid / 4;
78 assert(dst_off % 4 == 0);
79 uint32_t num_unit = sizedwords / 4;
80 assert(num_unit % 4 == 0);
81
82 emit_const_asserts(ring, v, regid, sizedwords);
83
84 OUT_PKT3(ring, CP_LOAD_STATE4, 2);
85 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(dst_off) |
86 CP_LOAD_STATE4_0_STATE_SRC(SS4_INDIRECT) |
87 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) |
88 CP_LOAD_STATE4_0_NUM_UNIT(num_unit));
89 OUT_RELOC(ring, bo, offset, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
90 }
91
92 static void
fd4_emit_const_ptrs(struct fd_ringbuffer * ring,gl_shader_stage type,uint32_t regid,uint32_t num,struct fd_bo ** bos,uint32_t * offsets)93 fd4_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type,
94 uint32_t regid, uint32_t num, struct fd_bo **bos,
95 uint32_t *offsets)
96 {
97 uint32_t anum = align(num, 4);
98 uint32_t i;
99
100 debug_assert((regid % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + anum);
103 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) |
104 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
105 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
106 CP_LOAD_STATE4_0_NUM_UNIT(anum / 4));
107 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (bos[i]) {
112 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
113 } else {
114 OUT_RING(ring, 0xbad00000 | (i << 16));
115 }
116 }
117
118 for (; i < anum; i++)
119 OUT_RING(ring, 0xffffffff);
120 }
121
122 static bool
is_stateobj(struct fd_ringbuffer * ring)123 is_stateobj(struct fd_ringbuffer *ring)
124 {
125 return false;
126 }
127
128 static void
emit_const_ptrs(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t dst_offset,uint32_t num,struct fd_bo ** bos,uint32_t * offsets)129 emit_const_ptrs(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
130 uint32_t dst_offset, uint32_t num, struct fd_bo **bos,
131 uint32_t *offsets)
132 {
133 /* TODO inline this */
134 assert(dst_offset + num <= v->constlen * 4);
135 fd4_emit_const_ptrs(ring, v->type, dst_offset, num, bos, offsets);
136 }
137
138 static void
emit_textures(struct fd_context * ctx,struct fd_ringbuffer * ring,enum a4xx_state_block sb,struct fd_texture_stateobj * tex,const struct ir3_shader_variant * v)139 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
140 enum a4xx_state_block sb, struct fd_texture_stateobj *tex,
141 const struct ir3_shader_variant *v)
142 {
143 static const uint32_t bcolor_reg[] = {
144 [SB4_VS_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
145 [SB4_FS_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
146 };
147 struct fd4_context *fd4_ctx = fd4_context(ctx);
148 bool needs_border = false;
149 unsigned i;
150
151 if (tex->num_samplers > 0) {
152 int num_samplers;
153
154 /* not sure if this is an a420.0 workaround, but we seem
155 * to need to emit these in pairs.. emit a final dummy
156 * entry if odd # of samplers:
157 */
158 num_samplers = align(tex->num_samplers, 2);
159
160 /* output sampler state: */
161 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * num_samplers));
162 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
163 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
164 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
165 CP_LOAD_STATE4_0_NUM_UNIT(num_samplers));
166 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
167 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
168 for (i = 0; i < tex->num_samplers; i++) {
169 static const struct fd4_sampler_stateobj dummy_sampler = {};
170 const struct fd4_sampler_stateobj *sampler =
171 tex->samplers[i] ? fd4_sampler_stateobj(tex->samplers[i])
172 : &dummy_sampler;
173 OUT_RING(ring, sampler->texsamp0);
174 OUT_RING(ring, sampler->texsamp1);
175
176 needs_border |= sampler->needs_border;
177 }
178
179 for (; i < num_samplers; i++) {
180 OUT_RING(ring, 0x00000000);
181 OUT_RING(ring, 0x00000000);
182 }
183 }
184
185 if (tex->num_textures > 0) {
186 unsigned num_textures = tex->num_textures + v->astc_srgb.count;
187
188 /* emit texture state: */
189 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * num_textures));
190 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
191 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
192 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
193 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
194 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
195 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
196 for (i = 0; i < tex->num_textures; i++) {
197 static const struct fd4_pipe_sampler_view dummy_view = {};
198 const struct fd4_pipe_sampler_view *view =
199 tex->textures[i] ? fd4_pipe_sampler_view(tex->textures[i])
200 : &dummy_view;
201
202 OUT_RING(ring, view->texconst0);
203 OUT_RING(ring, view->texconst1);
204 OUT_RING(ring, view->texconst2);
205 OUT_RING(ring, view->texconst3);
206 if (view->base.texture) {
207 struct fd_resource *rsc = fd_resource(view->base.texture);
208 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
209 rsc = rsc->stencil;
210 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
211 } else {
212 OUT_RING(ring, 0x00000000);
213 }
214 OUT_RING(ring, 0x00000000);
215 OUT_RING(ring, 0x00000000);
216 OUT_RING(ring, 0x00000000);
217 }
218
219 for (i = 0; i < v->astc_srgb.count; i++) {
220 static const struct fd4_pipe_sampler_view dummy_view = {};
221 const struct fd4_pipe_sampler_view *view;
222 unsigned idx = v->astc_srgb.orig_idx[i];
223
224 view = tex->textures[idx] ? fd4_pipe_sampler_view(tex->textures[idx])
225 : &dummy_view;
226
227 debug_assert(view->texconst0 & A4XX_TEX_CONST_0_SRGB);
228
229 OUT_RING(ring, view->texconst0 & ~A4XX_TEX_CONST_0_SRGB);
230 OUT_RING(ring, view->texconst1);
231 OUT_RING(ring, view->texconst2);
232 OUT_RING(ring, view->texconst3);
233 if (view->base.texture) {
234 struct fd_resource *rsc = fd_resource(view->base.texture);
235 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
236 } else {
237 OUT_RING(ring, 0x00000000);
238 }
239 OUT_RING(ring, 0x00000000);
240 OUT_RING(ring, 0x00000000);
241 OUT_RING(ring, 0x00000000);
242 }
243 } else {
244 debug_assert(v->astc_srgb.count == 0);
245 }
246
247 if (needs_border) {
248 unsigned off;
249 void *ptr;
250
251 u_upload_alloc(fd4_ctx->border_color_uploader, 0,
252 BORDER_COLOR_UPLOAD_SIZE, BORDER_COLOR_UPLOAD_SIZE, &off,
253 &fd4_ctx->border_color_buf, &ptr);
254
255 fd_setup_border_colors(tex, ptr, 0);
256 OUT_PKT0(ring, bcolor_reg[sb], 1);
257 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
258
259 u_upload_unmap(fd4_ctx->border_color_uploader);
260 }
261 }
262
263 /* emit texture state for mem->gmem restore operation.. eventually it would
264 * be good to get rid of this and use normal CSO/etc state for more of these
265 * special cases..
266 */
267 void
fd4_emit_gmem_restore_tex(struct fd_ringbuffer * ring,unsigned nr_bufs,struct pipe_surface ** bufs)268 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
269 struct pipe_surface **bufs)
270 {
271 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
272 int i;
273
274 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
275 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
276 }
277
278 /* output sampler state: */
279 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * nr_bufs));
280 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
281 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
282 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
283 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
284 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
285 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
286 for (i = 0; i < nr_bufs; i++) {
287 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
288 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
289 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
290 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
291 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
292 OUT_RING(ring, 0x00000000);
293 }
294
295 /* emit texture state: */
296 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * nr_bufs));
297 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
298 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
299 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
300 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
301 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
302 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
303 for (i = 0; i < nr_bufs; i++) {
304 if (bufs[i]) {
305 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
306 enum pipe_format format = fd_gmem_restore_format(bufs[i]->format);
307
308 /* The restore blit_zs shader expects stencil in sampler 0,
309 * and depth in sampler 1
310 */
311 if (rsc->stencil && (i == 0)) {
312 rsc = rsc->stencil;
313 format = fd_gmem_restore_format(rsc->b.b.format);
314 }
315
316 /* note: PIPE_BUFFER disallowed for surfaces */
317 unsigned lvl = bufs[i]->u.tex.level;
318 unsigned offset =
319 fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
320
321 /* z32 restore is accomplished using depth write. If there is
322 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
323 * then no render target:
324 *
325 * (The same applies for z32_s8x24, since for stencil sampler
326 * state the above 'if' will replace 'format' with s8)
327 */
328 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
329 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
330 mrt_comp[i] = 0;
331
332 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
333
334 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
335 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
336 fd4_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
337 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
338 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
339 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
340 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc, lvl)));
341 OUT_RING(ring, 0x00000000);
342 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
343 OUT_RING(ring, 0x00000000);
344 OUT_RING(ring, 0x00000000);
345 OUT_RING(ring, 0x00000000);
346 } else {
347 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
348 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
349 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
350 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
351 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
352 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
353 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) | A4XX_TEX_CONST_1_HEIGHT(0));
354 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
355 OUT_RING(ring, 0x00000000);
356 OUT_RING(ring, 0x00000000);
357 OUT_RING(ring, 0x00000000);
358 OUT_RING(ring, 0x00000000);
359 OUT_RING(ring, 0x00000000);
360 }
361 }
362
363 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
364 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
365 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
366 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
367 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
368 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
369 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
370 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
371 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
372 }
373
374 void
fd4_emit_vertex_bufs(struct fd_ringbuffer * ring,struct fd4_emit * emit)375 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
376 {
377 int32_t i, j, last = -1;
378 uint32_t total_in = 0;
379 const struct fd_vertex_state *vtx = emit->vtx;
380 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
381 unsigned vertex_regid = regid(63, 0);
382 unsigned instance_regid = regid(63, 0);
383 unsigned vtxcnt_regid = regid(63, 0);
384
385 /* Note that sysvals come *after* normal inputs: */
386 for (i = 0; i < vp->inputs_count; i++) {
387 if (!vp->inputs[i].compmask)
388 continue;
389 if (vp->inputs[i].sysval) {
390 switch (vp->inputs[i].slot) {
391 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
392 vertex_regid = vp->inputs[i].regid;
393 break;
394 case SYSTEM_VALUE_INSTANCE_ID:
395 instance_regid = vp->inputs[i].regid;
396 break;
397 case SYSTEM_VALUE_VERTEX_CNT:
398 vtxcnt_regid = vp->inputs[i].regid;
399 break;
400 default:
401 unreachable("invalid system value");
402 break;
403 }
404 } else if (i < vtx->vtx->num_elements) {
405 last = i;
406 }
407 }
408
409 for (i = 0, j = 0; i <= last; i++) {
410 assert(!vp->inputs[i].sysval);
411 if (vp->inputs[i].compmask) {
412 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
413 const struct pipe_vertex_buffer *vb =
414 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
415 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
416 enum pipe_format pfmt = elem->src_format;
417 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
418 bool switchnext = (i != last) || (vertex_regid != regid(63, 0)) ||
419 (instance_regid != regid(63, 0)) ||
420 (vtxcnt_regid != regid(63, 0));
421 bool isint = util_format_is_pure_integer(pfmt);
422 uint32_t fs = util_format_get_blocksize(pfmt);
423 uint32_t off = vb->buffer_offset + elem->src_offset;
424 uint32_t size = fd_bo_size(rsc->bo) - off;
425 debug_assert(fmt != VFMT4_NONE);
426
427 #ifdef DEBUG
428 /* see
429 * dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
430 */
431 if (off > fd_bo_size(rsc->bo))
432 continue;
433 #endif
434
435 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
436 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
437 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
438 COND(elem->instance_divisor,
439 A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
440 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
441 OUT_RELOC(ring, rsc->bo, off, 0, 0);
442 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
443 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(
444 MAX2(1, elem->instance_divisor)));
445
446 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
447 OUT_RING(ring,
448 A4XX_VFD_DECODE_INSTR_CONSTFILL |
449 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
450 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
451 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
452 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
453 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
454 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
455 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
456 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
457
458 total_in += util_bitcount(vp->inputs[i].compmask);
459 j++;
460 }
461 }
462
463 /* hw doesn't like to be configured for zero vbo's, it seems: */
464 if (last < 0) {
465 /* just recycle the shader bo, we just need to point to *something*
466 * valid:
467 */
468 struct fd_bo *dummy_vbo = vp->bo;
469 bool switchnext = (vertex_regid != regid(63, 0)) ||
470 (instance_regid != regid(63, 0)) ||
471 (vtxcnt_regid != regid(63, 0));
472
473 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
474 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
475 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
476 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
477 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
478 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
479 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
480
481 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
482 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
483 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
484 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
485 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
486 A4XX_VFD_DECODE_INSTR_REGID(regid(0, 0)) |
487 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
488 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
489 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
490
491 total_in = 1;
492 j = 1;
493 }
494
495 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
496 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
497 0xa0000 | /* XXX */
498 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
499 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
500 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
501 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
502 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
503 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
504 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
505 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
506
507 /* cache invalidate, otherwise vertex fetch could see
508 * stale vbo contents:
509 */
510 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
511 OUT_RING(ring, 0x00000000);
512 OUT_RING(ring, 0x00000012);
513 }
514
515 void
fd4_emit_state(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd4_emit * emit)516 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
517 struct fd4_emit *emit)
518 {
519 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
520 const struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
521 const enum fd_dirty_3d_state dirty = emit->dirty;
522
523 emit_marker(ring, 5);
524
525 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
526 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
527 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
528
529 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
530 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
531 }
532
533 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
534 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
535 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
536 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
537 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
538 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
539 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
540 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
541 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
542 }
543
544 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
545 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
546 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
547 uint32_t rb_alpha_control = zsa->rb_alpha_control;
548
549 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
550 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
551
552 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
553 OUT_RING(ring, rb_alpha_control);
554
555 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
556 OUT_RING(ring, zsa->rb_stencil_control);
557 OUT_RING(ring, zsa->rb_stencil_control2);
558 }
559
560 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
561 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
562 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
563
564 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
565 OUT_RING(ring, zsa->rb_stencilrefmask |
566 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
567 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
568 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
569 }
570
571 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
572 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
573 bool fragz = fp->no_earlyz | fp->has_kill | fp->writes_pos;
574 bool clamp = !ctx->rasterizer->depth_clip_near;
575
576 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
577 OUT_RING(ring, zsa->rb_depth_control |
578 COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) |
579 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
580 COND(fragz && fp->fragcoord_compmask != 0,
581 A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
582
583 /* maybe this register/bitfield needs a better name.. this
584 * appears to be just disabling early-z
585 */
586 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
587 OUT_RING(ring, zsa->gras_alpha_control |
588 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
589 COND(fragz && fp->fragcoord_compmask != 0,
590 A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
591 }
592
593 if (dirty & FD_DIRTY_RASTERIZER) {
594 struct fd4_rasterizer_stateobj *rasterizer =
595 fd4_rasterizer_stateobj(ctx->rasterizer);
596
597 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
598 OUT_RING(ring, rasterizer->gras_su_mode_control |
599 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
600
601 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
602 OUT_RING(ring, rasterizer->gras_su_point_minmax);
603 OUT_RING(ring, rasterizer->gras_su_point_size);
604
605 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
606 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
607 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
608 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
609
610 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
611 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
612 }
613
614 /* NOTE: since primitive_restart is not actually part of any
615 * state object, we need to make sure that we always emit
616 * PRIM_VTX_CNTL.. either that or be more clever and detect
617 * when it changes.
618 */
619 if (emit->info) {
620 const struct pipe_draw_info *info = emit->info;
621 struct fd4_rasterizer_stateobj *rast =
622 fd4_rasterizer_stateobj(ctx->rasterizer);
623 uint32_t val = rast->pc_prim_vtx_cntl;
624
625 if (info->index_size && info->primitive_restart)
626 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
627
628 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
629
630 if (fp->total_in > 0) {
631 uint32_t varout = align(fp->total_in, 16) / 16;
632 if (varout > 1)
633 varout = align(varout, 2);
634 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
635 }
636
637 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
638 OUT_RING(ring, val);
639 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
640 }
641
642 /* NOTE: scissor enabled bit is part of rasterizer state: */
643 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
644 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
645
646 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
647 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
648 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
649 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
650 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
651
652 ctx->batch->max_scissor.minx =
653 MIN2(ctx->batch->max_scissor.minx, scissor->minx);
654 ctx->batch->max_scissor.miny =
655 MIN2(ctx->batch->max_scissor.miny, scissor->miny);
656 ctx->batch->max_scissor.maxx =
657 MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
658 ctx->batch->max_scissor.maxy =
659 MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
660 }
661
662 if (dirty & FD_DIRTY_VIEWPORT) {
663 fd_wfi(ctx->batch, ring);
664 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
665 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
666 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
667 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
668 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
669 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
670 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
671 }
672
673 if (dirty &
674 (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
675 float zmin, zmax;
676 int depth = 24;
677 if (ctx->batch->framebuffer.zsbuf) {
678 depth = util_format_get_component_bits(
679 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
680 UTIL_FORMAT_COLORSPACE_ZS, 0);
681 }
682 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
683 &zmin, &zmax);
684
685 OUT_PKT0(ring, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
686 if (depth == 32) {
687 OUT_RING(ring, fui(zmin));
688 OUT_RING(ring, fui(zmax));
689 } else if (depth == 16) {
690 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
691 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
692 } else {
693 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
694 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
695 }
696 }
697
698 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
699 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
700 unsigned n = pfb->nr_cbufs;
701 /* if we have depth/stencil, we need at least on MRT: */
702 if (pfb->zsbuf)
703 n = MAX2(1, n);
704 fd4_program_emit(ring, emit, n, pfb->cbufs);
705 }
706
707 if (!emit->skip_consts) { /* evil hack to deal sanely with clear path */
708 ir3_emit_vs_consts(vp, ring, ctx, emit->info, emit->indirect, emit->draw);
709 if (!emit->binning_pass)
710 ir3_emit_fs_consts(fp, ring, ctx);
711 }
712
713 if ((dirty & FD_DIRTY_BLEND)) {
714 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
715 uint32_t i;
716
717 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
718 enum pipe_format format =
719 pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
720 bool is_int = util_format_is_pure_integer(format);
721 bool has_alpha = util_format_has_alpha(format);
722 uint32_t control = blend->rb_mrt[i].control;
723
724 if (is_int) {
725 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
726 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
727 }
728
729 if (!has_alpha) {
730 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
731 }
732
733 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
734 OUT_RING(ring, control);
735
736 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
737 OUT_RING(ring, blend->rb_mrt[i].blend_control);
738 }
739
740 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
741 OUT_RING(ring,
742 blend->rb_fs_output | A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
743 }
744
745 if (dirty & FD_DIRTY_BLEND_COLOR) {
746 struct pipe_blend_color *bcolor = &ctx->blend_color;
747
748 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
749 OUT_RING(ring, A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
750 A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
751 A4XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
752 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
753 OUT_RING(ring, A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
754 A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
755 A4XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
756 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[1]));
757 OUT_RING(ring, A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
758 A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
759 A4XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
760 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
761 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
762 A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
763 A4XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
764 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
765 }
766
767 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
768 emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX], vp);
769
770 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
771 emit_textures(ctx, ring, SB4_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT], fp);
772 }
773
774 /* emit setup at begin of new cmdstream buffer (don't rely on previous
775 * state, there could have been a context switch between ioctls):
776 */
777 void
fd4_emit_restore(struct fd_batch * batch,struct fd_ringbuffer * ring)778 fd4_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
779 {
780 struct fd_context *ctx = batch->ctx;
781 struct fd4_context *fd4_ctx = fd4_context(ctx);
782
783 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
784 OUT_RING(ring, 0x00000001);
785
786 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
787 OUT_RING(ring, 0x00000000);
788
789 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
790 OUT_RING(ring, 0x00000006);
791
792 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
793 OUT_RING(ring, 0x0000003a);
794
795 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
796 OUT_RING(ring, 0x00000001);
797
798 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
799 OUT_RING(ring, 0x00000000);
800
801 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
802 OUT_RING(ring, 0x00000007);
803
804 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
805 OUT_RING(ring, 0x00000000);
806
807 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
808 OUT_RING(ring, 0x00000000);
809 OUT_RING(ring, 0x00000012);
810
811 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
812 OUT_RING(ring, 0x00000000);
813
814 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
815 OUT_RING(ring, 0x00000006);
816
817 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
818 OUT_RING(ring, 0x00000000);
819
820 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
821 OUT_RING(ring, 0x00040000);
822
823 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
824 OUT_RING(ring, 0x00000000);
825
826 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
827 OUT_RING(ring, 0x00001000);
828
829 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
830 OUT_RING(ring, 0x00000000);
831
832 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
833 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) | A4XX_RB_BLEND_RED_FLOAT(0.0));
834 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) | A4XX_RB_BLEND_GREEN_FLOAT(0.0));
835 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) | A4XX_RB_BLEND_BLUE_FLOAT(0.0));
836 OUT_RING(ring,
837 A4XX_RB_BLEND_ALPHA_UINT(0x7fff) | A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
838
839 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
840 OUT_RING(ring, 0x00000000);
841
842 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
843 OUT_RING(ring, 0x00000000);
844
845 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
846 OUT_RING(ring, 0x00000000);
847
848 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
849 OUT_RING(ring, 0x00000000);
850
851 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
852 OUT_RING(ring, 0x00000000);
853
854 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
855 OUT_RING(ring, 0x00000000);
856
857 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
858 OUT_RING(ring, 0x0000001d);
859
860 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
861 OUT_RING(ring, 0x00000000);
862
863 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
864 OUT_RING(ring, 0x00000001);
865
866 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
867 OUT_RING(ring, 0x00000000);
868
869 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
870 OUT_RING(ring, 0x00000000);
871
872 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
873 OUT_RING(ring, 0x00000000);
874
875 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
876 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) | A4XX_TPL1_TP_TEX_COUNT_HS(0) |
877 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
878 A4XX_TPL1_TP_TEX_COUNT_GS(0));
879
880 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
881 OUT_RING(ring, 16);
882
883 /* we don't use this yet.. probably best to disable.. */
884 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
885 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
886 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
887 CP_SET_DRAW_STATE__0_GROUP_ID(0));
888 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
889
890 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
891 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
892 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0, 0, 0); /* SP_VS_PVT_MEM_ADDR */
893
894 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
895 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
896 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0, 0, 0); /* SP_FS_PVT_MEM_ADDR */
897
898 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
899 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
900 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
901 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
902 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
903
904 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
905 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
906 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
907
908 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
909 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
910 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
911
912 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
913 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
914
915 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
916 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
917
918 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
919 OUT_RING(ring, 0x0);
920
921 fd_hw_query_enable(batch, ring);
922 }
923
924 static void
fd4_mem_to_mem(struct fd_ringbuffer * ring,struct pipe_resource * dst,unsigned dst_off,struct pipe_resource * src,unsigned src_off,unsigned sizedwords)925 fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
926 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
927 unsigned sizedwords)
928 {
929 struct fd_bo *src_bo = fd_resource(src)->bo;
930 struct fd_bo *dst_bo = fd_resource(dst)->bo;
931 unsigned i;
932
933 for (i = 0; i < sizedwords; i++) {
934 OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
935 OUT_RING(ring, 0x00000000);
936 OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
937 OUT_RELOC(ring, src_bo, src_off, 0, 0);
938
939 dst_off += 4;
940 src_off += 4;
941 }
942 }
943
944 void
fd4_emit_init_screen(struct pipe_screen * pscreen)945 fd4_emit_init_screen(struct pipe_screen *pscreen)
946 {
947 struct fd_screen *screen = fd_screen(pscreen);
948
949 screen->emit_ib = fd4_emit_ib;
950 screen->mem_to_mem = fd4_mem_to_mem;
951 }
952
953 void
fd4_emit_init(struct pipe_context * pctx)954 fd4_emit_init(struct pipe_context *pctx)
955 {
956 }
957