1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * tools/testing/selftests/kvm/include/x86_64/processor.h
4 *
5 * Copyright (C) 2018, Google LLC.
6 */
7
8 #ifndef SELFTEST_KVM_PROCESSOR_H
9 #define SELFTEST_KVM_PROCESSOR_H
10
11 #include <assert.h>
12 #include <stdint.h>
13
14 #include <asm/msr-index.h>
15
16 #define X86_EFLAGS_FIXED (1u << 1)
17
18 #define X86_CR4_VME (1ul << 0)
19 #define X86_CR4_PVI (1ul << 1)
20 #define X86_CR4_TSD (1ul << 2)
21 #define X86_CR4_DE (1ul << 3)
22 #define X86_CR4_PSE (1ul << 4)
23 #define X86_CR4_PAE (1ul << 5)
24 #define X86_CR4_MCE (1ul << 6)
25 #define X86_CR4_PGE (1ul << 7)
26 #define X86_CR4_PCE (1ul << 8)
27 #define X86_CR4_OSFXSR (1ul << 9)
28 #define X86_CR4_OSXMMEXCPT (1ul << 10)
29 #define X86_CR4_UMIP (1ul << 11)
30 #define X86_CR4_VMXE (1ul << 13)
31 #define X86_CR4_SMXE (1ul << 14)
32 #define X86_CR4_FSGSBASE (1ul << 16)
33 #define X86_CR4_PCIDE (1ul << 17)
34 #define X86_CR4_OSXSAVE (1ul << 18)
35 #define X86_CR4_SMEP (1ul << 20)
36 #define X86_CR4_SMAP (1ul << 21)
37 #define X86_CR4_PKE (1ul << 22)
38
39 #define UNEXPECTED_VECTOR_PORT 0xfff0u
40
41 /* General Registers in 64-Bit Mode */
42 struct gpr64_regs {
43 u64 rax;
44 u64 rcx;
45 u64 rdx;
46 u64 rbx;
47 u64 rsp;
48 u64 rbp;
49 u64 rsi;
50 u64 rdi;
51 u64 r8;
52 u64 r9;
53 u64 r10;
54 u64 r11;
55 u64 r12;
56 u64 r13;
57 u64 r14;
58 u64 r15;
59 };
60
61 struct desc64 {
62 uint16_t limit0;
63 uint16_t base0;
64 unsigned base1:8, type:4, s:1, dpl:2, p:1;
65 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
66 uint32_t base3;
67 uint32_t zero1;
68 } __attribute__((packed));
69
70 struct desc_ptr {
71 uint16_t size;
72 uint64_t address;
73 } __attribute__((packed));
74
get_desc64_base(const struct desc64 * desc)75 static inline uint64_t get_desc64_base(const struct desc64 *desc)
76 {
77 return ((uint64_t)desc->base3 << 32) |
78 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
79 }
80
rdtsc(void)81 static inline uint64_t rdtsc(void)
82 {
83 uint32_t eax, edx;
84 uint64_t tsc_val;
85 /*
86 * The lfence is to wait (on Intel CPUs) until all previous
87 * instructions have been executed. If software requires RDTSC to be
88 * executed prior to execution of any subsequent instruction, it can
89 * execute LFENCE immediately after RDTSC
90 */
91 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
92 tsc_val = ((uint64_t)edx) << 32 | eax;
93 return tsc_val;
94 }
95
rdtscp(uint32_t * aux)96 static inline uint64_t rdtscp(uint32_t *aux)
97 {
98 uint32_t eax, edx;
99
100 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
101 return ((uint64_t)edx) << 32 | eax;
102 }
103
rdmsr(uint32_t msr)104 static inline uint64_t rdmsr(uint32_t msr)
105 {
106 uint32_t a, d;
107
108 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
109
110 return a | ((uint64_t) d << 32);
111 }
112
wrmsr(uint32_t msr,uint64_t value)113 static inline void wrmsr(uint32_t msr, uint64_t value)
114 {
115 uint32_t a = value;
116 uint32_t d = value >> 32;
117
118 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
119 }
120
121
inw(uint16_t port)122 static inline uint16_t inw(uint16_t port)
123 {
124 uint16_t tmp;
125
126 __asm__ __volatile__("in %%dx, %%ax"
127 : /* output */ "=a" (tmp)
128 : /* input */ "d" (port));
129
130 return tmp;
131 }
132
get_es(void)133 static inline uint16_t get_es(void)
134 {
135 uint16_t es;
136
137 __asm__ __volatile__("mov %%es, %[es]"
138 : /* output */ [es]"=rm"(es));
139 return es;
140 }
141
get_cs(void)142 static inline uint16_t get_cs(void)
143 {
144 uint16_t cs;
145
146 __asm__ __volatile__("mov %%cs, %[cs]"
147 : /* output */ [cs]"=rm"(cs));
148 return cs;
149 }
150
get_ss(void)151 static inline uint16_t get_ss(void)
152 {
153 uint16_t ss;
154
155 __asm__ __volatile__("mov %%ss, %[ss]"
156 : /* output */ [ss]"=rm"(ss));
157 return ss;
158 }
159
get_ds(void)160 static inline uint16_t get_ds(void)
161 {
162 uint16_t ds;
163
164 __asm__ __volatile__("mov %%ds, %[ds]"
165 : /* output */ [ds]"=rm"(ds));
166 return ds;
167 }
168
get_fs(void)169 static inline uint16_t get_fs(void)
170 {
171 uint16_t fs;
172
173 __asm__ __volatile__("mov %%fs, %[fs]"
174 : /* output */ [fs]"=rm"(fs));
175 return fs;
176 }
177
get_gs(void)178 static inline uint16_t get_gs(void)
179 {
180 uint16_t gs;
181
182 __asm__ __volatile__("mov %%gs, %[gs]"
183 : /* output */ [gs]"=rm"(gs));
184 return gs;
185 }
186
get_tr(void)187 static inline uint16_t get_tr(void)
188 {
189 uint16_t tr;
190
191 __asm__ __volatile__("str %[tr]"
192 : /* output */ [tr]"=rm"(tr));
193 return tr;
194 }
195
get_cr0(void)196 static inline uint64_t get_cr0(void)
197 {
198 uint64_t cr0;
199
200 __asm__ __volatile__("mov %%cr0, %[cr0]"
201 : /* output */ [cr0]"=r"(cr0));
202 return cr0;
203 }
204
get_cr3(void)205 static inline uint64_t get_cr3(void)
206 {
207 uint64_t cr3;
208
209 __asm__ __volatile__("mov %%cr3, %[cr3]"
210 : /* output */ [cr3]"=r"(cr3));
211 return cr3;
212 }
213
get_cr4(void)214 static inline uint64_t get_cr4(void)
215 {
216 uint64_t cr4;
217
218 __asm__ __volatile__("mov %%cr4, %[cr4]"
219 : /* output */ [cr4]"=r"(cr4));
220 return cr4;
221 }
222
set_cr4(uint64_t val)223 static inline void set_cr4(uint64_t val)
224 {
225 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
226 }
227
get_gdt(void)228 static inline struct desc_ptr get_gdt(void)
229 {
230 struct desc_ptr gdt;
231 __asm__ __volatile__("sgdt %[gdt]"
232 : /* output */ [gdt]"=m"(gdt));
233 return gdt;
234 }
235
get_idt(void)236 static inline struct desc_ptr get_idt(void)
237 {
238 struct desc_ptr idt;
239 __asm__ __volatile__("sidt %[idt]"
240 : /* output */ [idt]"=m"(idt));
241 return idt;
242 }
243
outl(uint16_t port,uint32_t value)244 static inline void outl(uint16_t port, uint32_t value)
245 {
246 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value));
247 }
248
249 #define SET_XMM(__var, __xmm) \
250 asm volatile("movq %0, %%"#__xmm : : "r"(__var) : #__xmm)
251
set_xmm(int n,unsigned long val)252 static inline void set_xmm(int n, unsigned long val)
253 {
254 switch (n) {
255 case 0:
256 SET_XMM(val, xmm0);
257 break;
258 case 1:
259 SET_XMM(val, xmm1);
260 break;
261 case 2:
262 SET_XMM(val, xmm2);
263 break;
264 case 3:
265 SET_XMM(val, xmm3);
266 break;
267 case 4:
268 SET_XMM(val, xmm4);
269 break;
270 case 5:
271 SET_XMM(val, xmm5);
272 break;
273 case 6:
274 SET_XMM(val, xmm6);
275 break;
276 case 7:
277 SET_XMM(val, xmm7);
278 break;
279 }
280 }
281
282 typedef unsigned long v1di __attribute__ ((vector_size (8)));
get_xmm(int n)283 static inline unsigned long get_xmm(int n)
284 {
285 assert(n >= 0 && n <= 7);
286
287 register v1di xmm0 __asm__("%xmm0");
288 register v1di xmm1 __asm__("%xmm1");
289 register v1di xmm2 __asm__("%xmm2");
290 register v1di xmm3 __asm__("%xmm3");
291 register v1di xmm4 __asm__("%xmm4");
292 register v1di xmm5 __asm__("%xmm5");
293 register v1di xmm6 __asm__("%xmm6");
294 register v1di xmm7 __asm__("%xmm7");
295 switch (n) {
296 case 0:
297 return (unsigned long)xmm0;
298 case 1:
299 return (unsigned long)xmm1;
300 case 2:
301 return (unsigned long)xmm2;
302 case 3:
303 return (unsigned long)xmm3;
304 case 4:
305 return (unsigned long)xmm4;
306 case 5:
307 return (unsigned long)xmm5;
308 case 6:
309 return (unsigned long)xmm6;
310 case 7:
311 return (unsigned long)xmm7;
312 }
313 return 0;
314 }
315
316 bool is_intel_cpu(void);
317
318 struct kvm_x86_state;
319 struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid);
320 void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid,
321 struct kvm_x86_state *state);
322
323 struct kvm_msr_list *kvm_get_msr_index_list(void);
324
325 struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
326 void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid,
327 struct kvm_cpuid2 *cpuid);
328
329 struct kvm_cpuid_entry2 *
330 kvm_get_supported_cpuid_index(uint32_t function, uint32_t index);
331
332 static inline struct kvm_cpuid_entry2 *
kvm_get_supported_cpuid_entry(uint32_t function)333 kvm_get_supported_cpuid_entry(uint32_t function)
334 {
335 return kvm_get_supported_cpuid_index(function, 0);
336 }
337
338 uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index);
339 int _vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
340 uint64_t msr_value);
341 void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
342 uint64_t msr_value);
343
344 uint32_t kvm_get_cpuid_max_basic(void);
345 uint32_t kvm_get_cpuid_max_extended(void);
346 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
347
348 struct ex_regs {
349 uint64_t rax, rcx, rdx, rbx;
350 uint64_t rbp, rsi, rdi;
351 uint64_t r8, r9, r10, r11;
352 uint64_t r12, r13, r14, r15;
353 uint64_t vector;
354 uint64_t error_code;
355 uint64_t rip;
356 uint64_t cs;
357 uint64_t rflags;
358 };
359
360 void vm_init_descriptor_tables(struct kvm_vm *vm);
361 void vcpu_init_descriptor_tables(struct kvm_vm *vm, uint32_t vcpuid);
362 void vm_handle_exception(struct kvm_vm *vm, int vector,
363 void (*handler)(struct ex_regs *));
364
365 /*
366 * set_cpuid() - overwrites a matching cpuid entry with the provided value.
367 * matches based on ent->function && ent->index. returns true
368 * if a match was found and successfully overwritten.
369 * @cpuid: the kvm cpuid list to modify.
370 * @ent: cpuid entry to insert
371 */
372 bool set_cpuid(struct kvm_cpuid2 *cpuid, struct kvm_cpuid_entry2 *ent);
373
374 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
375 uint64_t a3);
376
377 /*
378 * Basic CPU control in CR0
379 */
380 #define X86_CR0_PE (1UL<<0) /* Protection Enable */
381 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */
382 #define X86_CR0_EM (1UL<<2) /* Emulation */
383 #define X86_CR0_TS (1UL<<3) /* Task Switched */
384 #define X86_CR0_ET (1UL<<4) /* Extension Type */
385 #define X86_CR0_NE (1UL<<5) /* Numeric Error */
386 #define X86_CR0_WP (1UL<<16) /* Write Protect */
387 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */
388 #define X86_CR0_NW (1UL<<29) /* Not Write-through */
389 #define X86_CR0_CD (1UL<<30) /* Cache Disable */
390 #define X86_CR0_PG (1UL<<31) /* Paging */
391
392 #define APIC_BASE_MSR 0x800
393 #define X2APIC_ENABLE (1UL << 10)
394 #define APIC_ICR 0x300
395 #define APIC_DEST_SELF 0x40000
396 #define APIC_DEST_ALLINC 0x80000
397 #define APIC_DEST_ALLBUT 0xC0000
398 #define APIC_ICR_RR_MASK 0x30000
399 #define APIC_ICR_RR_INVALID 0x00000
400 #define APIC_ICR_RR_INPROG 0x10000
401 #define APIC_ICR_RR_VALID 0x20000
402 #define APIC_INT_LEVELTRIG 0x08000
403 #define APIC_INT_ASSERT 0x04000
404 #define APIC_ICR_BUSY 0x01000
405 #define APIC_DEST_LOGICAL 0x00800
406 #define APIC_DEST_PHYSICAL 0x00000
407 #define APIC_DM_FIXED 0x00000
408 #define APIC_DM_FIXED_MASK 0x00700
409 #define APIC_DM_LOWEST 0x00100
410 #define APIC_DM_SMI 0x00200
411 #define APIC_DM_REMRD 0x00300
412 #define APIC_DM_NMI 0x00400
413 #define APIC_DM_INIT 0x00500
414 #define APIC_DM_STARTUP 0x00600
415 #define APIC_DM_EXTINT 0x00700
416 #define APIC_VECTOR_MASK 0x000FF
417 #define APIC_ICR2 0x310
418
419 /* VMX_EPT_VPID_CAP bits */
420 #define VMX_EPT_VPID_CAP_AD_BITS (1ULL << 21)
421
422 #endif /* SELFTEST_KVM_PROCESSOR_H */
423