1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
6 #include <linux/mm.h>
7 #include <linux/smp.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
17 #include <linux/pm.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <linux/acpi.h>
26 #include <linux/elf-randomize.h>
27 #include <trace/events/power.h>
28 #include <linux/hw_breakpoint.h>
29 #include <asm/cpu.h>
30 #include <asm/apic.h>
31 #include <linux/uaccess.h>
32 #include <asm/mwait.h>
33 #include <asm/fpu/internal.h>
34 #include <asm/debugreg.h>
35 #include <asm/nmi.h>
36 #include <asm/tlbflush.h>
37 #include <asm/mce.h>
38 #include <asm/vm86.h>
39 #include <asm/switch_to.h>
40 #include <asm/desc.h>
41 #include <asm/prctl.h>
42 #include <asm/spec-ctrl.h>
43 #include <asm/io_bitmap.h>
44 #include <asm/proto.h>
45 #include <asm/frame.h>
46
47 #include "process.h"
48
49 /*
50 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
51 * no more per-task TSS's. The TSS size is kept cacheline-aligned
52 * so they are allowed to end up in the .data..cacheline_aligned
53 * section. Since TSS's are completely CPU-local, we want them
54 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
55 */
56 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
57 .x86_tss = {
58 /*
59 * .sp0 is only used when entering ring 0 from a lower
60 * privilege level. Since the init task never runs anything
61 * but ring 0 code, there is no need for a valid value here.
62 * Poison it.
63 */
64 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
65
66 /*
67 * .sp1 is cpu_current_top_of_stack. The init task never
68 * runs user code, but cpu_current_top_of_stack should still
69 * be well defined before the first context switch.
70 */
71 .sp1 = TOP_OF_INIT_STACK,
72
73 #ifdef CONFIG_X86_32
74 .ss0 = __KERNEL_DS,
75 .ss1 = __KERNEL_CS,
76 #endif
77 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
78 },
79 };
80 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
81
82 DEFINE_PER_CPU(bool, __tss_limit_invalid);
83 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
84
85 /*
86 * this gets called so that we can store lazy state into memory and copy the
87 * current task into the new thread.
88 */
arch_dup_task_struct(struct task_struct * dst,struct task_struct * src)89 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
90 {
91 memcpy(dst, src, arch_task_struct_size);
92 #ifdef CONFIG_VM86
93 dst->thread.vm86 = NULL;
94 #endif
95
96 return fpu__copy(dst, src);
97 }
98
99 /*
100 * Free thread data structures etc..
101 */
exit_thread(struct task_struct * tsk)102 void exit_thread(struct task_struct *tsk)
103 {
104 struct thread_struct *t = &tsk->thread;
105 struct fpu *fpu = &t->fpu;
106
107 if (test_thread_flag(TIF_IO_BITMAP))
108 io_bitmap_exit(tsk);
109
110 free_vm86(t);
111
112 fpu__drop(fpu);
113 }
114
set_new_tls(struct task_struct * p,unsigned long tls)115 static int set_new_tls(struct task_struct *p, unsigned long tls)
116 {
117 struct user_desc __user *utls = (struct user_desc __user *)tls;
118
119 if (in_ia32_syscall())
120 return do_set_thread_area(p, -1, utls, 0);
121 else
122 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
123 }
124
copy_thread(unsigned long clone_flags,unsigned long sp,unsigned long arg,struct task_struct * p,unsigned long tls)125 int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
126 struct task_struct *p, unsigned long tls)
127 {
128 struct inactive_task_frame *frame;
129 struct fork_frame *fork_frame;
130 struct pt_regs *childregs;
131 int ret = 0;
132
133 childregs = task_pt_regs(p);
134 fork_frame = container_of(childregs, struct fork_frame, regs);
135 frame = &fork_frame->frame;
136
137 frame->bp = encode_frame_pointer(childregs);
138 frame->ret_addr = (unsigned long) ret_from_fork;
139 p->thread.sp = (unsigned long) fork_frame;
140 p->thread.io_bitmap = NULL;
141 p->thread.iopl_warn = 0;
142 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
143
144 #ifdef CONFIG_X86_64
145 current_save_fsgs();
146 p->thread.fsindex = current->thread.fsindex;
147 p->thread.fsbase = current->thread.fsbase;
148 p->thread.gsindex = current->thread.gsindex;
149 p->thread.gsbase = current->thread.gsbase;
150
151 savesegment(es, p->thread.es);
152 savesegment(ds, p->thread.ds);
153 #else
154 p->thread.sp0 = (unsigned long) (childregs + 1);
155 /*
156 * Clear all status flags including IF and set fixed bit. 64bit
157 * does not have this initialization as the frame does not contain
158 * flags. The flags consistency (especially vs. AC) is there
159 * ensured via objtool, which lacks 32bit support.
160 */
161 frame->flags = X86_EFLAGS_FIXED;
162 #endif
163
164 /* Kernel thread ? */
165 if (unlikely(p->flags & PF_KTHREAD)) {
166 memset(childregs, 0, sizeof(struct pt_regs));
167 kthread_frame_init(frame, sp, arg);
168 return 0;
169 }
170
171 frame->bx = 0;
172 *childregs = *current_pt_regs();
173 childregs->ax = 0;
174 if (sp)
175 childregs->sp = sp;
176
177 #ifdef CONFIG_X86_32
178 task_user_gs(p) = get_user_gs(current_pt_regs());
179 #endif
180
181 /* Set a new TLS for the child thread? */
182 if (clone_flags & CLONE_SETTLS)
183 ret = set_new_tls(p, tls);
184
185 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
186 io_bitmap_share(p);
187
188 return ret;
189 }
190
flush_thread(void)191 void flush_thread(void)
192 {
193 struct task_struct *tsk = current;
194
195 flush_ptrace_hw_breakpoint(tsk);
196 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
197
198 fpu__clear_all(&tsk->thread.fpu);
199 }
200
disable_TSC(void)201 void disable_TSC(void)
202 {
203 preempt_disable();
204 if (!test_and_set_thread_flag(TIF_NOTSC))
205 /*
206 * Must flip the CPU state synchronously with
207 * TIF_NOTSC in the current running context.
208 */
209 cr4_set_bits(X86_CR4_TSD);
210 preempt_enable();
211 }
212
enable_TSC(void)213 static void enable_TSC(void)
214 {
215 preempt_disable();
216 if (test_and_clear_thread_flag(TIF_NOTSC))
217 /*
218 * Must flip the CPU state synchronously with
219 * TIF_NOTSC in the current running context.
220 */
221 cr4_clear_bits(X86_CR4_TSD);
222 preempt_enable();
223 }
224
get_tsc_mode(unsigned long adr)225 int get_tsc_mode(unsigned long adr)
226 {
227 unsigned int val;
228
229 if (test_thread_flag(TIF_NOTSC))
230 val = PR_TSC_SIGSEGV;
231 else
232 val = PR_TSC_ENABLE;
233
234 return put_user(val, (unsigned int __user *)adr);
235 }
236
set_tsc_mode(unsigned int val)237 int set_tsc_mode(unsigned int val)
238 {
239 if (val == PR_TSC_SIGSEGV)
240 disable_TSC();
241 else if (val == PR_TSC_ENABLE)
242 enable_TSC();
243 else
244 return -EINVAL;
245
246 return 0;
247 }
248
249 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
250
set_cpuid_faulting(bool on)251 static void set_cpuid_faulting(bool on)
252 {
253 u64 msrval;
254
255 msrval = this_cpu_read(msr_misc_features_shadow);
256 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
257 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
258 this_cpu_write(msr_misc_features_shadow, msrval);
259 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
260 }
261
disable_cpuid(void)262 static void disable_cpuid(void)
263 {
264 preempt_disable();
265 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
266 /*
267 * Must flip the CPU state synchronously with
268 * TIF_NOCPUID in the current running context.
269 */
270 set_cpuid_faulting(true);
271 }
272 preempt_enable();
273 }
274
enable_cpuid(void)275 static void enable_cpuid(void)
276 {
277 preempt_disable();
278 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
279 /*
280 * Must flip the CPU state synchronously with
281 * TIF_NOCPUID in the current running context.
282 */
283 set_cpuid_faulting(false);
284 }
285 preempt_enable();
286 }
287
get_cpuid_mode(void)288 static int get_cpuid_mode(void)
289 {
290 return !test_thread_flag(TIF_NOCPUID);
291 }
292
set_cpuid_mode(struct task_struct * task,unsigned long cpuid_enabled)293 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
294 {
295 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
296 return -ENODEV;
297
298 if (cpuid_enabled)
299 enable_cpuid();
300 else
301 disable_cpuid();
302
303 return 0;
304 }
305
306 /*
307 * Called immediately after a successful exec.
308 */
arch_setup_new_exec(void)309 void arch_setup_new_exec(void)
310 {
311 /* If cpuid was previously disabled for this task, re-enable it. */
312 if (test_thread_flag(TIF_NOCPUID))
313 enable_cpuid();
314
315 /*
316 * Don't inherit TIF_SSBD across exec boundary when
317 * PR_SPEC_DISABLE_NOEXEC is used.
318 */
319 if (test_thread_flag(TIF_SSBD) &&
320 task_spec_ssb_noexec(current)) {
321 clear_thread_flag(TIF_SSBD);
322 task_clear_spec_ssb_disable(current);
323 task_clear_spec_ssb_noexec(current);
324 speculation_ctrl_update(task_thread_info(current)->flags);
325 }
326 }
327
328 #ifdef CONFIG_X86_IOPL_IOPERM
switch_to_bitmap(unsigned long tifp)329 static inline void switch_to_bitmap(unsigned long tifp)
330 {
331 /*
332 * Invalidate I/O bitmap if the previous task used it. This prevents
333 * any possible leakage of an active I/O bitmap.
334 *
335 * If the next task has an I/O bitmap it will handle it on exit to
336 * user mode.
337 */
338 if (tifp & _TIF_IO_BITMAP)
339 tss_invalidate_io_bitmap();
340 }
341
tss_copy_io_bitmap(struct tss_struct * tss,struct io_bitmap * iobm)342 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
343 {
344 /*
345 * Copy at least the byte range of the incoming tasks bitmap which
346 * covers the permitted I/O ports.
347 *
348 * If the previous task which used an I/O bitmap had more bits
349 * permitted, then the copy needs to cover those as well so they
350 * get turned off.
351 */
352 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
353 max(tss->io_bitmap.prev_max, iobm->max));
354
355 /*
356 * Store the new max and the sequence number of this bitmap
357 * and a pointer to the bitmap itself.
358 */
359 tss->io_bitmap.prev_max = iobm->max;
360 tss->io_bitmap.prev_sequence = iobm->sequence;
361 }
362
363 /**
364 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
365 */
native_tss_update_io_bitmap(void)366 void native_tss_update_io_bitmap(void)
367 {
368 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
369 struct thread_struct *t = ¤t->thread;
370 u16 *base = &tss->x86_tss.io_bitmap_base;
371
372 if (!test_thread_flag(TIF_IO_BITMAP)) {
373 native_tss_invalidate_io_bitmap();
374 return;
375 }
376
377 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
378 *base = IO_BITMAP_OFFSET_VALID_ALL;
379 } else {
380 struct io_bitmap *iobm = t->io_bitmap;
381
382 /*
383 * Only copy bitmap data when the sequence number differs. The
384 * update time is accounted to the incoming task.
385 */
386 if (tss->io_bitmap.prev_sequence != iobm->sequence)
387 tss_copy_io_bitmap(tss, iobm);
388
389 /* Enable the bitmap */
390 *base = IO_BITMAP_OFFSET_VALID_MAP;
391 }
392
393 /*
394 * Make sure that the TSS limit is covering the IO bitmap. It might have
395 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
396 * access from user space to trigger a #GP because tbe bitmap is outside
397 * the TSS limit.
398 */
399 refresh_tss_limit();
400 }
401 #else /* CONFIG_X86_IOPL_IOPERM */
switch_to_bitmap(unsigned long tifp)402 static inline void switch_to_bitmap(unsigned long tifp) { }
403 #endif
404
405 #ifdef CONFIG_SMP
406
407 struct ssb_state {
408 struct ssb_state *shared_state;
409 raw_spinlock_t lock;
410 unsigned int disable_state;
411 unsigned long local_state;
412 };
413
414 #define LSTATE_SSB 0
415
416 static DEFINE_PER_CPU(struct ssb_state, ssb_state);
417
speculative_store_bypass_ht_init(void)418 void speculative_store_bypass_ht_init(void)
419 {
420 struct ssb_state *st = this_cpu_ptr(&ssb_state);
421 unsigned int this_cpu = smp_processor_id();
422 unsigned int cpu;
423
424 st->local_state = 0;
425
426 /*
427 * Shared state setup happens once on the first bringup
428 * of the CPU. It's not destroyed on CPU hotunplug.
429 */
430 if (st->shared_state)
431 return;
432
433 raw_spin_lock_init(&st->lock);
434
435 /*
436 * Go over HT siblings and check whether one of them has set up the
437 * shared state pointer already.
438 */
439 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
440 if (cpu == this_cpu)
441 continue;
442
443 if (!per_cpu(ssb_state, cpu).shared_state)
444 continue;
445
446 /* Link it to the state of the sibling: */
447 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
448 return;
449 }
450
451 /*
452 * First HT sibling to come up on the core. Link shared state of
453 * the first HT sibling to itself. The siblings on the same core
454 * which come up later will see the shared state pointer and link
455 * themself to the state of this CPU.
456 */
457 st->shared_state = st;
458 }
459
460 /*
461 * Logic is: First HT sibling enables SSBD for both siblings in the core
462 * and last sibling to disable it, disables it for the whole core. This how
463 * MSR_SPEC_CTRL works in "hardware":
464 *
465 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
466 */
amd_set_core_ssb_state(unsigned long tifn)467 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
468 {
469 struct ssb_state *st = this_cpu_ptr(&ssb_state);
470 u64 msr = x86_amd_ls_cfg_base;
471
472 if (!static_cpu_has(X86_FEATURE_ZEN)) {
473 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
474 wrmsrl(MSR_AMD64_LS_CFG, msr);
475 return;
476 }
477
478 if (tifn & _TIF_SSBD) {
479 /*
480 * Since this can race with prctl(), block reentry on the
481 * same CPU.
482 */
483 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
484 return;
485
486 msr |= x86_amd_ls_cfg_ssbd_mask;
487
488 raw_spin_lock(&st->shared_state->lock);
489 /* First sibling enables SSBD: */
490 if (!st->shared_state->disable_state)
491 wrmsrl(MSR_AMD64_LS_CFG, msr);
492 st->shared_state->disable_state++;
493 raw_spin_unlock(&st->shared_state->lock);
494 } else {
495 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
496 return;
497
498 raw_spin_lock(&st->shared_state->lock);
499 st->shared_state->disable_state--;
500 if (!st->shared_state->disable_state)
501 wrmsrl(MSR_AMD64_LS_CFG, msr);
502 raw_spin_unlock(&st->shared_state->lock);
503 }
504 }
505 #else
amd_set_core_ssb_state(unsigned long tifn)506 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
507 {
508 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
509
510 wrmsrl(MSR_AMD64_LS_CFG, msr);
511 }
512 #endif
513
amd_set_ssb_virt_state(unsigned long tifn)514 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
515 {
516 /*
517 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
518 * so ssbd_tif_to_spec_ctrl() just works.
519 */
520 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
521 }
522
523 /*
524 * Update the MSRs managing speculation control, during context switch.
525 *
526 * tifp: Previous task's thread flags
527 * tifn: Next task's thread flags
528 */
__speculation_ctrl_update(unsigned long tifp,unsigned long tifn)529 static __always_inline void __speculation_ctrl_update(unsigned long tifp,
530 unsigned long tifn)
531 {
532 unsigned long tif_diff = tifp ^ tifn;
533 u64 msr = x86_spec_ctrl_base;
534 bool updmsr = false;
535
536 lockdep_assert_irqs_disabled();
537
538 /* Handle change of TIF_SSBD depending on the mitigation method. */
539 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
540 if (tif_diff & _TIF_SSBD)
541 amd_set_ssb_virt_state(tifn);
542 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
543 if (tif_diff & _TIF_SSBD)
544 amd_set_core_ssb_state(tifn);
545 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
546 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
547 updmsr |= !!(tif_diff & _TIF_SSBD);
548 msr |= ssbd_tif_to_spec_ctrl(tifn);
549 }
550
551 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
552 if (IS_ENABLED(CONFIG_SMP) &&
553 static_branch_unlikely(&switch_to_cond_stibp)) {
554 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
555 msr |= stibp_tif_to_spec_ctrl(tifn);
556 }
557
558 if (updmsr)
559 write_spec_ctrl_current(msr, false);
560 }
561
speculation_ctrl_update_tif(struct task_struct * tsk)562 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
563 {
564 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
565 if (task_spec_ssb_disable(tsk))
566 set_tsk_thread_flag(tsk, TIF_SSBD);
567 else
568 clear_tsk_thread_flag(tsk, TIF_SSBD);
569
570 if (task_spec_ib_disable(tsk))
571 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
572 else
573 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
574 }
575 /* Return the updated threadinfo flags*/
576 return task_thread_info(tsk)->flags;
577 }
578
speculation_ctrl_update(unsigned long tif)579 void speculation_ctrl_update(unsigned long tif)
580 {
581 unsigned long flags;
582
583 /* Forced update. Make sure all relevant TIF flags are different */
584 local_irq_save(flags);
585 __speculation_ctrl_update(~tif, tif);
586 local_irq_restore(flags);
587 }
588
589 /* Called from seccomp/prctl update */
speculation_ctrl_update_current(void)590 void speculation_ctrl_update_current(void)
591 {
592 preempt_disable();
593 speculation_ctrl_update(speculation_ctrl_update_tif(current));
594 preempt_enable();
595 }
596
cr4_toggle_bits_irqsoff(unsigned long mask)597 static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
598 {
599 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
600
601 newval = cr4 ^ mask;
602 if (newval != cr4) {
603 this_cpu_write(cpu_tlbstate.cr4, newval);
604 __write_cr4(newval);
605 }
606 }
607
__switch_to_xtra(struct task_struct * prev_p,struct task_struct * next_p)608 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
609 {
610 unsigned long tifp, tifn;
611
612 tifn = READ_ONCE(task_thread_info(next_p)->flags);
613 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
614
615 switch_to_bitmap(tifp);
616
617 propagate_user_return_notify(prev_p, next_p);
618
619 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
620 arch_has_block_step()) {
621 unsigned long debugctl, msk;
622
623 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
624 debugctl &= ~DEBUGCTLMSR_BTF;
625 msk = tifn & _TIF_BLOCKSTEP;
626 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
627 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
628 }
629
630 if ((tifp ^ tifn) & _TIF_NOTSC)
631 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
632
633 if ((tifp ^ tifn) & _TIF_NOCPUID)
634 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
635
636 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
637 __speculation_ctrl_update(tifp, tifn);
638 } else {
639 speculation_ctrl_update_tif(prev_p);
640 tifn = speculation_ctrl_update_tif(next_p);
641
642 /* Enforce MSR update to ensure consistent state */
643 __speculation_ctrl_update(~tifn, tifn);
644 }
645
646 if ((tifp ^ tifn) & _TIF_SLD)
647 switch_to_sld(tifn);
648 }
649
650 /*
651 * Idle related variables and functions
652 */
653 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
654 EXPORT_SYMBOL(boot_option_idle_override);
655
656 static void (*x86_idle)(void);
657
658 #ifndef CONFIG_SMP
play_dead(void)659 static inline void play_dead(void)
660 {
661 BUG();
662 }
663 #endif
664
arch_cpu_idle_enter(void)665 void arch_cpu_idle_enter(void)
666 {
667 tsc_verify_tsc_adjust(false);
668 local_touch_nmi();
669 }
670
arch_cpu_idle_dead(void)671 void arch_cpu_idle_dead(void)
672 {
673 play_dead();
674 }
675
676 /*
677 * Called from the generic idle code.
678 */
arch_cpu_idle(void)679 void arch_cpu_idle(void)
680 {
681 x86_idle();
682 }
683
684 /*
685 * We use this if we don't have any better idle routine..
686 */
default_idle(void)687 void __cpuidle default_idle(void)
688 {
689 raw_safe_halt();
690 }
691 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
692 EXPORT_SYMBOL(default_idle);
693 #endif
694
695 #ifdef CONFIG_XEN
xen_set_default_idle(void)696 bool xen_set_default_idle(void)
697 {
698 bool ret = !!x86_idle;
699
700 x86_idle = default_idle;
701
702 return ret;
703 }
704 #endif
705
stop_this_cpu(void * dummy)706 void stop_this_cpu(void *dummy)
707 {
708 local_irq_disable();
709 /*
710 * Remove this CPU:
711 */
712 set_cpu_online(smp_processor_id(), false);
713 disable_local_APIC();
714 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
715
716 /*
717 * Use wbinvd on processors that support SME. This provides support
718 * for performing a successful kexec when going from SME inactive
719 * to SME active (or vice-versa). The cache must be cleared so that
720 * if there are entries with the same physical address, both with and
721 * without the encryption bit, they don't race each other when flushed
722 * and potentially end up with the wrong entry being committed to
723 * memory.
724 */
725 if (boot_cpu_has(X86_FEATURE_SME))
726 native_wbinvd();
727 for (;;) {
728 /*
729 * Use native_halt() so that memory contents don't change
730 * (stack usage and variables) after possibly issuing the
731 * native_wbinvd() above.
732 */
733 native_halt();
734 }
735 }
736
737 /*
738 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
739 * states (local apic timer and TSC stop).
740 *
741 * XXX this function is completely buggered vs RCU and tracing.
742 */
amd_e400_idle(void)743 static void amd_e400_idle(void)
744 {
745 /*
746 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
747 * gets set after static_cpu_has() places have been converted via
748 * alternatives.
749 */
750 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
751 default_idle();
752 return;
753 }
754
755 tick_broadcast_enter();
756
757 default_idle();
758
759 /*
760 * The switch back from broadcast mode needs to be called with
761 * interrupts disabled.
762 */
763 raw_local_irq_disable();
764 tick_broadcast_exit();
765 raw_local_irq_enable();
766 }
767
768 /*
769 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
770 * We can't rely on cpuidle installing MWAIT, because it will not load
771 * on systems that support only C1 -- so the boot default must be MWAIT.
772 *
773 * Some AMD machines are the opposite, they depend on using HALT.
774 *
775 * So for default C1, which is used during boot until cpuidle loads,
776 * use MWAIT-C1 on Intel HW that has it, else use HALT.
777 */
prefer_mwait_c1_over_halt(const struct cpuinfo_x86 * c)778 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
779 {
780 if (c->x86_vendor != X86_VENDOR_INTEL)
781 return 0;
782
783 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
784 return 0;
785
786 return 1;
787 }
788
789 /*
790 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
791 * with interrupts enabled and no flags, which is backwards compatible with the
792 * original MWAIT implementation.
793 */
mwait_idle(void)794 static __cpuidle void mwait_idle(void)
795 {
796 if (!current_set_polling_and_test()) {
797 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
798 mb(); /* quirk */
799 clflush((void *)¤t_thread_info()->flags);
800 mb(); /* quirk */
801 }
802
803 __monitor((void *)¤t_thread_info()->flags, 0, 0);
804 if (!need_resched())
805 __sti_mwait(0, 0);
806 else
807 raw_local_irq_enable();
808 } else {
809 raw_local_irq_enable();
810 }
811 __current_clr_polling();
812 }
813
select_idle_routine(const struct cpuinfo_x86 * c)814 void select_idle_routine(const struct cpuinfo_x86 *c)
815 {
816 #ifdef CONFIG_SMP
817 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
818 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
819 #endif
820 if (x86_idle || boot_option_idle_override == IDLE_POLL)
821 return;
822
823 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
824 pr_info("using AMD E400 aware idle routine\n");
825 x86_idle = amd_e400_idle;
826 } else if (prefer_mwait_c1_over_halt(c)) {
827 pr_info("using mwait in idle threads\n");
828 x86_idle = mwait_idle;
829 } else
830 x86_idle = default_idle;
831 }
832
amd_e400_c1e_apic_setup(void)833 void amd_e400_c1e_apic_setup(void)
834 {
835 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
836 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
837 local_irq_disable();
838 tick_broadcast_force();
839 local_irq_enable();
840 }
841 }
842
arch_post_acpi_subsys_init(void)843 void __init arch_post_acpi_subsys_init(void)
844 {
845 u32 lo, hi;
846
847 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
848 return;
849
850 /*
851 * AMD E400 detection needs to happen after ACPI has been enabled. If
852 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
853 * MSR_K8_INT_PENDING_MSG.
854 */
855 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
856 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
857 return;
858
859 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
860
861 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
862 mark_tsc_unstable("TSC halt in AMD C1E");
863 pr_info("System has AMD C1E enabled\n");
864 }
865
idle_setup(char * str)866 static int __init idle_setup(char *str)
867 {
868 if (!str)
869 return -EINVAL;
870
871 if (!strcmp(str, "poll")) {
872 pr_info("using polling idle threads\n");
873 boot_option_idle_override = IDLE_POLL;
874 cpu_idle_poll_ctrl(true);
875 } else if (!strcmp(str, "halt")) {
876 /*
877 * When the boot option of idle=halt is added, halt is
878 * forced to be used for CPU idle. In such case CPU C2/C3
879 * won't be used again.
880 * To continue to load the CPU idle driver, don't touch
881 * the boot_option_idle_override.
882 */
883 x86_idle = default_idle;
884 boot_option_idle_override = IDLE_HALT;
885 } else if (!strcmp(str, "nomwait")) {
886 /*
887 * If the boot option of "idle=nomwait" is added,
888 * it means that mwait will be disabled for CPU C2/C3
889 * states. In such case it won't touch the variable
890 * of boot_option_idle_override.
891 */
892 boot_option_idle_override = IDLE_NOMWAIT;
893 } else
894 return -1;
895
896 return 0;
897 }
898 early_param("idle", idle_setup);
899
arch_align_stack(unsigned long sp)900 unsigned long arch_align_stack(unsigned long sp)
901 {
902 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
903 sp -= get_random_int() % 8192;
904 return sp & ~0xf;
905 }
906
arch_randomize_brk(struct mm_struct * mm)907 unsigned long arch_randomize_brk(struct mm_struct *mm)
908 {
909 return randomize_page(mm->brk, 0x02000000);
910 }
911
912 /*
913 * Called from fs/proc with a reference on @p to find the function
914 * which called into schedule(). This needs to be done carefully
915 * because the task might wake up and we might look at a stack
916 * changing under us.
917 */
get_wchan(struct task_struct * p)918 unsigned long get_wchan(struct task_struct *p)
919 {
920 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
921 int count = 0;
922
923 if (p == current || p->state == TASK_RUNNING)
924 return 0;
925
926 if (!try_get_task_stack(p))
927 return 0;
928
929 start = (unsigned long)task_stack_page(p);
930 if (!start)
931 goto out;
932
933 /*
934 * Layout of the stack page:
935 *
936 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
937 * PADDING
938 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
939 * stack
940 * ----------- bottom = start
941 *
942 * The tasks stack pointer points at the location where the
943 * framepointer is stored. The data on the stack is:
944 * ... IP FP ... IP FP
945 *
946 * We need to read FP and IP, so we need to adjust the upper
947 * bound by another unsigned long.
948 */
949 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
950 top -= 2 * sizeof(unsigned long);
951 bottom = start;
952
953 sp = READ_ONCE(p->thread.sp);
954 if (sp < bottom || sp > top)
955 goto out;
956
957 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
958 do {
959 if (fp < bottom || fp > top)
960 goto out;
961 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
962 if (!in_sched_functions(ip)) {
963 ret = ip;
964 goto out;
965 }
966 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
967 } while (count++ < 16 && p->state != TASK_RUNNING);
968
969 out:
970 put_task_stack(p);
971 return ret;
972 }
973
do_arch_prctl_common(struct task_struct * task,int option,unsigned long cpuid_enabled)974 long do_arch_prctl_common(struct task_struct *task, int option,
975 unsigned long cpuid_enabled)
976 {
977 switch (option) {
978 case ARCH_GET_CPUID:
979 return get_cpuid_mode();
980 case ARCH_SET_CPUID:
981 return set_cpuid_mode(task, cpuid_enabled);
982 }
983
984 return -EINVAL;
985 }
986