1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "main/macros.h"
25 #include "brw_batch.h"
26 #include "brw_context.h"
27 #include "brw_state.h"
28 #include "brw_defines.h"
29
30 #include "common/intel_l3_config.h"
31
32 /**
33 * The following diagram shows how we partition the URB:
34 *
35 * 16kB or 32kB Rest of the URB space
36 * __________-__________ _________________-_________________
37 * / \ / \
38 * +-------------------------------------------------------------+
39 * | VS/HS/DS/GS/FS Push | VS/HS/DS/GS URB |
40 * | Constants | Entries |
41 * +-------------------------------------------------------------+
42 *
43 * Notably, push constants must be stored at the beginning of the URB
44 * space, while entries can be stored anywhere. Ivybridge and Haswell
45 * GT1/GT2 have a maximum constant buffer size of 16kB, while Haswell GT3
46 * doubles this (32kB).
47 *
48 * Ivybridge and Haswell GT1/GT2 allow push constants to be located (and
49 * sized) in increments of 1kB. Haswell GT3 requires them to be located and
50 * sized in increments of 2kB.
51 *
52 * Currently we split the constant buffer space evenly among whatever stages
53 * are active. This is probably not ideal, but simple.
54 *
55 * Ivybridge GT1 and Haswell GT1 have 128kB of URB space.
56 * Ivybridge GT2 and Haswell GT2 have 256kB of URB space.
57 * Haswell GT3 has 512kB of URB space.
58 *
59 * See "Volume 2a: 3D Pipeline," section 1.8, "Volume 1b: Configurations",
60 * and the documentation for 3DSTATE_PUSH_CONSTANT_ALLOC_xS.
61 */
62 static void
gfx7_allocate_push_constants(struct brw_context * brw)63 gfx7_allocate_push_constants(struct brw_context *brw)
64 {
65 const struct intel_device_info *devinfo = &brw->screen->devinfo;
66
67 /* BRW_NEW_GEOMETRY_PROGRAM */
68 bool gs_present = brw->programs[MESA_SHADER_GEOMETRY];
69
70 /* BRW_NEW_TESS_PROGRAMS */
71 bool tess_present = brw->programs[MESA_SHADER_TESS_EVAL];
72
73 unsigned avail_size = 16;
74 unsigned multiplier = devinfo->max_constant_urb_size_kb / 16;
75
76 int stages = 2 + gs_present + 2 * tess_present;
77
78 /* Divide up the available space equally between stages. Because we
79 * round down (using floor division), there may be some left over
80 * space. We allocate that to the pixel shader stage.
81 */
82 unsigned size_per_stage = avail_size / stages;
83
84 unsigned vs_size = size_per_stage;
85 unsigned hs_size = tess_present ? size_per_stage : 0;
86 unsigned ds_size = tess_present ? size_per_stage : 0;
87 unsigned gs_size = gs_present ? size_per_stage : 0;
88 unsigned fs_size = avail_size - size_per_stage * (stages - 1);
89
90 gfx7_emit_push_constant_state(brw, multiplier * vs_size,
91 multiplier * hs_size, multiplier * ds_size,
92 multiplier * gs_size, multiplier * fs_size);
93
94 /* From p115 of the Ivy Bridge PRM (3.2.1.4 3DSTATE_PUSH_CONSTANT_ALLOC_VS):
95 *
96 * Programming Restriction:
97 *
98 * The 3DSTATE_CONSTANT_VS must be reprogrammed prior to the next
99 * 3DPRIMITIVE command after programming the
100 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS.
101 *
102 * Similar text exists for the other 3DSTATE_PUSH_CONSTANT_ALLOC_*
103 * commands.
104 */
105 brw->vs.base.push_constants_dirty = true;
106 brw->tcs.base.push_constants_dirty = true;
107 brw->tes.base.push_constants_dirty = true;
108 brw->gs.base.push_constants_dirty = true;
109 brw->wm.base.push_constants_dirty = true;
110 }
111
112 void
gfx7_emit_push_constant_state(struct brw_context * brw,unsigned vs_size,unsigned hs_size,unsigned ds_size,unsigned gs_size,unsigned fs_size)113 gfx7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
114 unsigned hs_size, unsigned ds_size,
115 unsigned gs_size, unsigned fs_size)
116 {
117 const struct intel_device_info *devinfo = &brw->screen->devinfo;
118 unsigned offset = 0;
119
120 /* From the SKL PRM, Workarounds section (#878):
121 *
122 * Push constant buffer corruption possible. WA: Insert 2 zero-length
123 * PushConst_PS before every intended PushConst_PS update, issue a
124 * NULLPRIM after each of the zero len PC update to make sure CS commits
125 * them.
126 *
127 * This workaround is attempting to solve a pixel shader push constant
128 * synchronization issue.
129 *
130 * There's an unpublished WA that involves re-emitting
131 * 3DSTATE_PUSH_CONSTANT_ALLOC_PS for every 500-ish 3DSTATE_CONSTANT_PS
132 * packets. Since our counting methods may not be reliable due to
133 * context-switching and pre-emption, we instead choose to approximate this
134 * behavior by re-emitting the packet at the top of the batch.
135 */
136 if (brw->ctx.NewDriverState == BRW_NEW_BATCH) {
137 /* SKL GT2 and GLK 2x6 have reliably demonstrated this issue thus far.
138 * We've also seen some intermittent failures from SKL GT4 and BXT in
139 * the past.
140 */
141 if (!devinfo->is_skylake &&
142 !devinfo->is_broxton &&
143 !devinfo->is_geminilake)
144 return;
145 }
146
147 BEGIN_BATCH(10);
148 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
149 OUT_BATCH(vs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
150 offset += vs_size;
151
152 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_HS << 16 | (2 - 2));
153 OUT_BATCH(hs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
154 offset += hs_size;
155
156 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_DS << 16 | (2 - 2));
157 OUT_BATCH(ds_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
158 offset += ds_size;
159
160 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_GS << 16 | (2 - 2));
161 OUT_BATCH(gs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
162 offset += gs_size;
163
164 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2));
165 OUT_BATCH(fs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
166 ADVANCE_BATCH();
167
168 /* From p292 of the Ivy Bridge PRM (11.2.4 3DSTATE_PUSH_CONSTANT_ALLOC_PS):
169 *
170 * A PIPE_CONTROL command with the CS Stall bit set must be programmed
171 * in the ring after this instruction.
172 *
173 * No such restriction exists for Haswell or Baytrail.
174 */
175 if (devinfo->verx10 <= 70 && !devinfo->is_baytrail)
176 gfx7_emit_cs_stall_flush(brw);
177 }
178
179 const struct brw_tracked_state gfx7_push_constant_space = {
180 .dirty = {
181 .mesa = 0,
182 .brw = BRW_NEW_CONTEXT |
183 BRW_NEW_BATCH | /* Push constant workaround */
184 BRW_NEW_GEOMETRY_PROGRAM |
185 BRW_NEW_TESS_PROGRAMS,
186 },
187 .emit = gfx7_allocate_push_constants,
188 };
189
190 static void
upload_urb(struct brw_context * brw)191 upload_urb(struct brw_context *brw)
192 {
193 /* BRW_NEW_VS_PROG_DATA */
194 const struct brw_vue_prog_data *vs_vue_prog_data =
195 brw_vue_prog_data(brw->vs.base.prog_data);
196 const unsigned vs_size = MAX2(vs_vue_prog_data->urb_entry_size, 1);
197 /* BRW_NEW_GS_PROG_DATA */
198 const bool gs_present = brw->gs.base.prog_data;
199 /* BRW_NEW_TES_PROG_DATA */
200 const bool tess_present = brw->tes.base.prog_data;
201
202 gfx7_upload_urb(brw, vs_size, gs_present, tess_present);
203 }
204
205 void
gfx7_upload_urb(struct brw_context * brw,unsigned vs_size,bool gs_present,bool tess_present)206 gfx7_upload_urb(struct brw_context *brw, unsigned vs_size,
207 bool gs_present, bool tess_present)
208 {
209 const struct intel_device_info *devinfo = &brw->screen->devinfo;
210
211 /* BRW_NEW_{VS,TCS,TES,GS}_PROG_DATA */
212 struct brw_vue_prog_data *prog_data[4] = {
213 [MESA_SHADER_VERTEX] =
214 brw_vue_prog_data(brw->vs.base.prog_data),
215 [MESA_SHADER_TESS_CTRL] =
216 tess_present ? brw_vue_prog_data(brw->tcs.base.prog_data) : NULL,
217 [MESA_SHADER_TESS_EVAL] =
218 tess_present ? brw_vue_prog_data(brw->tes.base.prog_data) : NULL,
219 [MESA_SHADER_GEOMETRY] =
220 gs_present ? brw_vue_prog_data(brw->gs.base.prog_data) : NULL,
221 };
222
223 unsigned entry_size[4];
224 entry_size[MESA_SHADER_VERTEX] = vs_size;
225 for (int i = MESA_SHADER_TESS_CTRL; i <= MESA_SHADER_GEOMETRY; i++) {
226 entry_size[i] = prog_data[i] ? prog_data[i]->urb_entry_size : 1;
227 }
228
229 /* If we're just switching between programs with the same URB requirements,
230 * skip the rest of the logic.
231 */
232 if (brw->urb.vsize == entry_size[MESA_SHADER_VERTEX] &&
233 brw->urb.gs_present == gs_present &&
234 brw->urb.gsize == entry_size[MESA_SHADER_GEOMETRY] &&
235 brw->urb.tess_present == tess_present &&
236 brw->urb.hsize == entry_size[MESA_SHADER_TESS_CTRL] &&
237 brw->urb.dsize == entry_size[MESA_SHADER_TESS_EVAL]) {
238 return;
239 }
240 brw->urb.vsize = entry_size[MESA_SHADER_VERTEX];
241 brw->urb.gs_present = gs_present;
242 brw->urb.gsize = entry_size[MESA_SHADER_GEOMETRY];
243 brw->urb.tess_present = tess_present;
244 brw->urb.hsize = entry_size[MESA_SHADER_TESS_CTRL];
245 brw->urb.dsize = entry_size[MESA_SHADER_TESS_EVAL];
246
247 unsigned entries[4];
248 unsigned start[4];
249 bool constrained;
250 intel_get_urb_config(devinfo, brw->l3.config,
251 tess_present, gs_present, entry_size,
252 entries, start, NULL, &constrained);
253
254 if (devinfo->verx10 == 70 && !devinfo->is_baytrail)
255 gfx7_emit_vs_workaround_flush(brw);
256
257 BEGIN_BATCH(8);
258 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
259 assert(devinfo->ver != 10 || entry_size[i] % 3);
260 OUT_BATCH((_3DSTATE_URB_VS + i) << 16 | (2 - 2));
261 OUT_BATCH(entries[i] |
262 ((entry_size[i] - 1) << GFX7_URB_ENTRY_SIZE_SHIFT) |
263 (start[i] << GFX7_URB_STARTING_ADDRESS_SHIFT));
264 }
265 ADVANCE_BATCH();
266 }
267
268 const struct brw_tracked_state gfx7_urb = {
269 .dirty = {
270 .mesa = 0,
271 .brw = BRW_NEW_BLORP |
272 BRW_NEW_CONTEXT |
273 BRW_NEW_URB_SIZE |
274 BRW_NEW_GS_PROG_DATA |
275 BRW_NEW_TCS_PROG_DATA |
276 BRW_NEW_TES_PROG_DATA |
277 BRW_NEW_VS_PROG_DATA,
278 },
279 .emit = upload_urb,
280 };
281