1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #if defined(CONFIG_DRM_AMD_DC_DCN) 37 #include "mpc.h" 38 #endif 39 #include "dwb.h" 40 #include "mcif_wb.h" 41 #include "panel_cntl.h" 42 43 #define MAX_CLOCK_SOURCES 7 44 45 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 46 uint32_t controller_id); 47 48 #include "grph_object_id.h" 49 #include "link_encoder.h" 50 #include "stream_encoder.h" 51 #include "clock_source.h" 52 #include "audio.h" 53 #include "dm_pp_smu.h" 54 #ifdef CONFIG_DRM_AMD_DC_HDCP 55 #include "dm_cp_psp.h" 56 #endif 57 58 /************ link *****************/ 59 struct link_init_data { 60 const struct dc *dc; 61 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 62 uint32_t connector_index; /* this will be mapped to the HPD pins */ 63 uint32_t link_index; /* this is mapped to DAL display_index 64 TODO: remove it when DC is complete. */ 65 }; 66 67 struct dc_link *link_create(const struct link_init_data *init_params); 68 void link_destroy(struct dc_link **link); 69 70 enum dc_status dc_link_validate_mode_timing( 71 const struct dc_stream_state *stream, 72 struct dc_link *link, 73 const struct dc_crtc_timing *timing); 74 75 void core_link_resume(struct dc_link *link); 76 77 void core_link_enable_stream( 78 struct dc_state *state, 79 struct pipe_ctx *pipe_ctx); 80 81 void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 82 83 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 84 /********** DAL Core*********************/ 85 #include "transform.h" 86 #include "dpp.h" 87 88 struct resource_pool; 89 struct dc_state; 90 struct resource_context; 91 struct clk_bw_params; 92 93 struct resource_funcs { 94 void (*destroy)(struct resource_pool **pool); 95 void (*link_init)(struct dc_link *link); 96 struct panel_cntl*(*panel_cntl_create)( 97 const struct panel_cntl_init_data *panel_cntl_init_data); 98 struct link_encoder *(*link_enc_create)( 99 const struct encoder_init_data *init); 100 bool (*validate_bandwidth)( 101 struct dc *dc, 102 struct dc_state *context, 103 bool fast_validate); 104 void (*calculate_wm_and_dlg)( 105 struct dc *dc, struct dc_state *context, 106 display_e2e_pipe_params_st *pipes, 107 int pipe_cnt, 108 int vlevel); 109 int (*populate_dml_pipes)( 110 struct dc *dc, 111 struct dc_state *context, 112 display_e2e_pipe_params_st *pipes); 113 114 enum dc_status (*validate_global)( 115 struct dc *dc, 116 struct dc_state *context); 117 118 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 119 struct dc_state *context, 120 const struct resource_pool *pool, 121 struct dc_stream_state *stream); 122 123 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 124 125 enum dc_status (*add_stream_to_ctx)( 126 struct dc *dc, 127 struct dc_state *new_ctx, 128 struct dc_stream_state *dc_stream); 129 130 enum dc_status (*remove_stream_from_ctx)( 131 struct dc *dc, 132 struct dc_state *new_ctx, 133 struct dc_stream_state *stream); 134 enum dc_status (*patch_unknown_plane_state)( 135 struct dc_plane_state *plane_state); 136 137 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 138 struct resource_context *res_ctx, 139 const struct resource_pool *pool, 140 struct dc_stream_state *stream); 141 void (*populate_dml_writeback_from_context)( 142 struct dc *dc, 143 struct resource_context *res_ctx, 144 display_e2e_pipe_params_st *pipes); 145 146 void (*set_mcif_arb_params)( 147 struct dc *dc, 148 struct dc_state *context, 149 display_e2e_pipe_params_st *pipes, 150 int pipe_cnt); 151 void (*update_bw_bounding_box)( 152 struct dc *dc, 153 struct clk_bw_params *bw_params); 154 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 155 bool (*acquire_post_bldn_3dlut)( 156 struct resource_context *res_ctx, 157 const struct resource_pool *pool, 158 int mpcc_id, 159 struct dc_3dlut **lut, 160 struct dc_transfer_func **shaper); 161 162 bool (*release_post_bldn_3dlut)( 163 struct resource_context *res_ctx, 164 const struct resource_pool *pool, 165 struct dc_3dlut **lut, 166 struct dc_transfer_func **shaper); 167 #endif 168 enum dc_status (*add_dsc_to_stream_resource)( 169 struct dc *dc, struct dc_state *state, 170 struct dc_stream_state *stream); 171 }; 172 173 struct audio_support{ 174 bool dp_audio; 175 bool hdmi_audio_on_dongle; 176 bool hdmi_audio_native; 177 }; 178 179 #define NO_UNDERLAY_PIPE -1 180 181 struct resource_pool { 182 struct mem_input *mis[MAX_PIPES]; 183 struct hubp *hubps[MAX_PIPES]; 184 struct input_pixel_processor *ipps[MAX_PIPES]; 185 struct transform *transforms[MAX_PIPES]; 186 struct dpp *dpps[MAX_PIPES]; 187 struct output_pixel_processor *opps[MAX_PIPES]; 188 struct timing_generator *timing_generators[MAX_PIPES]; 189 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 190 struct hubbub *hubbub; 191 struct mpc *mpc; 192 struct pp_smu_funcs *pp_smu; 193 struct dce_aux *engines[MAX_PIPES]; 194 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 195 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 196 bool i2c_hw_buffer_in_use; 197 198 struct dwbc *dwbc[MAX_DWB_PIPES]; 199 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 200 struct { 201 unsigned int gsl_0:1; 202 unsigned int gsl_1:1; 203 unsigned int gsl_2:1; 204 } gsl_groups; 205 206 struct display_stream_compressor *dscs[MAX_PIPES]; 207 208 unsigned int pipe_count; 209 unsigned int underlay_pipe_index; 210 unsigned int stream_enc_count; 211 212 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 213 struct dc_3dlut *mpc_lut[MAX_PIPES]; 214 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 215 #endif 216 struct { 217 unsigned int xtalin_clock_inKhz; 218 unsigned int dccg_ref_clock_inKhz; 219 unsigned int dchub_ref_clock_inKhz; 220 } ref_clocks; 221 unsigned int timing_generator_count; 222 unsigned int mpcc_count; 223 224 unsigned int writeback_pipe_count; 225 /* 226 * reserved clock source for DP 227 */ 228 struct clock_source *dp_clock_source; 229 230 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 231 unsigned int clk_src_count; 232 233 struct audio *audios[MAX_AUDIOS]; 234 unsigned int audio_count; 235 struct audio_support audio_support; 236 237 struct dccg *dccg; 238 struct irq_service *irqs; 239 240 struct abm *abm; 241 struct dmcu *dmcu; 242 struct dmub_psr *psr; 243 244 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 245 struct abm *multiple_abms[MAX_PIPES]; 246 #endif 247 248 const struct resource_funcs *funcs; 249 const struct resource_caps *res_cap; 250 251 struct ddc_service *oem_device; 252 }; 253 254 struct dcn_fe_bandwidth { 255 int dppclk_khz; 256 257 }; 258 259 struct stream_resource { 260 struct output_pixel_processor *opp; 261 struct display_stream_compressor *dsc; 262 struct timing_generator *tg; 263 struct stream_encoder *stream_enc; 264 struct audio *audio; 265 266 struct pixel_clk_params pix_clk_params; 267 struct encoder_info_frame encoder_info_frame; 268 269 struct abm *abm; 270 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 271 * otherwise it's using group number 'gsl_group-1' 272 */ 273 uint8_t gsl_group; 274 }; 275 276 struct plane_resource { 277 struct scaler_data scl_data; 278 struct hubp *hubp; 279 struct mem_input *mi; 280 struct input_pixel_processor *ipp; 281 struct transform *xfm; 282 struct dpp *dpp; 283 uint8_t mpcc_inst; 284 285 struct dcn_fe_bandwidth bw; 286 }; 287 288 union pipe_update_flags { 289 struct { 290 uint32_t enable : 1; 291 uint32_t disable : 1; 292 uint32_t odm : 1; 293 uint32_t global_sync : 1; 294 uint32_t opp_changed : 1; 295 uint32_t tg_changed : 1; 296 uint32_t mpcc : 1; 297 uint32_t dppclk : 1; 298 uint32_t hubp_interdependent : 1; 299 uint32_t hubp_rq_dlg_ttu : 1; 300 uint32_t gamut_remap : 1; 301 uint32_t scaler : 1; 302 uint32_t viewport : 1; 303 uint32_t plane_changed : 1; 304 } bits; 305 uint32_t raw; 306 }; 307 308 struct pipe_ctx { 309 struct dc_plane_state *plane_state; 310 struct dc_stream_state *stream; 311 312 struct plane_resource plane_res; 313 struct stream_resource stream_res; 314 315 struct clock_source *clock_source; 316 317 struct pll_settings pll_settings; 318 319 uint8_t pipe_idx; 320 321 struct pipe_ctx *top_pipe; 322 struct pipe_ctx *bottom_pipe; 323 struct pipe_ctx *next_odm_pipe; 324 struct pipe_ctx *prev_odm_pipe; 325 326 #ifdef CONFIG_DRM_AMD_DC_DCN 327 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 328 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 329 struct _vcs_dpi_display_rq_regs_st rq_regs; 330 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 331 #endif 332 union pipe_update_flags update_flags; 333 struct dwbc *dwbc; 334 struct mcif_wb *mcif_wb; 335 }; 336 337 struct resource_context { 338 struct pipe_ctx pipe_ctx[MAX_PIPES]; 339 bool is_stream_enc_acquired[MAX_PIPES * 2]; 340 bool is_audio_acquired[MAX_PIPES]; 341 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 342 uint8_t dp_clock_source_ref_count; 343 bool is_dsc_acquired[MAX_PIPES]; 344 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 345 bool is_mpc_3dlut_acquired[MAX_PIPES]; 346 #endif 347 }; 348 349 struct dce_bw_output { 350 bool cpuc_state_change_enable; 351 bool cpup_state_change_enable; 352 bool stutter_mode_enable; 353 bool nbp_state_change_enable; 354 bool all_displays_in_sync; 355 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 356 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 357 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 358 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 359 int sclk_khz; 360 int sclk_deep_sleep_khz; 361 int yclk_khz; 362 int dispclk_khz; 363 int blackout_recovery_time_us; 364 }; 365 366 struct dcn_bw_writeback { 367 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 368 }; 369 370 struct dcn_bw_output { 371 struct dc_clocks clk; 372 struct dcn_watermark_set watermarks; 373 struct dcn_bw_writeback bw_writeback; 374 }; 375 376 union bw_output { 377 struct dcn_bw_output dcn; 378 struct dce_bw_output dce; 379 }; 380 381 struct bw_context { 382 union bw_output bw; 383 struct display_mode_lib dml; 384 }; 385 /** 386 * struct dc_state - The full description of a state requested by a user 387 * 388 * @streams: Stream properties 389 * @stream_status: The planes on a given stream 390 * @res_ctx: Persistent state of resources 391 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 392 * @pp_display_cfg: PowerPlay clocks and settings 393 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 394 * 395 */ 396 struct dc_state { 397 struct dc_stream_state *streams[MAX_PIPES]; 398 struct dc_stream_status stream_status[MAX_PIPES]; 399 uint8_t stream_count; 400 uint8_t stream_mask; 401 402 struct resource_context res_ctx; 403 404 struct bw_context bw_ctx; 405 406 /* Note: these are big structures, do *not* put on stack! */ 407 struct dm_pp_display_configuration pp_display_cfg; 408 #ifdef CONFIG_DRM_AMD_DC_DCN 409 struct dcn_bw_internal_vars dcn_bw_vars; 410 #endif 411 412 struct clk_mgr *clk_mgr; 413 414 struct kref refcount; 415 416 struct { 417 unsigned int stutter_period_us; 418 } perf_params; 419 }; 420 421 #endif /* _CORE_TYPES_H_ */ 422