1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4 #include "i40e.h"
5 #include <linux/ptp_classify.h>
6
7 /* The XL710 timesync is very much like Intel's 82599 design when it comes to
8 * the fundamental clock design. However, the clock operations are much simpler
9 * in the XL710 because the device supports a full 64 bits of nanoseconds.
10 * Because the field is so wide, we can forgo the cycle counter and just
11 * operate with the nanosecond field directly without fear of overflow.
12 *
13 * Much like the 82599, the update period is dependent upon the link speed:
14 * At 40Gb, 25Gb, or no link, the period is 1.6ns.
15 * At 10Gb or 5Gb link, the period is multiplied by 2. (3.2ns)
16 * At 1Gb link, the period is multiplied by 20. (32ns)
17 * 1588 functionality is not supported at 100Mbps.
18 */
19 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
20 #define I40E_PTP_10GB_INCVAL_MULT 2
21 #define I40E_PTP_5GB_INCVAL_MULT 2
22 #define I40E_PTP_1GB_INCVAL_MULT 20
23
24 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
25 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \
26 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
27
28 /**
29 * i40e_ptp_read - Read the PHC time from the device
30 * @pf: Board private structure
31 * @ts: timespec structure to hold the current time value
32 * @sts: structure to hold the system time before and after reading the PHC
33 *
34 * This function reads the PRTTSYN_TIME registers and stores them in a
35 * timespec. However, since the registers are 64 bits of nanoseconds, we must
36 * convert the result to a timespec before we can return.
37 **/
i40e_ptp_read(struct i40e_pf * pf,struct timespec64 * ts,struct ptp_system_timestamp * sts)38 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts,
39 struct ptp_system_timestamp *sts)
40 {
41 struct i40e_hw *hw = &pf->hw;
42 u32 hi, lo;
43 u64 ns;
44
45 /* The timer latches on the lowest register read. */
46 ptp_read_system_prets(sts);
47 lo = rd32(hw, I40E_PRTTSYN_TIME_L);
48 ptp_read_system_postts(sts);
49 hi = rd32(hw, I40E_PRTTSYN_TIME_H);
50
51 ns = (((u64)hi) << 32) | lo;
52
53 *ts = ns_to_timespec64(ns);
54 }
55
56 /**
57 * i40e_ptp_write - Write the PHC time to the device
58 * @pf: Board private structure
59 * @ts: timespec structure that holds the new time value
60 *
61 * This function writes the PRTTSYN_TIME registers with the user value. Since
62 * we receive a timespec from the stack, we must convert that timespec into
63 * nanoseconds before programming the registers.
64 **/
i40e_ptp_write(struct i40e_pf * pf,const struct timespec64 * ts)65 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts)
66 {
67 struct i40e_hw *hw = &pf->hw;
68 u64 ns = timespec64_to_ns(ts);
69
70 /* The timer will not update until the high register is written, so
71 * write the low register first.
72 */
73 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
74 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
75 }
76
77 /**
78 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
79 * @hwtstamps: Timestamp structure to update
80 * @timestamp: Timestamp from the hardware
81 *
82 * We need to convert the NIC clock value into a hwtstamp which can be used by
83 * the upper level timestamping functions. Since the timestamp is simply a 64-
84 * bit nanosecond value, we can call ns_to_ktime directly to handle this.
85 **/
i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps * hwtstamps,u64 timestamp)86 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
87 u64 timestamp)
88 {
89 memset(hwtstamps, 0, sizeof(*hwtstamps));
90
91 hwtstamps->hwtstamp = ns_to_ktime(timestamp);
92 }
93
94 /**
95 * i40e_ptp_adjfreq - Adjust the PHC frequency
96 * @ptp: The PTP clock structure
97 * @ppb: Parts per billion adjustment from the base
98 *
99 * Adjust the frequency of the PHC by the indicated parts per billion from the
100 * base frequency.
101 **/
i40e_ptp_adjfreq(struct ptp_clock_info * ptp,s32 ppb)102 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
103 {
104 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
105 struct i40e_hw *hw = &pf->hw;
106 u64 adj, freq, diff;
107 int neg_adj = 0;
108
109 if (ppb < 0) {
110 neg_adj = 1;
111 ppb = -ppb;
112 }
113
114 freq = I40E_PTP_40GB_INCVAL;
115 freq *= ppb;
116 diff = div_u64(freq, 1000000000ULL);
117
118 if (neg_adj)
119 adj = I40E_PTP_40GB_INCVAL - diff;
120 else
121 adj = I40E_PTP_40GB_INCVAL + diff;
122
123 /* At some link speeds, the base incval is so large that directly
124 * multiplying by ppb would result in arithmetic overflow even when
125 * using a u64. Avoid this by instead calculating the new incval
126 * always in terms of the 40GbE clock rate and then multiplying by the
127 * link speed factor afterwards. This does result in slightly lower
128 * precision at lower link speeds, but it is fairly minor.
129 */
130 smp_mb(); /* Force any pending update before accessing. */
131 adj *= READ_ONCE(pf->ptp_adj_mult);
132
133 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
134 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
135
136 return 0;
137 }
138
139 /**
140 * i40e_ptp_adjtime - Adjust the PHC time
141 * @ptp: The PTP clock structure
142 * @delta: Offset in nanoseconds to adjust the PHC time by
143 *
144 * Adjust the current clock time by a delta specified in nanoseconds.
145 **/
i40e_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)146 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
147 {
148 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
149 struct timespec64 now, then;
150
151 then = ns_to_timespec64(delta);
152 mutex_lock(&pf->tmreg_lock);
153
154 i40e_ptp_read(pf, &now, NULL);
155 now = timespec64_add(now, then);
156 i40e_ptp_write(pf, (const struct timespec64 *)&now);
157
158 mutex_unlock(&pf->tmreg_lock);
159
160 return 0;
161 }
162
163 /**
164 * i40e_ptp_gettimex - Get the time of the PHC
165 * @ptp: The PTP clock structure
166 * @ts: timespec structure to hold the current time value
167 * @sts: structure to hold the system time before and after reading the PHC
168 *
169 * Read the device clock and return the correct value on ns, after converting it
170 * into a timespec struct.
171 **/
i40e_ptp_gettimex(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)172 static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
173 struct ptp_system_timestamp *sts)
174 {
175 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
176
177 mutex_lock(&pf->tmreg_lock);
178 i40e_ptp_read(pf, ts, sts);
179 mutex_unlock(&pf->tmreg_lock);
180
181 return 0;
182 }
183
184 /**
185 * i40e_ptp_settime - Set the time of the PHC
186 * @ptp: The PTP clock structure
187 * @ts: timespec structure that holds the new time value
188 *
189 * Set the device clock to the user input value. The conversion from timespec
190 * to ns happens in the write function.
191 **/
i40e_ptp_settime(struct ptp_clock_info * ptp,const struct timespec64 * ts)192 static int i40e_ptp_settime(struct ptp_clock_info *ptp,
193 const struct timespec64 *ts)
194 {
195 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
196
197 mutex_lock(&pf->tmreg_lock);
198 i40e_ptp_write(pf, ts);
199 mutex_unlock(&pf->tmreg_lock);
200
201 return 0;
202 }
203
204 /**
205 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem
206 * @ptp: The PTP clock structure
207 * @rq: The requested feature to change
208 * @on: Enable/disable flag
209 *
210 * The XL710 does not support any of the ancillary features of the PHC
211 * subsystem, so this function may just return.
212 **/
i40e_ptp_feature_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)213 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp,
214 struct ptp_clock_request *rq, int on)
215 {
216 return -EOPNOTSUPP;
217 }
218
219 /**
220 * i40e_ptp_update_latch_events - Read I40E_PRTTSYN_STAT_1 and latch events
221 * @pf: the PF data structure
222 *
223 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers
224 * for noticed latch events. This allows the driver to keep track of the first
225 * time a latch event was noticed which will be used to help clear out Rx
226 * timestamps for packets that got dropped or lost.
227 *
228 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is
229 * expected to be called only while under the ptp_rx_lock.
230 **/
i40e_ptp_get_rx_events(struct i40e_pf * pf)231 static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf)
232 {
233 struct i40e_hw *hw = &pf->hw;
234 u32 prttsyn_stat, new_latch_events;
235 int i;
236
237 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
238 new_latch_events = prttsyn_stat & ~pf->latch_event_flags;
239
240 /* Update the jiffies time for any newly latched timestamp. This
241 * ensures that we store the time that we first discovered a timestamp
242 * was latched by the hardware. The service task will later determine
243 * if we should free the latch and drop that timestamp should too much
244 * time pass. This flow ensures that we only update jiffies for new
245 * events latched since the last time we checked, and not all events
246 * currently latched, so that the service task accounting remains
247 * accurate.
248 */
249 for (i = 0; i < 4; i++) {
250 if (new_latch_events & BIT(i))
251 pf->latch_events[i] = jiffies;
252 }
253
254 /* Finally, we store the current status of the Rx timestamp latches */
255 pf->latch_event_flags = prttsyn_stat;
256
257 return prttsyn_stat;
258 }
259
260 /**
261 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
262 * @pf: The PF private data structure
263 *
264 * This watchdog task is scheduled to detect error case where hardware has
265 * dropped an Rx packet that was timestamped when the ring is full. The
266 * particular error is rare but leaves the device in a state unable to timestamp
267 * any future packets.
268 **/
i40e_ptp_rx_hang(struct i40e_pf * pf)269 void i40e_ptp_rx_hang(struct i40e_pf *pf)
270 {
271 struct i40e_hw *hw = &pf->hw;
272 unsigned int i, cleared = 0;
273
274 /* Since we cannot turn off the Rx timestamp logic if the device is
275 * configured for Tx timestamping, we check if Rx timestamping is
276 * configured. We don't want to spuriously warn about Rx timestamp
277 * hangs if we don't care about the timestamps.
278 */
279 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
280 return;
281
282 spin_lock_bh(&pf->ptp_rx_lock);
283
284 /* Update current latch times for Rx events */
285 i40e_ptp_get_rx_events(pf);
286
287 /* Check all the currently latched Rx events and see whether they have
288 * been latched for over a second. It is assumed that any timestamp
289 * should have been cleared within this time, or else it was captured
290 * for a dropped frame that the driver never received. Thus, we will
291 * clear any timestamp that has been latched for over 1 second.
292 */
293 for (i = 0; i < 4; i++) {
294 if ((pf->latch_event_flags & BIT(i)) &&
295 time_is_before_jiffies(pf->latch_events[i] + HZ)) {
296 rd32(hw, I40E_PRTTSYN_RXTIME_H(i));
297 pf->latch_event_flags &= ~BIT(i);
298 cleared++;
299 }
300 }
301
302 spin_unlock_bh(&pf->ptp_rx_lock);
303
304 /* Log a warning if more than 2 timestamps got dropped in the same
305 * check. We don't want to warn about all drops because it can occur
306 * in normal scenarios such as PTP frames on multicast addresses we
307 * aren't listening to. However, administrator should know if this is
308 * the reason packets aren't receiving timestamps.
309 */
310 if (cleared > 2)
311 dev_dbg(&pf->pdev->dev,
312 "Dropped %d missed RXTIME timestamp events\n",
313 cleared);
314
315 /* Finally, update the rx_hwtstamp_cleared counter */
316 pf->rx_hwtstamp_cleared += cleared;
317 }
318
319 /**
320 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung
321 * @pf: The PF private data structure
322 *
323 * This watchdog task is run periodically to make sure that we clear the Tx
324 * timestamp logic if we don't obtain a timestamp in a reasonable amount of
325 * time. It is unexpected in the normal case but if it occurs it results in
326 * permanently preventing timestamps of future packets.
327 **/
i40e_ptp_tx_hang(struct i40e_pf * pf)328 void i40e_ptp_tx_hang(struct i40e_pf *pf)
329 {
330 struct sk_buff *skb;
331
332 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
333 return;
334
335 /* Nothing to do if we're not already waiting for a timestamp */
336 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state))
337 return;
338
339 /* We already have a handler routine which is run when we are notified
340 * of a Tx timestamp in the hardware. If we don't get an interrupt
341 * within a second it is reasonable to assume that we never will.
342 */
343 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) {
344 skb = pf->ptp_tx_skb;
345 pf->ptp_tx_skb = NULL;
346 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
347
348 /* Free the skb after we clear the bitlock */
349 dev_kfree_skb_any(skb);
350 pf->tx_hwtstamp_timeouts++;
351 }
352 }
353
354 /**
355 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
356 * @pf: Board private structure
357 *
358 * Read the value of the Tx timestamp from the registers, convert it into a
359 * value consumable by the stack, and store that result into the shhwtstamps
360 * struct before returning it up the stack.
361 **/
i40e_ptp_tx_hwtstamp(struct i40e_pf * pf)362 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
363 {
364 struct skb_shared_hwtstamps shhwtstamps;
365 struct sk_buff *skb = pf->ptp_tx_skb;
366 struct i40e_hw *hw = &pf->hw;
367 u32 hi, lo;
368 u64 ns;
369
370 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
371 return;
372
373 /* don't attempt to timestamp if we don't have an skb */
374 if (!pf->ptp_tx_skb)
375 return;
376
377 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
378 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
379
380 ns = (((u64)hi) << 32) | lo;
381 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
382
383 /* Clear the bit lock as soon as possible after reading the register,
384 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise
385 * applications might wake up and attempt to request another transmit
386 * timestamp prior to the bit lock being cleared.
387 */
388 pf->ptp_tx_skb = NULL;
389 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
390
391 /* Notify the stack and free the skb after we've unlocked */
392 skb_tstamp_tx(skb, &shhwtstamps);
393 dev_kfree_skb_any(skb);
394 }
395
396 /**
397 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
398 * @pf: Board private structure
399 * @skb: Particular skb to send timestamp with
400 * @index: Index into the receive timestamp registers for the timestamp
401 *
402 * The XL710 receives a notification in the receive descriptor with an offset
403 * into the set of RXTIME registers where the timestamp is for that skb. This
404 * function goes and fetches the receive timestamp from that offset, if a valid
405 * one exists. The RXTIME registers are in ns, so we must convert the result
406 * first.
407 **/
i40e_ptp_rx_hwtstamp(struct i40e_pf * pf,struct sk_buff * skb,u8 index)408 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
409 {
410 u32 prttsyn_stat, hi, lo;
411 struct i40e_hw *hw;
412 u64 ns;
413
414 /* Since we cannot turn off the Rx timestamp logic if the device is
415 * doing Tx timestamping, check if Rx timestamping is configured.
416 */
417 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
418 return;
419
420 hw = &pf->hw;
421
422 spin_lock_bh(&pf->ptp_rx_lock);
423
424 /* Get current Rx events and update latch times */
425 prttsyn_stat = i40e_ptp_get_rx_events(pf);
426
427 /* TODO: Should we warn about missing Rx timestamp event? */
428 if (!(prttsyn_stat & BIT(index))) {
429 spin_unlock_bh(&pf->ptp_rx_lock);
430 return;
431 }
432
433 /* Clear the latched event since we're about to read its register */
434 pf->latch_event_flags &= ~BIT(index);
435
436 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
437 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
438
439 spin_unlock_bh(&pf->ptp_rx_lock);
440
441 ns = (((u64)hi) << 32) | lo;
442
443 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
444 }
445
446 /**
447 * i40e_ptp_set_increment - Utility function to update clock increment rate
448 * @pf: Board private structure
449 *
450 * During a link change, the DMA frequency that drives the 1588 logic will
451 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
452 * we must update the increment value per clock tick.
453 **/
i40e_ptp_set_increment(struct i40e_pf * pf)454 void i40e_ptp_set_increment(struct i40e_pf *pf)
455 {
456 struct i40e_link_status *hw_link_info;
457 struct i40e_hw *hw = &pf->hw;
458 u64 incval;
459 u32 mult;
460
461 hw_link_info = &hw->phy.link_info;
462
463 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
464
465 switch (hw_link_info->link_speed) {
466 case I40E_LINK_SPEED_10GB:
467 mult = I40E_PTP_10GB_INCVAL_MULT;
468 break;
469 case I40E_LINK_SPEED_5GB:
470 mult = I40E_PTP_5GB_INCVAL_MULT;
471 break;
472 case I40E_LINK_SPEED_1GB:
473 mult = I40E_PTP_1GB_INCVAL_MULT;
474 break;
475 case I40E_LINK_SPEED_100MB:
476 {
477 static int warn_once;
478
479 if (!warn_once) {
480 dev_warn(&pf->pdev->dev,
481 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n");
482 warn_once++;
483 }
484 mult = 0;
485 break;
486 }
487 case I40E_LINK_SPEED_40GB:
488 default:
489 mult = 1;
490 break;
491 }
492
493 /* The increment value is calculated by taking the base 40GbE incvalue
494 * and multiplying it by a factor based on the link speed.
495 */
496 incval = I40E_PTP_40GB_INCVAL * mult;
497
498 /* Write the new increment value into the increment register. The
499 * hardware will not update the clock until both registers have been
500 * written.
501 */
502 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
503 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
504
505 /* Update the base adjustement value. */
506 WRITE_ONCE(pf->ptp_adj_mult, mult);
507 smp_mb(); /* Force the above update. */
508 }
509
510 /**
511 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
512 * @pf: Board private structure
513 * @ifr: ioctl data
514 *
515 * Obtain the current hardware timestamping settigs as requested. To do this,
516 * keep a shadow copy of the timestamp settings rather than attempting to
517 * deconstruct it from the registers.
518 **/
i40e_ptp_get_ts_config(struct i40e_pf * pf,struct ifreq * ifr)519 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
520 {
521 struct hwtstamp_config *config = &pf->tstamp_config;
522
523 if (!(pf->flags & I40E_FLAG_PTP))
524 return -EOPNOTSUPP;
525
526 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
527 -EFAULT : 0;
528 }
529
530 /**
531 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode
532 * @pf: Board private structure
533 * @config: hwtstamp settings requested or saved
534 *
535 * Control hardware registers to enter the specific mode requested by the
536 * user. Also used during reset path to ensure that timestamp settings are
537 * maintained.
538 *
539 * Note: modifies config in place, and may update the requested mode to be
540 * more broad if the specific filter is not directly supported.
541 **/
i40e_ptp_set_timestamp_mode(struct i40e_pf * pf,struct hwtstamp_config * config)542 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
543 struct hwtstamp_config *config)
544 {
545 struct i40e_hw *hw = &pf->hw;
546 u32 tsyntype, regval;
547
548 /* Reserved for future extensions. */
549 if (config->flags)
550 return -EINVAL;
551
552 switch (config->tx_type) {
553 case HWTSTAMP_TX_OFF:
554 pf->ptp_tx = false;
555 break;
556 case HWTSTAMP_TX_ON:
557 pf->ptp_tx = true;
558 break;
559 default:
560 return -ERANGE;
561 }
562
563 switch (config->rx_filter) {
564 case HWTSTAMP_FILTER_NONE:
565 pf->ptp_rx = false;
566 /* We set the type to V1, but do not enable UDP packet
567 * recognition. In this way, we should be as close to
568 * disabling PTP Rx timestamps as possible since V1 packets
569 * are always UDP, since L2 packets are a V2 feature.
570 */
571 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1;
572 break;
573 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
574 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
575 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
576 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
577 return -ERANGE;
578 pf->ptp_rx = true;
579 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
580 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
581 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
582 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
583 break;
584 case HWTSTAMP_FILTER_PTP_V2_EVENT:
585 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
586 case HWTSTAMP_FILTER_PTP_V2_SYNC:
587 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
588 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
589 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
590 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
591 return -ERANGE;
592 fallthrough;
593 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
594 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
595 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
596 pf->ptp_rx = true;
597 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
598 I40E_PRTTSYN_CTL1_TSYNTYPE_V2;
599 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) {
600 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
601 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
602 } else {
603 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
604 }
605 break;
606 case HWTSTAMP_FILTER_NTP_ALL:
607 case HWTSTAMP_FILTER_ALL:
608 default:
609 return -ERANGE;
610 }
611
612 /* Clear out all 1588-related registers to clear and unlatch them. */
613 spin_lock_bh(&pf->ptp_rx_lock);
614 rd32(hw, I40E_PRTTSYN_STAT_0);
615 rd32(hw, I40E_PRTTSYN_TXTIME_H);
616 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
617 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
618 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
619 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
620 pf->latch_event_flags = 0;
621 spin_unlock_bh(&pf->ptp_rx_lock);
622
623 /* Enable/disable the Tx timestamp interrupt based on user input. */
624 regval = rd32(hw, I40E_PRTTSYN_CTL0);
625 if (pf->ptp_tx)
626 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
627 else
628 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
629 wr32(hw, I40E_PRTTSYN_CTL0, regval);
630
631 regval = rd32(hw, I40E_PFINT_ICR0_ENA);
632 if (pf->ptp_tx)
633 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
634 else
635 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
636 wr32(hw, I40E_PFINT_ICR0_ENA, regval);
637
638 /* Although there is no simple on/off switch for Rx, we "disable" Rx
639 * timestamps by setting to V1 only mode and clear the UDP
640 * recognition. This ought to disable all PTP Rx timestamps as V1
641 * packets are always over UDP. Note that software is configured to
642 * ignore Rx timestamps via the pf->ptp_rx flag.
643 */
644 regval = rd32(hw, I40E_PRTTSYN_CTL1);
645 /* clear everything but the enable bit */
646 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
647 /* now enable bits for desired Rx timestamps */
648 regval |= tsyntype;
649 wr32(hw, I40E_PRTTSYN_CTL1, regval);
650
651 return 0;
652 }
653
654 /**
655 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
656 * @pf: Board private structure
657 * @ifr: ioctl data
658 *
659 * Respond to the user filter requests and make the appropriate hardware
660 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
661 * logic, so keep track in software of whether to indicate these timestamps
662 * or not.
663 *
664 * It is permissible to "upgrade" the user request to a broader filter, as long
665 * as the user receives the timestamps they care about and the user is notified
666 * the filter has been broadened.
667 **/
i40e_ptp_set_ts_config(struct i40e_pf * pf,struct ifreq * ifr)668 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
669 {
670 struct hwtstamp_config config;
671 int err;
672
673 if (!(pf->flags & I40E_FLAG_PTP))
674 return -EOPNOTSUPP;
675
676 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
677 return -EFAULT;
678
679 err = i40e_ptp_set_timestamp_mode(pf, &config);
680 if (err)
681 return err;
682
683 /* save these settings for future reference */
684 pf->tstamp_config = config;
685
686 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
687 -EFAULT : 0;
688 }
689
690 /**
691 * i40e_ptp_create_clock - Create PTP clock device for userspace
692 * @pf: Board private structure
693 *
694 * This function creates a new PTP clock device. It only creates one if we
695 * don't already have one, so it is safe to call. Will return error if it
696 * can't create one, but success if we already have a device. Should be used
697 * by i40e_ptp_init to create clock initially, and prevent global resets from
698 * creating new clock devices.
699 **/
i40e_ptp_create_clock(struct i40e_pf * pf)700 static long i40e_ptp_create_clock(struct i40e_pf *pf)
701 {
702 /* no need to create a clock device if we already have one */
703 if (!IS_ERR_OR_NULL(pf->ptp_clock))
704 return 0;
705
706 strlcpy(pf->ptp_caps.name, i40e_driver_name,
707 sizeof(pf->ptp_caps.name) - 1);
708 pf->ptp_caps.owner = THIS_MODULE;
709 pf->ptp_caps.max_adj = 999999999;
710 pf->ptp_caps.n_ext_ts = 0;
711 pf->ptp_caps.pps = 0;
712 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
713 pf->ptp_caps.adjtime = i40e_ptp_adjtime;
714 pf->ptp_caps.gettimex64 = i40e_ptp_gettimex;
715 pf->ptp_caps.settime64 = i40e_ptp_settime;
716 pf->ptp_caps.enable = i40e_ptp_feature_enable;
717
718 /* Attempt to register the clock before enabling the hardware. */
719 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
720 if (IS_ERR(pf->ptp_clock))
721 return PTR_ERR(pf->ptp_clock);
722
723 /* clear the hwtstamp settings here during clock create, instead of
724 * during regular init, so that we can maintain settings across a
725 * reset or suspend.
726 */
727 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
728 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
729
730 /* Set the previous "reset" time to the current Kernel clock time */
731 ktime_get_real_ts64(&pf->ptp_prev_hw_time);
732 pf->ptp_reset_start = ktime_get();
733
734 return 0;
735 }
736
737 /**
738 * i40e_ptp_save_hw_time - Save the current PTP time as ptp_prev_hw_time
739 * @pf: Board private structure
740 *
741 * Read the current PTP time and save it into pf->ptp_prev_hw_time. This should
742 * be called at the end of preparing to reset, just before hardware reset
743 * occurs, in order to preserve the PTP time as close as possible across
744 * resets.
745 */
i40e_ptp_save_hw_time(struct i40e_pf * pf)746 void i40e_ptp_save_hw_time(struct i40e_pf *pf)
747 {
748 /* don't try to access the PTP clock if it's not enabled */
749 if (!(pf->flags & I40E_FLAG_PTP))
750 return;
751
752 i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL);
753 /* Get a monotonic starting time for this reset */
754 pf->ptp_reset_start = ktime_get();
755 }
756
757 /**
758 * i40e_ptp_restore_hw_time - Restore the ptp_prev_hw_time + delta to PTP regs
759 * @pf: Board private structure
760 *
761 * Restore the PTP hardware clock registers. We previously cached the PTP
762 * hardware time as pf->ptp_prev_hw_time. To be as accurate as possible,
763 * update this value based on the time delta since the time was saved, using
764 * CLOCK_MONOTONIC (via ktime_get()) to calculate the time difference.
765 *
766 * This ensures that the hardware clock is restored to nearly what it should
767 * have been if a reset had not occurred.
768 */
i40e_ptp_restore_hw_time(struct i40e_pf * pf)769 void i40e_ptp_restore_hw_time(struct i40e_pf *pf)
770 {
771 ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start);
772
773 /* Update the previous HW time with the ktime delta */
774 timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta));
775
776 /* Restore the hardware clock registers */
777 i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time);
778 }
779
780 /**
781 * i40e_ptp_init - Initialize the 1588 support after device probe or reset
782 * @pf: Board private structure
783 *
784 * This function sets device up for 1588 support. The first time it is run, it
785 * will create a PHC clock device. It does not create a clock device if one
786 * already exists. It also reconfigures the device after a reset.
787 *
788 * The first time a clock is created, i40e_ptp_create_clock will set
789 * pf->ptp_prev_hw_time to the current system time. During resets, it is
790 * expected that this timespec will be set to the last known PTP clock time,
791 * in order to preserve the clock time as close as possible across a reset.
792 **/
i40e_ptp_init(struct i40e_pf * pf)793 void i40e_ptp_init(struct i40e_pf *pf)
794 {
795 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
796 struct i40e_hw *hw = &pf->hw;
797 u32 pf_id;
798 long err;
799
800 /* Only one PF is assigned to control 1588 logic per port. Do not
801 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID
802 */
803 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
804 I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
805 if (hw->pf_id != pf_id) {
806 pf->flags &= ~I40E_FLAG_PTP;
807 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n",
808 __func__,
809 netdev->name);
810 return;
811 }
812
813 mutex_init(&pf->tmreg_lock);
814 spin_lock_init(&pf->ptp_rx_lock);
815
816 /* ensure we have a clock device */
817 err = i40e_ptp_create_clock(pf);
818 if (err) {
819 pf->ptp_clock = NULL;
820 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
821 __func__);
822 } else if (pf->ptp_clock) {
823 u32 regval;
824
825 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
826 dev_info(&pf->pdev->dev, "PHC enabled\n");
827 pf->flags |= I40E_FLAG_PTP;
828
829 /* Ensure the clocks are running. */
830 regval = rd32(hw, I40E_PRTTSYN_CTL0);
831 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
832 wr32(hw, I40E_PRTTSYN_CTL0, regval);
833 regval = rd32(hw, I40E_PRTTSYN_CTL1);
834 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
835 wr32(hw, I40E_PRTTSYN_CTL1, regval);
836
837 /* Set the increment value per clock tick. */
838 i40e_ptp_set_increment(pf);
839
840 /* reset timestamping mode */
841 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config);
842
843 /* Restore the clock time based on last known value */
844 i40e_ptp_restore_hw_time(pf);
845 }
846 }
847
848 /**
849 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
850 * @pf: Board private structure
851 *
852 * This function handles the cleanup work required from the initialization by
853 * clearing out the important information and unregistering the PHC.
854 **/
i40e_ptp_stop(struct i40e_pf * pf)855 void i40e_ptp_stop(struct i40e_pf *pf)
856 {
857 pf->flags &= ~I40E_FLAG_PTP;
858 pf->ptp_tx = false;
859 pf->ptp_rx = false;
860
861 if (pf->ptp_tx_skb) {
862 struct sk_buff *skb = pf->ptp_tx_skb;
863
864 pf->ptp_tx_skb = NULL;
865 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
866 dev_kfree_skb_any(skb);
867 }
868
869 if (pf->ptp_clock) {
870 ptp_clock_unregister(pf->ptp_clock);
871 pf->ptp_clock = NULL;
872 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
873 pf->vsi[pf->lan_vsi]->netdev->name);
874 }
875 }
876