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1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3 
4 #include <linux/prefetch.h>
5 #include <linux/bpf_trace.h>
6 #include <net/xdp.h>
7 #include "i40e.h"
8 #include "i40e_trace.h"
9 #include "i40e_prototype.h"
10 #include "i40e_txrx_common.h"
11 #include "i40e_xsk.h"
12 
13 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
14 /**
15  * i40e_fdir - Generate a Flow Director descriptor based on fdata
16  * @tx_ring: Tx ring to send buffer on
17  * @fdata: Flow director filter data
18  * @add: Indicate if we are adding a rule or deleting one
19  *
20  **/
i40e_fdir(struct i40e_ring * tx_ring,struct i40e_fdir_filter * fdata,bool add)21 static void i40e_fdir(struct i40e_ring *tx_ring,
22 		      struct i40e_fdir_filter *fdata, bool add)
23 {
24 	struct i40e_filter_program_desc *fdir_desc;
25 	struct i40e_pf *pf = tx_ring->vsi->back;
26 	u32 flex_ptype, dtype_cmd;
27 	u16 i;
28 
29 	/* grab the next descriptor */
30 	i = tx_ring->next_to_use;
31 	fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
32 
33 	i++;
34 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
35 
36 	flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK &
37 		     (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT);
38 
39 	flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK &
40 		      (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
41 
42 	flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
43 		      (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
44 
45 	flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
46 		      (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
47 
48 	/* Use LAN VSI Id if not programmed by user */
49 	flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK &
50 		      ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) <<
51 		       I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);
52 
53 	dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
54 
55 	dtype_cmd |= add ?
56 		     I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
57 		     I40E_TXD_FLTR_QW1_PCMD_SHIFT :
58 		     I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
59 		     I40E_TXD_FLTR_QW1_PCMD_SHIFT;
60 
61 	dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK &
62 		     (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT);
63 
64 	dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK &
65 		     (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT);
66 
67 	if (fdata->cnt_index) {
68 		dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
69 		dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK &
70 			     ((u32)fdata->cnt_index <<
71 			      I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT);
72 	}
73 
74 	fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
75 	fdir_desc->rsvd = cpu_to_le32(0);
76 	fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
77 	fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
78 }
79 
80 #define I40E_FD_CLEAN_DELAY 10
81 /**
82  * i40e_program_fdir_filter - Program a Flow Director filter
83  * @fdir_data: Packet data that will be filter parameters
84  * @raw_packet: the pre-allocated packet buffer for FDir
85  * @pf: The PF pointer
86  * @add: True for add/update, False for remove
87  **/
i40e_program_fdir_filter(struct i40e_fdir_filter * fdir_data,u8 * raw_packet,struct i40e_pf * pf,bool add)88 static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
89 				    u8 *raw_packet, struct i40e_pf *pf,
90 				    bool add)
91 {
92 	struct i40e_tx_buffer *tx_buf, *first;
93 	struct i40e_tx_desc *tx_desc;
94 	struct i40e_ring *tx_ring;
95 	struct i40e_vsi *vsi;
96 	struct device *dev;
97 	dma_addr_t dma;
98 	u32 td_cmd = 0;
99 	u16 i;
100 
101 	/* find existing FDIR VSI */
102 	vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
103 	if (!vsi)
104 		return -ENOENT;
105 
106 	tx_ring = vsi->tx_rings[0];
107 	dev = tx_ring->dev;
108 
109 	/* we need two descriptors to add/del a filter and we can wait */
110 	for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
111 		if (!i)
112 			return -EAGAIN;
113 		msleep_interruptible(1);
114 	}
115 
116 	dma = dma_map_single(dev, raw_packet,
117 			     I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
118 	if (dma_mapping_error(dev, dma))
119 		goto dma_fail;
120 
121 	/* grab the next descriptor */
122 	i = tx_ring->next_to_use;
123 	first = &tx_ring->tx_bi[i];
124 	i40e_fdir(tx_ring, fdir_data, add);
125 
126 	/* Now program a dummy descriptor */
127 	i = tx_ring->next_to_use;
128 	tx_desc = I40E_TX_DESC(tx_ring, i);
129 	tx_buf = &tx_ring->tx_bi[i];
130 
131 	tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
132 
133 	memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
134 
135 	/* record length, and DMA address */
136 	dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
137 	dma_unmap_addr_set(tx_buf, dma, dma);
138 
139 	tx_desc->buffer_addr = cpu_to_le64(dma);
140 	td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
141 
142 	tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
143 	tx_buf->raw_buf = (void *)raw_packet;
144 
145 	tx_desc->cmd_type_offset_bsz =
146 		build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
147 
148 	/* Force memory writes to complete before letting h/w
149 	 * know there are new descriptors to fetch.
150 	 */
151 	wmb();
152 
153 	/* Mark the data descriptor to be watched */
154 	first->next_to_watch = tx_desc;
155 
156 	writel(tx_ring->next_to_use, tx_ring->tail);
157 	return 0;
158 
159 dma_fail:
160 	return -1;
161 }
162 
163 #define IP_HEADER_OFFSET 14
164 #define I40E_UDPIP_DUMMY_PACKET_LEN 42
165 /**
166  * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
167  * @vsi: pointer to the targeted VSI
168  * @fd_data: the flow director data required for the FDir descriptor
169  * @add: true adds a filter, false removes it
170  *
171  * Returns 0 if the filters were successfully added or removed
172  **/
i40e_add_del_fdir_udpv4(struct i40e_vsi * vsi,struct i40e_fdir_filter * fd_data,bool add)173 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
174 				   struct i40e_fdir_filter *fd_data,
175 				   bool add)
176 {
177 	struct i40e_pf *pf = vsi->back;
178 	struct udphdr *udp;
179 	struct iphdr *ip;
180 	u8 *raw_packet;
181 	int ret;
182 	static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
183 		0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
184 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
185 
186 	raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
187 	if (!raw_packet)
188 		return -ENOMEM;
189 	memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
190 
191 	ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
192 	udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
193 	      + sizeof(struct iphdr));
194 
195 	ip->daddr = fd_data->dst_ip;
196 	udp->dest = fd_data->dst_port;
197 	ip->saddr = fd_data->src_ip;
198 	udp->source = fd_data->src_port;
199 
200 	if (fd_data->flex_filter) {
201 		u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN;
202 		__be16 pattern = fd_data->flex_word;
203 		u16 off = fd_data->flex_offset;
204 
205 		*((__force __be16 *)(payload + off)) = pattern;
206 	}
207 
208 	fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
209 	ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
210 	if (ret) {
211 		dev_info(&pf->pdev->dev,
212 			 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
213 			 fd_data->pctype, fd_data->fd_id, ret);
214 		/* Free the packet buffer since it wasn't added to the ring */
215 		kfree(raw_packet);
216 		return -EOPNOTSUPP;
217 	} else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
218 		if (add)
219 			dev_info(&pf->pdev->dev,
220 				 "Filter OK for PCTYPE %d loc = %d\n",
221 				 fd_data->pctype, fd_data->fd_id);
222 		else
223 			dev_info(&pf->pdev->dev,
224 				 "Filter deleted for PCTYPE %d loc = %d\n",
225 				 fd_data->pctype, fd_data->fd_id);
226 	}
227 
228 	if (add)
229 		pf->fd_udp4_filter_cnt++;
230 	else
231 		pf->fd_udp4_filter_cnt--;
232 
233 	return 0;
234 }
235 
236 #define I40E_TCPIP_DUMMY_PACKET_LEN 54
237 /**
238  * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
239  * @vsi: pointer to the targeted VSI
240  * @fd_data: the flow director data required for the FDir descriptor
241  * @add: true adds a filter, false removes it
242  *
243  * Returns 0 if the filters were successfully added or removed
244  **/
i40e_add_del_fdir_tcpv4(struct i40e_vsi * vsi,struct i40e_fdir_filter * fd_data,bool add)245 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
246 				   struct i40e_fdir_filter *fd_data,
247 				   bool add)
248 {
249 	struct i40e_pf *pf = vsi->back;
250 	struct tcphdr *tcp;
251 	struct iphdr *ip;
252 	u8 *raw_packet;
253 	int ret;
254 	/* Dummy packet */
255 	static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
256 		0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
257 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
258 		0x0, 0x72, 0, 0, 0, 0};
259 
260 	raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
261 	if (!raw_packet)
262 		return -ENOMEM;
263 	memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
264 
265 	ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
266 	tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
267 	      + sizeof(struct iphdr));
268 
269 	ip->daddr = fd_data->dst_ip;
270 	tcp->dest = fd_data->dst_port;
271 	ip->saddr = fd_data->src_ip;
272 	tcp->source = fd_data->src_port;
273 
274 	if (fd_data->flex_filter) {
275 		u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN;
276 		__be16 pattern = fd_data->flex_word;
277 		u16 off = fd_data->flex_offset;
278 
279 		*((__force __be16 *)(payload + off)) = pattern;
280 	}
281 
282 	fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
283 	ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
284 	if (ret) {
285 		dev_info(&pf->pdev->dev,
286 			 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
287 			 fd_data->pctype, fd_data->fd_id, ret);
288 		/* Free the packet buffer since it wasn't added to the ring */
289 		kfree(raw_packet);
290 		return -EOPNOTSUPP;
291 	} else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
292 		if (add)
293 			dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
294 				 fd_data->pctype, fd_data->fd_id);
295 		else
296 			dev_info(&pf->pdev->dev,
297 				 "Filter deleted for PCTYPE %d loc = %d\n",
298 				 fd_data->pctype, fd_data->fd_id);
299 	}
300 
301 	if (add) {
302 		pf->fd_tcp4_filter_cnt++;
303 		if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
304 		    I40E_DEBUG_FD & pf->hw.debug_mask)
305 			dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
306 		set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
307 	} else {
308 		pf->fd_tcp4_filter_cnt--;
309 	}
310 
311 	return 0;
312 }
313 
314 #define I40E_SCTPIP_DUMMY_PACKET_LEN 46
315 /**
316  * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
317  * a specific flow spec
318  * @vsi: pointer to the targeted VSI
319  * @fd_data: the flow director data required for the FDir descriptor
320  * @add: true adds a filter, false removes it
321  *
322  * Returns 0 if the filters were successfully added or removed
323  **/
i40e_add_del_fdir_sctpv4(struct i40e_vsi * vsi,struct i40e_fdir_filter * fd_data,bool add)324 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
325 				    struct i40e_fdir_filter *fd_data,
326 				    bool add)
327 {
328 	struct i40e_pf *pf = vsi->back;
329 	struct sctphdr *sctp;
330 	struct iphdr *ip;
331 	u8 *raw_packet;
332 	int ret;
333 	/* Dummy packet */
334 	static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
335 		0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0,
336 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
337 
338 	raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
339 	if (!raw_packet)
340 		return -ENOMEM;
341 	memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN);
342 
343 	ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
344 	sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET
345 	      + sizeof(struct iphdr));
346 
347 	ip->daddr = fd_data->dst_ip;
348 	sctp->dest = fd_data->dst_port;
349 	ip->saddr = fd_data->src_ip;
350 	sctp->source = fd_data->src_port;
351 
352 	if (fd_data->flex_filter) {
353 		u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN;
354 		__be16 pattern = fd_data->flex_word;
355 		u16 off = fd_data->flex_offset;
356 
357 		*((__force __be16 *)(payload + off)) = pattern;
358 	}
359 
360 	fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
361 	ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
362 	if (ret) {
363 		dev_info(&pf->pdev->dev,
364 			 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
365 			 fd_data->pctype, fd_data->fd_id, ret);
366 		/* Free the packet buffer since it wasn't added to the ring */
367 		kfree(raw_packet);
368 		return -EOPNOTSUPP;
369 	} else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
370 		if (add)
371 			dev_info(&pf->pdev->dev,
372 				 "Filter OK for PCTYPE %d loc = %d\n",
373 				 fd_data->pctype, fd_data->fd_id);
374 		else
375 			dev_info(&pf->pdev->dev,
376 				 "Filter deleted for PCTYPE %d loc = %d\n",
377 				 fd_data->pctype, fd_data->fd_id);
378 	}
379 
380 	if (add)
381 		pf->fd_sctp4_filter_cnt++;
382 	else
383 		pf->fd_sctp4_filter_cnt--;
384 
385 	return 0;
386 }
387 
388 #define I40E_IP_DUMMY_PACKET_LEN 34
389 /**
390  * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
391  * a specific flow spec
392  * @vsi: pointer to the targeted VSI
393  * @fd_data: the flow director data required for the FDir descriptor
394  * @add: true adds a filter, false removes it
395  *
396  * Returns 0 if the filters were successfully added or removed
397  **/
i40e_add_del_fdir_ipv4(struct i40e_vsi * vsi,struct i40e_fdir_filter * fd_data,bool add)398 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
399 				  struct i40e_fdir_filter *fd_data,
400 				  bool add)
401 {
402 	struct i40e_pf *pf = vsi->back;
403 	struct iphdr *ip;
404 	u8 *raw_packet;
405 	int ret;
406 	int i;
407 	static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
408 		0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
409 		0, 0, 0, 0};
410 
411 	for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
412 	     i <= I40E_FILTER_PCTYPE_FRAG_IPV4;	i++) {
413 		raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
414 		if (!raw_packet)
415 			return -ENOMEM;
416 		memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
417 		ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
418 
419 		ip->saddr = fd_data->src_ip;
420 		ip->daddr = fd_data->dst_ip;
421 		ip->protocol = 0;
422 
423 		if (fd_data->flex_filter) {
424 			u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN;
425 			__be16 pattern = fd_data->flex_word;
426 			u16 off = fd_data->flex_offset;
427 
428 			*((__force __be16 *)(payload + off)) = pattern;
429 		}
430 
431 		fd_data->pctype = i;
432 		ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
433 		if (ret) {
434 			dev_info(&pf->pdev->dev,
435 				 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
436 				 fd_data->pctype, fd_data->fd_id, ret);
437 			/* The packet buffer wasn't added to the ring so we
438 			 * need to free it now.
439 			 */
440 			kfree(raw_packet);
441 			return -EOPNOTSUPP;
442 		} else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
443 			if (add)
444 				dev_info(&pf->pdev->dev,
445 					 "Filter OK for PCTYPE %d loc = %d\n",
446 					 fd_data->pctype, fd_data->fd_id);
447 			else
448 				dev_info(&pf->pdev->dev,
449 					 "Filter deleted for PCTYPE %d loc = %d\n",
450 					 fd_data->pctype, fd_data->fd_id);
451 		}
452 	}
453 
454 	if (add)
455 		pf->fd_ip4_filter_cnt++;
456 	else
457 		pf->fd_ip4_filter_cnt--;
458 
459 	return 0;
460 }
461 
462 /**
463  * i40e_add_del_fdir - Build raw packets to add/del fdir filter
464  * @vsi: pointer to the targeted VSI
465  * @input: filter to add or delete
466  * @add: true adds a filter, false removes it
467  *
468  **/
i40e_add_del_fdir(struct i40e_vsi * vsi,struct i40e_fdir_filter * input,bool add)469 int i40e_add_del_fdir(struct i40e_vsi *vsi,
470 		      struct i40e_fdir_filter *input, bool add)
471 {
472 	struct i40e_pf *pf = vsi->back;
473 	int ret;
474 
475 	switch (input->flow_type & ~FLOW_EXT) {
476 	case TCP_V4_FLOW:
477 		ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
478 		break;
479 	case UDP_V4_FLOW:
480 		ret = i40e_add_del_fdir_udpv4(vsi, input, add);
481 		break;
482 	case SCTP_V4_FLOW:
483 		ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
484 		break;
485 	case IP_USER_FLOW:
486 		switch (input->ip4_proto) {
487 		case IPPROTO_TCP:
488 			ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
489 			break;
490 		case IPPROTO_UDP:
491 			ret = i40e_add_del_fdir_udpv4(vsi, input, add);
492 			break;
493 		case IPPROTO_SCTP:
494 			ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
495 			break;
496 		case IPPROTO_IP:
497 			ret = i40e_add_del_fdir_ipv4(vsi, input, add);
498 			break;
499 		default:
500 			/* We cannot support masking based on protocol */
501 			dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n",
502 				 input->ip4_proto);
503 			return -EINVAL;
504 		}
505 		break;
506 	default:
507 		dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n",
508 			 input->flow_type);
509 		return -EINVAL;
510 	}
511 
512 	/* The buffer allocated here will be normally be freed by
513 	 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit
514 	 * completion. In the event of an error adding the buffer to the FDIR
515 	 * ring, it will immediately be freed. It may also be freed by
516 	 * i40e_clean_tx_ring() when closing the VSI.
517 	 */
518 	return ret;
519 }
520 
521 /**
522  * i40e_fd_handle_status - check the Programming Status for FD
523  * @rx_ring: the Rx ring for this descriptor
524  * @qword0_raw: qword0
525  * @qword1: qword1 after le_to_cpu
526  * @prog_id: the id originally used for programming
527  *
528  * This is used to verify if the FD programming or invalidation
529  * requested by SW to the HW is successful or not and take actions accordingly.
530  **/
i40e_fd_handle_status(struct i40e_ring * rx_ring,u64 qword0_raw,u64 qword1,u8 prog_id)531 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw,
532 				  u64 qword1, u8 prog_id)
533 {
534 	struct i40e_pf *pf = rx_ring->vsi->back;
535 	struct pci_dev *pdev = pf->pdev;
536 	struct i40e_16b_rx_wb_qw0 *qw0;
537 	u32 fcnt_prog, fcnt_avail;
538 	u32 error;
539 
540 	qw0 = (struct i40e_16b_rx_wb_qw0 *)&qword0_raw;
541 	error = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
542 		I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
543 
544 	if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
545 		pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id);
546 		if (qw0->hi_dword.fd_id != 0 ||
547 		    (I40E_DEBUG_FD & pf->hw.debug_mask))
548 			dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
549 				 pf->fd_inv);
550 
551 		/* Check if the programming error is for ATR.
552 		 * If so, auto disable ATR and set a state for
553 		 * flush in progress. Next time we come here if flush is in
554 		 * progress do nothing, once flush is complete the state will
555 		 * be cleared.
556 		 */
557 		if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
558 			return;
559 
560 		pf->fd_add_err++;
561 		/* store the current atr filter count */
562 		pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
563 
564 		if (qw0->hi_dword.fd_id == 0 &&
565 		    test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) {
566 			/* These set_bit() calls aren't atomic with the
567 			 * test_bit() here, but worse case we potentially
568 			 * disable ATR and queue a flush right after SB
569 			 * support is re-enabled. That shouldn't cause an
570 			 * issue in practice
571 			 */
572 			set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
573 			set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
574 		}
575 
576 		/* filter programming failed most likely due to table full */
577 		fcnt_prog = i40e_get_global_fd_count(pf);
578 		fcnt_avail = pf->fdir_pf_filter_count;
579 		/* If ATR is running fcnt_prog can quickly change,
580 		 * if we are very close to full, it makes sense to disable
581 		 * FD ATR/SB and then re-enable it when there is room.
582 		 */
583 		if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
584 			if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
585 			    !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED,
586 					      pf->state))
587 				if (I40E_DEBUG_FD & pf->hw.debug_mask)
588 					dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
589 		}
590 	} else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
591 		if (I40E_DEBUG_FD & pf->hw.debug_mask)
592 			dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
593 				 qw0->hi_dword.fd_id);
594 	}
595 }
596 
597 /**
598  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
599  * @ring:      the ring that owns the buffer
600  * @tx_buffer: the buffer to free
601  **/
i40e_unmap_and_free_tx_resource(struct i40e_ring * ring,struct i40e_tx_buffer * tx_buffer)602 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
603 					    struct i40e_tx_buffer *tx_buffer)
604 {
605 	if (tx_buffer->skb) {
606 		if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
607 			kfree(tx_buffer->raw_buf);
608 		else if (ring_is_xdp(ring))
609 			xdp_return_frame(tx_buffer->xdpf);
610 		else
611 			dev_kfree_skb_any(tx_buffer->skb);
612 		if (dma_unmap_len(tx_buffer, len))
613 			dma_unmap_single(ring->dev,
614 					 dma_unmap_addr(tx_buffer, dma),
615 					 dma_unmap_len(tx_buffer, len),
616 					 DMA_TO_DEVICE);
617 	} else if (dma_unmap_len(tx_buffer, len)) {
618 		dma_unmap_page(ring->dev,
619 			       dma_unmap_addr(tx_buffer, dma),
620 			       dma_unmap_len(tx_buffer, len),
621 			       DMA_TO_DEVICE);
622 	}
623 
624 	tx_buffer->next_to_watch = NULL;
625 	tx_buffer->skb = NULL;
626 	dma_unmap_len_set(tx_buffer, len, 0);
627 	/* tx_buffer must be completely set up in the transmit path */
628 }
629 
630 /**
631  * i40e_clean_tx_ring - Free any empty Tx buffers
632  * @tx_ring: ring to be cleaned
633  **/
i40e_clean_tx_ring(struct i40e_ring * tx_ring)634 void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
635 {
636 	unsigned long bi_size;
637 	u16 i;
638 
639 	if (ring_is_xdp(tx_ring) && tx_ring->xsk_pool) {
640 		i40e_xsk_clean_tx_ring(tx_ring);
641 	} else {
642 		/* ring already cleared, nothing to do */
643 		if (!tx_ring->tx_bi)
644 			return;
645 
646 		/* Free all the Tx ring sk_buffs */
647 		for (i = 0; i < tx_ring->count; i++)
648 			i40e_unmap_and_free_tx_resource(tx_ring,
649 							&tx_ring->tx_bi[i]);
650 	}
651 
652 	bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
653 	memset(tx_ring->tx_bi, 0, bi_size);
654 
655 	/* Zero out the descriptor ring */
656 	memset(tx_ring->desc, 0, tx_ring->size);
657 
658 	tx_ring->next_to_use = 0;
659 	tx_ring->next_to_clean = 0;
660 
661 	if (!tx_ring->netdev)
662 		return;
663 
664 	/* cleanup Tx queue statistics */
665 	netdev_tx_reset_queue(txring_txq(tx_ring));
666 }
667 
668 /**
669  * i40e_free_tx_resources - Free Tx resources per queue
670  * @tx_ring: Tx descriptor ring for a specific queue
671  *
672  * Free all transmit software resources
673  **/
i40e_free_tx_resources(struct i40e_ring * tx_ring)674 void i40e_free_tx_resources(struct i40e_ring *tx_ring)
675 {
676 	i40e_clean_tx_ring(tx_ring);
677 	kfree(tx_ring->tx_bi);
678 	tx_ring->tx_bi = NULL;
679 
680 	if (tx_ring->desc) {
681 		dma_free_coherent(tx_ring->dev, tx_ring->size,
682 				  tx_ring->desc, tx_ring->dma);
683 		tx_ring->desc = NULL;
684 	}
685 }
686 
687 /**
688  * i40e_get_tx_pending - how many tx descriptors not processed
689  * @ring: the ring of descriptors
690  * @in_sw: use SW variables
691  *
692  * Since there is no access to the ring head register
693  * in XL710, we need to use our local copies
694  **/
i40e_get_tx_pending(struct i40e_ring * ring,bool in_sw)695 u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
696 {
697 	u32 head, tail;
698 
699 	if (!in_sw) {
700 		head = i40e_get_head(ring);
701 		tail = readl(ring->tail);
702 	} else {
703 		head = ring->next_to_clean;
704 		tail = ring->next_to_use;
705 	}
706 
707 	if (head != tail)
708 		return (head < tail) ?
709 			tail - head : (tail + ring->count - head);
710 
711 	return 0;
712 }
713 
714 /**
715  * i40e_detect_recover_hung - Function to detect and recover hung_queues
716  * @vsi:  pointer to vsi struct with tx queues
717  *
718  * VSI has netdev and netdev has TX queues. This function is to check each of
719  * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
720  **/
i40e_detect_recover_hung(struct i40e_vsi * vsi)721 void i40e_detect_recover_hung(struct i40e_vsi *vsi)
722 {
723 	struct i40e_ring *tx_ring = NULL;
724 	struct net_device *netdev;
725 	unsigned int i;
726 	int packets;
727 
728 	if (!vsi)
729 		return;
730 
731 	if (test_bit(__I40E_VSI_DOWN, vsi->state))
732 		return;
733 
734 	netdev = vsi->netdev;
735 	if (!netdev)
736 		return;
737 
738 	if (!netif_carrier_ok(netdev))
739 		return;
740 
741 	for (i = 0; i < vsi->num_queue_pairs; i++) {
742 		tx_ring = vsi->tx_rings[i];
743 		if (tx_ring && tx_ring->desc) {
744 			/* If packet counter has not changed the queue is
745 			 * likely stalled, so force an interrupt for this
746 			 * queue.
747 			 *
748 			 * prev_pkt_ctr would be negative if there was no
749 			 * pending work.
750 			 */
751 			packets = tx_ring->stats.packets & INT_MAX;
752 			if (tx_ring->tx_stats.prev_pkt_ctr == packets) {
753 				i40e_force_wb(vsi, tx_ring->q_vector);
754 				continue;
755 			}
756 
757 			/* Memory barrier between read of packet count and call
758 			 * to i40e_get_tx_pending()
759 			 */
760 			smp_rmb();
761 			tx_ring->tx_stats.prev_pkt_ctr =
762 			    i40e_get_tx_pending(tx_ring, true) ? packets : -1;
763 		}
764 	}
765 }
766 
767 /**
768  * i40e_clean_tx_irq - Reclaim resources after transmit completes
769  * @vsi: the VSI we care about
770  * @tx_ring: Tx ring to clean
771  * @napi_budget: Used to determine if we are in netpoll
772  *
773  * Returns true if there's any budget left (e.g. the clean is finished)
774  **/
i40e_clean_tx_irq(struct i40e_vsi * vsi,struct i40e_ring * tx_ring,int napi_budget)775 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
776 			      struct i40e_ring *tx_ring, int napi_budget)
777 {
778 	int i = tx_ring->next_to_clean;
779 	struct i40e_tx_buffer *tx_buf;
780 	struct i40e_tx_desc *tx_head;
781 	struct i40e_tx_desc *tx_desc;
782 	unsigned int total_bytes = 0, total_packets = 0;
783 	unsigned int budget = vsi->work_limit;
784 
785 	tx_buf = &tx_ring->tx_bi[i];
786 	tx_desc = I40E_TX_DESC(tx_ring, i);
787 	i -= tx_ring->count;
788 
789 	tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
790 
791 	do {
792 		struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
793 
794 		/* if next_to_watch is not set then there is no work pending */
795 		if (!eop_desc)
796 			break;
797 
798 		/* prevent any other reads prior to eop_desc */
799 		smp_rmb();
800 
801 		i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
802 		/* we have caught up to head, no work left to do */
803 		if (tx_head == tx_desc)
804 			break;
805 
806 		/* clear next_to_watch to prevent false hangs */
807 		tx_buf->next_to_watch = NULL;
808 
809 		/* update the statistics for this packet */
810 		total_bytes += tx_buf->bytecount;
811 		total_packets += tx_buf->gso_segs;
812 
813 		/* free the skb/XDP data */
814 		if (ring_is_xdp(tx_ring))
815 			xdp_return_frame(tx_buf->xdpf);
816 		else
817 			napi_consume_skb(tx_buf->skb, napi_budget);
818 
819 		/* unmap skb header data */
820 		dma_unmap_single(tx_ring->dev,
821 				 dma_unmap_addr(tx_buf, dma),
822 				 dma_unmap_len(tx_buf, len),
823 				 DMA_TO_DEVICE);
824 
825 		/* clear tx_buffer data */
826 		tx_buf->skb = NULL;
827 		dma_unmap_len_set(tx_buf, len, 0);
828 
829 		/* unmap remaining buffers */
830 		while (tx_desc != eop_desc) {
831 			i40e_trace(clean_tx_irq_unmap,
832 				   tx_ring, tx_desc, tx_buf);
833 
834 			tx_buf++;
835 			tx_desc++;
836 			i++;
837 			if (unlikely(!i)) {
838 				i -= tx_ring->count;
839 				tx_buf = tx_ring->tx_bi;
840 				tx_desc = I40E_TX_DESC(tx_ring, 0);
841 			}
842 
843 			/* unmap any remaining paged data */
844 			if (dma_unmap_len(tx_buf, len)) {
845 				dma_unmap_page(tx_ring->dev,
846 					       dma_unmap_addr(tx_buf, dma),
847 					       dma_unmap_len(tx_buf, len),
848 					       DMA_TO_DEVICE);
849 				dma_unmap_len_set(tx_buf, len, 0);
850 			}
851 		}
852 
853 		/* move us one more past the eop_desc for start of next pkt */
854 		tx_buf++;
855 		tx_desc++;
856 		i++;
857 		if (unlikely(!i)) {
858 			i -= tx_ring->count;
859 			tx_buf = tx_ring->tx_bi;
860 			tx_desc = I40E_TX_DESC(tx_ring, 0);
861 		}
862 
863 		prefetch(tx_desc);
864 
865 		/* update budget accounting */
866 		budget--;
867 	} while (likely(budget));
868 
869 	i += tx_ring->count;
870 	tx_ring->next_to_clean = i;
871 	i40e_update_tx_stats(tx_ring, total_packets, total_bytes);
872 	i40e_arm_wb(tx_ring, vsi, budget);
873 
874 	if (ring_is_xdp(tx_ring))
875 		return !!budget;
876 
877 	/* notify netdev of completed buffers */
878 	netdev_tx_completed_queue(txring_txq(tx_ring),
879 				  total_packets, total_bytes);
880 
881 #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
882 	if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
883 		     (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
884 		/* Make sure that anybody stopping the queue after this
885 		 * sees the new next_to_clean.
886 		 */
887 		smp_mb();
888 		if (__netif_subqueue_stopped(tx_ring->netdev,
889 					     tx_ring->queue_index) &&
890 		   !test_bit(__I40E_VSI_DOWN, vsi->state)) {
891 			netif_wake_subqueue(tx_ring->netdev,
892 					    tx_ring->queue_index);
893 			++tx_ring->tx_stats.restart_queue;
894 		}
895 	}
896 
897 	return !!budget;
898 }
899 
900 /**
901  * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
902  * @vsi: the VSI we care about
903  * @q_vector: the vector on which to enable writeback
904  *
905  **/
i40e_enable_wb_on_itr(struct i40e_vsi * vsi,struct i40e_q_vector * q_vector)906 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
907 				  struct i40e_q_vector *q_vector)
908 {
909 	u16 flags = q_vector->tx.ring[0].flags;
910 	u32 val;
911 
912 	if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
913 		return;
914 
915 	if (q_vector->arm_wb_state)
916 		return;
917 
918 	if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
919 		val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
920 		      I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
921 
922 		wr32(&vsi->back->hw,
923 		     I40E_PFINT_DYN_CTLN(q_vector->reg_idx),
924 		     val);
925 	} else {
926 		val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
927 		      I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
928 
929 		wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
930 	}
931 	q_vector->arm_wb_state = true;
932 }
933 
934 /**
935  * i40e_force_wb - Issue SW Interrupt so HW does a wb
936  * @vsi: the VSI we care about
937  * @q_vector: the vector  on which to force writeback
938  *
939  **/
i40e_force_wb(struct i40e_vsi * vsi,struct i40e_q_vector * q_vector)940 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
941 {
942 	if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
943 		u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
944 			  I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
945 			  I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
946 			  I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
947 			  /* allow 00 to be written to the index */
948 
949 		wr32(&vsi->back->hw,
950 		     I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val);
951 	} else {
952 		u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
953 			  I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
954 			  I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
955 			  I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
956 			/* allow 00 to be written to the index */
957 
958 		wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
959 	}
960 }
961 
i40e_container_is_rx(struct i40e_q_vector * q_vector,struct i40e_ring_container * rc)962 static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector,
963 					struct i40e_ring_container *rc)
964 {
965 	return &q_vector->rx == rc;
966 }
967 
i40e_itr_divisor(struct i40e_q_vector * q_vector)968 static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector)
969 {
970 	unsigned int divisor;
971 
972 	switch (q_vector->vsi->back->hw.phy.link_info.link_speed) {
973 	case I40E_LINK_SPEED_40GB:
974 		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024;
975 		break;
976 	case I40E_LINK_SPEED_25GB:
977 	case I40E_LINK_SPEED_20GB:
978 		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512;
979 		break;
980 	default:
981 	case I40E_LINK_SPEED_10GB:
982 		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256;
983 		break;
984 	case I40E_LINK_SPEED_1GB:
985 	case I40E_LINK_SPEED_100MB:
986 		divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32;
987 		break;
988 	}
989 
990 	return divisor;
991 }
992 
993 /**
994  * i40e_update_itr - update the dynamic ITR value based on statistics
995  * @q_vector: structure containing interrupt and ring information
996  * @rc: structure containing ring performance data
997  *
998  * Stores a new ITR value based on packets and byte
999  * counts during the last interrupt.  The advantage of per interrupt
1000  * computation is faster updates and more accurate ITR for the current
1001  * traffic pattern.  Constants in this function were computed
1002  * based on theoretical maximum wire speed and thresholds were set based
1003  * on testing data as well as attempting to minimize response time
1004  * while increasing bulk throughput.
1005  **/
i40e_update_itr(struct i40e_q_vector * q_vector,struct i40e_ring_container * rc)1006 static void i40e_update_itr(struct i40e_q_vector *q_vector,
1007 			    struct i40e_ring_container *rc)
1008 {
1009 	unsigned int avg_wire_size, packets, bytes, itr;
1010 	unsigned long next_update = jiffies;
1011 
1012 	/* If we don't have any rings just leave ourselves set for maximum
1013 	 * possible latency so we take ourselves out of the equation.
1014 	 */
1015 	if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
1016 		return;
1017 
1018 	/* For Rx we want to push the delay up and default to low latency.
1019 	 * for Tx we want to pull the delay down and default to high latency.
1020 	 */
1021 	itr = i40e_container_is_rx(q_vector, rc) ?
1022 	      I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY :
1023 	      I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY;
1024 
1025 	/* If we didn't update within up to 1 - 2 jiffies we can assume
1026 	 * that either packets are coming in so slow there hasn't been
1027 	 * any work, or that there is so much work that NAPI is dealing
1028 	 * with interrupt moderation and we don't need to do anything.
1029 	 */
1030 	if (time_after(next_update, rc->next_update))
1031 		goto clear_counts;
1032 
1033 	/* If itr_countdown is set it means we programmed an ITR within
1034 	 * the last 4 interrupt cycles. This has a side effect of us
1035 	 * potentially firing an early interrupt. In order to work around
1036 	 * this we need to throw out any data received for a few
1037 	 * interrupts following the update.
1038 	 */
1039 	if (q_vector->itr_countdown) {
1040 		itr = rc->target_itr;
1041 		goto clear_counts;
1042 	}
1043 
1044 	packets = rc->total_packets;
1045 	bytes = rc->total_bytes;
1046 
1047 	if (i40e_container_is_rx(q_vector, rc)) {
1048 		/* If Rx there are 1 to 4 packets and bytes are less than
1049 		 * 9000 assume insufficient data to use bulk rate limiting
1050 		 * approach unless Tx is already in bulk rate limiting. We
1051 		 * are likely latency driven.
1052 		 */
1053 		if (packets && packets < 4 && bytes < 9000 &&
1054 		    (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) {
1055 			itr = I40E_ITR_ADAPTIVE_LATENCY;
1056 			goto adjust_by_size;
1057 		}
1058 	} else if (packets < 4) {
1059 		/* If we have Tx and Rx ITR maxed and Tx ITR is running in
1060 		 * bulk mode and we are receiving 4 or fewer packets just
1061 		 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
1062 		 * that the Rx can relax.
1063 		 */
1064 		if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS &&
1065 		    (q_vector->rx.target_itr & I40E_ITR_MASK) ==
1066 		     I40E_ITR_ADAPTIVE_MAX_USECS)
1067 			goto clear_counts;
1068 	} else if (packets > 32) {
1069 		/* If we have processed over 32 packets in a single interrupt
1070 		 * for Tx assume we need to switch over to "bulk" mode.
1071 		 */
1072 		rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY;
1073 	}
1074 
1075 	/* We have no packets to actually measure against. This means
1076 	 * either one of the other queues on this vector is active or
1077 	 * we are a Tx queue doing TSO with too high of an interrupt rate.
1078 	 *
1079 	 * Between 4 and 56 we can assume that our current interrupt delay
1080 	 * is only slightly too low. As such we should increase it by a small
1081 	 * fixed amount.
1082 	 */
1083 	if (packets < 56) {
1084 		itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC;
1085 		if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1086 			itr &= I40E_ITR_ADAPTIVE_LATENCY;
1087 			itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1088 		}
1089 		goto clear_counts;
1090 	}
1091 
1092 	if (packets <= 256) {
1093 		itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
1094 		itr &= I40E_ITR_MASK;
1095 
1096 		/* Between 56 and 112 is our "goldilocks" zone where we are
1097 		 * working out "just right". Just report that our current
1098 		 * ITR is good for us.
1099 		 */
1100 		if (packets <= 112)
1101 			goto clear_counts;
1102 
1103 		/* If packet count is 128 or greater we are likely looking
1104 		 * at a slight overrun of the delay we want. Try halving
1105 		 * our delay to see if that will cut the number of packets
1106 		 * in half per interrupt.
1107 		 */
1108 		itr /= 2;
1109 		itr &= I40E_ITR_MASK;
1110 		if (itr < I40E_ITR_ADAPTIVE_MIN_USECS)
1111 			itr = I40E_ITR_ADAPTIVE_MIN_USECS;
1112 
1113 		goto clear_counts;
1114 	}
1115 
1116 	/* The paths below assume we are dealing with a bulk ITR since
1117 	 * number of packets is greater than 256. We are just going to have
1118 	 * to compute a value and try to bring the count under control,
1119 	 * though for smaller packet sizes there isn't much we can do as
1120 	 * NAPI polling will likely be kicking in sooner rather than later.
1121 	 */
1122 	itr = I40E_ITR_ADAPTIVE_BULK;
1123 
1124 adjust_by_size:
1125 	/* If packet counts are 256 or greater we can assume we have a gross
1126 	 * overestimation of what the rate should be. Instead of trying to fine
1127 	 * tune it just use the formula below to try and dial in an exact value
1128 	 * give the current packet size of the frame.
1129 	 */
1130 	avg_wire_size = bytes / packets;
1131 
1132 	/* The following is a crude approximation of:
1133 	 *  wmem_default / (size + overhead) = desired_pkts_per_int
1134 	 *  rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
1135 	 *  (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1136 	 *
1137 	 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1138 	 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1139 	 * formula down to
1140 	 *
1141 	 *  (170 * (size + 24)) / (size + 640) = ITR
1142 	 *
1143 	 * We first do some math on the packet size and then finally bitshift
1144 	 * by 8 after rounding up. We also have to account for PCIe link speed
1145 	 * difference as ITR scales based on this.
1146 	 */
1147 	if (avg_wire_size <= 60) {
1148 		/* Start at 250k ints/sec */
1149 		avg_wire_size = 4096;
1150 	} else if (avg_wire_size <= 380) {
1151 		/* 250K ints/sec to 60K ints/sec */
1152 		avg_wire_size *= 40;
1153 		avg_wire_size += 1696;
1154 	} else if (avg_wire_size <= 1084) {
1155 		/* 60K ints/sec to 36K ints/sec */
1156 		avg_wire_size *= 15;
1157 		avg_wire_size += 11452;
1158 	} else if (avg_wire_size <= 1980) {
1159 		/* 36K ints/sec to 30K ints/sec */
1160 		avg_wire_size *= 5;
1161 		avg_wire_size += 22420;
1162 	} else {
1163 		/* plateau at a limit of 30K ints/sec */
1164 		avg_wire_size = 32256;
1165 	}
1166 
1167 	/* If we are in low latency mode halve our delay which doubles the
1168 	 * rate to somewhere between 100K to 16K ints/sec
1169 	 */
1170 	if (itr & I40E_ITR_ADAPTIVE_LATENCY)
1171 		avg_wire_size /= 2;
1172 
1173 	/* Resultant value is 256 times larger than it needs to be. This
1174 	 * gives us room to adjust the value as needed to either increase
1175 	 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
1176 	 *
1177 	 * Use addition as we have already recorded the new latency flag
1178 	 * for the ITR value.
1179 	 */
1180 	itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) *
1181 	       I40E_ITR_ADAPTIVE_MIN_INC;
1182 
1183 	if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1184 		itr &= I40E_ITR_ADAPTIVE_LATENCY;
1185 		itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1186 	}
1187 
1188 clear_counts:
1189 	/* write back value */
1190 	rc->target_itr = itr;
1191 
1192 	/* next update should occur within next jiffy */
1193 	rc->next_update = next_update + 1;
1194 
1195 	rc->total_bytes = 0;
1196 	rc->total_packets = 0;
1197 }
1198 
i40e_rx_bi(struct i40e_ring * rx_ring,u32 idx)1199 static struct i40e_rx_buffer *i40e_rx_bi(struct i40e_ring *rx_ring, u32 idx)
1200 {
1201 	return &rx_ring->rx_bi[idx];
1202 }
1203 
1204 /**
1205  * i40e_reuse_rx_page - page flip buffer and store it back on the ring
1206  * @rx_ring: rx descriptor ring to store buffers on
1207  * @old_buff: donor buffer to have page reused
1208  *
1209  * Synchronizes page for reuse by the adapter
1210  **/
i40e_reuse_rx_page(struct i40e_ring * rx_ring,struct i40e_rx_buffer * old_buff)1211 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
1212 			       struct i40e_rx_buffer *old_buff)
1213 {
1214 	struct i40e_rx_buffer *new_buff;
1215 	u16 nta = rx_ring->next_to_alloc;
1216 
1217 	new_buff = i40e_rx_bi(rx_ring, nta);
1218 
1219 	/* update, and store next to alloc */
1220 	nta++;
1221 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1222 
1223 	/* transfer page from old buffer to new buffer */
1224 	new_buff->dma		= old_buff->dma;
1225 	new_buff->page		= old_buff->page;
1226 	new_buff->page_offset	= old_buff->page_offset;
1227 	new_buff->pagecnt_bias	= old_buff->pagecnt_bias;
1228 
1229 	rx_ring->rx_stats.page_reuse_count++;
1230 
1231 	/* clear contents of buffer_info */
1232 	old_buff->page = NULL;
1233 }
1234 
1235 /**
1236  * i40e_clean_programming_status - clean the programming status descriptor
1237  * @rx_ring: the rx ring that has this descriptor
1238  * @qword0_raw: qword0
1239  * @qword1: qword1 representing status_error_len in CPU ordering
1240  *
1241  * Flow director should handle FD_FILTER_STATUS to check its filter programming
1242  * status being successful or not and take actions accordingly. FCoE should
1243  * handle its context/filter programming/invalidation status and take actions.
1244  *
1245  * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL.
1246  **/
i40e_clean_programming_status(struct i40e_ring * rx_ring,u64 qword0_raw,u64 qword1)1247 void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw,
1248 				   u64 qword1)
1249 {
1250 	u8 id;
1251 
1252 	id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1253 		  I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1254 
1255 	if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
1256 		i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id);
1257 }
1258 
1259 /**
1260  * i40e_setup_tx_descriptors - Allocate the Tx descriptors
1261  * @tx_ring: the tx ring to set up
1262  *
1263  * Return 0 on success, negative on error
1264  **/
i40e_setup_tx_descriptors(struct i40e_ring * tx_ring)1265 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
1266 {
1267 	struct device *dev = tx_ring->dev;
1268 	int bi_size;
1269 
1270 	if (!dev)
1271 		return -ENOMEM;
1272 
1273 	/* warn if we are about to overwrite the pointer */
1274 	WARN_ON(tx_ring->tx_bi);
1275 	bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1276 	tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1277 	if (!tx_ring->tx_bi)
1278 		goto err;
1279 
1280 	u64_stats_init(&tx_ring->syncp);
1281 
1282 	/* round up to nearest 4K */
1283 	tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1284 	/* add u32 for head writeback, align after this takes care of
1285 	 * guaranteeing this is at least one cache line in size
1286 	 */
1287 	tx_ring->size += sizeof(u32);
1288 	tx_ring->size = ALIGN(tx_ring->size, 4096);
1289 	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1290 					   &tx_ring->dma, GFP_KERNEL);
1291 	if (!tx_ring->desc) {
1292 		dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1293 			 tx_ring->size);
1294 		goto err;
1295 	}
1296 
1297 	tx_ring->next_to_use = 0;
1298 	tx_ring->next_to_clean = 0;
1299 	tx_ring->tx_stats.prev_pkt_ctr = -1;
1300 	return 0;
1301 
1302 err:
1303 	kfree(tx_ring->tx_bi);
1304 	tx_ring->tx_bi = NULL;
1305 	return -ENOMEM;
1306 }
1307 
i40e_alloc_rx_bi(struct i40e_ring * rx_ring)1308 int i40e_alloc_rx_bi(struct i40e_ring *rx_ring)
1309 {
1310 	unsigned long sz = sizeof(*rx_ring->rx_bi) * rx_ring->count;
1311 
1312 	rx_ring->rx_bi = kzalloc(sz, GFP_KERNEL);
1313 	return rx_ring->rx_bi ? 0 : -ENOMEM;
1314 }
1315 
i40e_clear_rx_bi(struct i40e_ring * rx_ring)1316 static void i40e_clear_rx_bi(struct i40e_ring *rx_ring)
1317 {
1318 	memset(rx_ring->rx_bi, 0, sizeof(*rx_ring->rx_bi) * rx_ring->count);
1319 }
1320 
1321 /**
1322  * i40e_clean_rx_ring - Free Rx buffers
1323  * @rx_ring: ring to be cleaned
1324  **/
i40e_clean_rx_ring(struct i40e_ring * rx_ring)1325 void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1326 {
1327 	u16 i;
1328 
1329 	/* ring already cleared, nothing to do */
1330 	if (!rx_ring->rx_bi)
1331 		return;
1332 
1333 	if (rx_ring->skb) {
1334 		dev_kfree_skb(rx_ring->skb);
1335 		rx_ring->skb = NULL;
1336 	}
1337 
1338 	if (rx_ring->xsk_pool) {
1339 		i40e_xsk_clean_rx_ring(rx_ring);
1340 		goto skip_free;
1341 	}
1342 
1343 	/* Free all the Rx ring sk_buffs */
1344 	for (i = 0; i < rx_ring->count; i++) {
1345 		struct i40e_rx_buffer *rx_bi = i40e_rx_bi(rx_ring, i);
1346 
1347 		if (!rx_bi->page)
1348 			continue;
1349 
1350 		/* Invalidate cache lines that may have been written to by
1351 		 * device so that we avoid corrupting memory.
1352 		 */
1353 		dma_sync_single_range_for_cpu(rx_ring->dev,
1354 					      rx_bi->dma,
1355 					      rx_bi->page_offset,
1356 					      rx_ring->rx_buf_len,
1357 					      DMA_FROM_DEVICE);
1358 
1359 		/* free resources associated with mapping */
1360 		dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
1361 				     i40e_rx_pg_size(rx_ring),
1362 				     DMA_FROM_DEVICE,
1363 				     I40E_RX_DMA_ATTR);
1364 
1365 		__page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
1366 
1367 		rx_bi->page = NULL;
1368 		rx_bi->page_offset = 0;
1369 	}
1370 
1371 skip_free:
1372 	if (rx_ring->xsk_pool)
1373 		i40e_clear_rx_bi_zc(rx_ring);
1374 	else
1375 		i40e_clear_rx_bi(rx_ring);
1376 
1377 	/* Zero out the descriptor ring */
1378 	memset(rx_ring->desc, 0, rx_ring->size);
1379 
1380 	rx_ring->next_to_alloc = 0;
1381 	rx_ring->next_to_clean = 0;
1382 	rx_ring->next_to_use = 0;
1383 }
1384 
1385 /**
1386  * i40e_free_rx_resources - Free Rx resources
1387  * @rx_ring: ring to clean the resources from
1388  *
1389  * Free all receive software resources
1390  **/
i40e_free_rx_resources(struct i40e_ring * rx_ring)1391 void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1392 {
1393 	i40e_clean_rx_ring(rx_ring);
1394 	if (rx_ring->vsi->type == I40E_VSI_MAIN)
1395 		xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
1396 	rx_ring->xdp_prog = NULL;
1397 	kfree(rx_ring->rx_bi);
1398 	rx_ring->rx_bi = NULL;
1399 
1400 	if (rx_ring->desc) {
1401 		dma_free_coherent(rx_ring->dev, rx_ring->size,
1402 				  rx_ring->desc, rx_ring->dma);
1403 		rx_ring->desc = NULL;
1404 	}
1405 }
1406 
1407 /**
1408  * i40e_setup_rx_descriptors - Allocate Rx descriptors
1409  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1410  *
1411  * Returns 0 on success, negative on failure
1412  **/
i40e_setup_rx_descriptors(struct i40e_ring * rx_ring)1413 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1414 {
1415 	struct device *dev = rx_ring->dev;
1416 	int err;
1417 
1418 	u64_stats_init(&rx_ring->syncp);
1419 
1420 	/* Round up to nearest 4K */
1421 	rx_ring->size = rx_ring->count * sizeof(union i40e_rx_desc);
1422 	rx_ring->size = ALIGN(rx_ring->size, 4096);
1423 	rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1424 					   &rx_ring->dma, GFP_KERNEL);
1425 
1426 	if (!rx_ring->desc) {
1427 		dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1428 			 rx_ring->size);
1429 		return -ENOMEM;
1430 	}
1431 
1432 	rx_ring->next_to_alloc = 0;
1433 	rx_ring->next_to_clean = 0;
1434 	rx_ring->next_to_use = 0;
1435 
1436 	/* XDP RX-queue info only needed for RX rings exposed to XDP */
1437 	if (rx_ring->vsi->type == I40E_VSI_MAIN) {
1438 		err = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
1439 				       rx_ring->queue_index);
1440 		if (err < 0)
1441 			return err;
1442 	}
1443 
1444 	rx_ring->xdp_prog = rx_ring->vsi->xdp_prog;
1445 
1446 	return 0;
1447 }
1448 
1449 /**
1450  * i40e_release_rx_desc - Store the new tail and head values
1451  * @rx_ring: ring to bump
1452  * @val: new head index
1453  **/
i40e_release_rx_desc(struct i40e_ring * rx_ring,u32 val)1454 void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1455 {
1456 	rx_ring->next_to_use = val;
1457 
1458 	/* update next to alloc since we have filled the ring */
1459 	rx_ring->next_to_alloc = val;
1460 
1461 	/* Force memory writes to complete before letting h/w
1462 	 * know there are new descriptors to fetch.  (Only
1463 	 * applicable for weak-ordered memory model archs,
1464 	 * such as IA-64).
1465 	 */
1466 	wmb();
1467 	writel(val, rx_ring->tail);
1468 }
1469 
1470 /**
1471  * i40e_rx_offset - Return expected offset into page to access data
1472  * @rx_ring: Ring we are requesting offset of
1473  *
1474  * Returns the offset value for ring into the data buffer.
1475  */
i40e_rx_offset(struct i40e_ring * rx_ring)1476 static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring)
1477 {
1478 	return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0;
1479 }
1480 
i40e_rx_frame_truesize(struct i40e_ring * rx_ring,unsigned int size)1481 static unsigned int i40e_rx_frame_truesize(struct i40e_ring *rx_ring,
1482 					   unsigned int size)
1483 {
1484 	unsigned int truesize;
1485 
1486 #if (PAGE_SIZE < 8192)
1487 	truesize = i40e_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
1488 #else
1489 	truesize = i40e_rx_offset(rx_ring) ?
1490 		SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring)) +
1491 		SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
1492 		SKB_DATA_ALIGN(size);
1493 #endif
1494 	return truesize;
1495 }
1496 
1497 /**
1498  * i40e_alloc_mapped_page - recycle or make a new page
1499  * @rx_ring: ring to use
1500  * @bi: rx_buffer struct to modify
1501  *
1502  * Returns true if the page was successfully allocated or
1503  * reused.
1504  **/
i40e_alloc_mapped_page(struct i40e_ring * rx_ring,struct i40e_rx_buffer * bi)1505 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
1506 				   struct i40e_rx_buffer *bi)
1507 {
1508 	struct page *page = bi->page;
1509 	dma_addr_t dma;
1510 
1511 	/* since we are recycling buffers we should seldom need to alloc */
1512 	if (likely(page)) {
1513 		rx_ring->rx_stats.page_reuse_count++;
1514 		return true;
1515 	}
1516 
1517 	/* alloc new page for storage */
1518 	page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
1519 	if (unlikely(!page)) {
1520 		rx_ring->rx_stats.alloc_page_failed++;
1521 		return false;
1522 	}
1523 
1524 	/* map page for use */
1525 	dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1526 				 i40e_rx_pg_size(rx_ring),
1527 				 DMA_FROM_DEVICE,
1528 				 I40E_RX_DMA_ATTR);
1529 
1530 	/* if mapping failed free memory back to system since
1531 	 * there isn't much point in holding memory we can't use
1532 	 */
1533 	if (dma_mapping_error(rx_ring->dev, dma)) {
1534 		__free_pages(page, i40e_rx_pg_order(rx_ring));
1535 		rx_ring->rx_stats.alloc_page_failed++;
1536 		return false;
1537 	}
1538 
1539 	bi->dma = dma;
1540 	bi->page = page;
1541 	bi->page_offset = i40e_rx_offset(rx_ring);
1542 	page_ref_add(page, USHRT_MAX - 1);
1543 	bi->pagecnt_bias = USHRT_MAX;
1544 
1545 	return true;
1546 }
1547 
1548 /**
1549  * i40e_alloc_rx_buffers - Replace used receive buffers
1550  * @rx_ring: ring to place buffers on
1551  * @cleaned_count: number of buffers to replace
1552  *
1553  * Returns false if all allocations were successful, true if any fail
1554  **/
i40e_alloc_rx_buffers(struct i40e_ring * rx_ring,u16 cleaned_count)1555 bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1556 {
1557 	u16 ntu = rx_ring->next_to_use;
1558 	union i40e_rx_desc *rx_desc;
1559 	struct i40e_rx_buffer *bi;
1560 
1561 	/* do nothing if no valid netdev defined */
1562 	if (!rx_ring->netdev || !cleaned_count)
1563 		return false;
1564 
1565 	rx_desc = I40E_RX_DESC(rx_ring, ntu);
1566 	bi = i40e_rx_bi(rx_ring, ntu);
1567 
1568 	do {
1569 		if (!i40e_alloc_mapped_page(rx_ring, bi))
1570 			goto no_buffers;
1571 
1572 		/* sync the buffer for use by the device */
1573 		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1574 						 bi->page_offset,
1575 						 rx_ring->rx_buf_len,
1576 						 DMA_FROM_DEVICE);
1577 
1578 		/* Refresh the desc even if buffer_addrs didn't change
1579 		 * because each write-back erases this info.
1580 		 */
1581 		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1582 
1583 		rx_desc++;
1584 		bi++;
1585 		ntu++;
1586 		if (unlikely(ntu == rx_ring->count)) {
1587 			rx_desc = I40E_RX_DESC(rx_ring, 0);
1588 			bi = i40e_rx_bi(rx_ring, 0);
1589 			ntu = 0;
1590 		}
1591 
1592 		/* clear the status bits for the next_to_use descriptor */
1593 		rx_desc->wb.qword1.status_error_len = 0;
1594 
1595 		cleaned_count--;
1596 	} while (cleaned_count);
1597 
1598 	if (rx_ring->next_to_use != ntu)
1599 		i40e_release_rx_desc(rx_ring, ntu);
1600 
1601 	return false;
1602 
1603 no_buffers:
1604 	if (rx_ring->next_to_use != ntu)
1605 		i40e_release_rx_desc(rx_ring, ntu);
1606 
1607 	/* make sure to come back via polling to try again after
1608 	 * allocation failure
1609 	 */
1610 	return true;
1611 }
1612 
1613 /**
1614  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1615  * @vsi: the VSI we care about
1616  * @skb: skb currently being received and modified
1617  * @rx_desc: the receive descriptor
1618  **/
i40e_rx_checksum(struct i40e_vsi * vsi,struct sk_buff * skb,union i40e_rx_desc * rx_desc)1619 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1620 				    struct sk_buff *skb,
1621 				    union i40e_rx_desc *rx_desc)
1622 {
1623 	struct i40e_rx_ptype_decoded decoded;
1624 	u32 rx_error, rx_status;
1625 	bool ipv4, ipv6;
1626 	u8 ptype;
1627 	u64 qword;
1628 
1629 	qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1630 	ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
1631 	rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1632 		   I40E_RXD_QW1_ERROR_SHIFT;
1633 	rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1634 		    I40E_RXD_QW1_STATUS_SHIFT;
1635 	decoded = decode_rx_desc_ptype(ptype);
1636 
1637 	skb->ip_summed = CHECKSUM_NONE;
1638 
1639 	skb_checksum_none_assert(skb);
1640 
1641 	/* Rx csum enabled and ip headers found? */
1642 	if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1643 		return;
1644 
1645 	/* did the hardware decode the packet and checksum? */
1646 	if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1647 		return;
1648 
1649 	/* both known and outer_ip must be set for the below code to work */
1650 	if (!(decoded.known && decoded.outer_ip))
1651 		return;
1652 
1653 	ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1654 	       (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
1655 	ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1656 	       (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1657 
1658 	if (ipv4 &&
1659 	    (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1660 			 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1661 		goto checksum_fail;
1662 
1663 	/* likely incorrect csum if alternate IP extension headers found */
1664 	if (ipv6 &&
1665 	    rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1666 		/* don't increment checksum err here, non-fatal err */
1667 		return;
1668 
1669 	/* there was some L4 error, count error and punt packet to the stack */
1670 	if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1671 		goto checksum_fail;
1672 
1673 	/* handle packets that were not able to be checksummed due
1674 	 * to arrival speed, in this case the stack can compute
1675 	 * the csum.
1676 	 */
1677 	if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1678 		return;
1679 
1680 	/* If there is an outer header present that might contain a checksum
1681 	 * we need to bump the checksum level by 1 to reflect the fact that
1682 	 * we are indicating we validated the inner checksum.
1683 	 */
1684 	if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
1685 		skb->csum_level = 1;
1686 
1687 	/* Only report checksum unnecessary for TCP, UDP, or SCTP */
1688 	switch (decoded.inner_prot) {
1689 	case I40E_RX_PTYPE_INNER_PROT_TCP:
1690 	case I40E_RX_PTYPE_INNER_PROT_UDP:
1691 	case I40E_RX_PTYPE_INNER_PROT_SCTP:
1692 		skb->ip_summed = CHECKSUM_UNNECESSARY;
1693 		fallthrough;
1694 	default:
1695 		break;
1696 	}
1697 
1698 	return;
1699 
1700 checksum_fail:
1701 	vsi->back->hw_csum_rx_error++;
1702 }
1703 
1704 /**
1705  * i40e_ptype_to_htype - get a hash type
1706  * @ptype: the ptype value from the descriptor
1707  *
1708  * Returns a hash type to be used by skb_set_hash
1709  **/
i40e_ptype_to_htype(u8 ptype)1710 static inline int i40e_ptype_to_htype(u8 ptype)
1711 {
1712 	struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1713 
1714 	if (!decoded.known)
1715 		return PKT_HASH_TYPE_NONE;
1716 
1717 	if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1718 	    decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1719 		return PKT_HASH_TYPE_L4;
1720 	else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1721 		 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1722 		return PKT_HASH_TYPE_L3;
1723 	else
1724 		return PKT_HASH_TYPE_L2;
1725 }
1726 
1727 /**
1728  * i40e_rx_hash - set the hash value in the skb
1729  * @ring: descriptor ring
1730  * @rx_desc: specific descriptor
1731  * @skb: skb currently being received and modified
1732  * @rx_ptype: Rx packet type
1733  **/
i40e_rx_hash(struct i40e_ring * ring,union i40e_rx_desc * rx_desc,struct sk_buff * skb,u8 rx_ptype)1734 static inline void i40e_rx_hash(struct i40e_ring *ring,
1735 				union i40e_rx_desc *rx_desc,
1736 				struct sk_buff *skb,
1737 				u8 rx_ptype)
1738 {
1739 	u32 hash;
1740 	const __le64 rss_mask =
1741 		cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1742 			    I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1743 
1744 	if (!(ring->netdev->features & NETIF_F_RXHASH))
1745 		return;
1746 
1747 	if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1748 		hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1749 		skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1750 	}
1751 }
1752 
1753 /**
1754  * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
1755  * @rx_ring: rx descriptor ring packet is being transacted on
1756  * @rx_desc: pointer to the EOP Rx descriptor
1757  * @skb: pointer to current skb being populated
1758  *
1759  * This function checks the ring, descriptor, and packet information in
1760  * order to populate the hash, checksum, VLAN, protocol, and
1761  * other fields within the skb.
1762  **/
i40e_process_skb_fields(struct i40e_ring * rx_ring,union i40e_rx_desc * rx_desc,struct sk_buff * skb)1763 void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1764 			     union i40e_rx_desc *rx_desc, struct sk_buff *skb)
1765 {
1766 	u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1767 	u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1768 			I40E_RXD_QW1_STATUS_SHIFT;
1769 	u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
1770 	u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1771 		   I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;
1772 	u8 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1773 		      I40E_RXD_QW1_PTYPE_SHIFT;
1774 
1775 	if (unlikely(tsynvalid))
1776 		i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1777 
1778 	i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1779 
1780 	i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
1781 
1782 	skb_record_rx_queue(skb, rx_ring->queue_index);
1783 
1784 	if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1785 		__le16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;
1786 
1787 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1788 				       le16_to_cpu(vlan_tag));
1789 	}
1790 
1791 	/* modifies the skb - consumes the enet header */
1792 	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1793 }
1794 
1795 /**
1796  * i40e_cleanup_headers - Correct empty headers
1797  * @rx_ring: rx descriptor ring packet is being transacted on
1798  * @skb: pointer to current skb being fixed
1799  * @rx_desc: pointer to the EOP Rx descriptor
1800  *
1801  * Also address the case where we are pulling data in on pages only
1802  * and as such no data is present in the skb header.
1803  *
1804  * In addition if skb is not at least 60 bytes we need to pad it so that
1805  * it is large enough to qualify as a valid Ethernet frame.
1806  *
1807  * Returns true if an error was encountered and skb was freed.
1808  **/
i40e_cleanup_headers(struct i40e_ring * rx_ring,struct sk_buff * skb,union i40e_rx_desc * rx_desc)1809 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb,
1810 				 union i40e_rx_desc *rx_desc)
1811 
1812 {
1813 	/* ERR_MASK will only have valid bits if EOP set, and
1814 	 * what we are doing here is actually checking
1815 	 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1816 	 * the error field
1817 	 */
1818 	if (unlikely(i40e_test_staterr(rx_desc,
1819 				       BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1820 		dev_kfree_skb_any(skb);
1821 		return true;
1822 	}
1823 
1824 	/* if eth_skb_pad returns an error the skb was freed */
1825 	if (eth_skb_pad(skb))
1826 		return true;
1827 
1828 	return false;
1829 }
1830 
1831 /**
1832  * i40e_page_is_reusable - check if any reuse is possible
1833  * @page: page struct to check
1834  *
1835  * A page is not reusable if it was allocated under low memory
1836  * conditions, or it's not in the same NUMA node as this CPU.
1837  */
i40e_page_is_reusable(struct page * page)1838 static inline bool i40e_page_is_reusable(struct page *page)
1839 {
1840 	return (page_to_nid(page) == numa_mem_id()) &&
1841 		!page_is_pfmemalloc(page);
1842 }
1843 
1844 /**
1845  * i40e_can_reuse_rx_page - Determine if this page can be reused by
1846  * the adapter for another receive
1847  *
1848  * @rx_buffer: buffer containing the page
1849  * @rx_buffer_pgcnt: buffer page refcount pre xdp_do_redirect() call
1850  *
1851  * If page is reusable, rx_buffer->page_offset is adjusted to point to
1852  * an unused region in the page.
1853  *
1854  * For small pages, @truesize will be a constant value, half the size
1855  * of the memory at page.  We'll attempt to alternate between high and
1856  * low halves of the page, with one half ready for use by the hardware
1857  * and the other half being consumed by the stack.  We use the page
1858  * ref count to determine whether the stack has finished consuming the
1859  * portion of this page that was passed up with a previous packet.  If
1860  * the page ref count is >1, we'll assume the "other" half page is
1861  * still busy, and this page cannot be reused.
1862  *
1863  * For larger pages, @truesize will be the actual space used by the
1864  * received packet (adjusted upward to an even multiple of the cache
1865  * line size).  This will advance through the page by the amount
1866  * actually consumed by the received packets while there is still
1867  * space for a buffer.  Each region of larger pages will be used at
1868  * most once, after which the page will not be reused.
1869  *
1870  * In either case, if the page is reusable its refcount is increased.
1871  **/
i40e_can_reuse_rx_page(struct i40e_rx_buffer * rx_buffer,int rx_buffer_pgcnt)1872 static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer,
1873 				   int rx_buffer_pgcnt)
1874 {
1875 	unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1876 	struct page *page = rx_buffer->page;
1877 
1878 	/* Is any reuse possible? */
1879 	if (unlikely(!i40e_page_is_reusable(page)))
1880 		return false;
1881 
1882 #if (PAGE_SIZE < 8192)
1883 	/* if we are only owner of page we can reuse it */
1884 	if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
1885 		return false;
1886 #else
1887 #define I40E_LAST_OFFSET \
1888 	(SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
1889 	if (rx_buffer->page_offset > I40E_LAST_OFFSET)
1890 		return false;
1891 #endif
1892 
1893 	/* If we have drained the page fragment pool we need to update
1894 	 * the pagecnt_bias and page count so that we fully restock the
1895 	 * number of references the driver holds.
1896 	 */
1897 	if (unlikely(pagecnt_bias == 1)) {
1898 		page_ref_add(page, USHRT_MAX - 1);
1899 		rx_buffer->pagecnt_bias = USHRT_MAX;
1900 	}
1901 
1902 	return true;
1903 }
1904 
1905 /**
1906  * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
1907  * @rx_ring: rx descriptor ring to transact packets on
1908  * @rx_buffer: buffer containing page to add
1909  * @skb: sk_buff to place the data into
1910  * @size: packet length from rx_desc
1911  *
1912  * This function will add the data contained in rx_buffer->page to the skb.
1913  * It will just attach the page as a frag to the skb.
1914  *
1915  * The function will then update the page offset.
1916  **/
i40e_add_rx_frag(struct i40e_ring * rx_ring,struct i40e_rx_buffer * rx_buffer,struct sk_buff * skb,unsigned int size)1917 static void i40e_add_rx_frag(struct i40e_ring *rx_ring,
1918 			     struct i40e_rx_buffer *rx_buffer,
1919 			     struct sk_buff *skb,
1920 			     unsigned int size)
1921 {
1922 #if (PAGE_SIZE < 8192)
1923 	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1924 #else
1925 	unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring));
1926 #endif
1927 
1928 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1929 			rx_buffer->page_offset, size, truesize);
1930 
1931 	/* page is being used so we must update the page offset */
1932 #if (PAGE_SIZE < 8192)
1933 	rx_buffer->page_offset ^= truesize;
1934 #else
1935 	rx_buffer->page_offset += truesize;
1936 #endif
1937 }
1938 
1939 /**
1940  * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
1941  * @rx_ring: rx descriptor ring to transact packets on
1942  * @size: size of buffer to add to skb
1943  * @rx_buffer_pgcnt: buffer page refcount
1944  *
1945  * This function will pull an Rx buffer from the ring and synchronize it
1946  * for use by the CPU.
1947  */
i40e_get_rx_buffer(struct i40e_ring * rx_ring,const unsigned int size,int * rx_buffer_pgcnt)1948 static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
1949 						 const unsigned int size,
1950 						 int *rx_buffer_pgcnt)
1951 {
1952 	struct i40e_rx_buffer *rx_buffer;
1953 
1954 	rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
1955 	*rx_buffer_pgcnt =
1956 #if (PAGE_SIZE < 8192)
1957 		page_count(rx_buffer->page);
1958 #else
1959 		0;
1960 #endif
1961 	prefetch_page_address(rx_buffer->page);
1962 
1963 	/* we are reusing so sync this buffer for CPU use */
1964 	dma_sync_single_range_for_cpu(rx_ring->dev,
1965 				      rx_buffer->dma,
1966 				      rx_buffer->page_offset,
1967 				      size,
1968 				      DMA_FROM_DEVICE);
1969 
1970 	/* We have pulled a buffer for use, so decrement pagecnt_bias */
1971 	rx_buffer->pagecnt_bias--;
1972 
1973 	return rx_buffer;
1974 }
1975 
1976 /**
1977  * i40e_construct_skb - Allocate skb and populate it
1978  * @rx_ring: rx descriptor ring to transact packets on
1979  * @rx_buffer: rx buffer to pull data from
1980  * @xdp: xdp_buff pointing to the data
1981  *
1982  * This function allocates an skb.  It then populates it with the page
1983  * data from the current receive descriptor, taking care to set up the
1984  * skb correctly.
1985  */
i40e_construct_skb(struct i40e_ring * rx_ring,struct i40e_rx_buffer * rx_buffer,struct xdp_buff * xdp)1986 static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
1987 					  struct i40e_rx_buffer *rx_buffer,
1988 					  struct xdp_buff *xdp)
1989 {
1990 	unsigned int size = xdp->data_end - xdp->data;
1991 #if (PAGE_SIZE < 8192)
1992 	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1993 #else
1994 	unsigned int truesize = SKB_DATA_ALIGN(size);
1995 #endif
1996 	unsigned int headlen;
1997 	struct sk_buff *skb;
1998 
1999 	/* prefetch first cache line of first page */
2000 	net_prefetch(xdp->data);
2001 
2002 	/* Note, we get here by enabling legacy-rx via:
2003 	 *
2004 	 *    ethtool --set-priv-flags <dev> legacy-rx on
2005 	 *
2006 	 * In this mode, we currently get 0 extra XDP headroom as
2007 	 * opposed to having legacy-rx off, where we process XDP
2008 	 * packets going to stack via i40e_build_skb(). The latter
2009 	 * provides us currently with 192 bytes of headroom.
2010 	 *
2011 	 * For i40e_construct_skb() mode it means that the
2012 	 * xdp->data_meta will always point to xdp->data, since
2013 	 * the helper cannot expand the head. Should this ever
2014 	 * change in future for legacy-rx mode on, then lets also
2015 	 * add xdp->data_meta handling here.
2016 	 */
2017 
2018 	/* allocate a skb to store the frags */
2019 	skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
2020 			       I40E_RX_HDR_SIZE,
2021 			       GFP_ATOMIC | __GFP_NOWARN);
2022 	if (unlikely(!skb))
2023 		return NULL;
2024 
2025 	/* Determine available headroom for copy */
2026 	headlen = size;
2027 	if (headlen > I40E_RX_HDR_SIZE)
2028 		headlen = eth_get_headlen(skb->dev, xdp->data,
2029 					  I40E_RX_HDR_SIZE);
2030 
2031 	/* align pull length to size of long to optimize memcpy performance */
2032 	memcpy(__skb_put(skb, headlen), xdp->data,
2033 	       ALIGN(headlen, sizeof(long)));
2034 
2035 	/* update all of the pointers */
2036 	size -= headlen;
2037 	if (size) {
2038 		skb_add_rx_frag(skb, 0, rx_buffer->page,
2039 				rx_buffer->page_offset + headlen,
2040 				size, truesize);
2041 
2042 		/* buffer is used by skb, update page_offset */
2043 #if (PAGE_SIZE < 8192)
2044 		rx_buffer->page_offset ^= truesize;
2045 #else
2046 		rx_buffer->page_offset += truesize;
2047 #endif
2048 	} else {
2049 		/* buffer is unused, reset bias back to rx_buffer */
2050 		rx_buffer->pagecnt_bias++;
2051 	}
2052 
2053 	return skb;
2054 }
2055 
2056 /**
2057  * i40e_build_skb - Build skb around an existing buffer
2058  * @rx_ring: Rx descriptor ring to transact packets on
2059  * @rx_buffer: Rx buffer to pull data from
2060  * @xdp: xdp_buff pointing to the data
2061  *
2062  * This function builds an skb around an existing Rx buffer, taking care
2063  * to set up the skb correctly and avoid any memcpy overhead.
2064  */
i40e_build_skb(struct i40e_ring * rx_ring,struct i40e_rx_buffer * rx_buffer,struct xdp_buff * xdp)2065 static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
2066 				      struct i40e_rx_buffer *rx_buffer,
2067 				      struct xdp_buff *xdp)
2068 {
2069 	unsigned int metasize = xdp->data - xdp->data_meta;
2070 #if (PAGE_SIZE < 8192)
2071 	unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2072 #else
2073 	unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2074 				SKB_DATA_ALIGN(xdp->data_end -
2075 					       xdp->data_hard_start);
2076 #endif
2077 	struct sk_buff *skb;
2078 
2079 	/* Prefetch first cache line of first page. If xdp->data_meta
2080 	 * is unused, this points exactly as xdp->data, otherwise we
2081 	 * likely have a consumer accessing first few bytes of meta
2082 	 * data, and then actual data.
2083 	 */
2084 	net_prefetch(xdp->data_meta);
2085 
2086 	/* build an skb around the page buffer */
2087 	skb = build_skb(xdp->data_hard_start, truesize);
2088 	if (unlikely(!skb))
2089 		return NULL;
2090 
2091 	/* update pointers within the skb to store the data */
2092 	skb_reserve(skb, xdp->data - xdp->data_hard_start);
2093 	__skb_put(skb, xdp->data_end - xdp->data);
2094 	if (metasize)
2095 		skb_metadata_set(skb, metasize);
2096 
2097 	/* buffer is used by skb, update page_offset */
2098 #if (PAGE_SIZE < 8192)
2099 	rx_buffer->page_offset ^= truesize;
2100 #else
2101 	rx_buffer->page_offset += truesize;
2102 #endif
2103 
2104 	return skb;
2105 }
2106 
2107 /**
2108  * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
2109  * @rx_ring: rx descriptor ring to transact packets on
2110  * @rx_buffer: rx buffer to pull data from
2111  * @rx_buffer_pgcnt: rx buffer page refcount pre xdp_do_redirect() call
2112  *
2113  * This function will clean up the contents of the rx_buffer.  It will
2114  * either recycle the buffer or unmap it and free the associated resources.
2115  */
i40e_put_rx_buffer(struct i40e_ring * rx_ring,struct i40e_rx_buffer * rx_buffer,int rx_buffer_pgcnt)2116 static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
2117 			       struct i40e_rx_buffer *rx_buffer,
2118 			       int rx_buffer_pgcnt)
2119 {
2120 	if (i40e_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
2121 		/* hand second half of page back to the ring */
2122 		i40e_reuse_rx_page(rx_ring, rx_buffer);
2123 	} else {
2124 		/* we are not reusing the buffer so unmap it */
2125 		dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2126 				     i40e_rx_pg_size(rx_ring),
2127 				     DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
2128 		__page_frag_cache_drain(rx_buffer->page,
2129 					rx_buffer->pagecnt_bias);
2130 		/* clear contents of buffer_info */
2131 		rx_buffer->page = NULL;
2132 	}
2133 }
2134 
2135 /**
2136  * i40e_is_non_eop - process handling of non-EOP buffers
2137  * @rx_ring: Rx ring being processed
2138  * @rx_desc: Rx descriptor for current buffer
2139  * @skb: Current socket buffer containing buffer in progress
2140  *
2141  * This function updates next to clean.  If the buffer is an EOP buffer
2142  * this function exits returning false, otherwise it will place the
2143  * sk_buff in the next buffer to be chained and return true indicating
2144  * that this is in fact a non-EOP buffer.
2145  **/
i40e_is_non_eop(struct i40e_ring * rx_ring,union i40e_rx_desc * rx_desc,struct sk_buff * skb)2146 static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
2147 			    union i40e_rx_desc *rx_desc,
2148 			    struct sk_buff *skb)
2149 {
2150 	u32 ntc = rx_ring->next_to_clean + 1;
2151 
2152 	/* fetch, update, and store next to clean */
2153 	ntc = (ntc < rx_ring->count) ? ntc : 0;
2154 	rx_ring->next_to_clean = ntc;
2155 
2156 	prefetch(I40E_RX_DESC(rx_ring, ntc));
2157 
2158 	/* if we are the last buffer then there is nothing else to do */
2159 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
2160 	if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
2161 		return false;
2162 
2163 	rx_ring->rx_stats.non_eop_descs++;
2164 
2165 	return true;
2166 }
2167 
2168 static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
2169 			      struct i40e_ring *xdp_ring);
2170 
i40e_xmit_xdp_tx_ring(struct xdp_buff * xdp,struct i40e_ring * xdp_ring)2171 int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring)
2172 {
2173 	struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2174 
2175 	if (unlikely(!xdpf))
2176 		return I40E_XDP_CONSUMED;
2177 
2178 	return i40e_xmit_xdp_ring(xdpf, xdp_ring);
2179 }
2180 
2181 /**
2182  * i40e_run_xdp - run an XDP program
2183  * @rx_ring: Rx ring being processed
2184  * @xdp: XDP buffer containing the frame
2185  **/
i40e_run_xdp(struct i40e_ring * rx_ring,struct xdp_buff * xdp)2186 static int i40e_run_xdp(struct i40e_ring *rx_ring, struct xdp_buff *xdp)
2187 {
2188 	int err, result = I40E_XDP_PASS;
2189 	struct i40e_ring *xdp_ring;
2190 	struct bpf_prog *xdp_prog;
2191 	u32 act;
2192 
2193 	rcu_read_lock();
2194 	xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2195 
2196 	if (!xdp_prog)
2197 		goto xdp_out;
2198 
2199 	prefetchw(xdp->data_hard_start); /* xdp_frame write */
2200 
2201 	act = bpf_prog_run_xdp(xdp_prog, xdp);
2202 	switch (act) {
2203 	case XDP_PASS:
2204 		break;
2205 	case XDP_TX:
2206 		xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2207 		result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring);
2208 		if (result == I40E_XDP_CONSUMED)
2209 			goto out_failure;
2210 		break;
2211 	case XDP_REDIRECT:
2212 		err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog);
2213 		if (err)
2214 			goto out_failure;
2215 		result = I40E_XDP_REDIR;
2216 		break;
2217 	default:
2218 		bpf_warn_invalid_xdp_action(act);
2219 		fallthrough;
2220 	case XDP_ABORTED:
2221 out_failure:
2222 		trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2223 		fallthrough; /* handle aborts by dropping packet */
2224 	case XDP_DROP:
2225 		result = I40E_XDP_CONSUMED;
2226 		break;
2227 	}
2228 xdp_out:
2229 	rcu_read_unlock();
2230 	return result;
2231 }
2232 
2233 /**
2234  * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region
2235  * @rx_ring: Rx ring
2236  * @rx_buffer: Rx buffer to adjust
2237  * @size: Size of adjustment
2238  **/
i40e_rx_buffer_flip(struct i40e_ring * rx_ring,struct i40e_rx_buffer * rx_buffer,unsigned int size)2239 static void i40e_rx_buffer_flip(struct i40e_ring *rx_ring,
2240 				struct i40e_rx_buffer *rx_buffer,
2241 				unsigned int size)
2242 {
2243 	unsigned int truesize = i40e_rx_frame_truesize(rx_ring, size);
2244 
2245 #if (PAGE_SIZE < 8192)
2246 	rx_buffer->page_offset ^= truesize;
2247 #else
2248 	rx_buffer->page_offset += truesize;
2249 #endif
2250 }
2251 
2252 /**
2253  * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register
2254  * @xdp_ring: XDP Tx ring
2255  *
2256  * This function updates the XDP Tx ring tail register.
2257  **/
i40e_xdp_ring_update_tail(struct i40e_ring * xdp_ring)2258 void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring)
2259 {
2260 	/* Force memory writes to complete before letting h/w
2261 	 * know there are new descriptors to fetch.
2262 	 */
2263 	wmb();
2264 	writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
2265 }
2266 
2267 /**
2268  * i40e_update_rx_stats - Update Rx ring statistics
2269  * @rx_ring: rx descriptor ring
2270  * @total_rx_bytes: number of bytes received
2271  * @total_rx_packets: number of packets received
2272  *
2273  * This function updates the Rx ring statistics.
2274  **/
i40e_update_rx_stats(struct i40e_ring * rx_ring,unsigned int total_rx_bytes,unsigned int total_rx_packets)2275 void i40e_update_rx_stats(struct i40e_ring *rx_ring,
2276 			  unsigned int total_rx_bytes,
2277 			  unsigned int total_rx_packets)
2278 {
2279 	u64_stats_update_begin(&rx_ring->syncp);
2280 	rx_ring->stats.packets += total_rx_packets;
2281 	rx_ring->stats.bytes += total_rx_bytes;
2282 	u64_stats_update_end(&rx_ring->syncp);
2283 	rx_ring->q_vector->rx.total_packets += total_rx_packets;
2284 	rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
2285 }
2286 
2287 /**
2288  * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map
2289  * @rx_ring: Rx ring
2290  * @xdp_res: Result of the receive batch
2291  *
2292  * This function bumps XDP Tx tail and/or flush redirect map, and
2293  * should be called when a batch of packets has been processed in the
2294  * napi loop.
2295  **/
i40e_finalize_xdp_rx(struct i40e_ring * rx_ring,unsigned int xdp_res)2296 void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res)
2297 {
2298 	if (xdp_res & I40E_XDP_REDIR)
2299 		xdp_do_flush_map();
2300 
2301 	if (xdp_res & I40E_XDP_TX) {
2302 		struct i40e_ring *xdp_ring =
2303 			rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2304 
2305 		i40e_xdp_ring_update_tail(xdp_ring);
2306 	}
2307 }
2308 
2309 /**
2310  * i40e_inc_ntc: Advance the next_to_clean index
2311  * @rx_ring: Rx ring
2312  **/
i40e_inc_ntc(struct i40e_ring * rx_ring)2313 static void i40e_inc_ntc(struct i40e_ring *rx_ring)
2314 {
2315 	u32 ntc = rx_ring->next_to_clean + 1;
2316 
2317 	ntc = (ntc < rx_ring->count) ? ntc : 0;
2318 	rx_ring->next_to_clean = ntc;
2319 	prefetch(I40E_RX_DESC(rx_ring, ntc));
2320 }
2321 
2322 /**
2323  * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2324  * @rx_ring: rx descriptor ring to transact packets on
2325  * @budget: Total limit on number of packets to process
2326  *
2327  * This function provides a "bounce buffer" approach to Rx interrupt
2328  * processing.  The advantage to this is that on systems that have
2329  * expensive overhead for IOMMU access this provides a means of avoiding
2330  * it by maintaining the mapping of the page to the system.
2331  *
2332  * Returns amount of work completed
2333  **/
i40e_clean_rx_irq(struct i40e_ring * rx_ring,int budget)2334 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
2335 {
2336 	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2337 	struct sk_buff *skb = rx_ring->skb;
2338 	u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
2339 	unsigned int xdp_xmit = 0;
2340 	bool failure = false;
2341 	struct xdp_buff xdp;
2342 	int xdp_res = 0;
2343 
2344 #if (PAGE_SIZE < 8192)
2345 	xdp.frame_sz = i40e_rx_frame_truesize(rx_ring, 0);
2346 #endif
2347 	xdp.rxq = &rx_ring->xdp_rxq;
2348 
2349 	while (likely(total_rx_packets < (unsigned int)budget)) {
2350 		struct i40e_rx_buffer *rx_buffer;
2351 		union i40e_rx_desc *rx_desc;
2352 		int rx_buffer_pgcnt;
2353 		unsigned int size;
2354 		u64 qword;
2355 
2356 		/* return some buffers to hardware, one at a time is too slow */
2357 		if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
2358 			failure = failure ||
2359 				  i40e_alloc_rx_buffers(rx_ring, cleaned_count);
2360 			cleaned_count = 0;
2361 		}
2362 
2363 		rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
2364 
2365 		/* status_error_len will always be zero for unused descriptors
2366 		 * because it's cleared in cleanup, and overlaps with hdr_addr
2367 		 * which is always zero because packet split isn't used, if the
2368 		 * hardware wrote DD then the length will be non-zero
2369 		 */
2370 		qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2371 
2372 		/* This memory barrier is needed to keep us from reading
2373 		 * any other fields out of the rx_desc until we have
2374 		 * verified the descriptor has been written back.
2375 		 */
2376 		dma_rmb();
2377 
2378 		if (i40e_rx_is_programming_status(qword)) {
2379 			i40e_clean_programming_status(rx_ring,
2380 						      rx_desc->raw.qword[0],
2381 						      qword);
2382 			rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2383 			i40e_inc_ntc(rx_ring);
2384 			i40e_reuse_rx_page(rx_ring, rx_buffer);
2385 			cleaned_count++;
2386 			continue;
2387 		}
2388 
2389 		size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
2390 		       I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
2391 		if (!size)
2392 			break;
2393 
2394 		i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb);
2395 		rx_buffer = i40e_get_rx_buffer(rx_ring, size, &rx_buffer_pgcnt);
2396 
2397 		/* retrieve a buffer from the ring */
2398 		if (!skb) {
2399 			xdp.data = page_address(rx_buffer->page) +
2400 				   rx_buffer->page_offset;
2401 			xdp.data_meta = xdp.data;
2402 			xdp.data_hard_start = xdp.data -
2403 					      i40e_rx_offset(rx_ring);
2404 			xdp.data_end = xdp.data + size;
2405 #if (PAGE_SIZE > 4096)
2406 			/* At larger PAGE_SIZE, frame_sz depend on len size */
2407 			xdp.frame_sz = i40e_rx_frame_truesize(rx_ring, size);
2408 #endif
2409 			xdp_res = i40e_run_xdp(rx_ring, &xdp);
2410 		}
2411 
2412 		if (xdp_res) {
2413 			if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) {
2414 				xdp_xmit |= xdp_res;
2415 				i40e_rx_buffer_flip(rx_ring, rx_buffer, size);
2416 			} else {
2417 				rx_buffer->pagecnt_bias++;
2418 			}
2419 			total_rx_bytes += size;
2420 			total_rx_packets++;
2421 		} else if (skb) {
2422 			i40e_add_rx_frag(rx_ring, rx_buffer, skb, size);
2423 		} else if (ring_uses_build_skb(rx_ring)) {
2424 			skb = i40e_build_skb(rx_ring, rx_buffer, &xdp);
2425 		} else {
2426 			skb = i40e_construct_skb(rx_ring, rx_buffer, &xdp);
2427 		}
2428 
2429 		/* exit if we failed to retrieve a buffer */
2430 		if (!xdp_res && !skb) {
2431 			rx_ring->rx_stats.alloc_buff_failed++;
2432 			rx_buffer->pagecnt_bias++;
2433 			break;
2434 		}
2435 
2436 		i40e_put_rx_buffer(rx_ring, rx_buffer, rx_buffer_pgcnt);
2437 		cleaned_count++;
2438 
2439 		if (i40e_is_non_eop(rx_ring, rx_desc, skb))
2440 			continue;
2441 
2442 		if (xdp_res || i40e_cleanup_headers(rx_ring, skb, rx_desc)) {
2443 			skb = NULL;
2444 			continue;
2445 		}
2446 
2447 		/* probably a little skewed due to removing CRC */
2448 		total_rx_bytes += skb->len;
2449 
2450 		/* populate checksum, VLAN, and protocol */
2451 		i40e_process_skb_fields(rx_ring, rx_desc, skb);
2452 
2453 		i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
2454 		napi_gro_receive(&rx_ring->q_vector->napi, skb);
2455 		skb = NULL;
2456 
2457 		/* update budget accounting */
2458 		total_rx_packets++;
2459 	}
2460 
2461 	i40e_finalize_xdp_rx(rx_ring, xdp_xmit);
2462 	rx_ring->skb = skb;
2463 
2464 	i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets);
2465 
2466 	/* guarantee a trip back through this routine if there was a failure */
2467 	return failure ? budget : (int)total_rx_packets;
2468 }
2469 
i40e_buildreg_itr(const int type,u16 itr)2470 static inline u32 i40e_buildreg_itr(const int type, u16 itr)
2471 {
2472 	u32 val;
2473 
2474 	/* We don't bother with setting the CLEARPBA bit as the data sheet
2475 	 * points out doing so is "meaningless since it was already
2476 	 * auto-cleared". The auto-clearing happens when the interrupt is
2477 	 * asserted.
2478 	 *
2479 	 * Hardware errata 28 for also indicates that writing to a
2480 	 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
2481 	 * an event in the PBA anyway so we need to rely on the automask
2482 	 * to hold pending events for us until the interrupt is re-enabled
2483 	 *
2484 	 * The itr value is reported in microseconds, and the register
2485 	 * value is recorded in 2 microsecond units. For this reason we
2486 	 * only need to shift by the interval shift - 1 instead of the
2487 	 * full value.
2488 	 */
2489 	itr &= I40E_ITR_MASK;
2490 
2491 	val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2492 	      (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
2493 	      (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1));
2494 
2495 	return val;
2496 }
2497 
2498 /* a small macro to shorten up some long lines */
2499 #define INTREG I40E_PFINT_DYN_CTLN
2500 
2501 /* The act of updating the ITR will cause it to immediately trigger. In order
2502  * to prevent this from throwing off adaptive update statistics we defer the
2503  * update so that it can only happen so often. So after either Tx or Rx are
2504  * updated we make the adaptive scheme wait until either the ITR completely
2505  * expires via the next_update expiration or we have been through at least
2506  * 3 interrupts.
2507  */
2508 #define ITR_COUNTDOWN_START 3
2509 
2510 /**
2511  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
2512  * @vsi: the VSI we care about
2513  * @q_vector: q_vector for which itr is being updated and interrupt enabled
2514  *
2515  **/
i40e_update_enable_itr(struct i40e_vsi * vsi,struct i40e_q_vector * q_vector)2516 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
2517 					  struct i40e_q_vector *q_vector)
2518 {
2519 	struct i40e_hw *hw = &vsi->back->hw;
2520 	u32 intval;
2521 
2522 	/* If we don't have MSIX, then we only need to re-enable icr0 */
2523 	if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {
2524 		i40e_irq_dynamic_enable_icr0(vsi->back);
2525 		return;
2526 	}
2527 
2528 	/* These will do nothing if dynamic updates are not enabled */
2529 	i40e_update_itr(q_vector, &q_vector->tx);
2530 	i40e_update_itr(q_vector, &q_vector->rx);
2531 
2532 	/* This block of logic allows us to get away with only updating
2533 	 * one ITR value with each interrupt. The idea is to perform a
2534 	 * pseudo-lazy update with the following criteria.
2535 	 *
2536 	 * 1. Rx is given higher priority than Tx if both are in same state
2537 	 * 2. If we must reduce an ITR that is given highest priority.
2538 	 * 3. We then give priority to increasing ITR based on amount.
2539 	 */
2540 	if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
2541 		/* Rx ITR needs to be reduced, this is highest priority */
2542 		intval = i40e_buildreg_itr(I40E_RX_ITR,
2543 					   q_vector->rx.target_itr);
2544 		q_vector->rx.current_itr = q_vector->rx.target_itr;
2545 		q_vector->itr_countdown = ITR_COUNTDOWN_START;
2546 	} else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
2547 		   ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
2548 		    (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
2549 		/* Tx ITR needs to be reduced, this is second priority
2550 		 * Tx ITR needs to be increased more than Rx, fourth priority
2551 		 */
2552 		intval = i40e_buildreg_itr(I40E_TX_ITR,
2553 					   q_vector->tx.target_itr);
2554 		q_vector->tx.current_itr = q_vector->tx.target_itr;
2555 		q_vector->itr_countdown = ITR_COUNTDOWN_START;
2556 	} else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
2557 		/* Rx ITR needs to be increased, third priority */
2558 		intval = i40e_buildreg_itr(I40E_RX_ITR,
2559 					   q_vector->rx.target_itr);
2560 		q_vector->rx.current_itr = q_vector->rx.target_itr;
2561 		q_vector->itr_countdown = ITR_COUNTDOWN_START;
2562 	} else {
2563 		/* No ITR update, lowest priority */
2564 		intval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
2565 		if (q_vector->itr_countdown)
2566 			q_vector->itr_countdown--;
2567 	}
2568 
2569 	if (!test_bit(__I40E_VSI_DOWN, vsi->state))
2570 		wr32(hw, INTREG(q_vector->reg_idx), intval);
2571 }
2572 
2573 /**
2574  * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
2575  * @napi: napi struct with our devices info in it
2576  * @budget: amount of work driver is allowed to do this pass, in packets
2577  *
2578  * This function will clean all queues associated with a q_vector.
2579  *
2580  * Returns the amount of work done
2581  **/
i40e_napi_poll(struct napi_struct * napi,int budget)2582 int i40e_napi_poll(struct napi_struct *napi, int budget)
2583 {
2584 	struct i40e_q_vector *q_vector =
2585 			       container_of(napi, struct i40e_q_vector, napi);
2586 	struct i40e_vsi *vsi = q_vector->vsi;
2587 	struct i40e_ring *ring;
2588 	bool clean_complete = true;
2589 	bool arm_wb = false;
2590 	int budget_per_ring;
2591 	int work_done = 0;
2592 
2593 	if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
2594 		napi_complete(napi);
2595 		return 0;
2596 	}
2597 
2598 	/* Since the actual Tx work is minimal, we can give the Tx a larger
2599 	 * budget and be more aggressive about cleaning up the Tx descriptors.
2600 	 */
2601 	i40e_for_each_ring(ring, q_vector->tx) {
2602 		bool wd = ring->xsk_pool ?
2603 			  i40e_clean_xdp_tx_irq(vsi, ring) :
2604 			  i40e_clean_tx_irq(vsi, ring, budget);
2605 
2606 		if (!wd) {
2607 			clean_complete = false;
2608 			continue;
2609 		}
2610 		arm_wb |= ring->arm_wb;
2611 		ring->arm_wb = false;
2612 	}
2613 
2614 	/* Handle case where we are called by netpoll with a budget of 0 */
2615 	if (budget <= 0)
2616 		goto tx_only;
2617 
2618 	/* normally we have 1 Rx ring per q_vector */
2619 	if (unlikely(q_vector->num_ringpairs > 1))
2620 		/* We attempt to distribute budget to each Rx queue fairly, but
2621 		 * don't allow the budget to go below 1 because that would exit
2622 		 * polling early.
2623 		 */
2624 		budget_per_ring = max_t(int, budget / q_vector->num_ringpairs, 1);
2625 	else
2626 		/* Max of 1 Rx ring in this q_vector so give it the budget */
2627 		budget_per_ring = budget;
2628 
2629 	i40e_for_each_ring(ring, q_vector->rx) {
2630 		int cleaned = ring->xsk_pool ?
2631 			      i40e_clean_rx_irq_zc(ring, budget_per_ring) :
2632 			      i40e_clean_rx_irq(ring, budget_per_ring);
2633 
2634 		work_done += cleaned;
2635 		/* if we clean as many as budgeted, we must not be done */
2636 		if (cleaned >= budget_per_ring)
2637 			clean_complete = false;
2638 	}
2639 
2640 	/* If work not completed, return budget and polling will return */
2641 	if (!clean_complete) {
2642 		int cpu_id = smp_processor_id();
2643 
2644 		/* It is possible that the interrupt affinity has changed but,
2645 		 * if the cpu is pegged at 100%, polling will never exit while
2646 		 * traffic continues and the interrupt will be stuck on this
2647 		 * cpu.  We check to make sure affinity is correct before we
2648 		 * continue to poll, otherwise we must stop polling so the
2649 		 * interrupt can move to the correct cpu.
2650 		 */
2651 		if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
2652 			/* Tell napi that we are done polling */
2653 			napi_complete_done(napi, work_done);
2654 
2655 			/* Force an interrupt */
2656 			i40e_force_wb(vsi, q_vector);
2657 
2658 			/* Return budget-1 so that polling stops */
2659 			return budget - 1;
2660 		}
2661 tx_only:
2662 		if (arm_wb) {
2663 			q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2664 			i40e_enable_wb_on_itr(vsi, q_vector);
2665 		}
2666 		return budget;
2667 	}
2668 
2669 	if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
2670 		q_vector->arm_wb_state = false;
2671 
2672 	/* Exit the polling mode, but don't re-enable interrupts if stack might
2673 	 * poll us due to busy-polling
2674 	 */
2675 	if (likely(napi_complete_done(napi, work_done)))
2676 		i40e_update_enable_itr(vsi, q_vector);
2677 
2678 	return min(work_done, budget - 1);
2679 }
2680 
2681 /**
2682  * i40e_atr - Add a Flow Director ATR filter
2683  * @tx_ring:  ring to add programming descriptor to
2684  * @skb:      send buffer
2685  * @tx_flags: send tx flags
2686  **/
i40e_atr(struct i40e_ring * tx_ring,struct sk_buff * skb,u32 tx_flags)2687 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2688 		     u32 tx_flags)
2689 {
2690 	struct i40e_filter_program_desc *fdir_desc;
2691 	struct i40e_pf *pf = tx_ring->vsi->back;
2692 	union {
2693 		unsigned char *network;
2694 		struct iphdr *ipv4;
2695 		struct ipv6hdr *ipv6;
2696 	} hdr;
2697 	struct tcphdr *th;
2698 	unsigned int hlen;
2699 	u32 flex_ptype, dtype_cmd;
2700 	int l4_proto;
2701 	u16 i;
2702 
2703 	/* make sure ATR is enabled */
2704 	if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2705 		return;
2706 
2707 	if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2708 		return;
2709 
2710 	/* if sampling is disabled do nothing */
2711 	if (!tx_ring->atr_sample_rate)
2712 		return;
2713 
2714 	/* Currently only IPv4/IPv6 with TCP is supported */
2715 	if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2716 		return;
2717 
2718 	/* snag network header to get L4 type and address */
2719 	hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2720 		      skb_inner_network_header(skb) : skb_network_header(skb);
2721 
2722 	/* Note: tx_flags gets modified to reflect inner protocols in
2723 	 * tx_enable_csum function if encap is enabled.
2724 	 */
2725 	if (tx_flags & I40E_TX_FLAGS_IPV4) {
2726 		/* access ihl as u8 to avoid unaligned access on ia64 */
2727 		hlen = (hdr.network[0] & 0x0F) << 2;
2728 		l4_proto = hdr.ipv4->protocol;
2729 	} else {
2730 		/* find the start of the innermost ipv6 header */
2731 		unsigned int inner_hlen = hdr.network - skb->data;
2732 		unsigned int h_offset = inner_hlen;
2733 
2734 		/* this function updates h_offset to the end of the header */
2735 		l4_proto =
2736 		  ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL);
2737 		/* hlen will contain our best estimate of the tcp header */
2738 		hlen = h_offset - inner_hlen;
2739 	}
2740 
2741 	if (l4_proto != IPPROTO_TCP)
2742 		return;
2743 
2744 	th = (struct tcphdr *)(hdr.network + hlen);
2745 
2746 	/* Due to lack of space, no more new filters can be programmed */
2747 	if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2748 		return;
2749 	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) {
2750 		/* HW ATR eviction will take care of removing filters on FIN
2751 		 * and RST packets.
2752 		 */
2753 		if (th->fin || th->rst)
2754 			return;
2755 	}
2756 
2757 	tx_ring->atr_count++;
2758 
2759 	/* sample on all syn/fin/rst packets or once every atr sample rate */
2760 	if (!th->fin &&
2761 	    !th->syn &&
2762 	    !th->rst &&
2763 	    (tx_ring->atr_count < tx_ring->atr_sample_rate))
2764 		return;
2765 
2766 	tx_ring->atr_count = 0;
2767 
2768 	/* grab the next descriptor */
2769 	i = tx_ring->next_to_use;
2770 	fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2771 
2772 	i++;
2773 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2774 
2775 	flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2776 		      I40E_TXD_FLTR_QW0_QINDEX_MASK;
2777 	flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2778 		      (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2779 		       I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2780 		      (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2781 		       I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2782 
2783 	flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2784 
2785 	dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2786 
2787 	dtype_cmd |= (th->fin || th->rst) ?
2788 		     (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2789 		      I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2790 		     (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2791 		      I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2792 
2793 	dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2794 		     I40E_TXD_FLTR_QW1_DEST_SHIFT;
2795 
2796 	dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2797 		     I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2798 
2799 	dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2800 	if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2801 		dtype_cmd |=
2802 			((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2803 			I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2804 			I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2805 	else
2806 		dtype_cmd |=
2807 			((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2808 			I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2809 			I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2810 
2811 	if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED)
2812 		dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2813 
2814 	fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2815 	fdir_desc->rsvd = cpu_to_le32(0);
2816 	fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2817 	fdir_desc->fd_id = cpu_to_le32(0);
2818 }
2819 
2820 /**
2821  * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2822  * @skb:     send buffer
2823  * @tx_ring: ring to send buffer on
2824  * @flags:   the tx flags to be set
2825  *
2826  * Checks the skb and set up correspondingly several generic transmit flags
2827  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2828  *
2829  * Returns error code indicate the frame should be dropped upon error and the
2830  * otherwise  returns 0 to indicate the flags has been set properly.
2831  **/
i40e_tx_prepare_vlan_flags(struct sk_buff * skb,struct i40e_ring * tx_ring,u32 * flags)2832 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2833 					     struct i40e_ring *tx_ring,
2834 					     u32 *flags)
2835 {
2836 	__be16 protocol = skb->protocol;
2837 	u32  tx_flags = 0;
2838 
2839 	if (protocol == htons(ETH_P_8021Q) &&
2840 	    !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2841 		/* When HW VLAN acceleration is turned off by the user the
2842 		 * stack sets the protocol to 8021q so that the driver
2843 		 * can take any steps required to support the SW only
2844 		 * VLAN handling.  In our case the driver doesn't need
2845 		 * to take any further steps so just set the protocol
2846 		 * to the encapsulated ethertype.
2847 		 */
2848 		skb->protocol = vlan_get_protocol(skb);
2849 		goto out;
2850 	}
2851 
2852 	/* if we have a HW VLAN tag being added, default to the HW one */
2853 	if (skb_vlan_tag_present(skb)) {
2854 		tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2855 		tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2856 	/* else if it is a SW VLAN, check the next protocol and store the tag */
2857 	} else if (protocol == htons(ETH_P_8021Q)) {
2858 		struct vlan_hdr *vhdr, _vhdr;
2859 
2860 		vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2861 		if (!vhdr)
2862 			return -EINVAL;
2863 
2864 		protocol = vhdr->h_vlan_encapsulated_proto;
2865 		tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2866 		tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2867 	}
2868 
2869 	if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2870 		goto out;
2871 
2872 	/* Insert 802.1p priority into VLAN header */
2873 	if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2874 	    (skb->priority != TC_PRIO_CONTROL)) {
2875 		tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2876 		tx_flags |= (skb->priority & 0x7) <<
2877 				I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2878 		if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2879 			struct vlan_ethhdr *vhdr;
2880 			int rc;
2881 
2882 			rc = skb_cow_head(skb, 0);
2883 			if (rc < 0)
2884 				return rc;
2885 			vhdr = (struct vlan_ethhdr *)skb->data;
2886 			vhdr->h_vlan_TCI = htons(tx_flags >>
2887 						 I40E_TX_FLAGS_VLAN_SHIFT);
2888 		} else {
2889 			tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2890 		}
2891 	}
2892 
2893 out:
2894 	*flags = tx_flags;
2895 	return 0;
2896 }
2897 
2898 /**
2899  * i40e_tso - set up the tso context descriptor
2900  * @first:    pointer to first Tx buffer for xmit
2901  * @hdr_len:  ptr to the size of the packet header
2902  * @cd_type_cmd_tso_mss: Quad Word 1
2903  *
2904  * Returns 0 if no TSO can happen, 1 if tso is going, or error
2905  **/
i40e_tso(struct i40e_tx_buffer * first,u8 * hdr_len,u64 * cd_type_cmd_tso_mss)2906 static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
2907 		    u64 *cd_type_cmd_tso_mss)
2908 {
2909 	struct sk_buff *skb = first->skb;
2910 	u64 cd_cmd, cd_tso_len, cd_mss;
2911 	union {
2912 		struct iphdr *v4;
2913 		struct ipv6hdr *v6;
2914 		unsigned char *hdr;
2915 	} ip;
2916 	union {
2917 		struct tcphdr *tcp;
2918 		struct udphdr *udp;
2919 		unsigned char *hdr;
2920 	} l4;
2921 	u32 paylen, l4_offset;
2922 	u16 gso_segs, gso_size;
2923 	int err;
2924 
2925 	if (skb->ip_summed != CHECKSUM_PARTIAL)
2926 		return 0;
2927 
2928 	if (!skb_is_gso(skb))
2929 		return 0;
2930 
2931 	err = skb_cow_head(skb, 0);
2932 	if (err < 0)
2933 		return err;
2934 
2935 	ip.hdr = skb_network_header(skb);
2936 	l4.hdr = skb_transport_header(skb);
2937 
2938 	/* initialize outer IP header fields */
2939 	if (ip.v4->version == 4) {
2940 		ip.v4->tot_len = 0;
2941 		ip.v4->check = 0;
2942 	} else {
2943 		ip.v6->payload_len = 0;
2944 	}
2945 
2946 	if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
2947 					 SKB_GSO_GRE_CSUM |
2948 					 SKB_GSO_IPXIP4 |
2949 					 SKB_GSO_IPXIP6 |
2950 					 SKB_GSO_UDP_TUNNEL |
2951 					 SKB_GSO_UDP_TUNNEL_CSUM)) {
2952 		if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
2953 		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
2954 			l4.udp->len = 0;
2955 
2956 			/* determine offset of outer transport header */
2957 			l4_offset = l4.hdr - skb->data;
2958 
2959 			/* remove payload length from outer checksum */
2960 			paylen = skb->len - l4_offset;
2961 			csum_replace_by_diff(&l4.udp->check,
2962 					     (__force __wsum)htonl(paylen));
2963 		}
2964 
2965 		/* reset pointers to inner headers */
2966 		ip.hdr = skb_inner_network_header(skb);
2967 		l4.hdr = skb_inner_transport_header(skb);
2968 
2969 		/* initialize inner IP header fields */
2970 		if (ip.v4->version == 4) {
2971 			ip.v4->tot_len = 0;
2972 			ip.v4->check = 0;
2973 		} else {
2974 			ip.v6->payload_len = 0;
2975 		}
2976 	}
2977 
2978 	/* determine offset of inner transport header */
2979 	l4_offset = l4.hdr - skb->data;
2980 
2981 	/* remove payload length from inner checksum */
2982 	paylen = skb->len - l4_offset;
2983 
2984 	if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
2985 		csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen));
2986 		/* compute length of segmentation header */
2987 		*hdr_len = sizeof(*l4.udp) + l4_offset;
2988 	} else {
2989 		csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
2990 		/* compute length of segmentation header */
2991 		*hdr_len = (l4.tcp->doff * 4) + l4_offset;
2992 	}
2993 
2994 	/* pull values out of skb_shinfo */
2995 	gso_size = skb_shinfo(skb)->gso_size;
2996 	gso_segs = skb_shinfo(skb)->gso_segs;
2997 
2998 	/* update GSO size and bytecount with header size */
2999 	first->gso_segs = gso_segs;
3000 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
3001 
3002 	/* find the field values */
3003 	cd_cmd = I40E_TX_CTX_DESC_TSO;
3004 	cd_tso_len = skb->len - *hdr_len;
3005 	cd_mss = gso_size;
3006 	*cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
3007 				(cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
3008 				(cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
3009 	return 1;
3010 }
3011 
3012 /**
3013  * i40e_tsyn - set up the tsyn context descriptor
3014  * @tx_ring:  ptr to the ring to send
3015  * @skb:      ptr to the skb we're sending
3016  * @tx_flags: the collected send information
3017  * @cd_type_cmd_tso_mss: Quad Word 1
3018  *
3019  * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
3020  **/
i40e_tsyn(struct i40e_ring * tx_ring,struct sk_buff * skb,u32 tx_flags,u64 * cd_type_cmd_tso_mss)3021 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
3022 		     u32 tx_flags, u64 *cd_type_cmd_tso_mss)
3023 {
3024 	struct i40e_pf *pf;
3025 
3026 	if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
3027 		return 0;
3028 
3029 	/* Tx timestamps cannot be sampled when doing TSO */
3030 	if (tx_flags & I40E_TX_FLAGS_TSO)
3031 		return 0;
3032 
3033 	/* only timestamp the outbound packet if the user has requested it and
3034 	 * we are not already transmitting a packet to be timestamped
3035 	 */
3036 	pf = i40e_netdev_to_pf(tx_ring->netdev);
3037 	if (!(pf->flags & I40E_FLAG_PTP))
3038 		return 0;
3039 
3040 	if (pf->ptp_tx &&
3041 	    !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) {
3042 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3043 		pf->ptp_tx_start = jiffies;
3044 		pf->ptp_tx_skb = skb_get(skb);
3045 	} else {
3046 		pf->tx_hwtstamp_skipped++;
3047 		return 0;
3048 	}
3049 
3050 	*cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
3051 				I40E_TXD_CTX_QW1_CMD_SHIFT;
3052 
3053 	return 1;
3054 }
3055 
3056 /**
3057  * i40e_tx_enable_csum - Enable Tx checksum offloads
3058  * @skb: send buffer
3059  * @tx_flags: pointer to Tx flags currently set
3060  * @td_cmd: Tx descriptor command bits to set
3061  * @td_offset: Tx descriptor header offsets to set
3062  * @tx_ring: Tx descriptor ring
3063  * @cd_tunneling: ptr to context desc bits
3064  **/
i40e_tx_enable_csum(struct sk_buff * skb,u32 * tx_flags,u32 * td_cmd,u32 * td_offset,struct i40e_ring * tx_ring,u32 * cd_tunneling)3065 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
3066 			       u32 *td_cmd, u32 *td_offset,
3067 			       struct i40e_ring *tx_ring,
3068 			       u32 *cd_tunneling)
3069 {
3070 	union {
3071 		struct iphdr *v4;
3072 		struct ipv6hdr *v6;
3073 		unsigned char *hdr;
3074 	} ip;
3075 	union {
3076 		struct tcphdr *tcp;
3077 		struct udphdr *udp;
3078 		unsigned char *hdr;
3079 	} l4;
3080 	unsigned char *exthdr;
3081 	u32 offset, cmd = 0;
3082 	__be16 frag_off;
3083 	u8 l4_proto = 0;
3084 
3085 	if (skb->ip_summed != CHECKSUM_PARTIAL)
3086 		return 0;
3087 
3088 	ip.hdr = skb_network_header(skb);
3089 	l4.hdr = skb_transport_header(skb);
3090 
3091 	/* compute outer L2 header size */
3092 	offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
3093 
3094 	if (skb->encapsulation) {
3095 		u32 tunnel = 0;
3096 		/* define outer network header type */
3097 		if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3098 			tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3099 				  I40E_TX_CTX_EXT_IP_IPV4 :
3100 				  I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
3101 
3102 			l4_proto = ip.v4->protocol;
3103 		} else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3104 			int ret;
3105 
3106 			tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
3107 
3108 			exthdr = ip.hdr + sizeof(*ip.v6);
3109 			l4_proto = ip.v6->nexthdr;
3110 			ret = ipv6_skip_exthdr(skb, exthdr - skb->data,
3111 					       &l4_proto, &frag_off);
3112 			if (ret < 0)
3113 				return -1;
3114 		}
3115 
3116 		/* define outer transport */
3117 		switch (l4_proto) {
3118 		case IPPROTO_UDP:
3119 			tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
3120 			*tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3121 			break;
3122 		case IPPROTO_GRE:
3123 			tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
3124 			*tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3125 			break;
3126 		case IPPROTO_IPIP:
3127 		case IPPROTO_IPV6:
3128 			*tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3129 			l4.hdr = skb_inner_network_header(skb);
3130 			break;
3131 		default:
3132 			if (*tx_flags & I40E_TX_FLAGS_TSO)
3133 				return -1;
3134 
3135 			skb_checksum_help(skb);
3136 			return 0;
3137 		}
3138 
3139 		/* compute outer L3 header size */
3140 		tunnel |= ((l4.hdr - ip.hdr) / 4) <<
3141 			  I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
3142 
3143 		/* switch IP header pointer from outer to inner header */
3144 		ip.hdr = skb_inner_network_header(skb);
3145 
3146 		/* compute tunnel header size */
3147 		tunnel |= ((ip.hdr - l4.hdr) / 2) <<
3148 			  I40E_TXD_CTX_QW0_NATLEN_SHIFT;
3149 
3150 		/* indicate if we need to offload outer UDP header */
3151 		if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
3152 		    !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3153 		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
3154 			tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
3155 
3156 		/* record tunnel offload values */
3157 		*cd_tunneling |= tunnel;
3158 
3159 		/* switch L4 header pointer from outer to inner */
3160 		l4.hdr = skb_inner_transport_header(skb);
3161 		l4_proto = 0;
3162 
3163 		/* reset type as we transition from outer to inner headers */
3164 		*tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
3165 		if (ip.v4->version == 4)
3166 			*tx_flags |= I40E_TX_FLAGS_IPV4;
3167 		if (ip.v6->version == 6)
3168 			*tx_flags |= I40E_TX_FLAGS_IPV6;
3169 	}
3170 
3171 	/* Enable IP checksum offloads */
3172 	if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3173 		l4_proto = ip.v4->protocol;
3174 		/* the stack computes the IP header already, the only time we
3175 		 * need the hardware to recompute it is in the case of TSO.
3176 		 */
3177 		cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3178 		       I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
3179 		       I40E_TX_DESC_CMD_IIPT_IPV4;
3180 	} else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3181 		cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
3182 
3183 		exthdr = ip.hdr + sizeof(*ip.v6);
3184 		l4_proto = ip.v6->nexthdr;
3185 		if (l4.hdr != exthdr)
3186 			ipv6_skip_exthdr(skb, exthdr - skb->data,
3187 					 &l4_proto, &frag_off);
3188 	}
3189 
3190 	/* compute inner L3 header size */
3191 	offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
3192 
3193 	/* Enable L4 checksum offloads */
3194 	switch (l4_proto) {
3195 	case IPPROTO_TCP:
3196 		/* enable checksum offloads */
3197 		cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
3198 		offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3199 		break;
3200 	case IPPROTO_SCTP:
3201 		/* enable SCTP checksum offload */
3202 		cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
3203 		offset |= (sizeof(struct sctphdr) >> 2) <<
3204 			  I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3205 		break;
3206 	case IPPROTO_UDP:
3207 		/* enable UDP checksum offload */
3208 		cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
3209 		offset |= (sizeof(struct udphdr) >> 2) <<
3210 			  I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3211 		break;
3212 	default:
3213 		if (*tx_flags & I40E_TX_FLAGS_TSO)
3214 			return -1;
3215 		skb_checksum_help(skb);
3216 		return 0;
3217 	}
3218 
3219 	*td_cmd |= cmd;
3220 	*td_offset |= offset;
3221 
3222 	return 1;
3223 }
3224 
3225 /**
3226  * i40e_create_tx_ctx Build the Tx context descriptor
3227  * @tx_ring:  ring to create the descriptor on
3228  * @cd_type_cmd_tso_mss: Quad Word 1
3229  * @cd_tunneling: Quad Word 0 - bits 0-31
3230  * @cd_l2tag2: Quad Word 0 - bits 32-63
3231  **/
i40e_create_tx_ctx(struct i40e_ring * tx_ring,const u64 cd_type_cmd_tso_mss,const u32 cd_tunneling,const u32 cd_l2tag2)3232 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
3233 			       const u64 cd_type_cmd_tso_mss,
3234 			       const u32 cd_tunneling, const u32 cd_l2tag2)
3235 {
3236 	struct i40e_tx_context_desc *context_desc;
3237 	int i = tx_ring->next_to_use;
3238 
3239 	if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
3240 	    !cd_tunneling && !cd_l2tag2)
3241 		return;
3242 
3243 	/* grab the next descriptor */
3244 	context_desc = I40E_TX_CTXTDESC(tx_ring, i);
3245 
3246 	i++;
3247 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3248 
3249 	/* cpu_to_le32 and assign to struct fields */
3250 	context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
3251 	context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3252 	context_desc->rsvd = cpu_to_le16(0);
3253 	context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
3254 }
3255 
3256 /**
3257  * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
3258  * @tx_ring: the ring to be checked
3259  * @size:    the size buffer we want to assure is available
3260  *
3261  * Returns -EBUSY if a stop is needed, else 0
3262  **/
__i40e_maybe_stop_tx(struct i40e_ring * tx_ring,int size)3263 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
3264 {
3265 	netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
3266 	/* Memory barrier before checking head and tail */
3267 	smp_mb();
3268 
3269 	/* Check again in a case another CPU has just made room available. */
3270 	if (likely(I40E_DESC_UNUSED(tx_ring) < size))
3271 		return -EBUSY;
3272 
3273 	/* A reprieve! - use start_queue because it doesn't call schedule */
3274 	netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
3275 	++tx_ring->tx_stats.restart_queue;
3276 	return 0;
3277 }
3278 
3279 /**
3280  * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
3281  * @skb:      send buffer
3282  *
3283  * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
3284  * and so we need to figure out the cases where we need to linearize the skb.
3285  *
3286  * For TSO we need to count the TSO header and segment payload separately.
3287  * As such we need to check cases where we have 7 fragments or more as we
3288  * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
3289  * the segment payload in the first descriptor, and another 7 for the
3290  * fragments.
3291  **/
__i40e_chk_linearize(struct sk_buff * skb)3292 bool __i40e_chk_linearize(struct sk_buff *skb)
3293 {
3294 	const skb_frag_t *frag, *stale;
3295 	int nr_frags, sum;
3296 
3297 	/* no need to check if number of frags is less than 7 */
3298 	nr_frags = skb_shinfo(skb)->nr_frags;
3299 	if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
3300 		return false;
3301 
3302 	/* We need to walk through the list and validate that each group
3303 	 * of 6 fragments totals at least gso_size.
3304 	 */
3305 	nr_frags -= I40E_MAX_BUFFER_TXD - 2;
3306 	frag = &skb_shinfo(skb)->frags[0];
3307 
3308 	/* Initialize size to the negative value of gso_size minus 1.  We
3309 	 * use this as the worst case scenerio in which the frag ahead
3310 	 * of us only provides one byte which is why we are limited to 6
3311 	 * descriptors for a single transmit as the header and previous
3312 	 * fragment are already consuming 2 descriptors.
3313 	 */
3314 	sum = 1 - skb_shinfo(skb)->gso_size;
3315 
3316 	/* Add size of frags 0 through 4 to create our initial sum */
3317 	sum += skb_frag_size(frag++);
3318 	sum += skb_frag_size(frag++);
3319 	sum += skb_frag_size(frag++);
3320 	sum += skb_frag_size(frag++);
3321 	sum += skb_frag_size(frag++);
3322 
3323 	/* Walk through fragments adding latest fragment, testing it, and
3324 	 * then removing stale fragments from the sum.
3325 	 */
3326 	for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
3327 		int stale_size = skb_frag_size(stale);
3328 
3329 		sum += skb_frag_size(frag++);
3330 
3331 		/* The stale fragment may present us with a smaller
3332 		 * descriptor than the actual fragment size. To account
3333 		 * for that we need to remove all the data on the front and
3334 		 * figure out what the remainder would be in the last
3335 		 * descriptor associated with the fragment.
3336 		 */
3337 		if (stale_size > I40E_MAX_DATA_PER_TXD) {
3338 			int align_pad = -(skb_frag_off(stale)) &
3339 					(I40E_MAX_READ_REQ_SIZE - 1);
3340 
3341 			sum -= align_pad;
3342 			stale_size -= align_pad;
3343 
3344 			do {
3345 				sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3346 				stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3347 			} while (stale_size > I40E_MAX_DATA_PER_TXD);
3348 		}
3349 
3350 		/* if sum is negative we failed to make sufficient progress */
3351 		if (sum < 0)
3352 			return true;
3353 
3354 		if (!nr_frags--)
3355 			break;
3356 
3357 		sum -= stale_size;
3358 	}
3359 
3360 	return false;
3361 }
3362 
3363 /**
3364  * i40e_tx_map - Build the Tx descriptor
3365  * @tx_ring:  ring to send buffer on
3366  * @skb:      send buffer
3367  * @first:    first buffer info buffer to use
3368  * @tx_flags: collected send information
3369  * @hdr_len:  size of the packet header
3370  * @td_cmd:   the command field in the descriptor
3371  * @td_offset: offset for checksum or crc
3372  *
3373  * Returns 0 on success, -1 on failure to DMA
3374  **/
i40e_tx_map(struct i40e_ring * tx_ring,struct sk_buff * skb,struct i40e_tx_buffer * first,u32 tx_flags,const u8 hdr_len,u32 td_cmd,u32 td_offset)3375 static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
3376 			      struct i40e_tx_buffer *first, u32 tx_flags,
3377 			      const u8 hdr_len, u32 td_cmd, u32 td_offset)
3378 {
3379 	unsigned int data_len = skb->data_len;
3380 	unsigned int size = skb_headlen(skb);
3381 	skb_frag_t *frag;
3382 	struct i40e_tx_buffer *tx_bi;
3383 	struct i40e_tx_desc *tx_desc;
3384 	u16 i = tx_ring->next_to_use;
3385 	u32 td_tag = 0;
3386 	dma_addr_t dma;
3387 	u16 desc_count = 1;
3388 
3389 	if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
3390 		td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
3391 		td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
3392 			 I40E_TX_FLAGS_VLAN_SHIFT;
3393 	}
3394 
3395 	first->tx_flags = tx_flags;
3396 
3397 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
3398 
3399 	tx_desc = I40E_TX_DESC(tx_ring, i);
3400 	tx_bi = first;
3401 
3402 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
3403 		unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3404 
3405 		if (dma_mapping_error(tx_ring->dev, dma))
3406 			goto dma_error;
3407 
3408 		/* record length, and DMA address */
3409 		dma_unmap_len_set(tx_bi, len, size);
3410 		dma_unmap_addr_set(tx_bi, dma, dma);
3411 
3412 		/* align size to end of page */
3413 		max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
3414 		tx_desc->buffer_addr = cpu_to_le64(dma);
3415 
3416 		while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
3417 			tx_desc->cmd_type_offset_bsz =
3418 				build_ctob(td_cmd, td_offset,
3419 					   max_data, td_tag);
3420 
3421 			tx_desc++;
3422 			i++;
3423 			desc_count++;
3424 
3425 			if (i == tx_ring->count) {
3426 				tx_desc = I40E_TX_DESC(tx_ring, 0);
3427 				i = 0;
3428 			}
3429 
3430 			dma += max_data;
3431 			size -= max_data;
3432 
3433 			max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3434 			tx_desc->buffer_addr = cpu_to_le64(dma);
3435 		}
3436 
3437 		if (likely(!data_len))
3438 			break;
3439 
3440 		tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
3441 							  size, td_tag);
3442 
3443 		tx_desc++;
3444 		i++;
3445 		desc_count++;
3446 
3447 		if (i == tx_ring->count) {
3448 			tx_desc = I40E_TX_DESC(tx_ring, 0);
3449 			i = 0;
3450 		}
3451 
3452 		size = skb_frag_size(frag);
3453 		data_len -= size;
3454 
3455 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
3456 				       DMA_TO_DEVICE);
3457 
3458 		tx_bi = &tx_ring->tx_bi[i];
3459 	}
3460 
3461 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
3462 
3463 	i++;
3464 	if (i == tx_ring->count)
3465 		i = 0;
3466 
3467 	tx_ring->next_to_use = i;
3468 
3469 	i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
3470 
3471 	/* write last descriptor with EOP bit */
3472 	td_cmd |= I40E_TX_DESC_CMD_EOP;
3473 
3474 	/* We OR these values together to check both against 4 (WB_STRIDE)
3475 	 * below. This is safe since we don't re-use desc_count afterwards.
3476 	 */
3477 	desc_count |= ++tx_ring->packet_stride;
3478 
3479 	if (desc_count >= WB_STRIDE) {
3480 		/* write last descriptor with RS bit set */
3481 		td_cmd |= I40E_TX_DESC_CMD_RS;
3482 		tx_ring->packet_stride = 0;
3483 	}
3484 
3485 	tx_desc->cmd_type_offset_bsz =
3486 			build_ctob(td_cmd, td_offset, size, td_tag);
3487 
3488 	skb_tx_timestamp(skb);
3489 
3490 	/* Force memory writes to complete before letting h/w know there
3491 	 * are new descriptors to fetch.
3492 	 *
3493 	 * We also use this memory barrier to make certain all of the
3494 	 * status bits have been updated before next_to_watch is written.
3495 	 */
3496 	wmb();
3497 
3498 	/* set next_to_watch value indicating a packet is present */
3499 	first->next_to_watch = tx_desc;
3500 
3501 	/* notify HW of packet */
3502 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
3503 		writel(i, tx_ring->tail);
3504 	}
3505 
3506 	return 0;
3507 
3508 dma_error:
3509 	dev_info(tx_ring->dev, "TX DMA map failed\n");
3510 
3511 	/* clear dma mappings for failed tx_bi map */
3512 	for (;;) {
3513 		tx_bi = &tx_ring->tx_bi[i];
3514 		i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
3515 		if (tx_bi == first)
3516 			break;
3517 		if (i == 0)
3518 			i = tx_ring->count;
3519 		i--;
3520 	}
3521 
3522 	tx_ring->next_to_use = i;
3523 
3524 	return -1;
3525 }
3526 
i40e_swdcb_skb_tx_hash(struct net_device * dev,const struct sk_buff * skb,u16 num_tx_queues)3527 static u16 i40e_swdcb_skb_tx_hash(struct net_device *dev,
3528 				  const struct sk_buff *skb,
3529 				  u16 num_tx_queues)
3530 {
3531 	u32 jhash_initval_salt = 0xd631614b;
3532 	u32 hash;
3533 
3534 	if (skb->sk && skb->sk->sk_hash)
3535 		hash = skb->sk->sk_hash;
3536 	else
3537 		hash = (__force u16)skb->protocol ^ skb->hash;
3538 
3539 	hash = jhash_1word(hash, jhash_initval_salt);
3540 
3541 	return (u16)(((u64)hash * num_tx_queues) >> 32);
3542 }
3543 
i40e_lan_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device __always_unused * sb_dev)3544 u16 i40e_lan_select_queue(struct net_device *netdev,
3545 			  struct sk_buff *skb,
3546 			  struct net_device __always_unused *sb_dev)
3547 {
3548 	struct i40e_netdev_priv *np = netdev_priv(netdev);
3549 	struct i40e_vsi *vsi = np->vsi;
3550 	struct i40e_hw *hw;
3551 	u16 qoffset;
3552 	u16 qcount;
3553 	u8 tclass;
3554 	u16 hash;
3555 	u8 prio;
3556 
3557 	/* is DCB enabled at all? */
3558 	if (vsi->tc_config.numtc == 1)
3559 		return netdev_pick_tx(netdev, skb, sb_dev);
3560 
3561 	prio = skb->priority;
3562 	hw = &vsi->back->hw;
3563 	tclass = hw->local_dcbx_config.etscfg.prioritytable[prio];
3564 	/* sanity check */
3565 	if (unlikely(!(vsi->tc_config.enabled_tc & BIT(tclass))))
3566 		tclass = 0;
3567 
3568 	/* select a queue assigned for the given TC */
3569 	qcount = vsi->tc_config.tc_info[tclass].qcount;
3570 	hash = i40e_swdcb_skb_tx_hash(netdev, skb, qcount);
3571 
3572 	qoffset = vsi->tc_config.tc_info[tclass].qoffset;
3573 	return qoffset + hash;
3574 }
3575 
3576 /**
3577  * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
3578  * @xdpf: data to transmit
3579  * @xdp_ring: XDP Tx ring
3580  **/
i40e_xmit_xdp_ring(struct xdp_frame * xdpf,struct i40e_ring * xdp_ring)3581 static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
3582 			      struct i40e_ring *xdp_ring)
3583 {
3584 	u16 i = xdp_ring->next_to_use;
3585 	struct i40e_tx_buffer *tx_bi;
3586 	struct i40e_tx_desc *tx_desc;
3587 	void *data = xdpf->data;
3588 	u32 size = xdpf->len;
3589 	dma_addr_t dma;
3590 
3591 	if (!unlikely(I40E_DESC_UNUSED(xdp_ring))) {
3592 		xdp_ring->tx_stats.tx_busy++;
3593 		return I40E_XDP_CONSUMED;
3594 	}
3595 	dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE);
3596 	if (dma_mapping_error(xdp_ring->dev, dma))
3597 		return I40E_XDP_CONSUMED;
3598 
3599 	tx_bi = &xdp_ring->tx_bi[i];
3600 	tx_bi->bytecount = size;
3601 	tx_bi->gso_segs = 1;
3602 	tx_bi->xdpf = xdpf;
3603 
3604 	/* record length, and DMA address */
3605 	dma_unmap_len_set(tx_bi, len, size);
3606 	dma_unmap_addr_set(tx_bi, dma, dma);
3607 
3608 	tx_desc = I40E_TX_DESC(xdp_ring, i);
3609 	tx_desc->buffer_addr = cpu_to_le64(dma);
3610 	tx_desc->cmd_type_offset_bsz = build_ctob(I40E_TX_DESC_CMD_ICRC
3611 						  | I40E_TXD_CMD,
3612 						  0, size, 0);
3613 
3614 	/* Make certain all of the status bits have been updated
3615 	 * before next_to_watch is written.
3616 	 */
3617 	smp_wmb();
3618 
3619 	xdp_ring->xdp_tx_active++;
3620 	i++;
3621 	if (i == xdp_ring->count)
3622 		i = 0;
3623 
3624 	tx_bi->next_to_watch = tx_desc;
3625 	xdp_ring->next_to_use = i;
3626 
3627 	return I40E_XDP_TX;
3628 }
3629 
3630 /**
3631  * i40e_xmit_frame_ring - Sends buffer on Tx ring
3632  * @skb:     send buffer
3633  * @tx_ring: ring to send buffer on
3634  *
3635  * Returns NETDEV_TX_OK if sent, else an error code
3636  **/
i40e_xmit_frame_ring(struct sk_buff * skb,struct i40e_ring * tx_ring)3637 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
3638 					struct i40e_ring *tx_ring)
3639 {
3640 	u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
3641 	u32 cd_tunneling = 0, cd_l2tag2 = 0;
3642 	struct i40e_tx_buffer *first;
3643 	u32 td_offset = 0;
3644 	u32 tx_flags = 0;
3645 	__be16 protocol;
3646 	u32 td_cmd = 0;
3647 	u8 hdr_len = 0;
3648 	int tso, count;
3649 	int tsyn;
3650 
3651 	/* prefetch the data, we'll need it later */
3652 	prefetch(skb->data);
3653 
3654 	i40e_trace(xmit_frame_ring, skb, tx_ring);
3655 
3656 	count = i40e_xmit_descriptor_count(skb);
3657 	if (i40e_chk_linearize(skb, count)) {
3658 		if (__skb_linearize(skb)) {
3659 			dev_kfree_skb_any(skb);
3660 			return NETDEV_TX_OK;
3661 		}
3662 		count = i40e_txd_use_count(skb->len);
3663 		tx_ring->tx_stats.tx_linearize++;
3664 	}
3665 
3666 	/* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
3667 	 *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
3668 	 *       + 4 desc gap to avoid the cache line where head is,
3669 	 *       + 1 desc for context descriptor,
3670 	 * otherwise try next time
3671 	 */
3672 	if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
3673 		tx_ring->tx_stats.tx_busy++;
3674 		return NETDEV_TX_BUSY;
3675 	}
3676 
3677 	/* record the location of the first descriptor for this packet */
3678 	first = &tx_ring->tx_bi[tx_ring->next_to_use];
3679 	first->skb = skb;
3680 	first->bytecount = skb->len;
3681 	first->gso_segs = 1;
3682 
3683 	/* prepare the xmit flags */
3684 	if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
3685 		goto out_drop;
3686 
3687 	/* obtain protocol of skb */
3688 	protocol = vlan_get_protocol(skb);
3689 
3690 	/* setup IPv4/IPv6 offloads */
3691 	if (protocol == htons(ETH_P_IP))
3692 		tx_flags |= I40E_TX_FLAGS_IPV4;
3693 	else if (protocol == htons(ETH_P_IPV6))
3694 		tx_flags |= I40E_TX_FLAGS_IPV6;
3695 
3696 	tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
3697 
3698 	if (tso < 0)
3699 		goto out_drop;
3700 	else if (tso)
3701 		tx_flags |= I40E_TX_FLAGS_TSO;
3702 
3703 	/* Always offload the checksum, since it's in the data descriptor */
3704 	tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
3705 				  tx_ring, &cd_tunneling);
3706 	if (tso < 0)
3707 		goto out_drop;
3708 
3709 	tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
3710 
3711 	if (tsyn)
3712 		tx_flags |= I40E_TX_FLAGS_TSYN;
3713 
3714 	/* always enable CRC insertion offload */
3715 	td_cmd |= I40E_TX_DESC_CMD_ICRC;
3716 
3717 	i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
3718 			   cd_tunneling, cd_l2tag2);
3719 
3720 	/* Add Flow Director ATR if it's enabled.
3721 	 *
3722 	 * NOTE: this must always be directly before the data descriptor.
3723 	 */
3724 	i40e_atr(tx_ring, skb, tx_flags);
3725 
3726 	if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
3727 			td_cmd, td_offset))
3728 		goto cleanup_tx_tstamp;
3729 
3730 	return NETDEV_TX_OK;
3731 
3732 out_drop:
3733 	i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
3734 	dev_kfree_skb_any(first->skb);
3735 	first->skb = NULL;
3736 cleanup_tx_tstamp:
3737 	if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) {
3738 		struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev);
3739 
3740 		dev_kfree_skb_any(pf->ptp_tx_skb);
3741 		pf->ptp_tx_skb = NULL;
3742 		clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
3743 	}
3744 
3745 	return NETDEV_TX_OK;
3746 }
3747 
3748 /**
3749  * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
3750  * @skb:    send buffer
3751  * @netdev: network interface device structure
3752  *
3753  * Returns NETDEV_TX_OK if sent, else an error code
3754  **/
i40e_lan_xmit_frame(struct sk_buff * skb,struct net_device * netdev)3755 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3756 {
3757 	struct i40e_netdev_priv *np = netdev_priv(netdev);
3758 	struct i40e_vsi *vsi = np->vsi;
3759 	struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
3760 
3761 	/* hardware can't handle really short frames, hardware padding works
3762 	 * beyond this point
3763 	 */
3764 	if (skb_put_padto(skb, I40E_MIN_TX_LEN))
3765 		return NETDEV_TX_OK;
3766 
3767 	return i40e_xmit_frame_ring(skb, tx_ring);
3768 }
3769 
3770 /**
3771  * i40e_xdp_xmit - Implements ndo_xdp_xmit
3772  * @dev: netdev
3773  * @n: number of frames
3774  * @frames: array of XDP buffer pointers
3775  * @flags: XDP extra info
3776  *
3777  * Returns number of frames successfully sent. Frames that fail are
3778  * free'ed via XDP return API.
3779  *
3780  * For error cases, a negative errno code is returned and no-frames
3781  * are transmitted (caller must handle freeing frames).
3782  **/
i40e_xdp_xmit(struct net_device * dev,int n,struct xdp_frame ** frames,u32 flags)3783 int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
3784 		  u32 flags)
3785 {
3786 	struct i40e_netdev_priv *np = netdev_priv(dev);
3787 	unsigned int queue_index = smp_processor_id();
3788 	struct i40e_vsi *vsi = np->vsi;
3789 	struct i40e_pf *pf = vsi->back;
3790 	struct i40e_ring *xdp_ring;
3791 	int drops = 0;
3792 	int i;
3793 
3794 	if (test_bit(__I40E_VSI_DOWN, vsi->state))
3795 		return -ENETDOWN;
3796 
3797 	if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs ||
3798 	    test_bit(__I40E_CONFIG_BUSY, pf->state))
3799 		return -ENXIO;
3800 
3801 	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3802 		return -EINVAL;
3803 
3804 	xdp_ring = vsi->xdp_rings[queue_index];
3805 
3806 	for (i = 0; i < n; i++) {
3807 		struct xdp_frame *xdpf = frames[i];
3808 		int err;
3809 
3810 		err = i40e_xmit_xdp_ring(xdpf, xdp_ring);
3811 		if (err != I40E_XDP_TX) {
3812 			xdp_return_frame_rx_napi(xdpf);
3813 			drops++;
3814 		}
3815 	}
3816 
3817 	if (unlikely(flags & XDP_XMIT_FLUSH))
3818 		i40e_xdp_ring_update_tail(xdp_ring);
3819 
3820 	return n - drops;
3821 }
3822