1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/bsearch.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include "kfd_priv.h"
27 #include "kfd_device_queue_manager.h"
28 #include "kfd_pm4_headers_vi.h"
29 #include "cwsr_trap_handler.h"
30 #include "kfd_iommu.h"
31 #include "amdgpu_amdkfd.h"
32 #include "kfd_smi_events.h"
33
34 #define MQD_SIZE_ALIGNED 768
35
36 /*
37 * kfd_locked is used to lock the kfd driver during suspend or reset
38 * once locked, kfd driver will stop any further GPU execution.
39 * create process (open) will return -EAGAIN.
40 */
41 static atomic_t kfd_locked = ATOMIC_INIT(0);
42
43 #ifdef CONFIG_DRM_AMDGPU_CIK
44 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
45 #endif
46 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
47 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
48 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
49 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
50 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
51
52 static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
53 #ifdef KFD_SUPPORT_IOMMU_V2
54 #ifdef CONFIG_DRM_AMDGPU_CIK
55 [CHIP_KAVERI] = &gfx_v7_kfd2kgd,
56 #endif
57 [CHIP_CARRIZO] = &gfx_v8_kfd2kgd,
58 [CHIP_RAVEN] = &gfx_v9_kfd2kgd,
59 #endif
60 #ifdef CONFIG_DRM_AMDGPU_CIK
61 [CHIP_HAWAII] = &gfx_v7_kfd2kgd,
62 #endif
63 [CHIP_TONGA] = &gfx_v8_kfd2kgd,
64 [CHIP_FIJI] = &gfx_v8_kfd2kgd,
65 [CHIP_POLARIS10] = &gfx_v8_kfd2kgd,
66 [CHIP_POLARIS11] = &gfx_v8_kfd2kgd,
67 [CHIP_POLARIS12] = &gfx_v8_kfd2kgd,
68 [CHIP_VEGAM] = &gfx_v8_kfd2kgd,
69 [CHIP_VEGA10] = &gfx_v9_kfd2kgd,
70 [CHIP_VEGA12] = &gfx_v9_kfd2kgd,
71 [CHIP_VEGA20] = &gfx_v9_kfd2kgd,
72 [CHIP_RENOIR] = &gfx_v9_kfd2kgd,
73 [CHIP_ARCTURUS] = &arcturus_kfd2kgd,
74 [CHIP_NAVI10] = &gfx_v10_kfd2kgd,
75 [CHIP_NAVI12] = &gfx_v10_kfd2kgd,
76 [CHIP_NAVI14] = &gfx_v10_kfd2kgd,
77 [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
78 [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
79 };
80
81 #ifdef KFD_SUPPORT_IOMMU_V2
82 static const struct kfd_device_info kaveri_device_info = {
83 .asic_family = CHIP_KAVERI,
84 .asic_name = "kaveri",
85 .max_pasid_bits = 16,
86 /* max num of queues for KV.TODO should be a dynamic value */
87 .max_no_of_hqd = 24,
88 .doorbell_size = 4,
89 .ih_ring_entry_size = 4 * sizeof(uint32_t),
90 .event_interrupt_class = &event_interrupt_class_cik,
91 .num_of_watch_points = 4,
92 .mqd_size_aligned = MQD_SIZE_ALIGNED,
93 .supports_cwsr = false,
94 .needs_iommu_device = true,
95 .needs_pci_atomics = false,
96 .num_sdma_engines = 2,
97 .num_xgmi_sdma_engines = 0,
98 .num_sdma_queues_per_engine = 2,
99 };
100
101 static const struct kfd_device_info carrizo_device_info = {
102 .asic_family = CHIP_CARRIZO,
103 .asic_name = "carrizo",
104 .max_pasid_bits = 16,
105 /* max num of queues for CZ.TODO should be a dynamic value */
106 .max_no_of_hqd = 24,
107 .doorbell_size = 4,
108 .ih_ring_entry_size = 4 * sizeof(uint32_t),
109 .event_interrupt_class = &event_interrupt_class_cik,
110 .num_of_watch_points = 4,
111 .mqd_size_aligned = MQD_SIZE_ALIGNED,
112 .supports_cwsr = true,
113 .needs_iommu_device = true,
114 .needs_pci_atomics = false,
115 .num_sdma_engines = 2,
116 .num_xgmi_sdma_engines = 0,
117 .num_sdma_queues_per_engine = 2,
118 };
119 #endif
120
121 static const struct kfd_device_info raven_device_info = {
122 .asic_family = CHIP_RAVEN,
123 .asic_name = "raven",
124 .max_pasid_bits = 16,
125 .max_no_of_hqd = 24,
126 .doorbell_size = 8,
127 .ih_ring_entry_size = 8 * sizeof(uint32_t),
128 .event_interrupt_class = &event_interrupt_class_v9,
129 .num_of_watch_points = 4,
130 .mqd_size_aligned = MQD_SIZE_ALIGNED,
131 .supports_cwsr = true,
132 .needs_iommu_device = true,
133 .needs_pci_atomics = true,
134 .num_sdma_engines = 1,
135 .num_xgmi_sdma_engines = 0,
136 .num_sdma_queues_per_engine = 2,
137 };
138
139 static const struct kfd_device_info hawaii_device_info = {
140 .asic_family = CHIP_HAWAII,
141 .asic_name = "hawaii",
142 .max_pasid_bits = 16,
143 /* max num of queues for KV.TODO should be a dynamic value */
144 .max_no_of_hqd = 24,
145 .doorbell_size = 4,
146 .ih_ring_entry_size = 4 * sizeof(uint32_t),
147 .event_interrupt_class = &event_interrupt_class_cik,
148 .num_of_watch_points = 4,
149 .mqd_size_aligned = MQD_SIZE_ALIGNED,
150 .supports_cwsr = false,
151 .needs_iommu_device = false,
152 .needs_pci_atomics = false,
153 .num_sdma_engines = 2,
154 .num_xgmi_sdma_engines = 0,
155 .num_sdma_queues_per_engine = 2,
156 };
157
158 static const struct kfd_device_info tonga_device_info = {
159 .asic_family = CHIP_TONGA,
160 .asic_name = "tonga",
161 .max_pasid_bits = 16,
162 .max_no_of_hqd = 24,
163 .doorbell_size = 4,
164 .ih_ring_entry_size = 4 * sizeof(uint32_t),
165 .event_interrupt_class = &event_interrupt_class_cik,
166 .num_of_watch_points = 4,
167 .mqd_size_aligned = MQD_SIZE_ALIGNED,
168 .supports_cwsr = false,
169 .needs_iommu_device = false,
170 .needs_pci_atomics = true,
171 .num_sdma_engines = 2,
172 .num_xgmi_sdma_engines = 0,
173 .num_sdma_queues_per_engine = 2,
174 };
175
176 static const struct kfd_device_info fiji_device_info = {
177 .asic_family = CHIP_FIJI,
178 .asic_name = "fiji",
179 .max_pasid_bits = 16,
180 .max_no_of_hqd = 24,
181 .doorbell_size = 4,
182 .ih_ring_entry_size = 4 * sizeof(uint32_t),
183 .event_interrupt_class = &event_interrupt_class_cik,
184 .num_of_watch_points = 4,
185 .mqd_size_aligned = MQD_SIZE_ALIGNED,
186 .supports_cwsr = true,
187 .needs_iommu_device = false,
188 .needs_pci_atomics = true,
189 .num_sdma_engines = 2,
190 .num_xgmi_sdma_engines = 0,
191 .num_sdma_queues_per_engine = 2,
192 };
193
194 static const struct kfd_device_info fiji_vf_device_info = {
195 .asic_family = CHIP_FIJI,
196 .asic_name = "fiji",
197 .max_pasid_bits = 16,
198 .max_no_of_hqd = 24,
199 .doorbell_size = 4,
200 .ih_ring_entry_size = 4 * sizeof(uint32_t),
201 .event_interrupt_class = &event_interrupt_class_cik,
202 .num_of_watch_points = 4,
203 .mqd_size_aligned = MQD_SIZE_ALIGNED,
204 .supports_cwsr = true,
205 .needs_iommu_device = false,
206 .needs_pci_atomics = false,
207 .num_sdma_engines = 2,
208 .num_xgmi_sdma_engines = 0,
209 .num_sdma_queues_per_engine = 2,
210 };
211
212
213 static const struct kfd_device_info polaris10_device_info = {
214 .asic_family = CHIP_POLARIS10,
215 .asic_name = "polaris10",
216 .max_pasid_bits = 16,
217 .max_no_of_hqd = 24,
218 .doorbell_size = 4,
219 .ih_ring_entry_size = 4 * sizeof(uint32_t),
220 .event_interrupt_class = &event_interrupt_class_cik,
221 .num_of_watch_points = 4,
222 .mqd_size_aligned = MQD_SIZE_ALIGNED,
223 .supports_cwsr = true,
224 .needs_iommu_device = false,
225 .needs_pci_atomics = true,
226 .num_sdma_engines = 2,
227 .num_xgmi_sdma_engines = 0,
228 .num_sdma_queues_per_engine = 2,
229 };
230
231 static const struct kfd_device_info polaris10_vf_device_info = {
232 .asic_family = CHIP_POLARIS10,
233 .asic_name = "polaris10",
234 .max_pasid_bits = 16,
235 .max_no_of_hqd = 24,
236 .doorbell_size = 4,
237 .ih_ring_entry_size = 4 * sizeof(uint32_t),
238 .event_interrupt_class = &event_interrupt_class_cik,
239 .num_of_watch_points = 4,
240 .mqd_size_aligned = MQD_SIZE_ALIGNED,
241 .supports_cwsr = true,
242 .needs_iommu_device = false,
243 .needs_pci_atomics = false,
244 .num_sdma_engines = 2,
245 .num_xgmi_sdma_engines = 0,
246 .num_sdma_queues_per_engine = 2,
247 };
248
249 static const struct kfd_device_info polaris11_device_info = {
250 .asic_family = CHIP_POLARIS11,
251 .asic_name = "polaris11",
252 .max_pasid_bits = 16,
253 .max_no_of_hqd = 24,
254 .doorbell_size = 4,
255 .ih_ring_entry_size = 4 * sizeof(uint32_t),
256 .event_interrupt_class = &event_interrupt_class_cik,
257 .num_of_watch_points = 4,
258 .mqd_size_aligned = MQD_SIZE_ALIGNED,
259 .supports_cwsr = true,
260 .needs_iommu_device = false,
261 .needs_pci_atomics = true,
262 .num_sdma_engines = 2,
263 .num_xgmi_sdma_engines = 0,
264 .num_sdma_queues_per_engine = 2,
265 };
266
267 static const struct kfd_device_info polaris12_device_info = {
268 .asic_family = CHIP_POLARIS12,
269 .asic_name = "polaris12",
270 .max_pasid_bits = 16,
271 .max_no_of_hqd = 24,
272 .doorbell_size = 4,
273 .ih_ring_entry_size = 4 * sizeof(uint32_t),
274 .event_interrupt_class = &event_interrupt_class_cik,
275 .num_of_watch_points = 4,
276 .mqd_size_aligned = MQD_SIZE_ALIGNED,
277 .supports_cwsr = true,
278 .needs_iommu_device = false,
279 .needs_pci_atomics = true,
280 .num_sdma_engines = 2,
281 .num_xgmi_sdma_engines = 0,
282 .num_sdma_queues_per_engine = 2,
283 };
284
285 static const struct kfd_device_info vegam_device_info = {
286 .asic_family = CHIP_VEGAM,
287 .asic_name = "vegam",
288 .max_pasid_bits = 16,
289 .max_no_of_hqd = 24,
290 .doorbell_size = 4,
291 .ih_ring_entry_size = 4 * sizeof(uint32_t),
292 .event_interrupt_class = &event_interrupt_class_cik,
293 .num_of_watch_points = 4,
294 .mqd_size_aligned = MQD_SIZE_ALIGNED,
295 .supports_cwsr = true,
296 .needs_iommu_device = false,
297 .needs_pci_atomics = true,
298 .num_sdma_engines = 2,
299 .num_xgmi_sdma_engines = 0,
300 .num_sdma_queues_per_engine = 2,
301 };
302
303 static const struct kfd_device_info vega10_device_info = {
304 .asic_family = CHIP_VEGA10,
305 .asic_name = "vega10",
306 .max_pasid_bits = 16,
307 .max_no_of_hqd = 24,
308 .doorbell_size = 8,
309 .ih_ring_entry_size = 8 * sizeof(uint32_t),
310 .event_interrupt_class = &event_interrupt_class_v9,
311 .num_of_watch_points = 4,
312 .mqd_size_aligned = MQD_SIZE_ALIGNED,
313 .supports_cwsr = true,
314 .needs_iommu_device = false,
315 .needs_pci_atomics = false,
316 .num_sdma_engines = 2,
317 .num_xgmi_sdma_engines = 0,
318 .num_sdma_queues_per_engine = 2,
319 };
320
321 static const struct kfd_device_info vega10_vf_device_info = {
322 .asic_family = CHIP_VEGA10,
323 .asic_name = "vega10",
324 .max_pasid_bits = 16,
325 .max_no_of_hqd = 24,
326 .doorbell_size = 8,
327 .ih_ring_entry_size = 8 * sizeof(uint32_t),
328 .event_interrupt_class = &event_interrupt_class_v9,
329 .num_of_watch_points = 4,
330 .mqd_size_aligned = MQD_SIZE_ALIGNED,
331 .supports_cwsr = true,
332 .needs_iommu_device = false,
333 .needs_pci_atomics = false,
334 .num_sdma_engines = 2,
335 .num_xgmi_sdma_engines = 0,
336 .num_sdma_queues_per_engine = 2,
337 };
338
339 static const struct kfd_device_info vega12_device_info = {
340 .asic_family = CHIP_VEGA12,
341 .asic_name = "vega12",
342 .max_pasid_bits = 16,
343 .max_no_of_hqd = 24,
344 .doorbell_size = 8,
345 .ih_ring_entry_size = 8 * sizeof(uint32_t),
346 .event_interrupt_class = &event_interrupt_class_v9,
347 .num_of_watch_points = 4,
348 .mqd_size_aligned = MQD_SIZE_ALIGNED,
349 .supports_cwsr = true,
350 .needs_iommu_device = false,
351 .needs_pci_atomics = false,
352 .num_sdma_engines = 2,
353 .num_xgmi_sdma_engines = 0,
354 .num_sdma_queues_per_engine = 2,
355 };
356
357 static const struct kfd_device_info vega20_device_info = {
358 .asic_family = CHIP_VEGA20,
359 .asic_name = "vega20",
360 .max_pasid_bits = 16,
361 .max_no_of_hqd = 24,
362 .doorbell_size = 8,
363 .ih_ring_entry_size = 8 * sizeof(uint32_t),
364 .event_interrupt_class = &event_interrupt_class_v9,
365 .num_of_watch_points = 4,
366 .mqd_size_aligned = MQD_SIZE_ALIGNED,
367 .supports_cwsr = true,
368 .needs_iommu_device = false,
369 .needs_pci_atomics = false,
370 .num_sdma_engines = 2,
371 .num_xgmi_sdma_engines = 0,
372 .num_sdma_queues_per_engine = 8,
373 };
374
375 static const struct kfd_device_info arcturus_device_info = {
376 .asic_family = CHIP_ARCTURUS,
377 .asic_name = "arcturus",
378 .max_pasid_bits = 16,
379 .max_no_of_hqd = 24,
380 .doorbell_size = 8,
381 .ih_ring_entry_size = 8 * sizeof(uint32_t),
382 .event_interrupt_class = &event_interrupt_class_v9,
383 .num_of_watch_points = 4,
384 .mqd_size_aligned = MQD_SIZE_ALIGNED,
385 .supports_cwsr = true,
386 .needs_iommu_device = false,
387 .needs_pci_atomics = false,
388 .num_sdma_engines = 2,
389 .num_xgmi_sdma_engines = 6,
390 .num_sdma_queues_per_engine = 8,
391 };
392
393 static const struct kfd_device_info renoir_device_info = {
394 .asic_family = CHIP_RENOIR,
395 .asic_name = "renoir",
396 .max_pasid_bits = 16,
397 .max_no_of_hqd = 24,
398 .doorbell_size = 8,
399 .ih_ring_entry_size = 8 * sizeof(uint32_t),
400 .event_interrupt_class = &event_interrupt_class_v9,
401 .num_of_watch_points = 4,
402 .mqd_size_aligned = MQD_SIZE_ALIGNED,
403 .supports_cwsr = true,
404 .needs_iommu_device = false,
405 .needs_pci_atomics = false,
406 .num_sdma_engines = 1,
407 .num_xgmi_sdma_engines = 0,
408 .num_sdma_queues_per_engine = 2,
409 };
410
411 static const struct kfd_device_info navi10_device_info = {
412 .asic_family = CHIP_NAVI10,
413 .asic_name = "navi10",
414 .max_pasid_bits = 16,
415 .max_no_of_hqd = 24,
416 .doorbell_size = 8,
417 .ih_ring_entry_size = 8 * sizeof(uint32_t),
418 .event_interrupt_class = &event_interrupt_class_v9,
419 .num_of_watch_points = 4,
420 .mqd_size_aligned = MQD_SIZE_ALIGNED,
421 .needs_iommu_device = false,
422 .supports_cwsr = true,
423 .needs_pci_atomics = false,
424 .num_sdma_engines = 2,
425 .num_xgmi_sdma_engines = 0,
426 .num_sdma_queues_per_engine = 8,
427 };
428
429 static const struct kfd_device_info navi12_device_info = {
430 .asic_family = CHIP_NAVI12,
431 .asic_name = "navi12",
432 .max_pasid_bits = 16,
433 .max_no_of_hqd = 24,
434 .doorbell_size = 8,
435 .ih_ring_entry_size = 8 * sizeof(uint32_t),
436 .event_interrupt_class = &event_interrupt_class_v9,
437 .num_of_watch_points = 4,
438 .mqd_size_aligned = MQD_SIZE_ALIGNED,
439 .needs_iommu_device = false,
440 .supports_cwsr = true,
441 .needs_pci_atomics = false,
442 .num_sdma_engines = 2,
443 .num_xgmi_sdma_engines = 0,
444 .num_sdma_queues_per_engine = 8,
445 };
446
447 static const struct kfd_device_info navi14_device_info = {
448 .asic_family = CHIP_NAVI14,
449 .asic_name = "navi14",
450 .max_pasid_bits = 16,
451 .max_no_of_hqd = 24,
452 .doorbell_size = 8,
453 .ih_ring_entry_size = 8 * sizeof(uint32_t),
454 .event_interrupt_class = &event_interrupt_class_v9,
455 .num_of_watch_points = 4,
456 .mqd_size_aligned = MQD_SIZE_ALIGNED,
457 .needs_iommu_device = false,
458 .supports_cwsr = true,
459 .needs_pci_atomics = false,
460 .num_sdma_engines = 2,
461 .num_xgmi_sdma_engines = 0,
462 .num_sdma_queues_per_engine = 8,
463 };
464
465 static const struct kfd_device_info sienna_cichlid_device_info = {
466 .asic_family = CHIP_SIENNA_CICHLID,
467 .asic_name = "sienna_cichlid",
468 .max_pasid_bits = 16,
469 .max_no_of_hqd = 24,
470 .doorbell_size = 8,
471 .ih_ring_entry_size = 8 * sizeof(uint32_t),
472 .event_interrupt_class = &event_interrupt_class_v9,
473 .num_of_watch_points = 4,
474 .mqd_size_aligned = MQD_SIZE_ALIGNED,
475 .needs_iommu_device = false,
476 .supports_cwsr = true,
477 .needs_pci_atomics = false,
478 .num_sdma_engines = 4,
479 .num_xgmi_sdma_engines = 0,
480 .num_sdma_queues_per_engine = 8,
481 };
482
483 static const struct kfd_device_info navy_flounder_device_info = {
484 .asic_family = CHIP_NAVY_FLOUNDER,
485 .asic_name = "navy_flounder",
486 .max_pasid_bits = 16,
487 .max_no_of_hqd = 24,
488 .doorbell_size = 8,
489 .ih_ring_entry_size = 8 * sizeof(uint32_t),
490 .event_interrupt_class = &event_interrupt_class_v9,
491 .num_of_watch_points = 4,
492 .mqd_size_aligned = MQD_SIZE_ALIGNED,
493 .needs_iommu_device = false,
494 .supports_cwsr = true,
495 .needs_pci_atomics = false,
496 .num_sdma_engines = 2,
497 .num_xgmi_sdma_engines = 0,
498 .num_sdma_queues_per_engine = 8,
499 };
500
501 /* For each entry, [0] is regular and [1] is virtualisation device. */
502 static const struct kfd_device_info *kfd_supported_devices[][2] = {
503 #ifdef KFD_SUPPORT_IOMMU_V2
504 [CHIP_KAVERI] = {&kaveri_device_info, NULL},
505 [CHIP_CARRIZO] = {&carrizo_device_info, NULL},
506 #endif
507 [CHIP_RAVEN] = {&raven_device_info, NULL},
508 [CHIP_HAWAII] = {&hawaii_device_info, NULL},
509 [CHIP_TONGA] = {&tonga_device_info, NULL},
510 [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
511 [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
512 [CHIP_POLARIS11] = {&polaris11_device_info, NULL},
513 [CHIP_POLARIS12] = {&polaris12_device_info, NULL},
514 [CHIP_VEGAM] = {&vegam_device_info, NULL},
515 [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
516 [CHIP_VEGA12] = {&vega12_device_info, NULL},
517 [CHIP_VEGA20] = {&vega20_device_info, NULL},
518 [CHIP_RENOIR] = {&renoir_device_info, NULL},
519 [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
520 [CHIP_NAVI10] = {&navi10_device_info, NULL},
521 [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
522 [CHIP_NAVI14] = {&navi14_device_info, NULL},
523 [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
524 [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
525 };
526
527 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
528 unsigned int chunk_size);
529 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
530
531 static int kfd_resume(struct kfd_dev *kfd);
532
kgd2kfd_probe(struct kgd_dev * kgd,struct pci_dev * pdev,unsigned int asic_type,bool vf)533 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
534 struct pci_dev *pdev, unsigned int asic_type, bool vf)
535 {
536 struct kfd_dev *kfd;
537 const struct kfd_device_info *device_info;
538 const struct kfd2kgd_calls *f2g;
539
540 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
541 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
542 dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
543 return NULL; /* asic_type out of range */
544 }
545
546 device_info = kfd_supported_devices[asic_type][vf];
547 f2g = kfd2kgd_funcs[asic_type];
548
549 if (!device_info || !f2g) {
550 dev_err(kfd_device, "%s %s not supported in kfd\n",
551 amdgpu_asic_name[asic_type], vf ? "VF" : "");
552 return NULL;
553 }
554
555 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
556 if (!kfd)
557 return NULL;
558
559 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
560 * 32 and 64-bit requests are possible and must be
561 * supported.
562 */
563 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd);
564 if (device_info->needs_pci_atomics &&
565 !kfd->pci_atomic_requested) {
566 dev_info(kfd_device,
567 "skipped device %x:%x, PCI rejects atomics\n",
568 pdev->vendor, pdev->device);
569 kfree(kfd);
570 return NULL;
571 }
572
573 kfd->kgd = kgd;
574 kfd->device_info = device_info;
575 kfd->pdev = pdev;
576 kfd->init_complete = false;
577 kfd->kfd2kgd = f2g;
578 atomic_set(&kfd->compute_profile, 0);
579
580 mutex_init(&kfd->doorbell_mutex);
581 memset(&kfd->doorbell_available_index, 0,
582 sizeof(kfd->doorbell_available_index));
583
584 atomic_set(&kfd->sram_ecc_flag, 0);
585
586 ida_init(&kfd->doorbell_ida);
587
588 return kfd;
589 }
590
kfd_cwsr_init(struct kfd_dev * kfd)591 static void kfd_cwsr_init(struct kfd_dev *kfd)
592 {
593 if (cwsr_enable && kfd->device_info->supports_cwsr) {
594 if (kfd->device_info->asic_family < CHIP_VEGA10) {
595 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
596 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
597 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
598 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
599 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
600 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
601 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
602 } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
603 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
604 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
605 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
606 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) {
607 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
608 kfd->cwsr_isa = cwsr_trap_nv1x_hex;
609 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
610 } else {
611 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
612 kfd->cwsr_isa = cwsr_trap_gfx10_hex;
613 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
614 }
615
616 kfd->cwsr_enabled = true;
617 }
618 }
619
kfd_gws_init(struct kfd_dev * kfd)620 static int kfd_gws_init(struct kfd_dev *kfd)
621 {
622 int ret = 0;
623
624 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
625 return 0;
626
627 if (hws_gws_support
628 || (kfd->device_info->asic_family == CHIP_VEGA10
629 && kfd->mec2_fw_version >= 0x81b3)
630 || (kfd->device_info->asic_family >= CHIP_VEGA12
631 && kfd->device_info->asic_family <= CHIP_RAVEN
632 && kfd->mec2_fw_version >= 0x1b3)
633 || (kfd->device_info->asic_family == CHIP_ARCTURUS
634 && kfd->mec2_fw_version >= 0x30))
635 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd,
636 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws);
637
638 return ret;
639 }
640
kfd_smi_init(struct kfd_dev * dev)641 static void kfd_smi_init(struct kfd_dev *dev) {
642 INIT_LIST_HEAD(&dev->smi_clients);
643 spin_lock_init(&dev->smi_lock);
644 }
645
kgd2kfd_device_init(struct kfd_dev * kfd,struct drm_device * ddev,const struct kgd2kfd_shared_resources * gpu_resources)646 bool kgd2kfd_device_init(struct kfd_dev *kfd,
647 struct drm_device *ddev,
648 const struct kgd2kfd_shared_resources *gpu_resources)
649 {
650 unsigned int size;
651
652 kfd->ddev = ddev;
653 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
654 KGD_ENGINE_MEC1);
655 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
656 KGD_ENGINE_MEC2);
657 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
658 KGD_ENGINE_SDMA1);
659 kfd->shared_resources = *gpu_resources;
660
661 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
662 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
663 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
664 - kfd->vm_info.first_vmid_kfd + 1;
665
666 /* Verify module parameters regarding mapped process number*/
667 if ((hws_max_conc_proc < 0)
668 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
669 dev_err(kfd_device,
670 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
671 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
672 kfd->vm_info.vmid_num_kfd);
673 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
674 } else
675 kfd->max_proc_per_quantum = hws_max_conc_proc;
676
677 /* calculate max size of mqds needed for queues */
678 size = max_num_of_queues_per_device *
679 kfd->device_info->mqd_size_aligned;
680
681 /*
682 * calculate max size of runlist packet.
683 * There can be only 2 packets at once
684 */
685 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) +
686 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
687 + sizeof(struct pm4_mes_runlist)) * 2;
688
689 /* Add size of HIQ & DIQ */
690 size += KFD_KERNEL_QUEUE_SIZE * 2;
691
692 /* add another 512KB for all other allocations on gart (HPD, fences) */
693 size += 512 * 1024;
694
695 if (amdgpu_amdkfd_alloc_gtt_mem(
696 kfd->kgd, size, &kfd->gtt_mem,
697 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
698 false)) {
699 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
700 goto alloc_gtt_mem_failure;
701 }
702
703 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
704
705 /* Initialize GTT sa with 512 byte chunk size */
706 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
707 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
708 goto kfd_gtt_sa_init_error;
709 }
710
711 if (kfd_doorbell_init(kfd)) {
712 dev_err(kfd_device,
713 "Error initializing doorbell aperture\n");
714 goto kfd_doorbell_error;
715 }
716
717 kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd);
718
719 kfd->unique_id = amdgpu_amdkfd_get_unique_id(kfd->kgd);
720
721 kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd);
722
723 if (kfd_interrupt_init(kfd)) {
724 dev_err(kfd_device, "Error initializing interrupts\n");
725 goto kfd_interrupt_error;
726 }
727
728 kfd->dqm = device_queue_manager_init(kfd);
729 if (!kfd->dqm) {
730 dev_err(kfd_device, "Error initializing queue manager\n");
731 goto device_queue_manager_error;
732 }
733
734 /* If supported on this device, allocate global GWS that is shared
735 * by all KFD processes
736 */
737 if (kfd_gws_init(kfd)) {
738 dev_err(kfd_device, "Could not allocate %d gws\n",
739 amdgpu_amdkfd_get_num_gws(kfd->kgd));
740 goto gws_error;
741 }
742
743 /* If CRAT is broken, won't set iommu enabled */
744 kfd_double_confirm_iommu_support(kfd);
745
746 if (kfd_iommu_device_init(kfd)) {
747 kfd->use_iommu_v2 = false;
748 dev_err(kfd_device, "Error initializing iommuv2\n");
749 goto device_iommu_error;
750 }
751
752 kfd_cwsr_init(kfd);
753
754 if(kgd2kfd_resume_iommu(kfd))
755 goto device_iommu_error;
756
757 if (kfd_resume(kfd))
758 goto kfd_resume_error;
759
760 kfd->dbgmgr = NULL;
761
762 if (kfd_topology_add_device(kfd)) {
763 dev_err(kfd_device, "Error adding device to topology\n");
764 goto kfd_topology_add_device_error;
765 }
766
767 kfd_smi_init(kfd);
768
769 kfd->init_complete = true;
770 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
771 kfd->pdev->device);
772
773 pr_debug("Starting kfd with the following scheduling policy %d\n",
774 kfd->dqm->sched_policy);
775
776 goto out;
777
778 kfd_topology_add_device_error:
779 kfd_resume_error:
780 device_iommu_error:
781 gws_error:
782 device_queue_manager_uninit(kfd->dqm);
783 device_queue_manager_error:
784 kfd_interrupt_exit(kfd);
785 kfd_interrupt_error:
786 kfd_doorbell_fini(kfd);
787 kfd_doorbell_error:
788 kfd_gtt_sa_fini(kfd);
789 kfd_gtt_sa_init_error:
790 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
791 alloc_gtt_mem_failure:
792 if (kfd->gws)
793 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
794 dev_err(kfd_device,
795 "device %x:%x NOT added due to errors\n",
796 kfd->pdev->vendor, kfd->pdev->device);
797 out:
798 return kfd->init_complete;
799 }
800
kgd2kfd_device_exit(struct kfd_dev * kfd)801 void kgd2kfd_device_exit(struct kfd_dev *kfd)
802 {
803 if (kfd->init_complete) {
804 kgd2kfd_suspend(kfd, false);
805 device_queue_manager_uninit(kfd->dqm);
806 kfd_interrupt_exit(kfd);
807 kfd_topology_remove_device(kfd);
808 kfd_doorbell_fini(kfd);
809 ida_destroy(&kfd->doorbell_ida);
810 kfd_gtt_sa_fini(kfd);
811 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
812 if (kfd->gws)
813 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
814 }
815
816 kfree(kfd);
817 }
818
kgd2kfd_pre_reset(struct kfd_dev * kfd)819 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
820 {
821 if (!kfd->init_complete)
822 return 0;
823
824 kfd_smi_event_update_gpu_reset(kfd, false);
825
826 kfd->dqm->ops.pre_reset(kfd->dqm);
827
828 kgd2kfd_suspend(kfd, false);
829
830 kfd_signal_reset_event(kfd);
831 return 0;
832 }
833
834 /*
835 * Fix me. KFD won't be able to resume existing process for now.
836 * We will keep all existing process in a evicted state and
837 * wait the process to be terminated.
838 */
839
kgd2kfd_post_reset(struct kfd_dev * kfd)840 int kgd2kfd_post_reset(struct kfd_dev *kfd)
841 {
842 int ret;
843
844 if (!kfd->init_complete)
845 return 0;
846
847 ret = kfd_resume(kfd);
848 if (ret)
849 return ret;
850 atomic_dec(&kfd_locked);
851
852 atomic_set(&kfd->sram_ecc_flag, 0);
853
854 kfd_smi_event_update_gpu_reset(kfd, true);
855
856 return 0;
857 }
858
kfd_is_locked(void)859 bool kfd_is_locked(void)
860 {
861 return (atomic_read(&kfd_locked) > 0);
862 }
863
kgd2kfd_suspend(struct kfd_dev * kfd,bool run_pm)864 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
865 {
866 if (!kfd->init_complete)
867 return;
868
869 /* for runtime suspend, skip locking kfd */
870 if (!run_pm) {
871 /* For first KFD device suspend all the KFD processes */
872 if (atomic_inc_return(&kfd_locked) == 1)
873 kfd_suspend_all_processes();
874 }
875
876 kfd->dqm->ops.stop(kfd->dqm);
877 kfd_iommu_suspend(kfd);
878 }
879
kgd2kfd_resume(struct kfd_dev * kfd,bool run_pm)880 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
881 {
882 int ret, count;
883
884 if (!kfd->init_complete)
885 return 0;
886
887 ret = kfd_resume(kfd);
888 if (ret)
889 return ret;
890
891 /* for runtime resume, skip unlocking kfd */
892 if (!run_pm) {
893 count = atomic_dec_return(&kfd_locked);
894 WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
895 if (count == 0)
896 ret = kfd_resume_all_processes();
897 }
898
899 return ret;
900 }
901
kgd2kfd_resume_iommu(struct kfd_dev * kfd)902 int kgd2kfd_resume_iommu(struct kfd_dev *kfd)
903 {
904 int err = 0;
905
906 err = kfd_iommu_resume(kfd);
907 if (err)
908 dev_err(kfd_device,
909 "Failed to resume IOMMU for device %x:%x\n",
910 kfd->pdev->vendor, kfd->pdev->device);
911 return err;
912 }
913
kfd_resume(struct kfd_dev * kfd)914 static int kfd_resume(struct kfd_dev *kfd)
915 {
916 int err = 0;
917
918 err = kfd->dqm->ops.start(kfd->dqm);
919 if (err) {
920 dev_err(kfd_device,
921 "Error starting queue manager for device %x:%x\n",
922 kfd->pdev->vendor, kfd->pdev->device);
923 goto dqm_start_error;
924 }
925
926 return err;
927
928 dqm_start_error:
929 kfd_iommu_suspend(kfd);
930 return err;
931 }
932
kfd_queue_work(struct workqueue_struct * wq,struct work_struct * work)933 static inline void kfd_queue_work(struct workqueue_struct *wq,
934 struct work_struct *work)
935 {
936 int cpu, new_cpu;
937
938 cpu = new_cpu = smp_processor_id();
939 do {
940 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
941 if (cpu_to_node(new_cpu) == numa_node_id())
942 break;
943 } while (cpu != new_cpu);
944
945 queue_work_on(new_cpu, wq, work);
946 }
947
948 /* This is called directly from KGD at ISR. */
kgd2kfd_interrupt(struct kfd_dev * kfd,const void * ih_ring_entry)949 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
950 {
951 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
952 bool is_patched = false;
953 unsigned long flags;
954
955 if (!kfd->init_complete)
956 return;
957
958 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) {
959 dev_err_once(kfd_device, "Ring entry too small\n");
960 return;
961 }
962
963 spin_lock_irqsave(&kfd->interrupt_lock, flags);
964
965 if (kfd->interrupts_active
966 && interrupt_is_wanted(kfd, ih_ring_entry,
967 patched_ihre, &is_patched)
968 && enqueue_ih_ring_entry(kfd,
969 is_patched ? patched_ihre : ih_ring_entry))
970 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work);
971
972 spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
973 }
974
kgd2kfd_quiesce_mm(struct mm_struct * mm)975 int kgd2kfd_quiesce_mm(struct mm_struct *mm)
976 {
977 struct kfd_process *p;
978 int r;
979
980 /* Because we are called from arbitrary context (workqueue) as opposed
981 * to process context, kfd_process could attempt to exit while we are
982 * running so the lookup function increments the process ref count.
983 */
984 p = kfd_lookup_process_by_mm(mm);
985 if (!p)
986 return -ESRCH;
987
988 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
989 r = kfd_process_evict_queues(p);
990
991 kfd_unref_process(p);
992 return r;
993 }
994
kgd2kfd_resume_mm(struct mm_struct * mm)995 int kgd2kfd_resume_mm(struct mm_struct *mm)
996 {
997 struct kfd_process *p;
998 int r;
999
1000 /* Because we are called from arbitrary context (workqueue) as opposed
1001 * to process context, kfd_process could attempt to exit while we are
1002 * running so the lookup function increments the process ref count.
1003 */
1004 p = kfd_lookup_process_by_mm(mm);
1005 if (!p)
1006 return -ESRCH;
1007
1008 r = kfd_process_restore_queues(p);
1009
1010 kfd_unref_process(p);
1011 return r;
1012 }
1013
1014 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
1015 * prepare for safe eviction of KFD BOs that belong to the specified
1016 * process.
1017 *
1018 * @mm: mm_struct that identifies the specified KFD process
1019 * @fence: eviction fence attached to KFD process BOs
1020 *
1021 */
kgd2kfd_schedule_evict_and_restore_process(struct mm_struct * mm,struct dma_fence * fence)1022 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1023 struct dma_fence *fence)
1024 {
1025 struct kfd_process *p;
1026 unsigned long active_time;
1027 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1028
1029 if (!fence)
1030 return -EINVAL;
1031
1032 if (dma_fence_is_signaled(fence))
1033 return 0;
1034
1035 p = kfd_lookup_process_by_mm(mm);
1036 if (!p)
1037 return -ENODEV;
1038
1039 if (fence->seqno == p->last_eviction_seqno)
1040 goto out;
1041
1042 p->last_eviction_seqno = fence->seqno;
1043
1044 /* Avoid KFD process starvation. Wait for at least
1045 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1046 */
1047 active_time = get_jiffies_64() - p->last_restore_timestamp;
1048 if (delay_jiffies > active_time)
1049 delay_jiffies -= active_time;
1050 else
1051 delay_jiffies = 0;
1052
1053 /* During process initialization eviction_work.dwork is initialized
1054 * to kfd_evict_bo_worker
1055 */
1056 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1057 p->lead_thread->pid, delay_jiffies);
1058 schedule_delayed_work(&p->eviction_work, delay_jiffies);
1059 out:
1060 kfd_unref_process(p);
1061 return 0;
1062 }
1063
kfd_gtt_sa_init(struct kfd_dev * kfd,unsigned int buf_size,unsigned int chunk_size)1064 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1065 unsigned int chunk_size)
1066 {
1067 unsigned int num_of_longs;
1068
1069 if (WARN_ON(buf_size < chunk_size))
1070 return -EINVAL;
1071 if (WARN_ON(buf_size == 0))
1072 return -EINVAL;
1073 if (WARN_ON(chunk_size == 0))
1074 return -EINVAL;
1075
1076 kfd->gtt_sa_chunk_size = chunk_size;
1077 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1078
1079 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) /
1080 BITS_PER_LONG;
1081
1082 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL);
1083
1084 if (!kfd->gtt_sa_bitmap)
1085 return -ENOMEM;
1086
1087 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1088 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1089
1090 mutex_init(&kfd->gtt_sa_lock);
1091
1092 return 0;
1093
1094 }
1095
kfd_gtt_sa_fini(struct kfd_dev * kfd)1096 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1097 {
1098 mutex_destroy(&kfd->gtt_sa_lock);
1099 kfree(kfd->gtt_sa_bitmap);
1100 }
1101
kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,unsigned int bit_num,unsigned int chunk_size)1102 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1103 unsigned int bit_num,
1104 unsigned int chunk_size)
1105 {
1106 return start_addr + bit_num * chunk_size;
1107 }
1108
kfd_gtt_sa_calc_cpu_addr(void * start_addr,unsigned int bit_num,unsigned int chunk_size)1109 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1110 unsigned int bit_num,
1111 unsigned int chunk_size)
1112 {
1113 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1114 }
1115
kfd_gtt_sa_allocate(struct kfd_dev * kfd,unsigned int size,struct kfd_mem_obj ** mem_obj)1116 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
1117 struct kfd_mem_obj **mem_obj)
1118 {
1119 unsigned int found, start_search, cur_size;
1120
1121 if (size == 0)
1122 return -EINVAL;
1123
1124 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1125 return -ENOMEM;
1126
1127 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1128 if (!(*mem_obj))
1129 return -ENOMEM;
1130
1131 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1132
1133 start_search = 0;
1134
1135 mutex_lock(&kfd->gtt_sa_lock);
1136
1137 kfd_gtt_restart_search:
1138 /* Find the first chunk that is free */
1139 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1140 kfd->gtt_sa_num_of_chunks,
1141 start_search);
1142
1143 pr_debug("Found = %d\n", found);
1144
1145 /* If there wasn't any free chunk, bail out */
1146 if (found == kfd->gtt_sa_num_of_chunks)
1147 goto kfd_gtt_no_free_chunk;
1148
1149 /* Update fields of mem_obj */
1150 (*mem_obj)->range_start = found;
1151 (*mem_obj)->range_end = found;
1152 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1153 kfd->gtt_start_gpu_addr,
1154 found,
1155 kfd->gtt_sa_chunk_size);
1156 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1157 kfd->gtt_start_cpu_ptr,
1158 found,
1159 kfd->gtt_sa_chunk_size);
1160
1161 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1162 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1163
1164 /* If we need only one chunk, mark it as allocated and get out */
1165 if (size <= kfd->gtt_sa_chunk_size) {
1166 pr_debug("Single bit\n");
1167 set_bit(found, kfd->gtt_sa_bitmap);
1168 goto kfd_gtt_out;
1169 }
1170
1171 /* Otherwise, try to see if we have enough contiguous chunks */
1172 cur_size = size - kfd->gtt_sa_chunk_size;
1173 do {
1174 (*mem_obj)->range_end =
1175 find_next_zero_bit(kfd->gtt_sa_bitmap,
1176 kfd->gtt_sa_num_of_chunks, ++found);
1177 /*
1178 * If next free chunk is not contiguous than we need to
1179 * restart our search from the last free chunk we found (which
1180 * wasn't contiguous to the previous ones
1181 */
1182 if ((*mem_obj)->range_end != found) {
1183 start_search = found;
1184 goto kfd_gtt_restart_search;
1185 }
1186
1187 /*
1188 * If we reached end of buffer, bail out with error
1189 */
1190 if (found == kfd->gtt_sa_num_of_chunks)
1191 goto kfd_gtt_no_free_chunk;
1192
1193 /* Check if we don't need another chunk */
1194 if (cur_size <= kfd->gtt_sa_chunk_size)
1195 cur_size = 0;
1196 else
1197 cur_size -= kfd->gtt_sa_chunk_size;
1198
1199 } while (cur_size > 0);
1200
1201 pr_debug("range_start = %d, range_end = %d\n",
1202 (*mem_obj)->range_start, (*mem_obj)->range_end);
1203
1204 /* Mark the chunks as allocated */
1205 for (found = (*mem_obj)->range_start;
1206 found <= (*mem_obj)->range_end;
1207 found++)
1208 set_bit(found, kfd->gtt_sa_bitmap);
1209
1210 kfd_gtt_out:
1211 mutex_unlock(&kfd->gtt_sa_lock);
1212 return 0;
1213
1214 kfd_gtt_no_free_chunk:
1215 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1216 mutex_unlock(&kfd->gtt_sa_lock);
1217 kfree(*mem_obj);
1218 return -ENOMEM;
1219 }
1220
kfd_gtt_sa_free(struct kfd_dev * kfd,struct kfd_mem_obj * mem_obj)1221 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
1222 {
1223 unsigned int bit;
1224
1225 /* Act like kfree when trying to free a NULL object */
1226 if (!mem_obj)
1227 return 0;
1228
1229 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1230 mem_obj, mem_obj->range_start, mem_obj->range_end);
1231
1232 mutex_lock(&kfd->gtt_sa_lock);
1233
1234 /* Mark the chunks as free */
1235 for (bit = mem_obj->range_start;
1236 bit <= mem_obj->range_end;
1237 bit++)
1238 clear_bit(bit, kfd->gtt_sa_bitmap);
1239
1240 mutex_unlock(&kfd->gtt_sa_lock);
1241
1242 kfree(mem_obj);
1243 return 0;
1244 }
1245
kgd2kfd_set_sram_ecc_flag(struct kfd_dev * kfd)1246 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1247 {
1248 if (kfd)
1249 atomic_inc(&kfd->sram_ecc_flag);
1250 }
1251
kfd_inc_compute_active(struct kfd_dev * kfd)1252 void kfd_inc_compute_active(struct kfd_dev *kfd)
1253 {
1254 if (atomic_inc_return(&kfd->compute_profile) == 1)
1255 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false);
1256 }
1257
kfd_dec_compute_active(struct kfd_dev * kfd)1258 void kfd_dec_compute_active(struct kfd_dev *kfd)
1259 {
1260 int count = atomic_dec_return(&kfd->compute_profile);
1261
1262 if (count == 0)
1263 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true);
1264 WARN_ONCE(count < 0, "Compute profile ref. count error");
1265 }
1266
kgd2kfd_smi_event_throttle(struct kfd_dev * kfd,uint32_t throttle_bitmask)1267 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask)
1268 {
1269 if (kfd)
1270 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask);
1271 }
1272
1273 #if defined(CONFIG_DEBUG_FS)
1274
1275 /* This function will send a package to HIQ to hang the HWS
1276 * which will trigger a GPU reset and bring the HWS back to normal state
1277 */
kfd_debugfs_hang_hws(struct kfd_dev * dev)1278 int kfd_debugfs_hang_hws(struct kfd_dev *dev)
1279 {
1280 int r = 0;
1281
1282 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1283 pr_err("HWS is not enabled");
1284 return -EINVAL;
1285 }
1286
1287 r = pm_debugfs_hang_hws(&dev->dqm->packets);
1288 if (!r)
1289 r = dqm_debugfs_execute_queues(dev->dqm);
1290
1291 return r;
1292 }
1293
1294 #endif
1295