1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7 #include <linux/delay.h>
8
9 #include <drm/drm_vblank.h>
10
11 #include "msm_drv.h"
12 #include "msm_gem.h"
13 #include "msm_mmu.h"
14 #include "mdp4_kms.h"
15
16 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
17
mdp4_hw_init(struct msm_kms * kms)18 static int mdp4_hw_init(struct msm_kms *kms)
19 {
20 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
21 struct drm_device *dev = mdp4_kms->dev;
22 u32 dmap_cfg, vg_cfg;
23 unsigned long clk;
24 int ret = 0;
25
26 pm_runtime_get_sync(dev->dev);
27
28 if (mdp4_kms->rev > 1) {
29 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
30 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
31 }
32
33 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
34
35 /* max read pending cmd config, 3 pending requests: */
36 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
37
38 clk = clk_get_rate(mdp4_kms->clk);
39
40 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
41 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
42 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
43 } else {
44 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
45 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
46 }
47
48 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
49
50 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
51 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
52
53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
54 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
55 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
56 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
57
58 if (mdp4_kms->rev >= 2)
59 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
60 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
61
62 /* disable CSC matrix / YUV by default: */
63 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
64 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
65 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
66 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
67 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
68 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
69
70 if (mdp4_kms->rev > 1)
71 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
72
73 pm_runtime_put_sync(dev->dev);
74
75 return ret;
76 }
77
mdp4_enable_commit(struct msm_kms * kms)78 static void mdp4_enable_commit(struct msm_kms *kms)
79 {
80 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
81 mdp4_enable(mdp4_kms);
82 }
83
mdp4_disable_commit(struct msm_kms * kms)84 static void mdp4_disable_commit(struct msm_kms *kms)
85 {
86 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
87 mdp4_disable(mdp4_kms);
88 }
89
mdp4_prepare_commit(struct msm_kms * kms,struct drm_atomic_state * state)90 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
91 {
92 }
93
mdp4_flush_commit(struct msm_kms * kms,unsigned crtc_mask)94 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
95 {
96 /* TODO */
97 }
98
mdp4_wait_flush(struct msm_kms * kms,unsigned crtc_mask)99 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
100 {
101 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
102 struct drm_crtc *crtc;
103
104 for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
105 mdp4_crtc_wait_for_commit_done(crtc);
106 }
107
mdp4_complete_commit(struct msm_kms * kms,unsigned crtc_mask)108 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
109 {
110 }
111
mdp4_round_pixclk(struct msm_kms * kms,unsigned long rate,struct drm_encoder * encoder)112 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
113 struct drm_encoder *encoder)
114 {
115 /* if we had >1 encoder, we'd need something more clever: */
116 switch (encoder->encoder_type) {
117 case DRM_MODE_ENCODER_TMDS:
118 return mdp4_dtv_round_pixclk(encoder, rate);
119 case DRM_MODE_ENCODER_LVDS:
120 case DRM_MODE_ENCODER_DSI:
121 default:
122 return rate;
123 }
124 }
125
mdp4_destroy(struct msm_kms * kms)126 static void mdp4_destroy(struct msm_kms *kms)
127 {
128 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
129 struct device *dev = mdp4_kms->dev->dev;
130 struct msm_gem_address_space *aspace = kms->aspace;
131
132 if (mdp4_kms->blank_cursor_iova)
133 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
134 drm_gem_object_put(mdp4_kms->blank_cursor_bo);
135
136 if (aspace) {
137 aspace->mmu->funcs->detach(aspace->mmu);
138 msm_gem_address_space_put(aspace);
139 }
140
141 if (mdp4_kms->rpm_enabled)
142 pm_runtime_disable(dev);
143
144 kfree(mdp4_kms);
145 }
146
147 static const struct mdp_kms_funcs kms_funcs = {
148 .base = {
149 .hw_init = mdp4_hw_init,
150 .irq_preinstall = mdp4_irq_preinstall,
151 .irq_postinstall = mdp4_irq_postinstall,
152 .irq_uninstall = mdp4_irq_uninstall,
153 .irq = mdp4_irq,
154 .enable_vblank = mdp4_enable_vblank,
155 .disable_vblank = mdp4_disable_vblank,
156 .enable_commit = mdp4_enable_commit,
157 .disable_commit = mdp4_disable_commit,
158 .prepare_commit = mdp4_prepare_commit,
159 .flush_commit = mdp4_flush_commit,
160 .wait_flush = mdp4_wait_flush,
161 .complete_commit = mdp4_complete_commit,
162 .get_format = mdp_get_format,
163 .round_pixclk = mdp4_round_pixclk,
164 .destroy = mdp4_destroy,
165 },
166 .set_irqmask = mdp4_set_irqmask,
167 };
168
mdp4_disable(struct mdp4_kms * mdp4_kms)169 int mdp4_disable(struct mdp4_kms *mdp4_kms)
170 {
171 DBG("");
172
173 clk_disable_unprepare(mdp4_kms->clk);
174 if (mdp4_kms->pclk)
175 clk_disable_unprepare(mdp4_kms->pclk);
176 if (mdp4_kms->lut_clk)
177 clk_disable_unprepare(mdp4_kms->lut_clk);
178 if (mdp4_kms->axi_clk)
179 clk_disable_unprepare(mdp4_kms->axi_clk);
180
181 return 0;
182 }
183
mdp4_enable(struct mdp4_kms * mdp4_kms)184 int mdp4_enable(struct mdp4_kms *mdp4_kms)
185 {
186 DBG("");
187
188 clk_prepare_enable(mdp4_kms->clk);
189 if (mdp4_kms->pclk)
190 clk_prepare_enable(mdp4_kms->pclk);
191 if (mdp4_kms->lut_clk)
192 clk_prepare_enable(mdp4_kms->lut_clk);
193 if (mdp4_kms->axi_clk)
194 clk_prepare_enable(mdp4_kms->axi_clk);
195
196 return 0;
197 }
198
199
mdp4_modeset_init_intf(struct mdp4_kms * mdp4_kms,int intf_type)200 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
201 int intf_type)
202 {
203 struct drm_device *dev = mdp4_kms->dev;
204 struct msm_drm_private *priv = dev->dev_private;
205 struct drm_encoder *encoder;
206 struct drm_connector *connector;
207 struct device_node *panel_node;
208 int dsi_id;
209 int ret;
210
211 switch (intf_type) {
212 case DRM_MODE_ENCODER_LVDS:
213 /*
214 * bail out early if there is no panel node (no need to
215 * initialize LCDC encoder and LVDS connector)
216 */
217 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
218 if (!panel_node)
219 return 0;
220
221 encoder = mdp4_lcdc_encoder_init(dev, panel_node);
222 if (IS_ERR(encoder)) {
223 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
224 return PTR_ERR(encoder);
225 }
226
227 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
228 encoder->possible_crtcs = 1 << DMA_P;
229
230 connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
231 if (IS_ERR(connector)) {
232 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
233 return PTR_ERR(connector);
234 }
235
236 priv->encoders[priv->num_encoders++] = encoder;
237 priv->connectors[priv->num_connectors++] = connector;
238
239 break;
240 case DRM_MODE_ENCODER_TMDS:
241 encoder = mdp4_dtv_encoder_init(dev);
242 if (IS_ERR(encoder)) {
243 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n");
244 return PTR_ERR(encoder);
245 }
246
247 /* DTV can be hooked to DMA_E: */
248 encoder->possible_crtcs = 1 << 1;
249
250 if (priv->hdmi) {
251 /* Construct bridge/connector for HDMI: */
252 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
253 if (ret) {
254 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret);
255 return ret;
256 }
257 }
258
259 priv->encoders[priv->num_encoders++] = encoder;
260
261 break;
262 case DRM_MODE_ENCODER_DSI:
263 /* only DSI1 supported for now */
264 dsi_id = 0;
265
266 if (!priv->dsi[dsi_id])
267 break;
268
269 encoder = mdp4_dsi_encoder_init(dev);
270 if (IS_ERR(encoder)) {
271 ret = PTR_ERR(encoder);
272 DRM_DEV_ERROR(dev->dev,
273 "failed to construct DSI encoder: %d\n", ret);
274 return ret;
275 }
276
277 /* TODO: Add DMA_S later? */
278 encoder->possible_crtcs = 1 << DMA_P;
279 priv->encoders[priv->num_encoders++] = encoder;
280
281 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
282 if (ret) {
283 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n",
284 ret);
285 return ret;
286 }
287
288 break;
289 default:
290 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n");
291 return -EINVAL;
292 }
293
294 return 0;
295 }
296
modeset_init(struct mdp4_kms * mdp4_kms)297 static int modeset_init(struct mdp4_kms *mdp4_kms)
298 {
299 struct drm_device *dev = mdp4_kms->dev;
300 struct msm_drm_private *priv = dev->dev_private;
301 struct drm_plane *plane;
302 struct drm_crtc *crtc;
303 int i, ret;
304 static const enum mdp4_pipe rgb_planes[] = {
305 RGB1, RGB2,
306 };
307 static const enum mdp4_pipe vg_planes[] = {
308 VG1, VG2,
309 };
310 static const enum mdp4_dma mdp4_crtcs[] = {
311 DMA_P, DMA_E,
312 };
313 static const char * const mdp4_crtc_names[] = {
314 "DMA_P", "DMA_E",
315 };
316 static const int mdp4_intfs[] = {
317 DRM_MODE_ENCODER_LVDS,
318 DRM_MODE_ENCODER_DSI,
319 DRM_MODE_ENCODER_TMDS,
320 };
321
322 /* construct non-private planes: */
323 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
324 plane = mdp4_plane_init(dev, vg_planes[i], false);
325 if (IS_ERR(plane)) {
326 DRM_DEV_ERROR(dev->dev,
327 "failed to construct plane for VG%d\n", i + 1);
328 ret = PTR_ERR(plane);
329 goto fail;
330 }
331 priv->planes[priv->num_planes++] = plane;
332 }
333
334 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
335 plane = mdp4_plane_init(dev, rgb_planes[i], true);
336 if (IS_ERR(plane)) {
337 DRM_DEV_ERROR(dev->dev,
338 "failed to construct plane for RGB%d\n", i + 1);
339 ret = PTR_ERR(plane);
340 goto fail;
341 }
342
343 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
344 mdp4_crtcs[i]);
345 if (IS_ERR(crtc)) {
346 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n",
347 mdp4_crtc_names[i]);
348 ret = PTR_ERR(crtc);
349 goto fail;
350 }
351
352 priv->crtcs[priv->num_crtcs++] = crtc;
353 }
354
355 /*
356 * we currently set up two relatively fixed paths:
357 *
358 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
359 * or
360 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
361 *
362 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
363 */
364
365 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
366 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
367 if (ret) {
368 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n",
369 i, ret);
370 goto fail;
371 }
372 }
373
374 return 0;
375
376 fail:
377 return ret;
378 }
379
read_mdp_hw_revision(struct mdp4_kms * mdp4_kms,u32 * major,u32 * minor)380 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,
381 u32 *major, u32 *minor)
382 {
383 struct drm_device *dev = mdp4_kms->dev;
384 u32 version;
385
386 mdp4_enable(mdp4_kms);
387 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
388 mdp4_disable(mdp4_kms);
389
390 *major = FIELD(version, MDP4_VERSION_MAJOR);
391 *minor = FIELD(version, MDP4_VERSION_MINOR);
392
393 DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor);
394 }
395
mdp4_kms_init(struct drm_device * dev)396 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
397 {
398 struct platform_device *pdev = to_platform_device(dev->dev);
399 struct mdp4_platform_config *config = mdp4_get_config(pdev);
400 struct msm_drm_private *priv = dev->dev_private;
401 struct mdp4_kms *mdp4_kms;
402 struct msm_kms *kms = NULL;
403 struct msm_gem_address_space *aspace;
404 int irq, ret;
405 u32 major, minor;
406
407 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
408 if (!mdp4_kms) {
409 DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n");
410 ret = -ENOMEM;
411 goto fail;
412 }
413
414 mdp_kms_init(&mdp4_kms->base, &kms_funcs);
415
416 priv->kms = &mdp4_kms->base.base;
417 kms = priv->kms;
418
419 mdp4_kms->dev = dev;
420
421 mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
422 if (IS_ERR(mdp4_kms->mmio)) {
423 ret = PTR_ERR(mdp4_kms->mmio);
424 goto fail;
425 }
426
427 irq = platform_get_irq(pdev, 0);
428 if (irq < 0) {
429 ret = irq;
430 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
431 goto fail;
432 }
433
434 kms->irq = irq;
435
436 /* NOTE: driver for this regulator still missing upstream.. use
437 * _get_exclusive() and ignore the error if it does not exist
438 * (and hope that the bootloader left it on for us)
439 */
440 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
441 if (IS_ERR(mdp4_kms->vdd))
442 mdp4_kms->vdd = NULL;
443
444 if (mdp4_kms->vdd) {
445 ret = regulator_enable(mdp4_kms->vdd);
446 if (ret) {
447 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret);
448 goto fail;
449 }
450 }
451
452 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
453 if (IS_ERR(mdp4_kms->clk)) {
454 DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n");
455 ret = PTR_ERR(mdp4_kms->clk);
456 goto fail;
457 }
458
459 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
460 if (IS_ERR(mdp4_kms->pclk))
461 mdp4_kms->pclk = NULL;
462
463 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
464 if (IS_ERR(mdp4_kms->axi_clk)) {
465 DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n");
466 ret = PTR_ERR(mdp4_kms->axi_clk);
467 goto fail;
468 }
469
470 clk_set_rate(mdp4_kms->clk, config->max_clk);
471
472 read_mdp_hw_revision(mdp4_kms, &major, &minor);
473
474 if (major != 4) {
475 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
476 major, minor);
477 ret = -ENXIO;
478 goto fail;
479 }
480
481 mdp4_kms->rev = minor;
482
483 if (mdp4_kms->rev >= 2) {
484 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
485 if (IS_ERR(mdp4_kms->lut_clk)) {
486 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
487 ret = PTR_ERR(mdp4_kms->lut_clk);
488 goto fail;
489 }
490 clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
491 }
492
493 pm_runtime_enable(dev->dev);
494 mdp4_kms->rpm_enabled = true;
495
496 /* make sure things are off before attaching iommu (bootloader could
497 * have left things on, in which case we'll start getting faults if
498 * we don't disable):
499 */
500 mdp4_enable(mdp4_kms);
501 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
502 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
503 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
504 mdp4_disable(mdp4_kms);
505 mdelay(16);
506
507 if (config->iommu) {
508 struct msm_mmu *mmu = msm_iommu_new(&pdev->dev,
509 config->iommu);
510
511 aspace = msm_gem_address_space_create(mmu,
512 "mdp4", 0x1000, 0x100000000 - 0x1000);
513
514 if (IS_ERR(aspace)) {
515 if (!IS_ERR(mmu))
516 mmu->funcs->destroy(mmu);
517 ret = PTR_ERR(aspace);
518 goto fail;
519 }
520
521 kms->aspace = aspace;
522 } else {
523 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
524 "contig buffers for scanout\n");
525 aspace = NULL;
526 }
527
528 ret = modeset_init(mdp4_kms);
529 if (ret) {
530 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
531 goto fail;
532 }
533
534 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT);
535 if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
536 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
537 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
538 mdp4_kms->blank_cursor_bo = NULL;
539 goto fail;
540 }
541
542 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
543 &mdp4_kms->blank_cursor_iova);
544 if (ret) {
545 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
546 goto fail;
547 }
548
549 dev->mode_config.min_width = 0;
550 dev->mode_config.min_height = 0;
551 dev->mode_config.max_width = 2048;
552 dev->mode_config.max_height = 2048;
553
554 return kms;
555
556 fail:
557 if (kms)
558 mdp4_destroy(kms);
559 return ERR_PTR(ret);
560 }
561
mdp4_get_config(struct platform_device * dev)562 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
563 {
564 static struct mdp4_platform_config config = {};
565
566 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
567 config.max_clk = 266667000;
568 config.iommu = iommu_domain_alloc(&platform_bus_type);
569
570 return &config;
571 }
572