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1 /*
2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3  *
4  * Copyright (c) 2008-2009 USI Co., Ltd.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14  *    substantially similar to the "NO WARRANTY" disclaimer below
15  *    ("Disclaimer") and any redistribution must be conditioned upon
16  *    including a substantially similar Disclaimer requirement for further
17  *    binary redistribution.
18  * 3. Neither the names of the above-listed copyright holders nor the names
19  *    of any contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  * Alternatively, this software may be distributed under the terms of the
23  * GNU General Public License ("GPL") version 2 as published by the Free
24  * Software Foundation.
25  *
26  * NO WARRANTY
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGES.
38  *
39  */
40  #include <linux/slab.h>
41  #include "pm8001_sas.h"
42  #include "pm8001_hwi.h"
43  #include "pm8001_chips.h"
44  #include "pm8001_ctl.h"
45 
46 /**
47  * read_main_config_table - read the configure table and save it.
48  * @pm8001_ha: our hba card information
49  */
read_main_config_table(struct pm8001_hba_info * pm8001_ha)50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
51 {
52 	void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
53 	pm8001_ha->main_cfg_tbl.pm8001_tbl.signature	=
54 				pm8001_mr32(address, 0x00);
55 	pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
56 				pm8001_mr32(address, 0x04);
57 	pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev	=
58 				pm8001_mr32(address, 0x08);
59 	pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io	=
60 				pm8001_mr32(address, 0x0C);
61 	pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl	=
62 				pm8001_mr32(address, 0x10);
63 	pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
64 				pm8001_mr32(address, 0x14);
65 	pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset	=
66 				pm8001_mr32(address, 0x18);
67 	pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
68 		pm8001_mr32(address, MAIN_IBQ_OFFSET);
69 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
70 		pm8001_mr32(address, MAIN_OBQ_OFFSET);
71 	pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag	=
72 		pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
73 
74 	/* read analog Setting offset from the configuration table */
75 	pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
76 		pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
77 
78 	/* read Error Dump Offset and Length */
79 	pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
80 		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
81 	pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
82 		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
83 	pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
84 		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
85 	pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
86 		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
87 }
88 
89 /**
90  * read_general_status_table - read the general status table and save it.
91  * @pm8001_ha: our hba card information
92  */
read_general_status_table(struct pm8001_hba_info * pm8001_ha)93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
94 {
95 	void __iomem *address = pm8001_ha->general_stat_tbl_addr;
96 	pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate	=
97 				pm8001_mr32(address, 0x00);
98 	pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0	=
99 				pm8001_mr32(address, 0x04);
100 	pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1	=
101 				pm8001_mr32(address, 0x08);
102 	pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt		=
103 				pm8001_mr32(address, 0x0C);
104 	pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt		=
105 				pm8001_mr32(address, 0x10);
106 	pm8001_ha->gs_tbl.pm8001_tbl.rsvd		=
107 				pm8001_mr32(address, 0x14);
108 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]	=
109 				pm8001_mr32(address, 0x18);
110 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]	=
111 				pm8001_mr32(address, 0x1C);
112 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]	=
113 				pm8001_mr32(address, 0x20);
114 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]	=
115 				pm8001_mr32(address, 0x24);
116 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]	=
117 				pm8001_mr32(address, 0x28);
118 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]	=
119 				pm8001_mr32(address, 0x2C);
120 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]	=
121 				pm8001_mr32(address, 0x30);
122 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]	=
123 				pm8001_mr32(address, 0x34);
124 	pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val	=
125 				pm8001_mr32(address, 0x38);
126 	pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]		=
127 				pm8001_mr32(address, 0x3C);
128 	pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]		=
129 				pm8001_mr32(address, 0x40);
130 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]	=
131 				pm8001_mr32(address, 0x44);
132 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]	=
133 				pm8001_mr32(address, 0x48);
134 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]	=
135 				pm8001_mr32(address, 0x4C);
136 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]	=
137 				pm8001_mr32(address, 0x50);
138 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]	=
139 				pm8001_mr32(address, 0x54);
140 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]	=
141 				pm8001_mr32(address, 0x58);
142 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]	=
143 				pm8001_mr32(address, 0x5C);
144 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]	=
145 				pm8001_mr32(address, 0x60);
146 }
147 
148 /**
149  * read_inbnd_queue_table - read the inbound queue table and save it.
150  * @pm8001_ha: our hba card information
151  */
read_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha)152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
153 {
154 	int i;
155 	void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
156 	for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
157 		u32 offset = i * 0x20;
158 		pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
159 		      get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
160 		pm8001_ha->inbnd_q_tbl[i].pi_offset =
161 			pm8001_mr32(address, (offset + 0x18));
162 	}
163 }
164 
165 /**
166  * read_outbnd_queue_table - read the outbound queue table and save it.
167  * @pm8001_ha: our hba card information
168  */
read_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha)169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
170 {
171 	int i;
172 	void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
173 	for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
174 		u32 offset = i * 0x24;
175 		pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
176 		      get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
177 		pm8001_ha->outbnd_q_tbl[i].ci_offset =
178 			pm8001_mr32(address, (offset + 0x18));
179 	}
180 }
181 
182 /**
183  * init_default_table_values - init the default table.
184  * @pm8001_ha: our hba card information
185  */
init_default_table_values(struct pm8001_hba_info * pm8001_ha)186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
187 {
188 	int i;
189 	u32 offsetib, offsetob;
190 	void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
191 	void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
192 	u32 ib_offset = pm8001_ha->ib_offset;
193 	u32 ob_offset = pm8001_ha->ob_offset;
194 	u32 ci_offset = pm8001_ha->ci_offset;
195 	u32 pi_offset = pm8001_ha->pi_offset;
196 
197 	pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd		= 0;
198 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3	= 0;
199 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7	= 0;
200 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3	= 0;
201 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7	= 0;
202 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
203 									 0;
204 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
205 									 0;
206 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
207 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
208 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
209 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
210 
211 	pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr		=
212 		pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
213 	pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr		=
214 		pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
215 	pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size		=
216 		PM8001_EVENT_LOG_SIZE;
217 	pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option		= 0x01;
218 	pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr	=
219 		pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
220 	pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr	=
221 		pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
222 	pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size		=
223 		PM8001_EVENT_LOG_SIZE;
224 	pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option		= 0x01;
225 	pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt		= 0x01;
226 	for (i = 0; i < pm8001_ha->max_q_num; i++) {
227 		pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt	=
228 			PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
229 		pm8001_ha->inbnd_q_tbl[i].upper_base_addr	=
230 			pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
231 		pm8001_ha->inbnd_q_tbl[i].lower_base_addr	=
232 		pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
233 		pm8001_ha->inbnd_q_tbl[i].base_virt		=
234 		  (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
235 		pm8001_ha->inbnd_q_tbl[i].total_length		=
236 			pm8001_ha->memoryMap.region[ib_offset + i].total_len;
237 		pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr	=
238 			pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
239 		pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr	=
240 			pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
241 		pm8001_ha->inbnd_q_tbl[i].ci_virt		=
242 			pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
243 		offsetib = i * 0x20;
244 		pm8001_ha->inbnd_q_tbl[i].pi_pci_bar		=
245 			get_pci_bar_index(pm8001_mr32(addressib,
246 				(offsetib + 0x14)));
247 		pm8001_ha->inbnd_q_tbl[i].pi_offset		=
248 			pm8001_mr32(addressib, (offsetib + 0x18));
249 		pm8001_ha->inbnd_q_tbl[i].producer_idx		= 0;
250 		pm8001_ha->inbnd_q_tbl[i].consumer_index	= 0;
251 	}
252 	for (i = 0; i < pm8001_ha->max_q_num; i++) {
253 		pm8001_ha->outbnd_q_tbl[i].element_size_cnt	=
254 			PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
255 		pm8001_ha->outbnd_q_tbl[i].upper_base_addr	=
256 			pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
257 		pm8001_ha->outbnd_q_tbl[i].lower_base_addr	=
258 			pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
259 		pm8001_ha->outbnd_q_tbl[i].base_virt		=
260 		  (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
261 		pm8001_ha->outbnd_q_tbl[i].total_length		=
262 			pm8001_ha->memoryMap.region[ob_offset + i].total_len;
263 		pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr	=
264 			pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
265 		pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr	=
266 			pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
267 		pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay	=
268 			0 | (10 << 16) | (i << 24);
269 		pm8001_ha->outbnd_q_tbl[i].pi_virt		=
270 			pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
271 		offsetob = i * 0x24;
272 		pm8001_ha->outbnd_q_tbl[i].ci_pci_bar		=
273 			get_pci_bar_index(pm8001_mr32(addressob,
274 			offsetob + 0x14));
275 		pm8001_ha->outbnd_q_tbl[i].ci_offset		=
276 			pm8001_mr32(addressob, (offsetob + 0x18));
277 		pm8001_ha->outbnd_q_tbl[i].consumer_idx		= 0;
278 		pm8001_ha->outbnd_q_tbl[i].producer_index	= 0;
279 	}
280 }
281 
282 /**
283  * update_main_config_table - update the main default table to the HBA.
284  * @pm8001_ha: our hba card information
285  */
update_main_config_table(struct pm8001_hba_info * pm8001_ha)286 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
287 {
288 	void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
289 	pm8001_mw32(address, 0x24,
290 		pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
291 	pm8001_mw32(address, 0x28,
292 		pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
293 	pm8001_mw32(address, 0x2C,
294 		pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
295 	pm8001_mw32(address, 0x30,
296 		pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
297 	pm8001_mw32(address, 0x34,
298 		pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
299 	pm8001_mw32(address, 0x38,
300 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
301 					outbound_tgt_ITNexus_event_pid0_3);
302 	pm8001_mw32(address, 0x3C,
303 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
304 					outbound_tgt_ITNexus_event_pid4_7);
305 	pm8001_mw32(address, 0x40,
306 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
307 					outbound_tgt_ssp_event_pid0_3);
308 	pm8001_mw32(address, 0x44,
309 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
310 					outbound_tgt_ssp_event_pid4_7);
311 	pm8001_mw32(address, 0x48,
312 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
313 					outbound_tgt_smp_event_pid0_3);
314 	pm8001_mw32(address, 0x4C,
315 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
316 					outbound_tgt_smp_event_pid4_7);
317 	pm8001_mw32(address, 0x50,
318 		pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
319 	pm8001_mw32(address, 0x54,
320 		pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
321 	pm8001_mw32(address, 0x58,
322 		pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
323 	pm8001_mw32(address, 0x5C,
324 		pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
325 	pm8001_mw32(address, 0x60,
326 		pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
327 	pm8001_mw32(address, 0x64,
328 		pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
329 	pm8001_mw32(address, 0x68,
330 		pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
331 	pm8001_mw32(address, 0x6C,
332 		pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
333 	pm8001_mw32(address, 0x70,
334 		pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
335 }
336 
337 /**
338  * update_inbnd_queue_table - update the inbound queue table to the HBA.
339  * @pm8001_ha: our hba card information
340  * @number: entry in the queue
341  */
update_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)342 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
343 				     int number)
344 {
345 	void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
346 	u16 offset = number * 0x20;
347 	pm8001_mw32(address, offset + 0x00,
348 		pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
349 	pm8001_mw32(address, offset + 0x04,
350 		pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
351 	pm8001_mw32(address, offset + 0x08,
352 		pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
353 	pm8001_mw32(address, offset + 0x0C,
354 		pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
355 	pm8001_mw32(address, offset + 0x10,
356 		pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
357 }
358 
359 /**
360  * update_outbnd_queue_table - update the outbound queue table to the HBA.
361  * @pm8001_ha: our hba card information
362  * @number: entry in the queue
363  */
update_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)364 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
365 				      int number)
366 {
367 	void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
368 	u16 offset = number * 0x24;
369 	pm8001_mw32(address, offset + 0x00,
370 		pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
371 	pm8001_mw32(address, offset + 0x04,
372 		pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
373 	pm8001_mw32(address, offset + 0x08,
374 		pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
375 	pm8001_mw32(address, offset + 0x0C,
376 		pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
377 	pm8001_mw32(address, offset + 0x10,
378 		pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
379 	pm8001_mw32(address, offset + 0x1C,
380 		pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
381 }
382 
383 /**
384  * pm8001_bar4_shift - function is called to shift BAR base address
385  * @pm8001_ha : our hba card infomation
386  * @shiftValue : shifting value in memory bar.
387  */
pm8001_bar4_shift(struct pm8001_hba_info * pm8001_ha,u32 shiftValue)388 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
389 {
390 	u32 regVal;
391 	unsigned long start;
392 
393 	/* program the inbound AXI translation Lower Address */
394 	pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
395 
396 	/* confirm the setting is written */
397 	start = jiffies + HZ; /* 1 sec */
398 	do {
399 		regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
400 	} while ((regVal != shiftValue) && time_before(jiffies, start));
401 
402 	if (regVal != shiftValue) {
403 		pm8001_dbg(pm8001_ha, INIT,
404 			   "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n",
405 			   regVal);
406 		return -1;
407 	}
408 	return 0;
409 }
410 
411 /**
412  * mpi_set_phys_g3_with_ssc
413  * @pm8001_ha: our hba card information
414  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
415  */
mpi_set_phys_g3_with_ssc(struct pm8001_hba_info * pm8001_ha,u32 SSCbit)416 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
417 				     u32 SSCbit)
418 {
419 	u32 value, offset, i;
420 	unsigned long flags;
421 
422 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
423 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
424 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
425 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
426 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
427 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
428 #define SNW3_PHY_CAPABILITIES_PARITY 31
429 
430    /*
431     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
432     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
433     */
434 	spin_lock_irqsave(&pm8001_ha->lock, flags);
435 	if (-1 == pm8001_bar4_shift(pm8001_ha,
436 				SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
437 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
438 		return;
439 	}
440 
441 	for (i = 0; i < 4; i++) {
442 		offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
443 		pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
444 	}
445 	/* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
446 	if (-1 == pm8001_bar4_shift(pm8001_ha,
447 				SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
448 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
449 		return;
450 	}
451 	for (i = 4; i < 8; i++) {
452 		offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
453 		pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
454 	}
455 	/*************************************************************
456 	Change the SSC upspreading value to 0x0 so that upspreading is disabled.
457 	Device MABC SMOD0 Controls
458 	Address: (via MEMBASE-III):
459 	Using shifted destination address 0x0_0000: with Offset 0xD8
460 
461 	31:28 R/W Reserved Do not change
462 	27:24 R/W SAS_SMOD_SPRDUP 0000
463 	23:20 R/W SAS_SMOD_SPRDDN 0000
464 	19:0  R/W  Reserved Do not change
465 	Upon power-up this register will read as 0x8990c016,
466 	and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
467 	so that the written value will be 0x8090c016.
468 	This will ensure only down-spreading SSC is enabled on the SPC.
469 	*************************************************************/
470 	value = pm8001_cr32(pm8001_ha, 2, 0xd8);
471 	pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
472 
473 	/*set the shifted destination address to 0x0 to avoid error operation */
474 	pm8001_bar4_shift(pm8001_ha, 0x0);
475 	spin_unlock_irqrestore(&pm8001_ha->lock, flags);
476 	return;
477 }
478 
479 /**
480  * mpi_set_open_retry_interval_reg
481  * @pm8001_ha: our hba card information
482  * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us.
483  */
mpi_set_open_retry_interval_reg(struct pm8001_hba_info * pm8001_ha,u32 interval)484 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
485 					    u32 interval)
486 {
487 	u32 offset;
488 	u32 value;
489 	u32 i;
490 	unsigned long flags;
491 
492 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
493 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
494 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
495 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
496 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
497 
498 	value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
499 	spin_lock_irqsave(&pm8001_ha->lock, flags);
500 	/* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
501 	if (-1 == pm8001_bar4_shift(pm8001_ha,
502 			     OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
503 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
504 		return;
505 	}
506 	for (i = 0; i < 4; i++) {
507 		offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
508 		pm8001_cw32(pm8001_ha, 2, offset, value);
509 	}
510 
511 	if (-1 == pm8001_bar4_shift(pm8001_ha,
512 			     OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
513 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
514 		return;
515 	}
516 	for (i = 4; i < 8; i++) {
517 		offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
518 		pm8001_cw32(pm8001_ha, 2, offset, value);
519 	}
520 	/*set the shifted destination address to 0x0 to avoid error operation */
521 	pm8001_bar4_shift(pm8001_ha, 0x0);
522 	spin_unlock_irqrestore(&pm8001_ha->lock, flags);
523 	return;
524 }
525 
526 /**
527  * mpi_init_check - check firmware initialization status.
528  * @pm8001_ha: our hba card information
529  */
mpi_init_check(struct pm8001_hba_info * pm8001_ha)530 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
531 {
532 	u32 max_wait_count;
533 	u32 value;
534 	u32 gst_len_mpistate;
535 	/* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
536 	table is updated */
537 	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
538 	/* wait until Inbound DoorBell Clear Register toggled */
539 	max_wait_count = 1 * 1000 * 1000;/* 1 sec */
540 	do {
541 		udelay(1);
542 		value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
543 		value &= SPC_MSGU_CFG_TABLE_UPDATE;
544 	} while ((value != 0) && (--max_wait_count));
545 
546 	if (!max_wait_count)
547 		return -1;
548 	/* check the MPI-State for initialization */
549 	gst_len_mpistate =
550 		pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
551 		GST_GSTLEN_MPIS_OFFSET);
552 	if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
553 		return -1;
554 	/* check MPI Initialization error */
555 	gst_len_mpistate = gst_len_mpistate >> 16;
556 	if (0x0000 != gst_len_mpistate)
557 		return -1;
558 	return 0;
559 }
560 
561 /**
562  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
563  * @pm8001_ha: our hba card information
564  */
check_fw_ready(struct pm8001_hba_info * pm8001_ha)565 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
566 {
567 	u32 value, value1;
568 	u32 max_wait_count;
569 	/* check error state */
570 	value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
571 	value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
572 	/* check AAP error */
573 	if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
574 		/* error state */
575 		value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
576 		return -1;
577 	}
578 
579 	/* check IOP error */
580 	if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
581 		/* error state */
582 		value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
583 		return -1;
584 	}
585 
586 	/* bit 4-31 of scratch pad1 should be zeros if it is not
587 	in error state*/
588 	if (value & SCRATCH_PAD1_STATE_MASK) {
589 		/* error case */
590 		pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
591 		return -1;
592 	}
593 
594 	/* bit 2, 4-31 of scratch pad2 should be zeros if it is not
595 	in error state */
596 	if (value1 & SCRATCH_PAD2_STATE_MASK) {
597 		/* error case */
598 		return -1;
599 	}
600 
601 	max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
602 
603 	/* wait until scratch pad 1 and 2 registers in ready state  */
604 	do {
605 		udelay(1);
606 		value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
607 			& SCRATCH_PAD1_RDY;
608 		value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
609 			& SCRATCH_PAD2_RDY;
610 		if ((--max_wait_count) == 0)
611 			return -1;
612 	} while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
613 	return 0;
614 }
615 
init_pci_device_addresses(struct pm8001_hba_info * pm8001_ha)616 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
617 {
618 	void __iomem *base_addr;
619 	u32	value;
620 	u32	offset;
621 	u32	pcibar;
622 	u32	pcilogic;
623 
624 	value = pm8001_cr32(pm8001_ha, 0, 0x44);
625 	offset = value & 0x03FFFFFF;
626 	pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset);
627 	pcilogic = (value & 0xFC000000) >> 26;
628 	pcibar = get_pci_bar_index(pcilogic);
629 	pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
630 	pm8001_ha->main_cfg_tbl_addr = base_addr =
631 		pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
632 	pm8001_ha->general_stat_tbl_addr =
633 		base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
634 	pm8001_ha->inbnd_q_tbl_addr =
635 		base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
636 	pm8001_ha->outbnd_q_tbl_addr =
637 		base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
638 }
639 
640 /**
641  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
642  * @pm8001_ha: our hba card information
643  */
pm8001_chip_init(struct pm8001_hba_info * pm8001_ha)644 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
645 {
646 	u32 i = 0;
647 	u16 deviceid;
648 	pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
649 	/* 8081 controllers need BAR shift to access MPI space
650 	* as this is shared with BIOS data */
651 	if (deviceid == 0x8081 || deviceid == 0x0042) {
652 		if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
653 			pm8001_dbg(pm8001_ha, FAIL,
654 				   "Shift Bar4 to 0x%x failed\n",
655 				   GSM_SM_BASE);
656 			return -1;
657 		}
658 	}
659 	/* check the firmware status */
660 	if (-1 == check_fw_ready(pm8001_ha)) {
661 		pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
662 		return -EBUSY;
663 	}
664 
665 	/* Initialize pci space address eg: mpi offset */
666 	init_pci_device_addresses(pm8001_ha);
667 	init_default_table_values(pm8001_ha);
668 	read_main_config_table(pm8001_ha);
669 	read_general_status_table(pm8001_ha);
670 	read_inbnd_queue_table(pm8001_ha);
671 	read_outbnd_queue_table(pm8001_ha);
672 	/* update main config table ,inbound table and outbound table */
673 	update_main_config_table(pm8001_ha);
674 	for (i = 0; i < pm8001_ha->max_q_num; i++)
675 		update_inbnd_queue_table(pm8001_ha, i);
676 	for (i = 0; i < pm8001_ha->max_q_num; i++)
677 		update_outbnd_queue_table(pm8001_ha, i);
678 	/* 8081 controller donot require these operations */
679 	if (deviceid != 0x8081 && deviceid != 0x0042) {
680 		mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
681 		/* 7->130ms, 34->500ms, 119->1.5s */
682 		mpi_set_open_retry_interval_reg(pm8001_ha, 119);
683 	}
684 	/* notify firmware update finished and check initialization status */
685 	if (0 == mpi_init_check(pm8001_ha)) {
686 		pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
687 	} else
688 		return -EBUSY;
689 	/*This register is a 16-bit timer with a resolution of 1us. This is the
690 	timer used for interrupt delay/coalescing in the PCIe Application Layer.
691 	Zero is not a valid value. A value of 1 in the register will cause the
692 	interrupts to be normal. A value greater than 1 will cause coalescing
693 	delays.*/
694 	pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
695 	pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
696 	return 0;
697 }
698 
mpi_uninit_check(struct pm8001_hba_info * pm8001_ha)699 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
700 {
701 	u32 max_wait_count;
702 	u32 value;
703 	u32 gst_len_mpistate;
704 	u16 deviceid;
705 	pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
706 	if (deviceid == 0x8081 || deviceid == 0x0042) {
707 		if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
708 			pm8001_dbg(pm8001_ha, FAIL,
709 				   "Shift Bar4 to 0x%x failed\n",
710 				   GSM_SM_BASE);
711 			return -1;
712 		}
713 	}
714 	init_pci_device_addresses(pm8001_ha);
715 	/* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
716 	table is stop */
717 	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
718 
719 	/* wait until Inbound DoorBell Clear Register toggled */
720 	max_wait_count = 1 * 1000 * 1000;/* 1 sec */
721 	do {
722 		udelay(1);
723 		value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
724 		value &= SPC_MSGU_CFG_TABLE_RESET;
725 	} while ((value != 0) && (--max_wait_count));
726 
727 	if (!max_wait_count) {
728 		pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n",
729 			   value);
730 		return -1;
731 	}
732 
733 	/* check the MPI-State for termination in progress */
734 	/* wait until Inbound DoorBell Clear Register toggled */
735 	max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
736 	do {
737 		udelay(1);
738 		gst_len_mpistate =
739 			pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
740 			GST_GSTLEN_MPIS_OFFSET);
741 		if (GST_MPI_STATE_UNINIT ==
742 			(gst_len_mpistate & GST_MPI_STATE_MASK))
743 			break;
744 	} while (--max_wait_count);
745 	if (!max_wait_count) {
746 		pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
747 			   gst_len_mpistate & GST_MPI_STATE_MASK);
748 		return -1;
749 	}
750 	return 0;
751 }
752 
753 /**
754  * soft_reset_ready_check - Function to check FW is ready for soft reset.
755  * @pm8001_ha: our hba card information
756  */
soft_reset_ready_check(struct pm8001_hba_info * pm8001_ha)757 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
758 {
759 	u32 regVal, regVal1, regVal2;
760 	if (mpi_uninit_check(pm8001_ha) != 0) {
761 		pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n");
762 		return -1;
763 	}
764 	/* read the scratch pad 2 register bit 2 */
765 	regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
766 		& SCRATCH_PAD2_FWRDY_RST;
767 	if (regVal == SCRATCH_PAD2_FWRDY_RST) {
768 		pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n");
769 	} else {
770 		unsigned long flags;
771 		/* Trigger NMI twice via RB6 */
772 		spin_lock_irqsave(&pm8001_ha->lock, flags);
773 		if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
774 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
775 			pm8001_dbg(pm8001_ha, FAIL,
776 				   "Shift Bar4 to 0x%x failed\n",
777 				   RB6_ACCESS_REG);
778 			return -1;
779 		}
780 		pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
781 			RB6_MAGIC_NUMBER_RST);
782 		pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
783 		/* wait for 100 ms */
784 		mdelay(100);
785 		regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
786 			SCRATCH_PAD2_FWRDY_RST;
787 		if (regVal != SCRATCH_PAD2_FWRDY_RST) {
788 			regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
789 			regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
790 			pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
791 				   regVal1, regVal2);
792 			pm8001_dbg(pm8001_ha, FAIL,
793 				   "SCRATCH_PAD0 value = 0x%x\n",
794 				   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
795 			pm8001_dbg(pm8001_ha, FAIL,
796 				   "SCRATCH_PAD3 value = 0x%x\n",
797 				   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
798 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
799 			return -1;
800 		}
801 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
802 	}
803 	return 0;
804 }
805 
806 /**
807  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
808  * the FW register status to the originated status.
809  * @pm8001_ha: our hba card information
810  */
811 static int
pm8001_chip_soft_rst(struct pm8001_hba_info * pm8001_ha)812 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
813 {
814 	u32	regVal, toggleVal;
815 	u32	max_wait_count;
816 	u32	regVal1, regVal2, regVal3;
817 	u32	signature = 0x252acbcd; /* for host scratch pad0 */
818 	unsigned long flags;
819 
820 	/* step1: Check FW is ready for soft reset */
821 	if (soft_reset_ready_check(pm8001_ha) != 0) {
822 		pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n");
823 		return -1;
824 	}
825 
826 	/* step 2: clear NMI status register on AAP1 and IOP, write the same
827 	value to clear */
828 	/* map 0x60000 to BAR4(0x20), BAR2(win) */
829 	spin_lock_irqsave(&pm8001_ha->lock, flags);
830 	if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
831 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
832 		pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
833 			   MBIC_AAP1_ADDR_BASE);
834 		return -1;
835 	}
836 	regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
837 	pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n",
838 		   regVal);
839 	pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
840 	/* map 0x70000 to BAR4(0x20), BAR2(win) */
841 	if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
842 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
843 		pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
844 			   MBIC_IOP_ADDR_BASE);
845 		return -1;
846 	}
847 	regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
848 	pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n",
849 		   regVal);
850 	pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
851 
852 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
853 	pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n",
854 		   regVal);
855 	pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
856 
857 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
858 	pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt  = 0x%x\n",
859 		   regVal);
860 	pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
861 
862 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
863 	pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n",
864 		   regVal);
865 	pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
866 
867 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
868 	pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
869 	pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
870 
871 	/* read the scratch pad 1 register bit 2 */
872 	regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
873 		& SCRATCH_PAD1_RST;
874 	toggleVal = regVal ^ SCRATCH_PAD1_RST;
875 
876 	/* set signature in host scratch pad0 register to tell SPC that the
877 	host performs the soft reset */
878 	pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
879 
880 	/* read required registers for confirmming */
881 	/* map 0x0700000 to BAR4(0x20), BAR2(win) */
882 	if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
883 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
884 		pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
885 			   GSM_ADDR_BASE);
886 		return -1;
887 	}
888 	pm8001_dbg(pm8001_ha, INIT,
889 		   "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n",
890 		   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
891 
892 	/* step 3: host read GSM Configuration and Reset register */
893 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
894 	/* Put those bits to low */
895 	/* GSM XCBI offset = 0x70 0000
896 	0x00 Bit 13 COM_SLV_SW_RSTB 1
897 	0x00 Bit 12 QSSP_SW_RSTB 1
898 	0x00 Bit 11 RAAE_SW_RSTB 1
899 	0x00 Bit 9 RB_1_SW_RSTB 1
900 	0x00 Bit 8 SM_SW_RSTB 1
901 	*/
902 	regVal &= ~(0x00003b00);
903 	/* host write GSM Configuration and Reset register */
904 	pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
905 	pm8001_dbg(pm8001_ha, INIT,
906 		   "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n",
907 		   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
908 
909 	/* step 4: */
910 	/* disable GSM - Read Address Parity Check */
911 	regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
912 	pm8001_dbg(pm8001_ha, INIT,
913 		   "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
914 		   regVal1);
915 	pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
916 	pm8001_dbg(pm8001_ha, INIT,
917 		   "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
918 		   pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
919 
920 	/* disable GSM - Write Address Parity Check */
921 	regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
922 	pm8001_dbg(pm8001_ha, INIT,
923 		   "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n",
924 		   regVal2);
925 	pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
926 	pm8001_dbg(pm8001_ha, INIT,
927 		   "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
928 		   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
929 
930 	/* disable GSM - Write Data Parity Check */
931 	regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
932 	pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n",
933 		   regVal3);
934 	pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
935 	pm8001_dbg(pm8001_ha, INIT,
936 		   "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n",
937 		   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
938 
939 	/* step 5: delay 10 usec */
940 	udelay(10);
941 	/* step 5-b: set GPIO-0 output control to tristate anyway */
942 	if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
943 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
944 		pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n",
945 			   GPIO_ADDR_BASE);
946 		return -1;
947 	}
948 	regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
949 	pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n",
950 		   regVal);
951 	/* set GPIO-0 output control to tri-state */
952 	regVal &= 0xFFFFFFFC;
953 	pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
954 
955 	/* Step 6: Reset the IOP and AAP1 */
956 	/* map 0x00000 to BAR4(0x20), BAR2(win) */
957 	if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
958 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
959 		pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
960 			   SPC_TOP_LEVEL_ADDR_BASE);
961 		return -1;
962 	}
963 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
964 	pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n",
965 		   regVal);
966 	regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
967 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
968 
969 	/* step 7: Reset the BDMA/OSSP */
970 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
971 	pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n",
972 		   regVal);
973 	regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
974 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
975 
976 	/* step 8: delay 10 usec */
977 	udelay(10);
978 
979 	/* step 9: bring the BDMA and OSSP out of reset */
980 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
981 	pm8001_dbg(pm8001_ha, INIT,
982 		   "Top Register before bringing up BDMA/OSSP:= 0x%x\n",
983 		   regVal);
984 	regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
985 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
986 
987 	/* step 10: delay 10 usec */
988 	udelay(10);
989 
990 	/* step 11: reads and sets the GSM Configuration and Reset Register */
991 	/* map 0x0700000 to BAR4(0x20), BAR2(win) */
992 	if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
993 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
994 		pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
995 			   GSM_ADDR_BASE);
996 		return -1;
997 	}
998 	pm8001_dbg(pm8001_ha, INIT,
999 		   "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n",
1000 		   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1001 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1002 	/* Put those bits to high */
1003 	/* GSM XCBI offset = 0x70 0000
1004 	0x00 Bit 13 COM_SLV_SW_RSTB 1
1005 	0x00 Bit 12 QSSP_SW_RSTB 1
1006 	0x00 Bit 11 RAAE_SW_RSTB 1
1007 	0x00 Bit 9   RB_1_SW_RSTB 1
1008 	0x00 Bit 8   SM_SW_RSTB 1
1009 	*/
1010 	regVal |= (GSM_CONFIG_RESET_VALUE);
1011 	pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1012 	pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n",
1013 		   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1014 
1015 	/* step 12: Restore GSM - Read Address Parity Check */
1016 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1017 	/* just for debugging */
1018 	pm8001_dbg(pm8001_ha, INIT,
1019 		   "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
1020 		   regVal);
1021 	pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1022 	pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
1023 		   pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
1024 	/* Restore GSM - Write Address Parity Check */
1025 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1026 	pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1027 	pm8001_dbg(pm8001_ha, INIT,
1028 		   "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
1029 		   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
1030 	/* Restore GSM - Write Data Parity Check */
1031 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1032 	pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1033 	pm8001_dbg(pm8001_ha, INIT,
1034 		   "GSM 0x700048 - Write Data Parity Check Enableis set to = 0x%x\n",
1035 		   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
1036 
1037 	/* step 13: bring the IOP and AAP1 out of reset */
1038 	/* map 0x00000 to BAR4(0x20), BAR2(win) */
1039 	if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1040 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1041 		pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
1042 			   SPC_TOP_LEVEL_ADDR_BASE);
1043 		return -1;
1044 	}
1045 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1046 	regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1047 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1048 
1049 	/* step 14: delay 10 usec - Normal Mode */
1050 	udelay(10);
1051 	/* check Soft Reset Normal mode or Soft Reset HDA mode */
1052 	if (signature == SPC_SOFT_RESET_SIGNATURE) {
1053 		/* step 15 (Normal Mode): wait until scratch pad1 register
1054 		bit 2 toggled */
1055 		max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1056 		do {
1057 			udelay(1);
1058 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1059 				SCRATCH_PAD1_RST;
1060 		} while ((regVal != toggleVal) && (--max_wait_count));
1061 
1062 		if (!max_wait_count) {
1063 			regVal = pm8001_cr32(pm8001_ha, 0,
1064 				MSGU_SCRATCH_PAD_1);
1065 			pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n",
1066 				   toggleVal, regVal);
1067 			pm8001_dbg(pm8001_ha, FAIL,
1068 				   "SCRATCH_PAD0 value = 0x%x\n",
1069 				   pm8001_cr32(pm8001_ha, 0,
1070 					       MSGU_SCRATCH_PAD_0));
1071 			pm8001_dbg(pm8001_ha, FAIL,
1072 				   "SCRATCH_PAD2 value = 0x%x\n",
1073 				   pm8001_cr32(pm8001_ha, 0,
1074 					       MSGU_SCRATCH_PAD_2));
1075 			pm8001_dbg(pm8001_ha, FAIL,
1076 				   "SCRATCH_PAD3 value = 0x%x\n",
1077 				   pm8001_cr32(pm8001_ha, 0,
1078 					       MSGU_SCRATCH_PAD_3));
1079 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1080 			return -1;
1081 		}
1082 
1083 		/* step 16 (Normal) - Clear ODMR and ODCR */
1084 		pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1085 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1086 
1087 		/* step 17 (Normal Mode): wait for the FW and IOP to get
1088 		ready - 1 sec timeout */
1089 		/* Wait for the SPC Configuration Table to be ready */
1090 		if (check_fw_ready(pm8001_ha) == -1) {
1091 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1092 			/* return error if MPI Configuration Table not ready */
1093 			pm8001_dbg(pm8001_ha, INIT,
1094 				   "FW not ready SCRATCH_PAD1 = 0x%x\n",
1095 				   regVal);
1096 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1097 			/* return error if MPI Configuration Table not ready */
1098 			pm8001_dbg(pm8001_ha, INIT,
1099 				   "FW not ready SCRATCH_PAD2 = 0x%x\n",
1100 				   regVal);
1101 			pm8001_dbg(pm8001_ha, INIT,
1102 				   "SCRATCH_PAD0 value = 0x%x\n",
1103 				   pm8001_cr32(pm8001_ha, 0,
1104 					       MSGU_SCRATCH_PAD_0));
1105 			pm8001_dbg(pm8001_ha, INIT,
1106 				   "SCRATCH_PAD3 value = 0x%x\n",
1107 				   pm8001_cr32(pm8001_ha, 0,
1108 					       MSGU_SCRATCH_PAD_3));
1109 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1110 			return -1;
1111 		}
1112 	}
1113 	pm8001_bar4_shift(pm8001_ha, 0);
1114 	spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1115 
1116 	pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1117 	return 0;
1118 }
1119 
pm8001_hw_chip_rst(struct pm8001_hba_info * pm8001_ha)1120 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1121 {
1122 	u32 i;
1123 	u32 regVal;
1124 	pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1125 
1126 	/* do SPC chip reset. */
1127 	regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1128 	regVal &= ~(SPC_REG_RESET_DEVICE);
1129 	pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1130 
1131 	/* delay 10 usec */
1132 	udelay(10);
1133 
1134 	/* bring chip reset out of reset */
1135 	regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1136 	regVal |= SPC_REG_RESET_DEVICE;
1137 	pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1138 
1139 	/* delay 10 usec */
1140 	udelay(10);
1141 
1142 	/* wait for 20 msec until the firmware gets reloaded */
1143 	i = 20;
1144 	do {
1145 		mdelay(1);
1146 	} while ((--i) != 0);
1147 
1148 	pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1149 }
1150 
1151 /**
1152  * pm8001_chip_iounmap - which maped when initialized.
1153  * @pm8001_ha: our hba card information
1154  */
pm8001_chip_iounmap(struct pm8001_hba_info * pm8001_ha)1155 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1156 {
1157 	s8 bar, logical = 0;
1158 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
1159 		/*
1160 		** logical BARs for SPC:
1161 		** bar 0 and 1 - logical BAR0
1162 		** bar 2 and 3 - logical BAR1
1163 		** bar4 - logical BAR2
1164 		** bar5 - logical BAR3
1165 		** Skip the appropriate assignments:
1166 		*/
1167 		if ((bar == 1) || (bar == 3))
1168 			continue;
1169 		if (pm8001_ha->io_mem[logical].memvirtaddr) {
1170 			iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1171 			logical++;
1172 		}
1173 	}
1174 }
1175 
1176 #ifndef PM8001_USE_MSIX
1177 /**
1178  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1179  * @pm8001_ha: our hba card information
1180  */
1181 static void
pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info * pm8001_ha)1182 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1183 {
1184 	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1185 	pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1186 }
1187 
1188  /**
1189   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1190   * @pm8001_ha: our hba card information
1191   */
1192 static void
pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info * pm8001_ha)1193 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1194 {
1195 	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1196 }
1197 
1198 #else
1199 
1200 /**
1201  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1202  * @pm8001_ha: our hba card information
1203  * @int_vec_idx: interrupt number to enable
1204  */
1205 static void
pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info * pm8001_ha,u32 int_vec_idx)1206 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1207 	u32 int_vec_idx)
1208 {
1209 	u32 msi_index;
1210 	u32 value;
1211 	msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1212 	msi_index += MSIX_TABLE_BASE;
1213 	pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1214 	value = (1 << int_vec_idx);
1215 	pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1216 
1217 }
1218 
1219 /**
1220  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1221  * @pm8001_ha: our hba card information
1222  * @int_vec_idx: interrupt number to disable
1223  */
1224 static void
pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info * pm8001_ha,u32 int_vec_idx)1225 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1226 	u32 int_vec_idx)
1227 {
1228 	u32 msi_index;
1229 	msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1230 	msi_index += MSIX_TABLE_BASE;
1231 	pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1232 }
1233 #endif
1234 
1235 /**
1236  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1237  * @pm8001_ha: our hba card information
1238  * @vec: unused
1239  */
1240 static void
pm8001_chip_interrupt_enable(struct pm8001_hba_info * pm8001_ha,u8 vec)1241 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1242 {
1243 #ifdef PM8001_USE_MSIX
1244 	pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1245 #else
1246 	pm8001_chip_intx_interrupt_enable(pm8001_ha);
1247 #endif
1248 }
1249 
1250 /**
1251  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1252  * @pm8001_ha: our hba card information
1253  * @vec: unused
1254  */
1255 static void
pm8001_chip_interrupt_disable(struct pm8001_hba_info * pm8001_ha,u8 vec)1256 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1257 {
1258 #ifdef PM8001_USE_MSIX
1259 	pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1260 #else
1261 	pm8001_chip_intx_interrupt_disable(pm8001_ha);
1262 #endif
1263 }
1264 
1265 /**
1266  * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1267  * inbound queue.
1268  * @circularQ: the inbound queue  we want to transfer to HBA.
1269  * @messageSize: the message size of this transfer, normally it is 64 bytes
1270  * @messagePtr: the pointer to message.
1271  */
pm8001_mpi_msg_free_get(struct inbound_queue_table * circularQ,u16 messageSize,void ** messagePtr)1272 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1273 			    u16 messageSize, void **messagePtr)
1274 {
1275 	u32 offset, consumer_index;
1276 	struct mpi_msg_hdr *msgHeader;
1277 	u8 bcCount = 1; /* only support single buffer */
1278 
1279 	/* Checks is the requested message size can be allocated in this queue*/
1280 	if (messageSize > IOMB_SIZE_SPCV) {
1281 		*messagePtr = NULL;
1282 		return -1;
1283 	}
1284 
1285 	/* Stores the new consumer index */
1286 	consumer_index = pm8001_read_32(circularQ->ci_virt);
1287 	circularQ->consumer_index = cpu_to_le32(consumer_index);
1288 	if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1289 		le32_to_cpu(circularQ->consumer_index)) {
1290 		*messagePtr = NULL;
1291 		return -1;
1292 	}
1293 	/* get memory IOMB buffer address */
1294 	offset = circularQ->producer_idx * messageSize;
1295 	/* increment to next bcCount element */
1296 	circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1297 				% PM8001_MPI_QUEUE;
1298 	/* Adds that distance to the base of the region virtual address plus
1299 	the message header size*/
1300 	msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt	+ offset);
1301 	*messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1302 	return 0;
1303 }
1304 
1305 /**
1306  * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1307  * FW to tell the fw to get this message from IOMB.
1308  * @pm8001_ha: our hba card information
1309  * @circularQ: the inbound queue we want to transfer to HBA.
1310  * @opCode: the operation code represents commands which LLDD and fw recognized.
1311  * @payload: the command payload of each operation command.
1312  * @nb: size in bytes of the command payload
1313  * @responseQueue: queue to interrupt on w/ command response (if any)
1314  */
pm8001_mpi_build_cmd(struct pm8001_hba_info * pm8001_ha,struct inbound_queue_table * circularQ,u32 opCode,void * payload,size_t nb,u32 responseQueue)1315 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1316 			 struct inbound_queue_table *circularQ,
1317 			 u32 opCode, void *payload, size_t nb,
1318 			 u32 responseQueue)
1319 {
1320 	u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1321 	void *pMessage;
1322 	unsigned long flags;
1323 	int q_index = circularQ - pm8001_ha->inbnd_q_tbl;
1324 	int rv = -1;
1325 
1326 	if (WARN_ON(q_index >= pm8001_ha->max_q_num))
1327 		return -EINVAL;
1328 
1329 	spin_lock_irqsave(&circularQ->iq_lock, flags);
1330 	rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1331 			&pMessage);
1332 	if (rv < 0) {
1333 		pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n");
1334 		rv = -ENOMEM;
1335 		goto done;
1336 	}
1337 
1338 	if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr)))
1339 		nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr);
1340 	memcpy(pMessage, payload, nb);
1341 	if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size)
1342 		memset(pMessage + nb, 0, pm8001_ha->iomb_size -
1343 				(nb + sizeof(struct mpi_msg_hdr)));
1344 
1345 	/*Build the header*/
1346 	Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1347 		| ((responseQueue & 0x3F) << 16)
1348 		| ((category & 0xF) << 12) | (opCode & 0xFFF));
1349 
1350 	pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1351 	/*Update the PI to the firmware*/
1352 	pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1353 		circularQ->pi_offset, circularQ->producer_idx);
1354 	pm8001_dbg(pm8001_ha, DEVIO,
1355 		   "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1356 		   responseQueue, opCode, circularQ->producer_idx,
1357 		   circularQ->consumer_index);
1358 done:
1359 	spin_unlock_irqrestore(&circularQ->iq_lock, flags);
1360 	return rv;
1361 }
1362 
pm8001_mpi_msg_free_set(struct pm8001_hba_info * pm8001_ha,void * pMsg,struct outbound_queue_table * circularQ,u8 bc)1363 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1364 			    struct outbound_queue_table *circularQ, u8 bc)
1365 {
1366 	u32 producer_index;
1367 	struct mpi_msg_hdr *msgHeader;
1368 	struct mpi_msg_hdr *pOutBoundMsgHeader;
1369 
1370 	msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1371 	pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1372 				circularQ->consumer_idx * pm8001_ha->iomb_size);
1373 	if (pOutBoundMsgHeader != msgHeader) {
1374 		pm8001_dbg(pm8001_ha, FAIL,
1375 			   "consumer_idx = %d msgHeader = %p\n",
1376 			   circularQ->consumer_idx, msgHeader);
1377 
1378 		/* Update the producer index from SPC */
1379 		producer_index = pm8001_read_32(circularQ->pi_virt);
1380 		circularQ->producer_index = cpu_to_le32(producer_index);
1381 		pm8001_dbg(pm8001_ha, FAIL,
1382 			   "consumer_idx = %d producer_index = %dmsgHeader = %p\n",
1383 			   circularQ->consumer_idx,
1384 			   circularQ->producer_index, msgHeader);
1385 		return 0;
1386 	}
1387 	/* free the circular queue buffer elements associated with the message*/
1388 	circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1389 				% PM8001_MPI_QUEUE;
1390 	/* update the CI of outbound queue */
1391 	pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1392 		circularQ->consumer_idx);
1393 	/* Update the producer index from SPC*/
1394 	producer_index = pm8001_read_32(circularQ->pi_virt);
1395 	circularQ->producer_index = cpu_to_le32(producer_index);
1396 	pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n",
1397 		   circularQ->consumer_idx, circularQ->producer_index);
1398 	return 0;
1399 }
1400 
1401 /**
1402  * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1403  * message table.
1404  * @pm8001_ha: our hba card information
1405  * @circularQ: the outbound queue  table.
1406  * @messagePtr1: the message contents of this outbound message.
1407  * @pBC: the message size.
1408  */
pm8001_mpi_msg_consume(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void ** messagePtr1,u8 * pBC)1409 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1410 			   struct outbound_queue_table *circularQ,
1411 			   void **messagePtr1, u8 *pBC)
1412 {
1413 	struct mpi_msg_hdr	*msgHeader;
1414 	__le32	msgHeader_tmp;
1415 	u32 header_tmp;
1416 	do {
1417 		/* If there are not-yet-delivered messages ... */
1418 		if (le32_to_cpu(circularQ->producer_index)
1419 			!= circularQ->consumer_idx) {
1420 			/*Get the pointer to the circular queue buffer element*/
1421 			msgHeader = (struct mpi_msg_hdr *)
1422 				(circularQ->base_virt +
1423 				circularQ->consumer_idx * pm8001_ha->iomb_size);
1424 			/* read header */
1425 			header_tmp = pm8001_read_32(msgHeader);
1426 			msgHeader_tmp = cpu_to_le32(header_tmp);
1427 			pm8001_dbg(pm8001_ha, DEVIO,
1428 				   "outbound opcode msgheader:%x ci=%d pi=%d\n",
1429 				   msgHeader_tmp, circularQ->consumer_idx,
1430 				   circularQ->producer_index);
1431 			if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1432 				if (OPC_OUB_SKIP_ENTRY !=
1433 					(le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1434 					*messagePtr1 =
1435 						((u8 *)msgHeader) +
1436 						sizeof(struct mpi_msg_hdr);
1437 					*pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1438 						>> 24) & 0x1f);
1439 					pm8001_dbg(pm8001_ha, IO,
1440 						   ": CI=%d PI=%d msgHeader=%x\n",
1441 						   circularQ->consumer_idx,
1442 						   circularQ->producer_index,
1443 						   msgHeader_tmp);
1444 					return MPI_IO_STATUS_SUCCESS;
1445 				} else {
1446 					circularQ->consumer_idx =
1447 						(circularQ->consumer_idx +
1448 						((le32_to_cpu(msgHeader_tmp)
1449 						 >> 24) & 0x1f))
1450 							% PM8001_MPI_QUEUE;
1451 					msgHeader_tmp = 0;
1452 					pm8001_write_32(msgHeader, 0, 0);
1453 					/* update the CI of outbound queue */
1454 					pm8001_cw32(pm8001_ha,
1455 						circularQ->ci_pci_bar,
1456 						circularQ->ci_offset,
1457 						circularQ->consumer_idx);
1458 				}
1459 			} else {
1460 				circularQ->consumer_idx =
1461 					(circularQ->consumer_idx +
1462 					((le32_to_cpu(msgHeader_tmp) >> 24) &
1463 					0x1f)) % PM8001_MPI_QUEUE;
1464 				msgHeader_tmp = 0;
1465 				pm8001_write_32(msgHeader, 0, 0);
1466 				/* update the CI of outbound queue */
1467 				pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1468 					circularQ->ci_offset,
1469 					circularQ->consumer_idx);
1470 				return MPI_IO_STATUS_FAIL;
1471 			}
1472 		} else {
1473 			u32 producer_index;
1474 			void *pi_virt = circularQ->pi_virt;
1475 			/* spurious interrupt during setup if
1476 			 * kexec-ing and driver doing a doorbell access
1477 			 * with the pre-kexec oq interrupt setup
1478 			 */
1479 			if (!pi_virt)
1480 				break;
1481 			/* Update the producer index from SPC */
1482 			producer_index = pm8001_read_32(pi_virt);
1483 			circularQ->producer_index = cpu_to_le32(producer_index);
1484 		}
1485 	} while (le32_to_cpu(circularQ->producer_index) !=
1486 		circularQ->consumer_idx);
1487 	/* while we don't have any more not-yet-delivered message */
1488 	/* report empty */
1489 	return MPI_IO_STATUS_BUSY;
1490 }
1491 
pm8001_work_fn(struct work_struct * work)1492 void pm8001_work_fn(struct work_struct *work)
1493 {
1494 	struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1495 	struct pm8001_device *pm8001_dev;
1496 	struct domain_device *dev;
1497 
1498 	/*
1499 	 * So far, all users of this stash an associated structure here.
1500 	 * If we get here, and this pointer is null, then the action
1501 	 * was cancelled. This nullification happens when the device
1502 	 * goes away.
1503 	 */
1504 	pm8001_dev = pw->data; /* Most stash device structure */
1505 	if ((pm8001_dev == NULL)
1506 	 || ((pw->handler != IO_XFER_ERROR_BREAK)
1507 	  && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1508 		kfree(pw);
1509 		return;
1510 	}
1511 
1512 	switch (pw->handler) {
1513 	case IO_XFER_ERROR_BREAK:
1514 	{	/* This one stashes the sas_task instead */
1515 		struct sas_task *t = (struct sas_task *)pm8001_dev;
1516 		u32 tag;
1517 		struct pm8001_ccb_info *ccb;
1518 		struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1519 		unsigned long flags, flags1;
1520 		struct task_status_struct *ts;
1521 		int i;
1522 
1523 		if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1524 			break; /* Task still on lu */
1525 		spin_lock_irqsave(&pm8001_ha->lock, flags);
1526 
1527 		spin_lock_irqsave(&t->task_state_lock, flags1);
1528 		if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1529 			spin_unlock_irqrestore(&t->task_state_lock, flags1);
1530 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1531 			break; /* Task got completed by another */
1532 		}
1533 		spin_unlock_irqrestore(&t->task_state_lock, flags1);
1534 
1535 		/* Search for a possible ccb that matches the task */
1536 		for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1537 			ccb = &pm8001_ha->ccb_info[i];
1538 			tag = ccb->ccb_tag;
1539 			if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1540 				break;
1541 		}
1542 		if (!ccb) {
1543 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1544 			break; /* Task got freed by another */
1545 		}
1546 		ts = &t->task_status;
1547 		ts->resp = SAS_TASK_COMPLETE;
1548 		/* Force the midlayer to retry */
1549 		ts->stat = SAS_QUEUE_FULL;
1550 		pm8001_dev = ccb->device;
1551 		if (pm8001_dev)
1552 			atomic_dec(&pm8001_dev->running_req);
1553 		spin_lock_irqsave(&t->task_state_lock, flags1);
1554 		t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1555 		t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1556 		t->task_state_flags |= SAS_TASK_STATE_DONE;
1557 		if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1558 			spin_unlock_irqrestore(&t->task_state_lock, flags1);
1559 			pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
1560 				   t, pw->handler, ts->resp, ts->stat);
1561 			pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1562 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1563 		} else {
1564 			spin_unlock_irqrestore(&t->task_state_lock, flags1);
1565 			pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1566 			mb();/* in order to force CPU ordering */
1567 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1568 			t->task_done(t);
1569 		}
1570 	}	break;
1571 	case IO_XFER_OPEN_RETRY_TIMEOUT:
1572 	{	/* This one stashes the sas_task instead */
1573 		struct sas_task *t = (struct sas_task *)pm8001_dev;
1574 		u32 tag;
1575 		struct pm8001_ccb_info *ccb;
1576 		struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1577 		unsigned long flags, flags1;
1578 		int i, ret = 0;
1579 
1580 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1581 
1582 		ret = pm8001_query_task(t);
1583 
1584 		if (ret == TMF_RESP_FUNC_SUCC)
1585 			pm8001_dbg(pm8001_ha, IO, "...Task on lu\n");
1586 		else if (ret == TMF_RESP_FUNC_COMPLETE)
1587 			pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n");
1588 		else
1589 			pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n");
1590 
1591 		spin_lock_irqsave(&pm8001_ha->lock, flags);
1592 
1593 		spin_lock_irqsave(&t->task_state_lock, flags1);
1594 
1595 		if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1596 			spin_unlock_irqrestore(&t->task_state_lock, flags1);
1597 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1598 			if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1599 				(void)pm8001_abort_task(t);
1600 			break; /* Task got completed by another */
1601 		}
1602 
1603 		spin_unlock_irqrestore(&t->task_state_lock, flags1);
1604 
1605 		/* Search for a possible ccb that matches the task */
1606 		for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1607 			ccb = &pm8001_ha->ccb_info[i];
1608 			tag = ccb->ccb_tag;
1609 			if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1610 				break;
1611 		}
1612 		if (!ccb) {
1613 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1614 			if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1615 				(void)pm8001_abort_task(t);
1616 			break; /* Task got freed by another */
1617 		}
1618 
1619 		pm8001_dev = ccb->device;
1620 		dev = pm8001_dev->sas_device;
1621 
1622 		switch (ret) {
1623 		case TMF_RESP_FUNC_SUCC: /* task on lu */
1624 			ccb->open_retry = 1; /* Snub completion */
1625 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1626 			ret = pm8001_abort_task(t);
1627 			ccb->open_retry = 0;
1628 			switch (ret) {
1629 			case TMF_RESP_FUNC_SUCC:
1630 			case TMF_RESP_FUNC_COMPLETE:
1631 				break;
1632 			default: /* device misbehavior */
1633 				ret = TMF_RESP_FUNC_FAILED;
1634 				pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1635 				pm8001_I_T_nexus_reset(dev);
1636 				break;
1637 			}
1638 			break;
1639 
1640 		case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1641 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1642 			/* Do we need to abort the task locally? */
1643 			break;
1644 
1645 		default: /* device misbehavior */
1646 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1647 			ret = TMF_RESP_FUNC_FAILED;
1648 			pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1649 			pm8001_I_T_nexus_reset(dev);
1650 		}
1651 
1652 		if (ret == TMF_RESP_FUNC_FAILED)
1653 			t = NULL;
1654 		pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1655 		pm8001_dbg(pm8001_ha, IO, "...Complete\n");
1656 	}	break;
1657 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1658 		dev = pm8001_dev->sas_device;
1659 		pm8001_I_T_nexus_event_handler(dev);
1660 		break;
1661 	case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1662 		dev = pm8001_dev->sas_device;
1663 		pm8001_I_T_nexus_reset(dev);
1664 		break;
1665 	case IO_DS_IN_ERROR:
1666 		dev = pm8001_dev->sas_device;
1667 		pm8001_I_T_nexus_reset(dev);
1668 		break;
1669 	case IO_DS_NON_OPERATIONAL:
1670 		dev = pm8001_dev->sas_device;
1671 		pm8001_I_T_nexus_reset(dev);
1672 		break;
1673 	}
1674 	kfree(pw);
1675 }
1676 
pm8001_handle_event(struct pm8001_hba_info * pm8001_ha,void * data,int handler)1677 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1678 			       int handler)
1679 {
1680 	struct pm8001_work *pw;
1681 	int ret = 0;
1682 
1683 	pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1684 	if (pw) {
1685 		pw->pm8001_ha = pm8001_ha;
1686 		pw->data = data;
1687 		pw->handler = handler;
1688 		INIT_WORK(&pw->work, pm8001_work_fn);
1689 		queue_work(pm8001_wq, &pw->work);
1690 	} else
1691 		ret = -ENOMEM;
1692 
1693 	return ret;
1694 }
1695 
pm8001_send_abort_all(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_ha_dev)1696 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1697 		struct pm8001_device *pm8001_ha_dev)
1698 {
1699 	int res;
1700 	u32 ccb_tag;
1701 	struct pm8001_ccb_info *ccb;
1702 	struct sas_task *task = NULL;
1703 	struct task_abort_req task_abort;
1704 	struct inbound_queue_table *circularQ;
1705 	u32 opc = OPC_INB_SATA_ABORT;
1706 	int ret;
1707 
1708 	if (!pm8001_ha_dev) {
1709 		pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
1710 		return;
1711 	}
1712 
1713 	task = sas_alloc_slow_task(GFP_ATOMIC);
1714 
1715 	if (!task) {
1716 		pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1717 		return;
1718 	}
1719 
1720 	task->task_done = pm8001_task_done;
1721 
1722 	res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1723 	if (res)
1724 		return;
1725 
1726 	ccb = &pm8001_ha->ccb_info[ccb_tag];
1727 	ccb->device = pm8001_ha_dev;
1728 	ccb->ccb_tag = ccb_tag;
1729 	ccb->task = task;
1730 
1731 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
1732 
1733 	memset(&task_abort, 0, sizeof(task_abort));
1734 	task_abort.abort_all = cpu_to_le32(1);
1735 	task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1736 	task_abort.tag = cpu_to_le32(ccb_tag);
1737 
1738 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1739 			sizeof(task_abort), 0);
1740 	if (ret)
1741 		pm8001_tag_free(pm8001_ha, ccb_tag);
1742 
1743 }
1744 
pm8001_send_read_log(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_ha_dev)1745 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1746 		struct pm8001_device *pm8001_ha_dev)
1747 {
1748 	struct sata_start_req sata_cmd;
1749 	int res;
1750 	u32 ccb_tag;
1751 	struct pm8001_ccb_info *ccb;
1752 	struct sas_task *task = NULL;
1753 	struct host_to_dev_fis fis;
1754 	struct domain_device *dev;
1755 	struct inbound_queue_table *circularQ;
1756 	u32 opc = OPC_INB_SATA_HOST_OPSTART;
1757 
1758 	task = sas_alloc_slow_task(GFP_ATOMIC);
1759 
1760 	if (!task) {
1761 		pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1762 		return;
1763 	}
1764 	task->task_done = pm8001_task_done;
1765 
1766 	res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1767 	if (res) {
1768 		sas_free_task(task);
1769 		pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
1770 		return;
1771 	}
1772 
1773 	/* allocate domain device by ourselves as libsas
1774 	 * is not going to provide any
1775 	*/
1776 	dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1777 	if (!dev) {
1778 		sas_free_task(task);
1779 		pm8001_tag_free(pm8001_ha, ccb_tag);
1780 		pm8001_dbg(pm8001_ha, FAIL,
1781 			   "Domain device cannot be allocated\n");
1782 		return;
1783 	}
1784 	task->dev = dev;
1785 	task->dev->lldd_dev = pm8001_ha_dev;
1786 
1787 	ccb = &pm8001_ha->ccb_info[ccb_tag];
1788 	ccb->device = pm8001_ha_dev;
1789 	ccb->ccb_tag = ccb_tag;
1790 	ccb->task = task;
1791 	pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1792 	pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1793 
1794 	memset(&sata_cmd, 0, sizeof(sata_cmd));
1795 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
1796 
1797 	/* construct read log FIS */
1798 	memset(&fis, 0, sizeof(struct host_to_dev_fis));
1799 	fis.fis_type = 0x27;
1800 	fis.flags = 0x80;
1801 	fis.command = ATA_CMD_READ_LOG_EXT;
1802 	fis.lbal = 0x10;
1803 	fis.sector_count = 0x1;
1804 
1805 	sata_cmd.tag = cpu_to_le32(ccb_tag);
1806 	sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1807 	sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9));
1808 	memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1809 
1810 	res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1811 			sizeof(sata_cmd), 0);
1812 	if (res) {
1813 		sas_free_task(task);
1814 		pm8001_tag_free(pm8001_ha, ccb_tag);
1815 		kfree(dev);
1816 	}
1817 }
1818 
1819 /**
1820  * mpi_ssp_completion- process the event that FW response to the SSP request.
1821  * @pm8001_ha: our hba card information
1822  * @piomb: the message contents of this outbound message.
1823  *
1824  * When FW has completed a ssp request for example a IO request, after it has
1825  * filled the SG data with the data, it will trigger this event represent
1826  * that he has finished the job,please check the coresponding buffer.
1827  * So we will tell the caller who maybe waiting the result to tell upper layer
1828  * that the task has been finished.
1829  */
1830 static void
mpi_ssp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)1831 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1832 {
1833 	struct sas_task *t;
1834 	struct pm8001_ccb_info *ccb;
1835 	unsigned long flags;
1836 	u32 status;
1837 	u32 param;
1838 	u32 tag;
1839 	struct ssp_completion_resp *psspPayload;
1840 	struct task_status_struct *ts;
1841 	struct ssp_response_iu *iu;
1842 	struct pm8001_device *pm8001_dev;
1843 	psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1844 	status = le32_to_cpu(psspPayload->status);
1845 	tag = le32_to_cpu(psspPayload->tag);
1846 	ccb = &pm8001_ha->ccb_info[tag];
1847 	if ((status == IO_ABORTED) && ccb->open_retry) {
1848 		/* Being completed by another */
1849 		ccb->open_retry = 0;
1850 		return;
1851 	}
1852 	pm8001_dev = ccb->device;
1853 	param = le32_to_cpu(psspPayload->param);
1854 
1855 	t = ccb->task;
1856 
1857 	if (status && status != IO_UNDERFLOW)
1858 		pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1859 	if (unlikely(!t || !t->lldd_task || !t->dev))
1860 		return;
1861 	ts = &t->task_status;
1862 	/* Print sas address of IO failed device */
1863 	if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1864 		(status != IO_UNDERFLOW))
1865 		pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1866 			   SAS_ADDR(t->dev->sas_addr));
1867 
1868 	if (status)
1869 		pm8001_dbg(pm8001_ha, IOERR,
1870 			   "status:0x%x, tag:0x%x, task:0x%p\n",
1871 			   status, tag, t);
1872 
1873 	switch (status) {
1874 	case IO_SUCCESS:
1875 		pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n",
1876 			   param);
1877 		if (param == 0) {
1878 			ts->resp = SAS_TASK_COMPLETE;
1879 			ts->stat = SAM_STAT_GOOD;
1880 		} else {
1881 			ts->resp = SAS_TASK_COMPLETE;
1882 			ts->stat = SAS_PROTO_RESPONSE;
1883 			ts->residual = param;
1884 			iu = &psspPayload->ssp_resp_iu;
1885 			sas_ssp_task_response(pm8001_ha->dev, t, iu);
1886 		}
1887 		if (pm8001_dev)
1888 			atomic_dec(&pm8001_dev->running_req);
1889 		break;
1890 	case IO_ABORTED:
1891 		pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1892 		ts->resp = SAS_TASK_COMPLETE;
1893 		ts->stat = SAS_ABORTED_TASK;
1894 		break;
1895 	case IO_UNDERFLOW:
1896 		/* SSP Completion with error */
1897 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n",
1898 			   param);
1899 		ts->resp = SAS_TASK_COMPLETE;
1900 		ts->stat = SAS_DATA_UNDERRUN;
1901 		ts->residual = param;
1902 		if (pm8001_dev)
1903 			atomic_dec(&pm8001_dev->running_req);
1904 		break;
1905 	case IO_NO_DEVICE:
1906 		pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1907 		ts->resp = SAS_TASK_UNDELIVERED;
1908 		ts->stat = SAS_PHY_DOWN;
1909 		break;
1910 	case IO_XFER_ERROR_BREAK:
1911 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1912 		ts->resp = SAS_TASK_COMPLETE;
1913 		ts->stat = SAS_OPEN_REJECT;
1914 		/* Force the midlayer to retry */
1915 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1916 		break;
1917 	case IO_XFER_ERROR_PHY_NOT_READY:
1918 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1919 		ts->resp = SAS_TASK_COMPLETE;
1920 		ts->stat = SAS_OPEN_REJECT;
1921 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1922 		break;
1923 	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1924 		pm8001_dbg(pm8001_ha, IO,
1925 			   "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1926 		ts->resp = SAS_TASK_COMPLETE;
1927 		ts->stat = SAS_OPEN_REJECT;
1928 		ts->open_rej_reason = SAS_OREJ_EPROTO;
1929 		break;
1930 	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1931 		pm8001_dbg(pm8001_ha, IO,
1932 			   "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1933 		ts->resp = SAS_TASK_COMPLETE;
1934 		ts->stat = SAS_OPEN_REJECT;
1935 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1936 		break;
1937 	case IO_OPEN_CNX_ERROR_BREAK:
1938 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
1939 		ts->resp = SAS_TASK_COMPLETE;
1940 		ts->stat = SAS_OPEN_REJECT;
1941 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1942 		break;
1943 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1944 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
1945 		ts->resp = SAS_TASK_COMPLETE;
1946 		ts->stat = SAS_OPEN_REJECT;
1947 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1948 		if (!t->uldd_task)
1949 			pm8001_handle_event(pm8001_ha,
1950 				pm8001_dev,
1951 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1952 		break;
1953 	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1954 		pm8001_dbg(pm8001_ha, IO,
1955 			   "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
1956 		ts->resp = SAS_TASK_COMPLETE;
1957 		ts->stat = SAS_OPEN_REJECT;
1958 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1959 		break;
1960 	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1961 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
1962 		ts->resp = SAS_TASK_COMPLETE;
1963 		ts->stat = SAS_OPEN_REJECT;
1964 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1965 		break;
1966 	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1967 		pm8001_dbg(pm8001_ha, IO,
1968 			   "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
1969 		ts->resp = SAS_TASK_UNDELIVERED;
1970 		ts->stat = SAS_OPEN_REJECT;
1971 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1972 		break;
1973 	case IO_XFER_ERROR_NAK_RECEIVED:
1974 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
1975 		ts->resp = SAS_TASK_COMPLETE;
1976 		ts->stat = SAS_OPEN_REJECT;
1977 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1978 		break;
1979 	case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1980 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
1981 		ts->resp = SAS_TASK_COMPLETE;
1982 		ts->stat = SAS_NAK_R_ERR;
1983 		break;
1984 	case IO_XFER_ERROR_DMA:
1985 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
1986 		ts->resp = SAS_TASK_COMPLETE;
1987 		ts->stat = SAS_OPEN_REJECT;
1988 		break;
1989 	case IO_XFER_OPEN_RETRY_TIMEOUT:
1990 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1991 		ts->resp = SAS_TASK_COMPLETE;
1992 		ts->stat = SAS_OPEN_REJECT;
1993 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1994 		break;
1995 	case IO_XFER_ERROR_OFFSET_MISMATCH:
1996 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
1997 		ts->resp = SAS_TASK_COMPLETE;
1998 		ts->stat = SAS_OPEN_REJECT;
1999 		break;
2000 	case IO_PORT_IN_RESET:
2001 		pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2002 		ts->resp = SAS_TASK_COMPLETE;
2003 		ts->stat = SAS_OPEN_REJECT;
2004 		break;
2005 	case IO_DS_NON_OPERATIONAL:
2006 		pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2007 		ts->resp = SAS_TASK_COMPLETE;
2008 		ts->stat = SAS_OPEN_REJECT;
2009 		if (!t->uldd_task)
2010 			pm8001_handle_event(pm8001_ha,
2011 				pm8001_dev,
2012 				IO_DS_NON_OPERATIONAL);
2013 		break;
2014 	case IO_DS_IN_RECOVERY:
2015 		pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2016 		ts->resp = SAS_TASK_COMPLETE;
2017 		ts->stat = SAS_OPEN_REJECT;
2018 		break;
2019 	case IO_TM_TAG_NOT_FOUND:
2020 		pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2021 		ts->resp = SAS_TASK_COMPLETE;
2022 		ts->stat = SAS_OPEN_REJECT;
2023 		break;
2024 	case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2025 		pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2026 		ts->resp = SAS_TASK_COMPLETE;
2027 		ts->stat = SAS_OPEN_REJECT;
2028 		break;
2029 	case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2030 		pm8001_dbg(pm8001_ha, IO,
2031 			   "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2032 		ts->resp = SAS_TASK_COMPLETE;
2033 		ts->stat = SAS_OPEN_REJECT;
2034 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2035 		break;
2036 	default:
2037 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2038 		/* not allowed case. Therefore, return failed status */
2039 		ts->resp = SAS_TASK_COMPLETE;
2040 		ts->stat = SAS_OPEN_REJECT;
2041 		break;
2042 	}
2043 	pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n",
2044 		   psspPayload->ssp_resp_iu.status);
2045 	spin_lock_irqsave(&t->task_state_lock, flags);
2046 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2047 	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2048 	t->task_state_flags |= SAS_TASK_STATE_DONE;
2049 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2050 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2051 		pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2052 			   t, status, ts->resp, ts->stat);
2053 		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2054 	} else {
2055 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2056 		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2057 		mb();/* in order to force CPU ordering */
2058 		t->task_done(t);
2059 	}
2060 }
2061 
2062 /*See the comments for mpi_ssp_completion */
mpi_ssp_event(struct pm8001_hba_info * pm8001_ha,void * piomb)2063 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2064 {
2065 	struct sas_task *t;
2066 	unsigned long flags;
2067 	struct task_status_struct *ts;
2068 	struct pm8001_ccb_info *ccb;
2069 	struct pm8001_device *pm8001_dev;
2070 	struct ssp_event_resp *psspPayload =
2071 		(struct ssp_event_resp *)(piomb + 4);
2072 	u32 event = le32_to_cpu(psspPayload->event);
2073 	u32 tag = le32_to_cpu(psspPayload->tag);
2074 	u32 port_id = le32_to_cpu(psspPayload->port_id);
2075 	u32 dev_id = le32_to_cpu(psspPayload->device_id);
2076 
2077 	ccb = &pm8001_ha->ccb_info[tag];
2078 	t = ccb->task;
2079 	pm8001_dev = ccb->device;
2080 	if (event)
2081 		pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2082 	if (unlikely(!t || !t->lldd_task || !t->dev))
2083 		return;
2084 	ts = &t->task_status;
2085 	pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n",
2086 		   port_id, dev_id);
2087 	switch (event) {
2088 	case IO_OVERFLOW:
2089 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2090 		ts->resp = SAS_TASK_COMPLETE;
2091 		ts->stat = SAS_DATA_OVERRUN;
2092 		ts->residual = 0;
2093 		if (pm8001_dev)
2094 			atomic_dec(&pm8001_dev->running_req);
2095 		break;
2096 	case IO_XFER_ERROR_BREAK:
2097 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2098 		pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2099 		return;
2100 	case IO_XFER_ERROR_PHY_NOT_READY:
2101 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2102 		ts->resp = SAS_TASK_COMPLETE;
2103 		ts->stat = SAS_OPEN_REJECT;
2104 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2105 		break;
2106 	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2107 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2108 		ts->resp = SAS_TASK_COMPLETE;
2109 		ts->stat = SAS_OPEN_REJECT;
2110 		ts->open_rej_reason = SAS_OREJ_EPROTO;
2111 		break;
2112 	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2113 		pm8001_dbg(pm8001_ha, IO,
2114 			   "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2115 		ts->resp = SAS_TASK_COMPLETE;
2116 		ts->stat = SAS_OPEN_REJECT;
2117 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2118 		break;
2119 	case IO_OPEN_CNX_ERROR_BREAK:
2120 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2121 		ts->resp = SAS_TASK_COMPLETE;
2122 		ts->stat = SAS_OPEN_REJECT;
2123 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2124 		break;
2125 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2126 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2127 		ts->resp = SAS_TASK_COMPLETE;
2128 		ts->stat = SAS_OPEN_REJECT;
2129 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2130 		if (!t->uldd_task)
2131 			pm8001_handle_event(pm8001_ha,
2132 				pm8001_dev,
2133 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2134 		break;
2135 	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2136 		pm8001_dbg(pm8001_ha, IO,
2137 			   "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2138 		ts->resp = SAS_TASK_COMPLETE;
2139 		ts->stat = SAS_OPEN_REJECT;
2140 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2141 		break;
2142 	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2143 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2144 		ts->resp = SAS_TASK_COMPLETE;
2145 		ts->stat = SAS_OPEN_REJECT;
2146 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2147 		break;
2148 	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2149 		pm8001_dbg(pm8001_ha, IO,
2150 			   "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2151 		ts->resp = SAS_TASK_COMPLETE;
2152 		ts->stat = SAS_OPEN_REJECT;
2153 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2154 		break;
2155 	case IO_XFER_ERROR_NAK_RECEIVED:
2156 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2157 		ts->resp = SAS_TASK_COMPLETE;
2158 		ts->stat = SAS_OPEN_REJECT;
2159 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2160 		break;
2161 	case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2162 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2163 		ts->resp = SAS_TASK_COMPLETE;
2164 		ts->stat = SAS_NAK_R_ERR;
2165 		break;
2166 	case IO_XFER_OPEN_RETRY_TIMEOUT:
2167 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2168 		pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2169 		return;
2170 	case IO_XFER_ERROR_UNEXPECTED_PHASE:
2171 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2172 		ts->resp = SAS_TASK_COMPLETE;
2173 		ts->stat = SAS_DATA_OVERRUN;
2174 		break;
2175 	case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2176 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2177 		ts->resp = SAS_TASK_COMPLETE;
2178 		ts->stat = SAS_DATA_OVERRUN;
2179 		break;
2180 	case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2181 		pm8001_dbg(pm8001_ha, IO,
2182 			   "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2183 		ts->resp = SAS_TASK_COMPLETE;
2184 		ts->stat = SAS_DATA_OVERRUN;
2185 		break;
2186 	case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2187 		pm8001_dbg(pm8001_ha, IO,
2188 			   "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2189 		ts->resp = SAS_TASK_COMPLETE;
2190 		ts->stat = SAS_DATA_OVERRUN;
2191 		break;
2192 	case IO_XFER_ERROR_OFFSET_MISMATCH:
2193 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2194 		ts->resp = SAS_TASK_COMPLETE;
2195 		ts->stat = SAS_DATA_OVERRUN;
2196 		break;
2197 	case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2198 		pm8001_dbg(pm8001_ha, IO,
2199 			   "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2200 		ts->resp = SAS_TASK_COMPLETE;
2201 		ts->stat = SAS_DATA_OVERRUN;
2202 		break;
2203 	case IO_XFER_CMD_FRAME_ISSUED:
2204 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2205 		return;
2206 	default:
2207 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2208 		/* not allowed case. Therefore, return failed status */
2209 		ts->resp = SAS_TASK_COMPLETE;
2210 		ts->stat = SAS_DATA_OVERRUN;
2211 		break;
2212 	}
2213 	spin_lock_irqsave(&t->task_state_lock, flags);
2214 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2215 	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2216 	t->task_state_flags |= SAS_TASK_STATE_DONE;
2217 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2218 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2219 		pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2220 			   t, event, ts->resp, ts->stat);
2221 		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2222 	} else {
2223 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2224 		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2225 		mb();/* in order to force CPU ordering */
2226 		t->task_done(t);
2227 	}
2228 }
2229 
2230 /*See the comments for mpi_ssp_completion */
2231 static void
mpi_sata_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)2232 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2233 {
2234 	struct sas_task *t;
2235 	struct pm8001_ccb_info *ccb;
2236 	u32 param;
2237 	u32 status;
2238 	u32 tag;
2239 	int i, j;
2240 	u8 sata_addr_low[4];
2241 	u32 temp_sata_addr_low;
2242 	u8 sata_addr_hi[4];
2243 	u32 temp_sata_addr_hi;
2244 	struct sata_completion_resp *psataPayload;
2245 	struct task_status_struct *ts;
2246 	struct ata_task_resp *resp ;
2247 	u32 *sata_resp;
2248 	struct pm8001_device *pm8001_dev;
2249 	unsigned long flags;
2250 
2251 	psataPayload = (struct sata_completion_resp *)(piomb + 4);
2252 	status = le32_to_cpu(psataPayload->status);
2253 	tag = le32_to_cpu(psataPayload->tag);
2254 
2255 	if (!tag) {
2256 		pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
2257 		return;
2258 	}
2259 	ccb = &pm8001_ha->ccb_info[tag];
2260 	param = le32_to_cpu(psataPayload->param);
2261 	if (ccb) {
2262 		t = ccb->task;
2263 		pm8001_dev = ccb->device;
2264 	} else {
2265 		pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
2266 		return;
2267 	}
2268 
2269 	if (t) {
2270 		if (t->dev && (t->dev->lldd_dev))
2271 			pm8001_dev = t->dev->lldd_dev;
2272 	} else {
2273 		pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2274 		return;
2275 	}
2276 
2277 	if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2278 		&& unlikely(!t || !t->lldd_task || !t->dev)) {
2279 		pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2280 		return;
2281 	}
2282 
2283 	ts = &t->task_status;
2284 	if (!ts) {
2285 		pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
2286 		return;
2287 	}
2288 
2289 	if (status)
2290 		pm8001_dbg(pm8001_ha, IOERR,
2291 			   "status:0x%x, tag:0x%x, task::0x%p\n",
2292 			   status, tag, t);
2293 
2294 	/* Print sas address of IO failed device */
2295 	if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2296 		(status != IO_UNDERFLOW)) {
2297 		if (!((t->dev->parent) &&
2298 			(dev_is_expander(t->dev->parent->dev_type)))) {
2299 			for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++)
2300 				sata_addr_low[i] = pm8001_ha->sas_addr[j];
2301 			for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++)
2302 				sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2303 			memcpy(&temp_sata_addr_low, sata_addr_low,
2304 				sizeof(sata_addr_low));
2305 			memcpy(&temp_sata_addr_hi, sata_addr_hi,
2306 				sizeof(sata_addr_hi));
2307 			temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2308 						|((temp_sata_addr_hi << 8) &
2309 						0xff0000) |
2310 						((temp_sata_addr_hi >> 8)
2311 						& 0xff00) |
2312 						((temp_sata_addr_hi << 24) &
2313 						0xff000000));
2314 			temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2315 						& 0xff) |
2316 						((temp_sata_addr_low << 8)
2317 						& 0xff0000) |
2318 						((temp_sata_addr_low >> 8)
2319 						& 0xff00) |
2320 						((temp_sata_addr_low << 24)
2321 						& 0xff000000)) +
2322 						pm8001_dev->attached_phy +
2323 						0x10);
2324 			pm8001_dbg(pm8001_ha, FAIL,
2325 				   "SAS Address of IO Failure Drive:%08x%08x\n",
2326 				   temp_sata_addr_hi,
2327 				   temp_sata_addr_low);
2328 		} else {
2329 			pm8001_dbg(pm8001_ha, FAIL,
2330 				   "SAS Address of IO Failure Drive:%016llx\n",
2331 				   SAS_ADDR(t->dev->sas_addr));
2332 		}
2333 	}
2334 	switch (status) {
2335 	case IO_SUCCESS:
2336 		pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2337 		if (param == 0) {
2338 			ts->resp = SAS_TASK_COMPLETE;
2339 			ts->stat = SAM_STAT_GOOD;
2340 			/* check if response is for SEND READ LOG */
2341 			if (pm8001_dev &&
2342 				(pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2343 				/* set new bit for abort_all */
2344 				pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2345 				/* clear bit for read log */
2346 				pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2347 				pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2348 				/* Free the tag */
2349 				pm8001_tag_free(pm8001_ha, tag);
2350 				sas_free_task(t);
2351 				return;
2352 			}
2353 		} else {
2354 			u8 len;
2355 			ts->resp = SAS_TASK_COMPLETE;
2356 			ts->stat = SAS_PROTO_RESPONSE;
2357 			ts->residual = param;
2358 			pm8001_dbg(pm8001_ha, IO,
2359 				   "SAS_PROTO_RESPONSE len = %d\n",
2360 				   param);
2361 			sata_resp = &psataPayload->sata_resp[0];
2362 			resp = (struct ata_task_resp *)ts->buf;
2363 			if (t->ata_task.dma_xfer == 0 &&
2364 			    t->data_dir == DMA_FROM_DEVICE) {
2365 				len = sizeof(struct pio_setup_fis);
2366 				pm8001_dbg(pm8001_ha, IO,
2367 					   "PIO read len = %d\n", len);
2368 			} else if (t->ata_task.use_ncq) {
2369 				len = sizeof(struct set_dev_bits_fis);
2370 				pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2371 					   len);
2372 			} else {
2373 				len = sizeof(struct dev_to_host_fis);
2374 				pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2375 					   len);
2376 			}
2377 			if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2378 				resp->frame_len = len;
2379 				memcpy(&resp->ending_fis[0], sata_resp, len);
2380 				ts->buf_valid_size = sizeof(*resp);
2381 			} else
2382 				pm8001_dbg(pm8001_ha, IO,
2383 					   "response too large\n");
2384 		}
2385 		if (pm8001_dev)
2386 			atomic_dec(&pm8001_dev->running_req);
2387 		break;
2388 	case IO_ABORTED:
2389 		pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2390 		ts->resp = SAS_TASK_COMPLETE;
2391 		ts->stat = SAS_ABORTED_TASK;
2392 		if (pm8001_dev)
2393 			atomic_dec(&pm8001_dev->running_req);
2394 		break;
2395 		/* following cases are to do cases */
2396 	case IO_UNDERFLOW:
2397 		/* SATA Completion with error */
2398 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2399 		ts->resp = SAS_TASK_COMPLETE;
2400 		ts->stat = SAS_DATA_UNDERRUN;
2401 		ts->residual =  param;
2402 		if (pm8001_dev)
2403 			atomic_dec(&pm8001_dev->running_req);
2404 		break;
2405 	case IO_NO_DEVICE:
2406 		pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2407 		ts->resp = SAS_TASK_UNDELIVERED;
2408 		ts->stat = SAS_PHY_DOWN;
2409 		if (pm8001_dev)
2410 			atomic_dec(&pm8001_dev->running_req);
2411 		break;
2412 	case IO_XFER_ERROR_BREAK:
2413 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2414 		ts->resp = SAS_TASK_COMPLETE;
2415 		ts->stat = SAS_INTERRUPTED;
2416 		if (pm8001_dev)
2417 			atomic_dec(&pm8001_dev->running_req);
2418 		break;
2419 	case IO_XFER_ERROR_PHY_NOT_READY:
2420 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2421 		ts->resp = SAS_TASK_COMPLETE;
2422 		ts->stat = SAS_OPEN_REJECT;
2423 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2424 		if (pm8001_dev)
2425 			atomic_dec(&pm8001_dev->running_req);
2426 		break;
2427 	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2428 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2429 		ts->resp = SAS_TASK_COMPLETE;
2430 		ts->stat = SAS_OPEN_REJECT;
2431 		ts->open_rej_reason = SAS_OREJ_EPROTO;
2432 		if (pm8001_dev)
2433 			atomic_dec(&pm8001_dev->running_req);
2434 		break;
2435 	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2436 		pm8001_dbg(pm8001_ha, IO,
2437 			   "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2438 		ts->resp = SAS_TASK_COMPLETE;
2439 		ts->stat = SAS_OPEN_REJECT;
2440 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2441 		if (pm8001_dev)
2442 			atomic_dec(&pm8001_dev->running_req);
2443 		break;
2444 	case IO_OPEN_CNX_ERROR_BREAK:
2445 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2446 		ts->resp = SAS_TASK_COMPLETE;
2447 		ts->stat = SAS_OPEN_REJECT;
2448 		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2449 		if (pm8001_dev)
2450 			atomic_dec(&pm8001_dev->running_req);
2451 		break;
2452 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2453 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2454 		ts->resp = SAS_TASK_COMPLETE;
2455 		ts->stat = SAS_DEV_NO_RESPONSE;
2456 		if (!t->uldd_task) {
2457 			pm8001_handle_event(pm8001_ha,
2458 				pm8001_dev,
2459 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2460 			ts->resp = SAS_TASK_UNDELIVERED;
2461 			ts->stat = SAS_QUEUE_FULL;
2462 			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2463 			return;
2464 		}
2465 		break;
2466 	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2467 		pm8001_dbg(pm8001_ha, IO,
2468 			   "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2469 		ts->resp = SAS_TASK_UNDELIVERED;
2470 		ts->stat = SAS_OPEN_REJECT;
2471 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2472 		if (!t->uldd_task) {
2473 			pm8001_handle_event(pm8001_ha,
2474 				pm8001_dev,
2475 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2476 			ts->resp = SAS_TASK_UNDELIVERED;
2477 			ts->stat = SAS_QUEUE_FULL;
2478 			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2479 			return;
2480 		}
2481 		break;
2482 	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2483 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2484 		ts->resp = SAS_TASK_COMPLETE;
2485 		ts->stat = SAS_OPEN_REJECT;
2486 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2487 		if (pm8001_dev)
2488 			atomic_dec(&pm8001_dev->running_req);
2489 		break;
2490 	case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2491 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2492 		ts->resp = SAS_TASK_COMPLETE;
2493 		ts->stat = SAS_DEV_NO_RESPONSE;
2494 		if (!t->uldd_task) {
2495 			pm8001_handle_event(pm8001_ha,
2496 				pm8001_dev,
2497 				IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2498 			ts->resp = SAS_TASK_UNDELIVERED;
2499 			ts->stat = SAS_QUEUE_FULL;
2500 			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2501 			return;
2502 		}
2503 		break;
2504 	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2505 		pm8001_dbg(pm8001_ha, IO,
2506 			   "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2507 		ts->resp = SAS_TASK_COMPLETE;
2508 		ts->stat = SAS_OPEN_REJECT;
2509 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2510 		if (pm8001_dev)
2511 			atomic_dec(&pm8001_dev->running_req);
2512 		break;
2513 	case IO_XFER_ERROR_NAK_RECEIVED:
2514 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2515 		ts->resp = SAS_TASK_COMPLETE;
2516 		ts->stat = SAS_NAK_R_ERR;
2517 		if (pm8001_dev)
2518 			atomic_dec(&pm8001_dev->running_req);
2519 		break;
2520 	case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2521 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2522 		ts->resp = SAS_TASK_COMPLETE;
2523 		ts->stat = SAS_NAK_R_ERR;
2524 		if (pm8001_dev)
2525 			atomic_dec(&pm8001_dev->running_req);
2526 		break;
2527 	case IO_XFER_ERROR_DMA:
2528 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2529 		ts->resp = SAS_TASK_COMPLETE;
2530 		ts->stat = SAS_ABORTED_TASK;
2531 		if (pm8001_dev)
2532 			atomic_dec(&pm8001_dev->running_req);
2533 		break;
2534 	case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2535 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2536 		ts->resp = SAS_TASK_UNDELIVERED;
2537 		ts->stat = SAS_DEV_NO_RESPONSE;
2538 		if (pm8001_dev)
2539 			atomic_dec(&pm8001_dev->running_req);
2540 		break;
2541 	case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2542 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2543 		ts->resp = SAS_TASK_COMPLETE;
2544 		ts->stat = SAS_DATA_UNDERRUN;
2545 		if (pm8001_dev)
2546 			atomic_dec(&pm8001_dev->running_req);
2547 		break;
2548 	case IO_XFER_OPEN_RETRY_TIMEOUT:
2549 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2550 		ts->resp = SAS_TASK_COMPLETE;
2551 		ts->stat = SAS_OPEN_TO;
2552 		if (pm8001_dev)
2553 			atomic_dec(&pm8001_dev->running_req);
2554 		break;
2555 	case IO_PORT_IN_RESET:
2556 		pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2557 		ts->resp = SAS_TASK_COMPLETE;
2558 		ts->stat = SAS_DEV_NO_RESPONSE;
2559 		if (pm8001_dev)
2560 			atomic_dec(&pm8001_dev->running_req);
2561 		break;
2562 	case IO_DS_NON_OPERATIONAL:
2563 		pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2564 		ts->resp = SAS_TASK_COMPLETE;
2565 		ts->stat = SAS_DEV_NO_RESPONSE;
2566 		if (!t->uldd_task) {
2567 			pm8001_handle_event(pm8001_ha, pm8001_dev,
2568 				    IO_DS_NON_OPERATIONAL);
2569 			ts->resp = SAS_TASK_UNDELIVERED;
2570 			ts->stat = SAS_QUEUE_FULL;
2571 			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2572 			return;
2573 		}
2574 		break;
2575 	case IO_DS_IN_RECOVERY:
2576 		pm8001_dbg(pm8001_ha, IO, "  IO_DS_IN_RECOVERY\n");
2577 		ts->resp = SAS_TASK_COMPLETE;
2578 		ts->stat = SAS_DEV_NO_RESPONSE;
2579 		if (pm8001_dev)
2580 			atomic_dec(&pm8001_dev->running_req);
2581 		break;
2582 	case IO_DS_IN_ERROR:
2583 		pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2584 		ts->resp = SAS_TASK_COMPLETE;
2585 		ts->stat = SAS_DEV_NO_RESPONSE;
2586 		if (!t->uldd_task) {
2587 			pm8001_handle_event(pm8001_ha, pm8001_dev,
2588 				    IO_DS_IN_ERROR);
2589 			ts->resp = SAS_TASK_UNDELIVERED;
2590 			ts->stat = SAS_QUEUE_FULL;
2591 			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2592 			return;
2593 		}
2594 		break;
2595 	case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2596 		pm8001_dbg(pm8001_ha, IO,
2597 			   "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2598 		ts->resp = SAS_TASK_COMPLETE;
2599 		ts->stat = SAS_OPEN_REJECT;
2600 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2601 		if (pm8001_dev)
2602 			atomic_dec(&pm8001_dev->running_req);
2603 		break;
2604 	default:
2605 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2606 		/* not allowed case. Therefore, return failed status */
2607 		ts->resp = SAS_TASK_COMPLETE;
2608 		ts->stat = SAS_DEV_NO_RESPONSE;
2609 		if (pm8001_dev)
2610 			atomic_dec(&pm8001_dev->running_req);
2611 		break;
2612 	}
2613 	spin_lock_irqsave(&t->task_state_lock, flags);
2614 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2615 	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2616 	t->task_state_flags |= SAS_TASK_STATE_DONE;
2617 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2618 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2619 		pm8001_dbg(pm8001_ha, FAIL,
2620 			   "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2621 			   t, status, ts->resp, ts->stat);
2622 		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2623 	} else {
2624 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2625 		pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2626 	}
2627 }
2628 
2629 /*See the comments for mpi_ssp_completion */
mpi_sata_event(struct pm8001_hba_info * pm8001_ha,void * piomb)2630 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2631 {
2632 	struct sas_task *t;
2633 	struct task_status_struct *ts;
2634 	struct pm8001_ccb_info *ccb;
2635 	struct pm8001_device *pm8001_dev;
2636 	struct sata_event_resp *psataPayload =
2637 		(struct sata_event_resp *)(piomb + 4);
2638 	u32 event = le32_to_cpu(psataPayload->event);
2639 	u32 tag = le32_to_cpu(psataPayload->tag);
2640 	u32 port_id = le32_to_cpu(psataPayload->port_id);
2641 	u32 dev_id = le32_to_cpu(psataPayload->device_id);
2642 	unsigned long flags;
2643 
2644 	ccb = &pm8001_ha->ccb_info[tag];
2645 
2646 	if (ccb) {
2647 		t = ccb->task;
2648 		pm8001_dev = ccb->device;
2649 	} else {
2650 		pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
2651 	}
2652 	if (event)
2653 		pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2654 
2655 	/* Check if this is NCQ error */
2656 	if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2657 		/* find device using device id */
2658 		pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2659 		/* send read log extension */
2660 		if (pm8001_dev)
2661 			pm8001_send_read_log(pm8001_ha, pm8001_dev);
2662 		return;
2663 	}
2664 
2665 	ccb = &pm8001_ha->ccb_info[tag];
2666 	t = ccb->task;
2667 	pm8001_dev = ccb->device;
2668 	if (event)
2669 		pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event);
2670 	if (unlikely(!t || !t->lldd_task || !t->dev))
2671 		return;
2672 	ts = &t->task_status;
2673 	pm8001_dbg(pm8001_ha, DEVIO,
2674 		   "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2675 		   port_id, dev_id, tag, event);
2676 	switch (event) {
2677 	case IO_OVERFLOW:
2678 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2679 		ts->resp = SAS_TASK_COMPLETE;
2680 		ts->stat = SAS_DATA_OVERRUN;
2681 		ts->residual = 0;
2682 		if (pm8001_dev)
2683 			atomic_dec(&pm8001_dev->running_req);
2684 		break;
2685 	case IO_XFER_ERROR_BREAK:
2686 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2687 		ts->resp = SAS_TASK_COMPLETE;
2688 		ts->stat = SAS_INTERRUPTED;
2689 		break;
2690 	case IO_XFER_ERROR_PHY_NOT_READY:
2691 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2692 		ts->resp = SAS_TASK_COMPLETE;
2693 		ts->stat = SAS_OPEN_REJECT;
2694 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2695 		break;
2696 	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2697 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2698 		ts->resp = SAS_TASK_COMPLETE;
2699 		ts->stat = SAS_OPEN_REJECT;
2700 		ts->open_rej_reason = SAS_OREJ_EPROTO;
2701 		break;
2702 	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2703 		pm8001_dbg(pm8001_ha, IO,
2704 			   "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2705 		ts->resp = SAS_TASK_COMPLETE;
2706 		ts->stat = SAS_OPEN_REJECT;
2707 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2708 		break;
2709 	case IO_OPEN_CNX_ERROR_BREAK:
2710 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2711 		ts->resp = SAS_TASK_COMPLETE;
2712 		ts->stat = SAS_OPEN_REJECT;
2713 		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2714 		break;
2715 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2716 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2717 		ts->resp = SAS_TASK_UNDELIVERED;
2718 		ts->stat = SAS_DEV_NO_RESPONSE;
2719 		if (!t->uldd_task) {
2720 			pm8001_handle_event(pm8001_ha,
2721 				pm8001_dev,
2722 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2723 			ts->resp = SAS_TASK_COMPLETE;
2724 			ts->stat = SAS_QUEUE_FULL;
2725 			pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2726 			return;
2727 		}
2728 		break;
2729 	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2730 		pm8001_dbg(pm8001_ha, IO,
2731 			   "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2732 		ts->resp = SAS_TASK_UNDELIVERED;
2733 		ts->stat = SAS_OPEN_REJECT;
2734 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2735 		break;
2736 	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2737 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2738 		ts->resp = SAS_TASK_COMPLETE;
2739 		ts->stat = SAS_OPEN_REJECT;
2740 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2741 		break;
2742 	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2743 		pm8001_dbg(pm8001_ha, IO,
2744 			   "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2745 		ts->resp = SAS_TASK_COMPLETE;
2746 		ts->stat = SAS_OPEN_REJECT;
2747 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2748 		break;
2749 	case IO_XFER_ERROR_NAK_RECEIVED:
2750 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2751 		ts->resp = SAS_TASK_COMPLETE;
2752 		ts->stat = SAS_NAK_R_ERR;
2753 		break;
2754 	case IO_XFER_ERROR_PEER_ABORTED:
2755 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2756 		ts->resp = SAS_TASK_COMPLETE;
2757 		ts->stat = SAS_NAK_R_ERR;
2758 		break;
2759 	case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2760 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2761 		ts->resp = SAS_TASK_COMPLETE;
2762 		ts->stat = SAS_DATA_UNDERRUN;
2763 		break;
2764 	case IO_XFER_OPEN_RETRY_TIMEOUT:
2765 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2766 		ts->resp = SAS_TASK_COMPLETE;
2767 		ts->stat = SAS_OPEN_TO;
2768 		break;
2769 	case IO_XFER_ERROR_UNEXPECTED_PHASE:
2770 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2771 		ts->resp = SAS_TASK_COMPLETE;
2772 		ts->stat = SAS_OPEN_TO;
2773 		break;
2774 	case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2775 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2776 		ts->resp = SAS_TASK_COMPLETE;
2777 		ts->stat = SAS_OPEN_TO;
2778 		break;
2779 	case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2780 		pm8001_dbg(pm8001_ha, IO,
2781 			   "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2782 		ts->resp = SAS_TASK_COMPLETE;
2783 		ts->stat = SAS_OPEN_TO;
2784 		break;
2785 	case IO_XFER_ERROR_OFFSET_MISMATCH:
2786 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2787 		ts->resp = SAS_TASK_COMPLETE;
2788 		ts->stat = SAS_OPEN_TO;
2789 		break;
2790 	case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2791 		pm8001_dbg(pm8001_ha, IO,
2792 			   "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2793 		ts->resp = SAS_TASK_COMPLETE;
2794 		ts->stat = SAS_OPEN_TO;
2795 		break;
2796 	case IO_XFER_CMD_FRAME_ISSUED:
2797 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2798 		break;
2799 	case IO_XFER_PIO_SETUP_ERROR:
2800 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2801 		ts->resp = SAS_TASK_COMPLETE;
2802 		ts->stat = SAS_OPEN_TO;
2803 		break;
2804 	default:
2805 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2806 		/* not allowed case. Therefore, return failed status */
2807 		ts->resp = SAS_TASK_COMPLETE;
2808 		ts->stat = SAS_OPEN_TO;
2809 		break;
2810 	}
2811 	spin_lock_irqsave(&t->task_state_lock, flags);
2812 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2813 	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2814 	t->task_state_flags |= SAS_TASK_STATE_DONE;
2815 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2816 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2817 		pm8001_dbg(pm8001_ha, FAIL,
2818 			   "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2819 			   t, event, ts->resp, ts->stat);
2820 		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2821 	} else {
2822 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2823 		pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2824 	}
2825 }
2826 
2827 /*See the comments for mpi_ssp_completion */
2828 static void
mpi_smp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)2829 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2830 {
2831 	struct sas_task *t;
2832 	struct pm8001_ccb_info *ccb;
2833 	unsigned long flags;
2834 	u32 status;
2835 	u32 tag;
2836 	struct smp_completion_resp *psmpPayload;
2837 	struct task_status_struct *ts;
2838 	struct pm8001_device *pm8001_dev;
2839 
2840 	psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2841 	status = le32_to_cpu(psmpPayload->status);
2842 	tag = le32_to_cpu(psmpPayload->tag);
2843 
2844 	ccb = &pm8001_ha->ccb_info[tag];
2845 	t = ccb->task;
2846 	ts = &t->task_status;
2847 	pm8001_dev = ccb->device;
2848 	if (status) {
2849 		pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2850 		pm8001_dbg(pm8001_ha, IOERR,
2851 			   "status:0x%x, tag:0x%x, task:0x%p\n",
2852 			   status, tag, t);
2853 	}
2854 	if (unlikely(!t || !t->lldd_task || !t->dev))
2855 		return;
2856 
2857 	switch (status) {
2858 	case IO_SUCCESS:
2859 		pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2860 		ts->resp = SAS_TASK_COMPLETE;
2861 		ts->stat = SAM_STAT_GOOD;
2862 		if (pm8001_dev)
2863 			atomic_dec(&pm8001_dev->running_req);
2864 		break;
2865 	case IO_ABORTED:
2866 		pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
2867 		ts->resp = SAS_TASK_COMPLETE;
2868 		ts->stat = SAS_ABORTED_TASK;
2869 		if (pm8001_dev)
2870 			atomic_dec(&pm8001_dev->running_req);
2871 		break;
2872 	case IO_OVERFLOW:
2873 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2874 		ts->resp = SAS_TASK_COMPLETE;
2875 		ts->stat = SAS_DATA_OVERRUN;
2876 		ts->residual = 0;
2877 		if (pm8001_dev)
2878 			atomic_dec(&pm8001_dev->running_req);
2879 		break;
2880 	case IO_NO_DEVICE:
2881 		pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2882 		ts->resp = SAS_TASK_COMPLETE;
2883 		ts->stat = SAS_PHY_DOWN;
2884 		break;
2885 	case IO_ERROR_HW_TIMEOUT:
2886 		pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
2887 		ts->resp = SAS_TASK_COMPLETE;
2888 		ts->stat = SAM_STAT_BUSY;
2889 		break;
2890 	case IO_XFER_ERROR_BREAK:
2891 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2892 		ts->resp = SAS_TASK_COMPLETE;
2893 		ts->stat = SAM_STAT_BUSY;
2894 		break;
2895 	case IO_XFER_ERROR_PHY_NOT_READY:
2896 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2897 		ts->resp = SAS_TASK_COMPLETE;
2898 		ts->stat = SAM_STAT_BUSY;
2899 		break;
2900 	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2901 		pm8001_dbg(pm8001_ha, IO,
2902 			   "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2903 		ts->resp = SAS_TASK_COMPLETE;
2904 		ts->stat = SAS_OPEN_REJECT;
2905 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2906 		break;
2907 	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2908 		pm8001_dbg(pm8001_ha, IO,
2909 			   "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2910 		ts->resp = SAS_TASK_COMPLETE;
2911 		ts->stat = SAS_OPEN_REJECT;
2912 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2913 		break;
2914 	case IO_OPEN_CNX_ERROR_BREAK:
2915 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2916 		ts->resp = SAS_TASK_COMPLETE;
2917 		ts->stat = SAS_OPEN_REJECT;
2918 		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2919 		break;
2920 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2921 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2922 		ts->resp = SAS_TASK_COMPLETE;
2923 		ts->stat = SAS_OPEN_REJECT;
2924 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2925 		pm8001_handle_event(pm8001_ha,
2926 				pm8001_dev,
2927 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2928 		break;
2929 	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2930 		pm8001_dbg(pm8001_ha, IO,
2931 			   "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2932 		ts->resp = SAS_TASK_COMPLETE;
2933 		ts->stat = SAS_OPEN_REJECT;
2934 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2935 		break;
2936 	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2937 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2938 		ts->resp = SAS_TASK_COMPLETE;
2939 		ts->stat = SAS_OPEN_REJECT;
2940 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2941 		break;
2942 	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2943 		pm8001_dbg(pm8001_ha, IO,
2944 			   "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2945 		ts->resp = SAS_TASK_COMPLETE;
2946 		ts->stat = SAS_OPEN_REJECT;
2947 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2948 		break;
2949 	case IO_XFER_ERROR_RX_FRAME:
2950 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
2951 		ts->resp = SAS_TASK_COMPLETE;
2952 		ts->stat = SAS_DEV_NO_RESPONSE;
2953 		break;
2954 	case IO_XFER_OPEN_RETRY_TIMEOUT:
2955 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2956 		ts->resp = SAS_TASK_COMPLETE;
2957 		ts->stat = SAS_OPEN_REJECT;
2958 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2959 		break;
2960 	case IO_ERROR_INTERNAL_SMP_RESOURCE:
2961 		pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
2962 		ts->resp = SAS_TASK_COMPLETE;
2963 		ts->stat = SAS_QUEUE_FULL;
2964 		break;
2965 	case IO_PORT_IN_RESET:
2966 		pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2967 		ts->resp = SAS_TASK_COMPLETE;
2968 		ts->stat = SAS_OPEN_REJECT;
2969 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2970 		break;
2971 	case IO_DS_NON_OPERATIONAL:
2972 		pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2973 		ts->resp = SAS_TASK_COMPLETE;
2974 		ts->stat = SAS_DEV_NO_RESPONSE;
2975 		break;
2976 	case IO_DS_IN_RECOVERY:
2977 		pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2978 		ts->resp = SAS_TASK_COMPLETE;
2979 		ts->stat = SAS_OPEN_REJECT;
2980 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2981 		break;
2982 	case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2983 		pm8001_dbg(pm8001_ha, IO,
2984 			   "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2985 		ts->resp = SAS_TASK_COMPLETE;
2986 		ts->stat = SAS_OPEN_REJECT;
2987 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2988 		break;
2989 	default:
2990 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2991 		ts->resp = SAS_TASK_COMPLETE;
2992 		ts->stat = SAS_DEV_NO_RESPONSE;
2993 		/* not allowed case. Therefore, return failed status */
2994 		break;
2995 	}
2996 	spin_lock_irqsave(&t->task_state_lock, flags);
2997 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2998 	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2999 	t->task_state_flags |= SAS_TASK_STATE_DONE;
3000 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3001 		spin_unlock_irqrestore(&t->task_state_lock, flags);
3002 		pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
3003 			   t, status, ts->resp, ts->stat);
3004 		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3005 	} else {
3006 		spin_unlock_irqrestore(&t->task_state_lock, flags);
3007 		pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3008 		mb();/* in order to force CPU ordering */
3009 		t->task_done(t);
3010 	}
3011 }
3012 
pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3013 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3014 		void *piomb)
3015 {
3016 	struct set_dev_state_resp *pPayload =
3017 		(struct set_dev_state_resp *)(piomb + 4);
3018 	u32 tag = le32_to_cpu(pPayload->tag);
3019 	struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3020 	struct pm8001_device *pm8001_dev = ccb->device;
3021 	u32 status = le32_to_cpu(pPayload->status);
3022 	u32 device_id = le32_to_cpu(pPayload->device_id);
3023 	u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3024 	u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3025 	pm8001_dbg(pm8001_ha, MSG, "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n",
3026 		   device_id, pds, nds, status);
3027 	complete(pm8001_dev->setds_completion);
3028 	ccb->task = NULL;
3029 	ccb->ccb_tag = 0xFFFFFFFF;
3030 	pm8001_tag_free(pm8001_ha, tag);
3031 }
3032 
pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3033 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3034 {
3035 	struct get_nvm_data_resp *pPayload =
3036 		(struct get_nvm_data_resp *)(piomb + 4);
3037 	u32 tag = le32_to_cpu(pPayload->tag);
3038 	struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3039 	u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3040 	complete(pm8001_ha->nvmd_completion);
3041 	pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n");
3042 	if ((dlen_status & NVMD_STAT) != 0) {
3043 		pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error!\n");
3044 		return;
3045 	}
3046 	ccb->task = NULL;
3047 	ccb->ccb_tag = 0xFFFFFFFF;
3048 	pm8001_tag_free(pm8001_ha, tag);
3049 }
3050 
3051 void
pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3052 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3053 {
3054 	struct fw_control_ex    *fw_control_context;
3055 	struct get_nvm_data_resp *pPayload =
3056 		(struct get_nvm_data_resp *)(piomb + 4);
3057 	u32 tag = le32_to_cpu(pPayload->tag);
3058 	struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3059 	u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3060 	u32 ir_tds_bn_dps_das_nvm =
3061 		le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3062 	void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3063 	fw_control_context = ccb->fw_control_context;
3064 
3065 	pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n");
3066 	if ((dlen_status & NVMD_STAT) != 0) {
3067 		pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error!\n");
3068 		complete(pm8001_ha->nvmd_completion);
3069 		return;
3070 	}
3071 
3072 	if (ir_tds_bn_dps_das_nvm & IPMode) {
3073 		/* indirect mode - IR bit set */
3074 		pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n");
3075 		if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3076 			if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3077 				memcpy(pm8001_ha->sas_addr,
3078 				      ((u8 *)virt_addr + 4),
3079 				       SAS_ADDR_SIZE);
3080 				pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n");
3081 			}
3082 		} else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3083 			|| ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3084 			((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3085 				;
3086 		} else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3087 			|| ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3088 			;
3089 		} else {
3090 			/* Should not be happened*/
3091 			pm8001_dbg(pm8001_ha, MSG,
3092 				   "(IR=1)Wrong Device type 0x%x\n",
3093 				   ir_tds_bn_dps_das_nvm);
3094 		}
3095 	} else /* direct mode */{
3096 		pm8001_dbg(pm8001_ha, MSG,
3097 			   "Get NVMD success, IR=0, dataLen=%d\n",
3098 			   (dlen_status & NVMD_LEN) >> 24);
3099 	}
3100 	/* Though fw_control_context is freed below, usrAddr still needs
3101 	 * to be updated as this holds the response to the request function
3102 	 */
3103 	memcpy(fw_control_context->usrAddr,
3104 		pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3105 		fw_control_context->len);
3106 	kfree(ccb->fw_control_context);
3107 	/* To avoid race condition, complete should be
3108 	 * called after the message is copied to
3109 	 * fw_control_context->usrAddr
3110 	 */
3111 	complete(pm8001_ha->nvmd_completion);
3112 	pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n");
3113 	ccb->task = NULL;
3114 	ccb->ccb_tag = 0xFFFFFFFF;
3115 	pm8001_tag_free(pm8001_ha, tag);
3116 }
3117 
pm8001_mpi_local_phy_ctl(struct pm8001_hba_info * pm8001_ha,void * piomb)3118 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3119 {
3120 	u32 tag;
3121 	struct local_phy_ctl_resp *pPayload =
3122 		(struct local_phy_ctl_resp *)(piomb + 4);
3123 	u32 status = le32_to_cpu(pPayload->status);
3124 	u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3125 	u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3126 	tag = le32_to_cpu(pPayload->tag);
3127 	if (status != 0) {
3128 		pm8001_dbg(pm8001_ha, MSG,
3129 			   "%x phy execute %x phy op failed!\n",
3130 			   phy_id, phy_op);
3131 	} else {
3132 		pm8001_dbg(pm8001_ha, MSG,
3133 			   "%x phy execute %x phy op success!\n",
3134 			   phy_id, phy_op);
3135 		pm8001_ha->phy[phy_id].reset_success = true;
3136 	}
3137 	if (pm8001_ha->phy[phy_id].enable_completion) {
3138 		complete(pm8001_ha->phy[phy_id].enable_completion);
3139 		pm8001_ha->phy[phy_id].enable_completion = NULL;
3140 	}
3141 	pm8001_tag_free(pm8001_ha, tag);
3142 	return 0;
3143 }
3144 
3145 /**
3146  * pm8001_bytes_dmaed - one of the interface function communication with libsas
3147  * @pm8001_ha: our hba card information
3148  * @i: which phy that received the event.
3149  *
3150  * when HBA driver received the identify done event or initiate FIS received
3151  * event(for SATA), it will invoke this function to notify the sas layer that
3152  * the sas toplogy has formed, please discover the the whole sas domain,
3153  * while receive a broadcast(change) primitive just tell the sas
3154  * layer to discover the changed domain rather than the whole domain.
3155  */
pm8001_bytes_dmaed(struct pm8001_hba_info * pm8001_ha,int i)3156 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3157 {
3158 	struct pm8001_phy *phy = &pm8001_ha->phy[i];
3159 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
3160 	if (!phy->phy_attached)
3161 		return;
3162 
3163 	if (sas_phy->phy) {
3164 		struct sas_phy *sphy = sas_phy->phy;
3165 		sphy->negotiated_linkrate = sas_phy->linkrate;
3166 		sphy->minimum_linkrate = phy->minimum_linkrate;
3167 		sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3168 		sphy->maximum_linkrate = phy->maximum_linkrate;
3169 		sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3170 	}
3171 
3172 	if (phy->phy_type & PORT_TYPE_SAS) {
3173 		struct sas_identify_frame *id;
3174 		id = (struct sas_identify_frame *)phy->frame_rcvd;
3175 		id->dev_type = phy->identify.device_type;
3176 		id->initiator_bits = SAS_PROTOCOL_ALL;
3177 		id->target_bits = phy->identify.target_port_protocols;
3178 	} else if (phy->phy_type & PORT_TYPE_SATA) {
3179 		/*Nothing*/
3180 	}
3181 	pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i);
3182 
3183 	sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3184 	sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3185 }
3186 
3187 /* Get the link rate speed  */
pm8001_get_lrate_mode(struct pm8001_phy * phy,u8 link_rate)3188 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3189 {
3190 	struct sas_phy *sas_phy = phy->sas_phy.phy;
3191 
3192 	switch (link_rate) {
3193 	case PHY_SPEED_120:
3194 		phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3195 		phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS;
3196 		break;
3197 	case PHY_SPEED_60:
3198 		phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3199 		phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3200 		break;
3201 	case PHY_SPEED_30:
3202 		phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3203 		phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3204 		break;
3205 	case PHY_SPEED_15:
3206 		phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3207 		phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3208 		break;
3209 	}
3210 	sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3211 	sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3212 	sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3213 	sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3214 	sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3215 }
3216 
3217 /**
3218  * asd_get_attached_sas_addr -- extract/generate attached SAS address
3219  * @phy: pointer to asd_phy
3220  * @sas_addr: pointer to buffer where the SAS address is to be written
3221  *
3222  * This function extracts the SAS address from an IDENTIFY frame
3223  * received.  If OOB is SATA, then a SAS address is generated from the
3224  * HA tables.
3225  *
3226  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3227  * buffer.
3228  */
pm8001_get_attached_sas_addr(struct pm8001_phy * phy,u8 * sas_addr)3229 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3230 	u8 *sas_addr)
3231 {
3232 	if (phy->sas_phy.frame_rcvd[0] == 0x34
3233 		&& phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3234 		struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3235 		/* FIS device-to-host */
3236 		u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3237 		addr += phy->sas_phy.id;
3238 		*(__be64 *)sas_addr = cpu_to_be64(addr);
3239 	} else {
3240 		struct sas_identify_frame *idframe =
3241 			(void *) phy->sas_phy.frame_rcvd;
3242 		memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3243 	}
3244 }
3245 
3246 /**
3247  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3248  * @pm8001_ha: our hba card information
3249  * @Qnum: the outbound queue message number.
3250  * @SEA: source of event to ack
3251  * @port_id: port id.
3252  * @phyId: phy id.
3253  * @param0: parameter 0.
3254  * @param1: parameter 1.
3255  */
pm8001_hw_event_ack_req(struct pm8001_hba_info * pm8001_ha,u32 Qnum,u32 SEA,u32 port_id,u32 phyId,u32 param0,u32 param1)3256 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3257 	u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3258 {
3259 	struct hw_event_ack_req	 payload;
3260 	u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3261 
3262 	struct inbound_queue_table *circularQ;
3263 
3264 	memset((u8 *)&payload, 0, sizeof(payload));
3265 	circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3266 	payload.tag = cpu_to_le32(1);
3267 	payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3268 		((phyId & 0x0F) << 4) | (port_id & 0x0F));
3269 	payload.param0 = cpu_to_le32(param0);
3270 	payload.param1 = cpu_to_le32(param1);
3271 	pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3272 			sizeof(payload), 0);
3273 }
3274 
3275 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3276 	u32 phyId, u32 phy_op);
3277 
3278 /**
3279  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3280  * @pm8001_ha: our hba card information
3281  * @piomb: IO message buffer
3282  */
3283 static void
hw_event_sas_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3284 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3285 {
3286 	struct hw_event_resp *pPayload =
3287 		(struct hw_event_resp *)(piomb + 4);
3288 	u32 lr_evt_status_phyid_portid =
3289 		le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3290 	u8 link_rate =
3291 		(u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3292 	u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3293 	u8 phy_id =
3294 		(u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3295 	u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3296 	u8 portstate = (u8)(npip_portstate & 0x0000000F);
3297 	struct pm8001_port *port = &pm8001_ha->port[port_id];
3298 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3299 	unsigned long flags;
3300 	u8 deviceType = pPayload->sas_identify.dev_type;
3301 	port->port_state =  portstate;
3302 	phy->phy_state = PHY_STATE_LINK_UP_SPC;
3303 	pm8001_dbg(pm8001_ha, MSG,
3304 		   "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3305 		   port_id, phy_id);
3306 
3307 	switch (deviceType) {
3308 	case SAS_PHY_UNUSED:
3309 		pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3310 		break;
3311 	case SAS_END_DEVICE:
3312 		pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3313 		pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3314 			PHY_NOTIFY_ENABLE_SPINUP);
3315 		port->port_attached = 1;
3316 		pm8001_get_lrate_mode(phy, link_rate);
3317 		break;
3318 	case SAS_EDGE_EXPANDER_DEVICE:
3319 		pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3320 		port->port_attached = 1;
3321 		pm8001_get_lrate_mode(phy, link_rate);
3322 		break;
3323 	case SAS_FANOUT_EXPANDER_DEVICE:
3324 		pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3325 		port->port_attached = 1;
3326 		pm8001_get_lrate_mode(phy, link_rate);
3327 		break;
3328 	default:
3329 		pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3330 			   deviceType);
3331 		break;
3332 	}
3333 	phy->phy_type |= PORT_TYPE_SAS;
3334 	phy->identify.device_type = deviceType;
3335 	phy->phy_attached = 1;
3336 	if (phy->identify.device_type == SAS_END_DEVICE)
3337 		phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3338 	else if (phy->identify.device_type != SAS_PHY_UNUSED)
3339 		phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3340 	phy->sas_phy.oob_mode = SAS_OOB_MODE;
3341 	sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3342 	spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3343 	memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3344 		sizeof(struct sas_identify_frame)-4);
3345 	phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3346 	pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3347 	spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3348 	if (pm8001_ha->flags == PM8001F_RUN_TIME)
3349 		mdelay(200);/*delay a moment to wait disk to spinup*/
3350 	pm8001_bytes_dmaed(pm8001_ha, phy_id);
3351 }
3352 
3353 /**
3354  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3355  * @pm8001_ha: our hba card information
3356  * @piomb: IO message buffer
3357  */
3358 static void
hw_event_sata_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3359 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3360 {
3361 	struct hw_event_resp *pPayload =
3362 		(struct hw_event_resp *)(piomb + 4);
3363 	u32 lr_evt_status_phyid_portid =
3364 		le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3365 	u8 link_rate =
3366 		(u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3367 	u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3368 	u8 phy_id =
3369 		(u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3370 	u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3371 	u8 portstate = (u8)(npip_portstate & 0x0000000F);
3372 	struct pm8001_port *port = &pm8001_ha->port[port_id];
3373 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3374 	unsigned long flags;
3375 	pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n",
3376 		   port_id, phy_id);
3377 	port->port_state =  portstate;
3378 	phy->phy_state = PHY_STATE_LINK_UP_SPC;
3379 	port->port_attached = 1;
3380 	pm8001_get_lrate_mode(phy, link_rate);
3381 	phy->phy_type |= PORT_TYPE_SATA;
3382 	phy->phy_attached = 1;
3383 	phy->sas_phy.oob_mode = SATA_OOB_MODE;
3384 	sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3385 	spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3386 	memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3387 		sizeof(struct dev_to_host_fis));
3388 	phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3389 	phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3390 	phy->identify.device_type = SAS_SATA_DEV;
3391 	pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3392 	spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3393 	pm8001_bytes_dmaed(pm8001_ha, phy_id);
3394 }
3395 
3396 /**
3397  * hw_event_phy_down -we should notify the libsas the phy is down.
3398  * @pm8001_ha: our hba card information
3399  * @piomb: IO message buffer
3400  */
3401 static void
hw_event_phy_down(struct pm8001_hba_info * pm8001_ha,void * piomb)3402 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3403 {
3404 	struct hw_event_resp *pPayload =
3405 		(struct hw_event_resp *)(piomb + 4);
3406 	u32 lr_evt_status_phyid_portid =
3407 		le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3408 	u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3409 	u8 phy_id =
3410 		(u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3411 	u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3412 	u8 portstate = (u8)(npip_portstate & 0x0000000F);
3413 	struct pm8001_port *port = &pm8001_ha->port[port_id];
3414 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3415 	port->port_state =  portstate;
3416 	phy->phy_type = 0;
3417 	phy->identify.device_type = 0;
3418 	phy->phy_attached = 0;
3419 	memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3420 	switch (portstate) {
3421 	case PORT_VALID:
3422 		break;
3423 	case PORT_INVALID:
3424 		pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3425 			   port_id);
3426 		pm8001_dbg(pm8001_ha, MSG,
3427 			   " Last phy Down and port invalid\n");
3428 		port->port_attached = 0;
3429 		pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3430 			port_id, phy_id, 0, 0);
3431 		break;
3432 	case PORT_IN_RESET:
3433 		pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3434 			   port_id);
3435 		break;
3436 	case PORT_NOT_ESTABLISHED:
3437 		pm8001_dbg(pm8001_ha, MSG,
3438 			   " phy Down and PORT_NOT_ESTABLISHED\n");
3439 		port->port_attached = 0;
3440 		break;
3441 	case PORT_LOSTCOMM:
3442 		pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n");
3443 		pm8001_dbg(pm8001_ha, MSG,
3444 			   " Last phy Down and port invalid\n");
3445 		port->port_attached = 0;
3446 		pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3447 			port_id, phy_id, 0, 0);
3448 		break;
3449 	default:
3450 		port->port_attached = 0;
3451 		pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n",
3452 			   portstate);
3453 		break;
3454 
3455 	}
3456 }
3457 
3458 /**
3459  * pm8001_mpi_reg_resp -process register device ID response.
3460  * @pm8001_ha: our hba card information
3461  * @piomb: IO message buffer
3462  *
3463  * when sas layer find a device it will notify LLDD, then the driver register
3464  * the domain device to FW, this event is the return device ID which the FW
3465  * has assigned, from now,inter-communication with FW is no longer using the
3466  * SAS address, use device ID which FW assigned.
3467  */
pm8001_mpi_reg_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3468 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3469 {
3470 	u32 status;
3471 	u32 device_id;
3472 	u32 htag;
3473 	struct pm8001_ccb_info *ccb;
3474 	struct pm8001_device *pm8001_dev;
3475 	struct dev_reg_resp *registerRespPayload =
3476 		(struct dev_reg_resp *)(piomb + 4);
3477 
3478 	htag = le32_to_cpu(registerRespPayload->tag);
3479 	ccb = &pm8001_ha->ccb_info[htag];
3480 	pm8001_dev = ccb->device;
3481 	status = le32_to_cpu(registerRespPayload->status);
3482 	device_id = le32_to_cpu(registerRespPayload->device_id);
3483 	pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n",
3484 		   status);
3485 	switch (status) {
3486 	case DEVREG_SUCCESS:
3487 		pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n");
3488 		pm8001_dev->device_id = device_id;
3489 		break;
3490 	case DEVREG_FAILURE_OUT_OF_RESOURCE:
3491 		pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n");
3492 		break;
3493 	case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3494 		pm8001_dbg(pm8001_ha, MSG,
3495 			   "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n");
3496 		break;
3497 	case DEVREG_FAILURE_INVALID_PHY_ID:
3498 		pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n");
3499 		break;
3500 	case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3501 		pm8001_dbg(pm8001_ha, MSG,
3502 			   "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n");
3503 		break;
3504 	case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3505 		pm8001_dbg(pm8001_ha, MSG,
3506 			   "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n");
3507 		break;
3508 	case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3509 		pm8001_dbg(pm8001_ha, MSG,
3510 			   "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n");
3511 		break;
3512 	case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3513 		pm8001_dbg(pm8001_ha, MSG,
3514 			   "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n");
3515 		break;
3516 	default:
3517 		pm8001_dbg(pm8001_ha, MSG,
3518 			   "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n");
3519 		break;
3520 	}
3521 	complete(pm8001_dev->dcompletion);
3522 	ccb->task = NULL;
3523 	ccb->ccb_tag = 0xFFFFFFFF;
3524 	pm8001_tag_free(pm8001_ha, htag);
3525 	return 0;
3526 }
3527 
pm8001_mpi_dereg_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3528 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3529 {
3530 	u32 status;
3531 	u32 device_id;
3532 	struct dev_reg_resp *registerRespPayload =
3533 		(struct dev_reg_resp *)(piomb + 4);
3534 
3535 	status = le32_to_cpu(registerRespPayload->status);
3536 	device_id = le32_to_cpu(registerRespPayload->device_id);
3537 	if (status != 0)
3538 		pm8001_dbg(pm8001_ha, MSG,
3539 			   " deregister device failed ,status = %x, device_id = %x\n",
3540 			   status, device_id);
3541 	return 0;
3542 }
3543 
3544 /**
3545  * fw_flash_update_resp - Response from FW for flash update command.
3546  * @pm8001_ha: our hba card information
3547  * @piomb: IO message buffer
3548  */
pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3549 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3550 		void *piomb)
3551 {
3552 	u32 status;
3553 	struct fw_flash_Update_resp *ppayload =
3554 		(struct fw_flash_Update_resp *)(piomb + 4);
3555 	u32 tag = le32_to_cpu(ppayload->tag);
3556 	struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3557 	status = le32_to_cpu(ppayload->status);
3558 	switch (status) {
3559 	case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3560 		pm8001_dbg(pm8001_ha, MSG,
3561 			   ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n");
3562 		break;
3563 	case FLASH_UPDATE_IN_PROGRESS:
3564 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n");
3565 		break;
3566 	case FLASH_UPDATE_HDR_ERR:
3567 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n");
3568 		break;
3569 	case FLASH_UPDATE_OFFSET_ERR:
3570 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n");
3571 		break;
3572 	case FLASH_UPDATE_CRC_ERR:
3573 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n");
3574 		break;
3575 	case FLASH_UPDATE_LENGTH_ERR:
3576 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n");
3577 		break;
3578 	case FLASH_UPDATE_HW_ERR:
3579 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n");
3580 		break;
3581 	case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3582 		pm8001_dbg(pm8001_ha, MSG,
3583 			   ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n");
3584 		break;
3585 	case FLASH_UPDATE_DISABLED:
3586 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n");
3587 		break;
3588 	default:
3589 		pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n",
3590 			   status);
3591 		break;
3592 	}
3593 	kfree(ccb->fw_control_context);
3594 	ccb->task = NULL;
3595 	ccb->ccb_tag = 0xFFFFFFFF;
3596 	pm8001_tag_free(pm8001_ha, tag);
3597 	complete(pm8001_ha->nvmd_completion);
3598 	return 0;
3599 }
3600 
pm8001_mpi_general_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3601 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3602 {
3603 	u32 status;
3604 	int i;
3605 	struct general_event_resp *pPayload =
3606 		(struct general_event_resp *)(piomb + 4);
3607 	status = le32_to_cpu(pPayload->status);
3608 	pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status);
3609 	for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3610 		pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n",
3611 			   i,
3612 			   pPayload->inb_IOMB_payload[i]);
3613 	return 0;
3614 }
3615 
pm8001_mpi_task_abort_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3616 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3617 {
3618 	struct sas_task *t;
3619 	struct pm8001_ccb_info *ccb;
3620 	unsigned long flags;
3621 	u32 status ;
3622 	u32 tag, scp;
3623 	struct task_status_struct *ts;
3624 	struct pm8001_device *pm8001_dev;
3625 
3626 	struct task_abort_resp *pPayload =
3627 		(struct task_abort_resp *)(piomb + 4);
3628 
3629 	status = le32_to_cpu(pPayload->status);
3630 	tag = le32_to_cpu(pPayload->tag);
3631 	if (!tag) {
3632 		pm8001_dbg(pm8001_ha, FAIL, " TAG NULL. RETURNING !!!\n");
3633 		return -1;
3634 	}
3635 
3636 	scp = le32_to_cpu(pPayload->scp);
3637 	ccb = &pm8001_ha->ccb_info[tag];
3638 	t = ccb->task;
3639 	pm8001_dev = ccb->device; /* retrieve device */
3640 
3641 	if (!t)	{
3642 		pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n");
3643 		return -1;
3644 	}
3645 	ts = &t->task_status;
3646 	if (status != 0)
3647 		pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n",
3648 			   status, tag, scp);
3649 	switch (status) {
3650 	case IO_SUCCESS:
3651 		pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n");
3652 		ts->resp = SAS_TASK_COMPLETE;
3653 		ts->stat = SAM_STAT_GOOD;
3654 		break;
3655 	case IO_NOT_VALID:
3656 		pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n");
3657 		ts->resp = TMF_RESP_FUNC_FAILED;
3658 		break;
3659 	}
3660 	spin_lock_irqsave(&t->task_state_lock, flags);
3661 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3662 	t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3663 	t->task_state_flags |= SAS_TASK_STATE_DONE;
3664 	spin_unlock_irqrestore(&t->task_state_lock, flags);
3665 	pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3666 	mb();
3667 
3668 	if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3669 		pm8001_tag_free(pm8001_ha, tag);
3670 		sas_free_task(t);
3671 		/* clear the flag */
3672 		pm8001_dev->id &= 0xBFFFFFFF;
3673 	} else
3674 		t->task_done(t);
3675 
3676 	return 0;
3677 }
3678 
3679 /**
3680  * mpi_hw_event -The hw event has come.
3681  * @pm8001_ha: our hba card information
3682  * @piomb: IO message buffer
3683  */
mpi_hw_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3684 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3685 {
3686 	unsigned long flags;
3687 	struct hw_event_resp *pPayload =
3688 		(struct hw_event_resp *)(piomb + 4);
3689 	u32 lr_evt_status_phyid_portid =
3690 		le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3691 	u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3692 	u8 phy_id =
3693 		(u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3694 	u16 eventType =
3695 		(u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3696 	u8 status =
3697 		(u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3698 	struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3699 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3700 	struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3701 	pm8001_dbg(pm8001_ha, DEVIO,
3702 		   "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n",
3703 		   port_id, phy_id, eventType, status);
3704 	switch (eventType) {
3705 	case HW_EVENT_PHY_START_STATUS:
3706 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n",
3707 			   status);
3708 		if (status == 0)
3709 			phy->phy_state = 1;
3710 
3711 		if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3712 				phy->enable_completion != NULL) {
3713 			complete(phy->enable_completion);
3714 			phy->enable_completion = NULL;
3715 		}
3716 		break;
3717 	case HW_EVENT_SAS_PHY_UP:
3718 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3719 		hw_event_sas_phy_up(pm8001_ha, piomb);
3720 		break;
3721 	case HW_EVENT_SATA_PHY_UP:
3722 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3723 		hw_event_sata_phy_up(pm8001_ha, piomb);
3724 		break;
3725 	case HW_EVENT_PHY_STOP_STATUS:
3726 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n",
3727 			   status);
3728 		if (status == 0)
3729 			phy->phy_state = 0;
3730 		break;
3731 	case HW_EVENT_SATA_SPINUP_HOLD:
3732 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3733 		sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3734 		break;
3735 	case HW_EVENT_PHY_DOWN:
3736 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3737 		sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3738 		phy->phy_attached = 0;
3739 		phy->phy_state = 0;
3740 		hw_event_phy_down(pm8001_ha, piomb);
3741 		break;
3742 	case HW_EVENT_PORT_INVALID:
3743 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3744 		sas_phy_disconnected(sas_phy);
3745 		phy->phy_attached = 0;
3746 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3747 		break;
3748 	/* the broadcast change primitive received, tell the LIBSAS this event
3749 	to revalidate the sas domain*/
3750 	case HW_EVENT_BROADCAST_CHANGE:
3751 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3752 		pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3753 			port_id, phy_id, 1, 0);
3754 		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3755 		sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3756 		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3757 		sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3758 		break;
3759 	case HW_EVENT_PHY_ERROR:
3760 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3761 		sas_phy_disconnected(&phy->sas_phy);
3762 		phy->phy_attached = 0;
3763 		sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3764 		break;
3765 	case HW_EVENT_BROADCAST_EXP:
3766 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3767 		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3768 		sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3769 		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3770 		sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3771 		break;
3772 	case HW_EVENT_LINK_ERR_INVALID_DWORD:
3773 		pm8001_dbg(pm8001_ha, MSG,
3774 			   "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3775 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3776 			HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3777 		sas_phy_disconnected(sas_phy);
3778 		phy->phy_attached = 0;
3779 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3780 		break;
3781 	case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3782 		pm8001_dbg(pm8001_ha, MSG,
3783 			   "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3784 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3785 			HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3786 			port_id, phy_id, 0, 0);
3787 		sas_phy_disconnected(sas_phy);
3788 		phy->phy_attached = 0;
3789 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3790 		break;
3791 	case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3792 		pm8001_dbg(pm8001_ha, MSG,
3793 			   "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3794 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3795 			HW_EVENT_LINK_ERR_CODE_VIOLATION,
3796 			port_id, phy_id, 0, 0);
3797 		sas_phy_disconnected(sas_phy);
3798 		phy->phy_attached = 0;
3799 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3800 		break;
3801 	case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3802 		pm8001_dbg(pm8001_ha, MSG,
3803 			   "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3804 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3805 			HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3806 			port_id, phy_id, 0, 0);
3807 		sas_phy_disconnected(sas_phy);
3808 		phy->phy_attached = 0;
3809 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3810 		break;
3811 	case HW_EVENT_MALFUNCTION:
3812 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3813 		break;
3814 	case HW_EVENT_BROADCAST_SES:
3815 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3816 		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3817 		sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3818 		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3819 		sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3820 		break;
3821 	case HW_EVENT_INBOUND_CRC_ERROR:
3822 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3823 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3824 			HW_EVENT_INBOUND_CRC_ERROR,
3825 			port_id, phy_id, 0, 0);
3826 		break;
3827 	case HW_EVENT_HARD_RESET_RECEIVED:
3828 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3829 		sas_notify_port_event(sas_phy, PORTE_HARD_RESET);
3830 		break;
3831 	case HW_EVENT_ID_FRAME_TIMEOUT:
3832 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3833 		sas_phy_disconnected(sas_phy);
3834 		phy->phy_attached = 0;
3835 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3836 		break;
3837 	case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3838 		pm8001_dbg(pm8001_ha, MSG,
3839 			   "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3840 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3841 			HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3842 			port_id, phy_id, 0, 0);
3843 		sas_phy_disconnected(sas_phy);
3844 		phy->phy_attached = 0;
3845 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3846 		break;
3847 	case HW_EVENT_PORT_RESET_TIMER_TMO:
3848 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3849 		sas_phy_disconnected(sas_phy);
3850 		phy->phy_attached = 0;
3851 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3852 		break;
3853 	case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3854 		pm8001_dbg(pm8001_ha, MSG,
3855 			   "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3856 		sas_phy_disconnected(sas_phy);
3857 		phy->phy_attached = 0;
3858 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3859 		break;
3860 	case HW_EVENT_PORT_RECOVER:
3861 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3862 		break;
3863 	case HW_EVENT_PORT_RESET_COMPLETE:
3864 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3865 		break;
3866 	case EVENT_BROADCAST_ASYNCH_EVENT:
3867 		pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3868 		break;
3869 	default:
3870 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n",
3871 			   eventType);
3872 		break;
3873 	}
3874 	return 0;
3875 }
3876 
3877 /**
3878  * process_one_iomb - process one outbound Queue memory block
3879  * @pm8001_ha: our hba card information
3880  * @piomb: IO message buffer
3881  */
process_one_iomb(struct pm8001_hba_info * pm8001_ha,void * piomb)3882 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3883 {
3884 	__le32 pHeader = *(__le32 *)piomb;
3885 	u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3886 
3887 	pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n");
3888 
3889 	switch (opc) {
3890 	case OPC_OUB_ECHO:
3891 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3892 		break;
3893 	case OPC_OUB_HW_EVENT:
3894 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3895 		mpi_hw_event(pm8001_ha, piomb);
3896 		break;
3897 	case OPC_OUB_SSP_COMP:
3898 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3899 		mpi_ssp_completion(pm8001_ha, piomb);
3900 		break;
3901 	case OPC_OUB_SMP_COMP:
3902 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3903 		mpi_smp_completion(pm8001_ha, piomb);
3904 		break;
3905 	case OPC_OUB_LOCAL_PHY_CNTRL:
3906 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3907 		pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3908 		break;
3909 	case OPC_OUB_DEV_REGIST:
3910 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3911 		pm8001_mpi_reg_resp(pm8001_ha, piomb);
3912 		break;
3913 	case OPC_OUB_DEREG_DEV:
3914 		pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3915 		pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3916 		break;
3917 	case OPC_OUB_GET_DEV_HANDLE:
3918 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3919 		break;
3920 	case OPC_OUB_SATA_COMP:
3921 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3922 		mpi_sata_completion(pm8001_ha, piomb);
3923 		break;
3924 	case OPC_OUB_SATA_EVENT:
3925 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3926 		mpi_sata_event(pm8001_ha, piomb);
3927 		break;
3928 	case OPC_OUB_SSP_EVENT:
3929 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3930 		mpi_ssp_event(pm8001_ha, piomb);
3931 		break;
3932 	case OPC_OUB_DEV_HANDLE_ARRIV:
3933 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3934 		/*This is for target*/
3935 		break;
3936 	case OPC_OUB_SSP_RECV_EVENT:
3937 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3938 		/*This is for target*/
3939 		break;
3940 	case OPC_OUB_DEV_INFO:
3941 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n");
3942 		break;
3943 	case OPC_OUB_FW_FLASH_UPDATE:
3944 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3945 		pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3946 		break;
3947 	case OPC_OUB_GPIO_RESPONSE:
3948 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3949 		break;
3950 	case OPC_OUB_GPIO_EVENT:
3951 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3952 		break;
3953 	case OPC_OUB_GENERAL_EVENT:
3954 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3955 		pm8001_mpi_general_event(pm8001_ha, piomb);
3956 		break;
3957 	case OPC_OUB_SSP_ABORT_RSP:
3958 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3959 		pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3960 		break;
3961 	case OPC_OUB_SATA_ABORT_RSP:
3962 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3963 		pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3964 		break;
3965 	case OPC_OUB_SAS_DIAG_MODE_START_END:
3966 		pm8001_dbg(pm8001_ha, MSG,
3967 			   "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3968 		break;
3969 	case OPC_OUB_SAS_DIAG_EXECUTE:
3970 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3971 		break;
3972 	case OPC_OUB_GET_TIME_STAMP:
3973 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3974 		break;
3975 	case OPC_OUB_SAS_HW_EVENT_ACK:
3976 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3977 		break;
3978 	case OPC_OUB_PORT_CONTROL:
3979 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3980 		break;
3981 	case OPC_OUB_SMP_ABORT_RSP:
3982 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3983 		pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3984 		break;
3985 	case OPC_OUB_GET_NVMD_DATA:
3986 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3987 		pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3988 		break;
3989 	case OPC_OUB_SET_NVMD_DATA:
3990 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3991 		pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3992 		break;
3993 	case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3994 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
3995 		break;
3996 	case OPC_OUB_SET_DEVICE_STATE:
3997 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
3998 		pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3999 		break;
4000 	case OPC_OUB_GET_DEVICE_STATE:
4001 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
4002 		break;
4003 	case OPC_OUB_SET_DEV_INFO:
4004 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
4005 		break;
4006 	case OPC_OUB_SAS_RE_INITIALIZE:
4007 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n");
4008 		break;
4009 	default:
4010 		pm8001_dbg(pm8001_ha, DEVIO,
4011 			   "Unknown outbound Queue IOMB OPC = %x\n",
4012 			   opc);
4013 		break;
4014 	}
4015 }
4016 
process_oq(struct pm8001_hba_info * pm8001_ha,u8 vec)4017 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4018 {
4019 	struct outbound_queue_table *circularQ;
4020 	void *pMsg1 = NULL;
4021 	u8 bc;
4022 	u32 ret = MPI_IO_STATUS_FAIL;
4023 	unsigned long flags;
4024 
4025 	spin_lock_irqsave(&pm8001_ha->lock, flags);
4026 	circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4027 	do {
4028 		ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4029 		if (MPI_IO_STATUS_SUCCESS == ret) {
4030 			/* process the outbound message */
4031 			process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4032 			/* free the message from the outbound circular buffer */
4033 			pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4034 							circularQ, bc);
4035 		}
4036 		if (MPI_IO_STATUS_BUSY == ret) {
4037 			/* Update the producer index from SPC */
4038 			circularQ->producer_index =
4039 				cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4040 			if (le32_to_cpu(circularQ->producer_index) ==
4041 				circularQ->consumer_idx)
4042 				/* OQ is empty */
4043 				break;
4044 		}
4045 	} while (1);
4046 	spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4047 	return ret;
4048 }
4049 
4050 /* DMA_... to our direction translation. */
4051 static const u8 data_dir_flags[] = {
4052 	[DMA_BIDIRECTIONAL]	= DATA_DIR_BYRECIPIENT,	/* UNSPECIFIED */
4053 	[DMA_TO_DEVICE]		= DATA_DIR_OUT,		/* OUTBOUND */
4054 	[DMA_FROM_DEVICE]	= DATA_DIR_IN,		/* INBOUND */
4055 	[DMA_NONE]		= DATA_DIR_NONE,	/* NO TRANSFER */
4056 };
4057 void
pm8001_chip_make_sg(struct scatterlist * scatter,int nr,void * prd)4058 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4059 {
4060 	int i;
4061 	struct scatterlist *sg;
4062 	struct pm8001_prd *buf_prd = prd;
4063 
4064 	for_each_sg(scatter, sg, nr, i) {
4065 		buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4066 		buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4067 		buf_prd->im_len.e = 0;
4068 		buf_prd++;
4069 	}
4070 }
4071 
build_smp_cmd(u32 deviceID,__le32 hTag,struct smp_req * psmp_cmd)4072 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4073 {
4074 	psmp_cmd->tag = hTag;
4075 	psmp_cmd->device_id = cpu_to_le32(deviceID);
4076 	psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4077 }
4078 
4079 /**
4080  * pm8001_chip_smp_req - send a SMP task to FW
4081  * @pm8001_ha: our hba card information.
4082  * @ccb: the ccb information this request used.
4083  */
pm8001_chip_smp_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4084 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4085 	struct pm8001_ccb_info *ccb)
4086 {
4087 	int elem, rc;
4088 	struct sas_task *task = ccb->task;
4089 	struct domain_device *dev = task->dev;
4090 	struct pm8001_device *pm8001_dev = dev->lldd_dev;
4091 	struct scatterlist *sg_req, *sg_resp;
4092 	u32 req_len, resp_len;
4093 	struct smp_req smp_cmd;
4094 	u32 opc;
4095 	struct inbound_queue_table *circularQ;
4096 
4097 	memset(&smp_cmd, 0, sizeof(smp_cmd));
4098 	/*
4099 	 * DMA-map SMP request, response buffers
4100 	 */
4101 	sg_req = &task->smp_task.smp_req;
4102 	elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4103 	if (!elem)
4104 		return -ENOMEM;
4105 	req_len = sg_dma_len(sg_req);
4106 
4107 	sg_resp = &task->smp_task.smp_resp;
4108 	elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4109 	if (!elem) {
4110 		rc = -ENOMEM;
4111 		goto err_out;
4112 	}
4113 	resp_len = sg_dma_len(sg_resp);
4114 	/* must be in dwords */
4115 	if ((req_len & 0x3) || (resp_len & 0x3)) {
4116 		rc = -EINVAL;
4117 		goto err_out_2;
4118 	}
4119 
4120 	opc = OPC_INB_SMP_REQUEST;
4121 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4122 	smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4123 	smp_cmd.long_smp_req.long_req_addr =
4124 		cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4125 	smp_cmd.long_smp_req.long_req_size =
4126 		cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4127 	smp_cmd.long_smp_req.long_resp_addr =
4128 		cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4129 	smp_cmd.long_smp_req.long_resp_size =
4130 		cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4131 	build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4132 	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4133 			&smp_cmd, sizeof(smp_cmd), 0);
4134 	if (rc)
4135 		goto err_out_2;
4136 
4137 	return 0;
4138 
4139 err_out_2:
4140 	dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4141 			DMA_FROM_DEVICE);
4142 err_out:
4143 	dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4144 			DMA_TO_DEVICE);
4145 	return rc;
4146 }
4147 
4148 /**
4149  * pm8001_chip_ssp_io_req - send a SSP task to FW
4150  * @pm8001_ha: our hba card information.
4151  * @ccb: the ccb information this request used.
4152  */
pm8001_chip_ssp_io_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4153 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4154 	struct pm8001_ccb_info *ccb)
4155 {
4156 	struct sas_task *task = ccb->task;
4157 	struct domain_device *dev = task->dev;
4158 	struct pm8001_device *pm8001_dev = dev->lldd_dev;
4159 	struct ssp_ini_io_start_req ssp_cmd;
4160 	u32 tag = ccb->ccb_tag;
4161 	int ret;
4162 	u64 phys_addr;
4163 	struct inbound_queue_table *circularQ;
4164 	u32 opc = OPC_INB_SSPINIIOSTART;
4165 	memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4166 	memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4167 	ssp_cmd.dir_m_tlr =
4168 		cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4169 	SAS 1.1 compatible TLR*/
4170 	ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4171 	ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4172 	ssp_cmd.tag = cpu_to_le32(tag);
4173 	if (task->ssp_task.enable_first_burst)
4174 		ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4175 	ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4176 	ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4177 	memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4178 	       task->ssp_task.cmd->cmd_len);
4179 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4180 
4181 	/* fill in PRD (scatter/gather) table, if any */
4182 	if (task->num_scatter > 1) {
4183 		pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4184 		phys_addr = ccb->ccb_dma_handle;
4185 		ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4186 		ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4187 		ssp_cmd.esgl = cpu_to_le32(1<<31);
4188 	} else if (task->num_scatter == 1) {
4189 		u64 dma_addr = sg_dma_address(task->scatter);
4190 		ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4191 		ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4192 		ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4193 		ssp_cmd.esgl = 0;
4194 	} else if (task->num_scatter == 0) {
4195 		ssp_cmd.addr_low = 0;
4196 		ssp_cmd.addr_high = 0;
4197 		ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4198 		ssp_cmd.esgl = 0;
4199 	}
4200 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd,
4201 			sizeof(ssp_cmd), 0);
4202 	return ret;
4203 }
4204 
pm8001_chip_sata_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4205 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4206 	struct pm8001_ccb_info *ccb)
4207 {
4208 	struct sas_task *task = ccb->task;
4209 	struct domain_device *dev = task->dev;
4210 	struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4211 	u32 tag = ccb->ccb_tag;
4212 	int ret;
4213 	struct sata_start_req sata_cmd;
4214 	u32 hdr_tag, ncg_tag = 0;
4215 	u64 phys_addr;
4216 	u32 ATAP = 0x0;
4217 	u32 dir;
4218 	struct inbound_queue_table *circularQ;
4219 	unsigned long flags;
4220 	u32  opc = OPC_INB_SATA_HOST_OPSTART;
4221 	memset(&sata_cmd, 0, sizeof(sata_cmd));
4222 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4223 	if (task->data_dir == DMA_NONE) {
4224 		ATAP = 0x04;  /* no data*/
4225 		pm8001_dbg(pm8001_ha, IO, "no data\n");
4226 	} else if (likely(!task->ata_task.device_control_reg_update)) {
4227 		if (task->ata_task.dma_xfer) {
4228 			ATAP = 0x06; /* DMA */
4229 			pm8001_dbg(pm8001_ha, IO, "DMA\n");
4230 		} else {
4231 			ATAP = 0x05; /* PIO*/
4232 			pm8001_dbg(pm8001_ha, IO, "PIO\n");
4233 		}
4234 		if (task->ata_task.use_ncq &&
4235 			dev->sata_dev.class != ATA_DEV_ATAPI) {
4236 			ATAP = 0x07; /* FPDMA */
4237 			pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4238 		}
4239 	}
4240 	if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4241 		task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4242 		ncg_tag = hdr_tag;
4243 	}
4244 	dir = data_dir_flags[task->data_dir] << 8;
4245 	sata_cmd.tag = cpu_to_le32(tag);
4246 	sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4247 	sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4248 	sata_cmd.ncqtag_atap_dir_m =
4249 		cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4250 	sata_cmd.sata_fis = task->ata_task.fis;
4251 	if (likely(!task->ata_task.device_control_reg_update))
4252 		sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4253 	sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4254 	/* fill in PRD (scatter/gather) table, if any */
4255 	if (task->num_scatter > 1) {
4256 		pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4257 		phys_addr = ccb->ccb_dma_handle;
4258 		sata_cmd.addr_low = lower_32_bits(phys_addr);
4259 		sata_cmd.addr_high = upper_32_bits(phys_addr);
4260 		sata_cmd.esgl = cpu_to_le32(1 << 31);
4261 	} else if (task->num_scatter == 1) {
4262 		u64 dma_addr = sg_dma_address(task->scatter);
4263 		sata_cmd.addr_low = lower_32_bits(dma_addr);
4264 		sata_cmd.addr_high = upper_32_bits(dma_addr);
4265 		sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4266 		sata_cmd.esgl = 0;
4267 	} else if (task->num_scatter == 0) {
4268 		sata_cmd.addr_low = 0;
4269 		sata_cmd.addr_high = 0;
4270 		sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4271 		sata_cmd.esgl = 0;
4272 	}
4273 
4274 	/* Check for read log for failed drive and return */
4275 	if (sata_cmd.sata_fis.command == 0x2f) {
4276 		if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4277 			(pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4278 			(pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4279 			struct task_status_struct *ts;
4280 
4281 			pm8001_ha_dev->id &= 0xDFFFFFFF;
4282 			ts = &task->task_status;
4283 
4284 			spin_lock_irqsave(&task->task_state_lock, flags);
4285 			ts->resp = SAS_TASK_COMPLETE;
4286 			ts->stat = SAM_STAT_GOOD;
4287 			task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4288 			task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4289 			task->task_state_flags |= SAS_TASK_STATE_DONE;
4290 			if (unlikely((task->task_state_flags &
4291 					SAS_TASK_STATE_ABORTED))) {
4292 				spin_unlock_irqrestore(&task->task_state_lock,
4293 							flags);
4294 				pm8001_dbg(pm8001_ha, FAIL,
4295 					   "task 0x%p resp 0x%x  stat 0x%x but aborted by upper layer\n",
4296 					   task, ts->resp,
4297 					   ts->stat);
4298 				pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4299 			} else {
4300 				spin_unlock_irqrestore(&task->task_state_lock,
4301 							flags);
4302 				pm8001_ccb_task_free_done(pm8001_ha, task,
4303 								ccb, tag);
4304 				return 0;
4305 			}
4306 		}
4307 	}
4308 
4309 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
4310 			sizeof(sata_cmd), 0);
4311 	return ret;
4312 }
4313 
4314 /**
4315  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4316  * @pm8001_ha: our hba card information.
4317  * @phy_id: the phy id which we wanted to start up.
4318  */
4319 static int
pm8001_chip_phy_start_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4320 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4321 {
4322 	struct phy_start_req payload;
4323 	struct inbound_queue_table *circularQ;
4324 	int ret;
4325 	u32 tag = 0x01;
4326 	u32 opcode = OPC_INB_PHYSTART;
4327 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4328 	memset(&payload, 0, sizeof(payload));
4329 	payload.tag = cpu_to_le32(tag);
4330 	/*
4331 	 ** [0:7]   PHY Identifier
4332 	 ** [8:11]  link rate 1.5G, 3G, 6G
4333 	 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4334 	 ** [14]    0b disable spin up hold; 1b enable spin up hold
4335 	 */
4336 	payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4337 		LINKMODE_AUTO |	LINKRATE_15 |
4338 		LINKRATE_30 | LINKRATE_60 | phy_id);
4339 	payload.sas_identify.dev_type = SAS_END_DEVICE;
4340 	payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4341 	memcpy(payload.sas_identify.sas_addr,
4342 		pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4343 	payload.sas_identify.phy_id = phy_id;
4344 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4345 			sizeof(payload), 0);
4346 	return ret;
4347 }
4348 
4349 /**
4350  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4351  * @pm8001_ha: our hba card information.
4352  * @phy_id: the phy id which we wanted to start up.
4353  */
pm8001_chip_phy_stop_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4354 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4355 				    u8 phy_id)
4356 {
4357 	struct phy_stop_req payload;
4358 	struct inbound_queue_table *circularQ;
4359 	int ret;
4360 	u32 tag = 0x01;
4361 	u32 opcode = OPC_INB_PHYSTOP;
4362 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4363 	memset(&payload, 0, sizeof(payload));
4364 	payload.tag = cpu_to_le32(tag);
4365 	payload.phy_id = cpu_to_le32(phy_id);
4366 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4367 			sizeof(payload), 0);
4368 	return ret;
4369 }
4370 
4371 /*
4372  * see comments on pm8001_mpi_reg_resp.
4373  */
pm8001_chip_reg_dev_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_dev,u32 flag)4374 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4375 	struct pm8001_device *pm8001_dev, u32 flag)
4376 {
4377 	struct reg_dev_req payload;
4378 	u32	opc;
4379 	u32 stp_sspsmp_sata = 0x4;
4380 	struct inbound_queue_table *circularQ;
4381 	u32 linkrate, phy_id;
4382 	int rc, tag = 0xdeadbeef;
4383 	struct pm8001_ccb_info *ccb;
4384 	u8 retryFlag = 0x1;
4385 	u16 firstBurstSize = 0;
4386 	u16 ITNT = 2000;
4387 	struct domain_device *dev = pm8001_dev->sas_device;
4388 	struct domain_device *parent_dev = dev->parent;
4389 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4390 
4391 	memset(&payload, 0, sizeof(payload));
4392 	rc = pm8001_tag_alloc(pm8001_ha, &tag);
4393 	if (rc)
4394 		return rc;
4395 	ccb = &pm8001_ha->ccb_info[tag];
4396 	ccb->device = pm8001_dev;
4397 	ccb->ccb_tag = tag;
4398 	payload.tag = cpu_to_le32(tag);
4399 	if (flag == 1)
4400 		stp_sspsmp_sata = 0x02; /*direct attached sata */
4401 	else {
4402 		if (pm8001_dev->dev_type == SAS_SATA_DEV)
4403 			stp_sspsmp_sata = 0x00; /* stp*/
4404 		else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4405 			pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4406 			pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4407 			stp_sspsmp_sata = 0x01; /*ssp or smp*/
4408 	}
4409 	if (parent_dev && dev_is_expander(parent_dev->dev_type))
4410 		phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4411 	else
4412 		phy_id = pm8001_dev->attached_phy;
4413 	opc = OPC_INB_REG_DEV;
4414 	linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4415 			pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4416 	payload.phyid_portid =
4417 		cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4418 		((phy_id & 0x0F) << 4));
4419 	payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4420 		((linkrate & 0x0F) * 0x1000000) |
4421 		((stp_sspsmp_sata & 0x03) * 0x10000000));
4422 	payload.firstburstsize_ITNexustimeout =
4423 		cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4424 	memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4425 		SAS_ADDR_SIZE);
4426 	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4427 			sizeof(payload), 0);
4428 	return rc;
4429 }
4430 
4431 /*
4432  * see comments on pm8001_mpi_reg_resp.
4433  */
pm8001_chip_dereg_dev_req(struct pm8001_hba_info * pm8001_ha,u32 device_id)4434 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4435 	u32 device_id)
4436 {
4437 	struct dereg_dev_req payload;
4438 	u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4439 	int ret;
4440 	struct inbound_queue_table *circularQ;
4441 
4442 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4443 	memset(&payload, 0, sizeof(payload));
4444 	payload.tag = cpu_to_le32(1);
4445 	payload.device_id = cpu_to_le32(device_id);
4446 	pm8001_dbg(pm8001_ha, MSG, "unregister device device_id = %d\n",
4447 		   device_id);
4448 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4449 			sizeof(payload), 0);
4450 	return ret;
4451 }
4452 
4453 /**
4454  * pm8001_chip_phy_ctl_req - support the local phy operation
4455  * @pm8001_ha: our hba card information.
4456  * @phyId: the phy id which we wanted to operate
4457  * @phy_op: the phy operation to request
4458  */
pm8001_chip_phy_ctl_req(struct pm8001_hba_info * pm8001_ha,u32 phyId,u32 phy_op)4459 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4460 	u32 phyId, u32 phy_op)
4461 {
4462 	struct local_phy_ctl_req payload;
4463 	struct inbound_queue_table *circularQ;
4464 	int ret;
4465 	u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4466 	memset(&payload, 0, sizeof(payload));
4467 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4468 	payload.tag = cpu_to_le32(1);
4469 	payload.phyop_phyid =
4470 		cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4471 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4472 			sizeof(payload), 0);
4473 	return ret;
4474 }
4475 
pm8001_chip_is_our_interrupt(struct pm8001_hba_info * pm8001_ha)4476 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4477 {
4478 #ifdef PM8001_USE_MSIX
4479 	return 1;
4480 #else
4481 	u32 value;
4482 
4483 	value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4484 	if (value)
4485 		return 1;
4486 	return 0;
4487 #endif
4488 }
4489 
4490 /**
4491  * pm8001_chip_isr - PM8001 isr handler.
4492  * @pm8001_ha: our hba card information.
4493  * @vec: IRQ number
4494  */
4495 static irqreturn_t
pm8001_chip_isr(struct pm8001_hba_info * pm8001_ha,u8 vec)4496 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4497 {
4498 	pm8001_chip_interrupt_disable(pm8001_ha, vec);
4499 	pm8001_dbg(pm8001_ha, DEVIO,
4500 		   "irq vec %d, ODMR:0x%x\n",
4501 		   vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4502 	process_oq(pm8001_ha, vec);
4503 	pm8001_chip_interrupt_enable(pm8001_ha, vec);
4504 	return IRQ_HANDLED;
4505 }
4506 
send_task_abort(struct pm8001_hba_info * pm8001_ha,u32 opc,u32 dev_id,u8 flag,u32 task_tag,u32 cmd_tag)4507 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4508 	u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4509 {
4510 	struct task_abort_req task_abort;
4511 	struct inbound_queue_table *circularQ;
4512 	int ret;
4513 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4514 	memset(&task_abort, 0, sizeof(task_abort));
4515 	if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4516 		task_abort.abort_all = 0;
4517 		task_abort.device_id = cpu_to_le32(dev_id);
4518 		task_abort.tag_to_abort = cpu_to_le32(task_tag);
4519 		task_abort.tag = cpu_to_le32(cmd_tag);
4520 	} else if (ABORT_ALL == (flag & ABORT_MASK)) {
4521 		task_abort.abort_all = cpu_to_le32(1);
4522 		task_abort.device_id = cpu_to_le32(dev_id);
4523 		task_abort.tag = cpu_to_le32(cmd_tag);
4524 	}
4525 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
4526 			sizeof(task_abort), 0);
4527 	return ret;
4528 }
4529 
4530 /*
4531  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4532  */
pm8001_chip_abort_task(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_dev,u8 flag,u32 task_tag,u32 cmd_tag)4533 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4534 	struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4535 {
4536 	u32 opc, device_id;
4537 	int rc = TMF_RESP_FUNC_FAILED;
4538 	pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n",
4539 		   cmd_tag, task_tag);
4540 	if (pm8001_dev->dev_type == SAS_END_DEVICE)
4541 		opc = OPC_INB_SSP_ABORT;
4542 	else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4543 		opc = OPC_INB_SATA_ABORT;
4544 	else
4545 		opc = OPC_INB_SMP_ABORT;/* SMP */
4546 	device_id = pm8001_dev->device_id;
4547 	rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4548 		task_tag, cmd_tag);
4549 	if (rc != TMF_RESP_FUNC_COMPLETE)
4550 		pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc);
4551 	return rc;
4552 }
4553 
4554 /**
4555  * pm8001_chip_ssp_tm_req - built the task management command.
4556  * @pm8001_ha: our hba card information.
4557  * @ccb: the ccb information.
4558  * @tmf: task management function.
4559  */
pm8001_chip_ssp_tm_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb,struct pm8001_tmf_task * tmf)4560 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4561 	struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4562 {
4563 	struct sas_task *task = ccb->task;
4564 	struct domain_device *dev = task->dev;
4565 	struct pm8001_device *pm8001_dev = dev->lldd_dev;
4566 	u32 opc = OPC_INB_SSPINITMSTART;
4567 	struct inbound_queue_table *circularQ;
4568 	struct ssp_ini_tm_start_req sspTMCmd;
4569 	int ret;
4570 
4571 	memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4572 	sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4573 	sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4574 	sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4575 	memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4576 	sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4577 	if (pm8001_ha->chip_id != chip_8001)
4578 		sspTMCmd.ds_ads_m = 0x08;
4579 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4580 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd,
4581 			sizeof(sspTMCmd), 0);
4582 	return ret;
4583 }
4584 
pm8001_chip_get_nvmd_req(struct pm8001_hba_info * pm8001_ha,void * payload)4585 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4586 	void *payload)
4587 {
4588 	u32 opc = OPC_INB_GET_NVMD_DATA;
4589 	u32 nvmd_type;
4590 	int rc;
4591 	u32 tag;
4592 	struct pm8001_ccb_info *ccb;
4593 	struct inbound_queue_table *circularQ;
4594 	struct get_nvm_data_req nvmd_req;
4595 	struct fw_control_ex *fw_control_context;
4596 	struct pm8001_ioctl_payload *ioctl_payload = payload;
4597 
4598 	nvmd_type = ioctl_payload->minor_function;
4599 	fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4600 	if (!fw_control_context)
4601 		return -ENOMEM;
4602 	fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4603 	fw_control_context->len = ioctl_payload->rd_length;
4604 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4605 	memset(&nvmd_req, 0, sizeof(nvmd_req));
4606 	rc = pm8001_tag_alloc(pm8001_ha, &tag);
4607 	if (rc) {
4608 		kfree(fw_control_context);
4609 		return rc;
4610 	}
4611 	ccb = &pm8001_ha->ccb_info[tag];
4612 	ccb->ccb_tag = tag;
4613 	ccb->fw_control_context = fw_control_context;
4614 	nvmd_req.tag = cpu_to_le32(tag);
4615 
4616 	switch (nvmd_type) {
4617 	case TWI_DEVICE: {
4618 		u32 twi_addr, twi_page_size;
4619 		twi_addr = 0xa8;
4620 		twi_page_size = 2;
4621 
4622 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4623 			twi_page_size << 8 | TWI_DEVICE);
4624 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4625 		nvmd_req.resp_addr_hi =
4626 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4627 		nvmd_req.resp_addr_lo =
4628 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4629 		break;
4630 	}
4631 	case C_SEEPROM: {
4632 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4633 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4634 		nvmd_req.resp_addr_hi =
4635 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4636 		nvmd_req.resp_addr_lo =
4637 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4638 		break;
4639 	}
4640 	case VPD_FLASH: {
4641 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4642 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4643 		nvmd_req.resp_addr_hi =
4644 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4645 		nvmd_req.resp_addr_lo =
4646 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4647 		break;
4648 	}
4649 	case EXPAN_ROM: {
4650 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4651 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4652 		nvmd_req.resp_addr_hi =
4653 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4654 		nvmd_req.resp_addr_lo =
4655 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4656 		break;
4657 	}
4658 	case IOP_RDUMP: {
4659 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4660 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4661 		nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4662 		nvmd_req.resp_addr_hi =
4663 		cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4664 		nvmd_req.resp_addr_lo =
4665 		cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4666 		break;
4667 	}
4668 	default:
4669 		break;
4670 	}
4671 	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
4672 			sizeof(nvmd_req), 0);
4673 	if (rc) {
4674 		kfree(fw_control_context);
4675 		pm8001_tag_free(pm8001_ha, tag);
4676 	}
4677 	return rc;
4678 }
4679 
pm8001_chip_set_nvmd_req(struct pm8001_hba_info * pm8001_ha,void * payload)4680 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4681 	void *payload)
4682 {
4683 	u32 opc = OPC_INB_SET_NVMD_DATA;
4684 	u32 nvmd_type;
4685 	int rc;
4686 	u32 tag;
4687 	struct pm8001_ccb_info *ccb;
4688 	struct inbound_queue_table *circularQ;
4689 	struct set_nvm_data_req nvmd_req;
4690 	struct fw_control_ex *fw_control_context;
4691 	struct pm8001_ioctl_payload *ioctl_payload = payload;
4692 
4693 	nvmd_type = ioctl_payload->minor_function;
4694 	fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4695 	if (!fw_control_context)
4696 		return -ENOMEM;
4697 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4698 	memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4699 		&ioctl_payload->func_specific,
4700 		ioctl_payload->wr_length);
4701 	memset(&nvmd_req, 0, sizeof(nvmd_req));
4702 	rc = pm8001_tag_alloc(pm8001_ha, &tag);
4703 	if (rc) {
4704 		kfree(fw_control_context);
4705 		return -EBUSY;
4706 	}
4707 	ccb = &pm8001_ha->ccb_info[tag];
4708 	ccb->fw_control_context = fw_control_context;
4709 	ccb->ccb_tag = tag;
4710 	nvmd_req.tag = cpu_to_le32(tag);
4711 	switch (nvmd_type) {
4712 	case TWI_DEVICE: {
4713 		u32 twi_addr, twi_page_size;
4714 		twi_addr = 0xa8;
4715 		twi_page_size = 2;
4716 		nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4717 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4718 			twi_page_size << 8 | TWI_DEVICE);
4719 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4720 		nvmd_req.resp_addr_hi =
4721 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4722 		nvmd_req.resp_addr_lo =
4723 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4724 		break;
4725 	}
4726 	case C_SEEPROM:
4727 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4728 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4729 		nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4730 		nvmd_req.resp_addr_hi =
4731 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4732 		nvmd_req.resp_addr_lo =
4733 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4734 		break;
4735 	case VPD_FLASH:
4736 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4737 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4738 		nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4739 		nvmd_req.resp_addr_hi =
4740 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4741 		nvmd_req.resp_addr_lo =
4742 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4743 		break;
4744 	case EXPAN_ROM:
4745 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4746 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4747 		nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4748 		nvmd_req.resp_addr_hi =
4749 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4750 		nvmd_req.resp_addr_lo =
4751 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4752 		break;
4753 	default:
4754 		break;
4755 	}
4756 	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
4757 			sizeof(nvmd_req), 0);
4758 	if (rc) {
4759 		kfree(fw_control_context);
4760 		pm8001_tag_free(pm8001_ha, tag);
4761 	}
4762 	return rc;
4763 }
4764 
4765 /**
4766  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4767  * @pm8001_ha: our hba card information.
4768  * @fw_flash_updata_info: firmware flash update param
4769  * @tag: Tag to apply to the payload
4770  */
4771 int
pm8001_chip_fw_flash_update_build(struct pm8001_hba_info * pm8001_ha,void * fw_flash_updata_info,u32 tag)4772 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4773 	void *fw_flash_updata_info, u32 tag)
4774 {
4775 	struct fw_flash_Update_req payload;
4776 	struct fw_flash_updata_info *info;
4777 	struct inbound_queue_table *circularQ;
4778 	int ret;
4779 	u32 opc = OPC_INB_FW_FLASH_UPDATE;
4780 
4781 	memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4782 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4783 	info = fw_flash_updata_info;
4784 	payload.tag = cpu_to_le32(tag);
4785 	payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4786 	payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4787 	payload.total_image_len = cpu_to_le32(info->total_image_len);
4788 	payload.len = info->sgl.im_len.len ;
4789 	payload.sgl_addr_lo =
4790 		cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4791 	payload.sgl_addr_hi =
4792 		cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4793 	ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4794 			sizeof(payload), 0);
4795 	return ret;
4796 }
4797 
4798 int
pm8001_chip_fw_flash_update_req(struct pm8001_hba_info * pm8001_ha,void * payload)4799 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4800 	void *payload)
4801 {
4802 	struct fw_flash_updata_info flash_update_info;
4803 	struct fw_control_info *fw_control;
4804 	struct fw_control_ex *fw_control_context;
4805 	int rc;
4806 	u32 tag;
4807 	struct pm8001_ccb_info *ccb;
4808 	void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4809 	dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4810 	struct pm8001_ioctl_payload *ioctl_payload = payload;
4811 
4812 	fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4813 	if (!fw_control_context)
4814 		return -ENOMEM;
4815 	fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4816 	pm8001_dbg(pm8001_ha, DEVIO,
4817 		   "dma fw_control context input length :%x\n",
4818 		   fw_control->len);
4819 	memcpy(buffer, fw_control->buffer, fw_control->len);
4820 	flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4821 	flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4822 	flash_update_info.sgl.im_len.e = 0;
4823 	flash_update_info.cur_image_offset = fw_control->offset;
4824 	flash_update_info.cur_image_len = fw_control->len;
4825 	flash_update_info.total_image_len = fw_control->size;
4826 	fw_control_context->fw_control = fw_control;
4827 	fw_control_context->virtAddr = buffer;
4828 	fw_control_context->phys_addr = phys_addr;
4829 	fw_control_context->len = fw_control->len;
4830 	rc = pm8001_tag_alloc(pm8001_ha, &tag);
4831 	if (rc) {
4832 		kfree(fw_control_context);
4833 		return -EBUSY;
4834 	}
4835 	ccb = &pm8001_ha->ccb_info[tag];
4836 	ccb->fw_control_context = fw_control_context;
4837 	ccb->ccb_tag = tag;
4838 	rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4839 		tag);
4840 	return rc;
4841 }
4842 
4843 ssize_t
pm8001_get_gsm_dump(struct device * cdev,u32 length,char * buf)4844 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
4845 {
4846 	u32 value, rem, offset = 0, bar = 0;
4847 	u32 index, work_offset, dw_length;
4848 	u32 shift_value, gsm_base, gsm_dump_offset;
4849 	char *direct_data;
4850 	struct Scsi_Host *shost = class_to_shost(cdev);
4851 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
4852 	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
4853 
4854 	direct_data = buf;
4855 	gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
4856 
4857 	/* check max is 1 Mbytes */
4858 	if ((length > 0x100000) || (gsm_dump_offset & 3) ||
4859 		((gsm_dump_offset + length) > 0x1000000))
4860 			return -EINVAL;
4861 
4862 	if (pm8001_ha->chip_id == chip_8001)
4863 		bar = 2;
4864 	else
4865 		bar = 1;
4866 
4867 	work_offset = gsm_dump_offset & 0xFFFF0000;
4868 	offset = gsm_dump_offset & 0x0000FFFF;
4869 	gsm_dump_offset = work_offset;
4870 	/* adjust length to dword boundary */
4871 	rem = length & 3;
4872 	dw_length = length >> 2;
4873 
4874 	for (index = 0; index < dw_length; index++) {
4875 		if ((work_offset + offset) & 0xFFFF0000) {
4876 			if (pm8001_ha->chip_id == chip_8001)
4877 				shift_value = ((gsm_dump_offset + offset) &
4878 						SHIFT_REG_64K_MASK);
4879 			else
4880 				shift_value = (((gsm_dump_offset + offset) &
4881 						SHIFT_REG_64K_MASK) >>
4882 						SHIFT_REG_BIT_SHIFT);
4883 
4884 			if (pm8001_ha->chip_id == chip_8001) {
4885 				gsm_base = GSM_BASE;
4886 				if (-1 == pm8001_bar4_shift(pm8001_ha,
4887 						(gsm_base + shift_value)))
4888 					return -EIO;
4889 			} else {
4890 				gsm_base = 0;
4891 				if (-1 == pm80xx_bar4_shift(pm8001_ha,
4892 						(gsm_base + shift_value)))
4893 					return -EIO;
4894 			}
4895 			gsm_dump_offset = (gsm_dump_offset + offset) &
4896 						0xFFFF0000;
4897 			work_offset = 0;
4898 			offset = offset & 0x0000FFFF;
4899 		}
4900 		value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4901 						0x0000FFFF);
4902 		direct_data += sprintf(direct_data, "%08x ", value);
4903 		offset += 4;
4904 	}
4905 	if (rem != 0) {
4906 		value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4907 						0x0000FFFF);
4908 		/* xfr for non_dw */
4909 		direct_data += sprintf(direct_data, "%08x ", value);
4910 	}
4911 	/* Shift back to BAR4 original address */
4912 	if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
4913 			return -EIO;
4914 	pm8001_ha->fatal_forensic_shift_offset += 1024;
4915 
4916 	if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
4917 		pm8001_ha->fatal_forensic_shift_offset = 0;
4918 	return direct_data - buf;
4919 }
4920 
4921 int
pm8001_chip_set_dev_state_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_dev,u32 state)4922 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4923 	struct pm8001_device *pm8001_dev, u32 state)
4924 {
4925 	struct set_dev_state_req payload;
4926 	struct inbound_queue_table *circularQ;
4927 	struct pm8001_ccb_info *ccb;
4928 	int rc;
4929 	u32 tag;
4930 	u32 opc = OPC_INB_SET_DEVICE_STATE;
4931 	memset(&payload, 0, sizeof(payload));
4932 	rc = pm8001_tag_alloc(pm8001_ha, &tag);
4933 	if (rc)
4934 		return -1;
4935 	ccb = &pm8001_ha->ccb_info[tag];
4936 	ccb->ccb_tag = tag;
4937 	ccb->device = pm8001_dev;
4938 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4939 	payload.tag = cpu_to_le32(tag);
4940 	payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4941 	payload.nds = cpu_to_le32(state);
4942 	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4943 			sizeof(payload), 0);
4944 	return rc;
4945 
4946 }
4947 
4948 static int
pm8001_chip_sas_re_initialization(struct pm8001_hba_info * pm8001_ha)4949 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4950 {
4951 	struct sas_re_initialization_req payload;
4952 	struct inbound_queue_table *circularQ;
4953 	struct pm8001_ccb_info *ccb;
4954 	int rc;
4955 	u32 tag;
4956 	u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4957 	memset(&payload, 0, sizeof(payload));
4958 	rc = pm8001_tag_alloc(pm8001_ha, &tag);
4959 	if (rc)
4960 		return -ENOMEM;
4961 	ccb = &pm8001_ha->ccb_info[tag];
4962 	ccb->ccb_tag = tag;
4963 	circularQ = &pm8001_ha->inbnd_q_tbl[0];
4964 	payload.tag = cpu_to_le32(tag);
4965 	payload.SSAHOLT = cpu_to_le32(0xd << 25);
4966 	payload.sata_hol_tmo = cpu_to_le32(80);
4967 	payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4968 	rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4969 			sizeof(payload), 0);
4970 	if (rc)
4971 		pm8001_tag_free(pm8001_ha, tag);
4972 	return rc;
4973 
4974 }
4975 
4976 const struct pm8001_dispatch pm8001_8001_dispatch = {
4977 	.name			= "pmc8001",
4978 	.chip_init		= pm8001_chip_init,
4979 	.chip_soft_rst		= pm8001_chip_soft_rst,
4980 	.chip_rst		= pm8001_hw_chip_rst,
4981 	.chip_iounmap		= pm8001_chip_iounmap,
4982 	.isr			= pm8001_chip_isr,
4983 	.is_our_interrupt	= pm8001_chip_is_our_interrupt,
4984 	.isr_process_oq		= process_oq,
4985 	.interrupt_enable 	= pm8001_chip_interrupt_enable,
4986 	.interrupt_disable	= pm8001_chip_interrupt_disable,
4987 	.make_prd		= pm8001_chip_make_sg,
4988 	.smp_req		= pm8001_chip_smp_req,
4989 	.ssp_io_req		= pm8001_chip_ssp_io_req,
4990 	.sata_req		= pm8001_chip_sata_req,
4991 	.phy_start_req		= pm8001_chip_phy_start_req,
4992 	.phy_stop_req		= pm8001_chip_phy_stop_req,
4993 	.reg_dev_req		= pm8001_chip_reg_dev_req,
4994 	.dereg_dev_req		= pm8001_chip_dereg_dev_req,
4995 	.phy_ctl_req		= pm8001_chip_phy_ctl_req,
4996 	.task_abort		= pm8001_chip_abort_task,
4997 	.ssp_tm_req		= pm8001_chip_ssp_tm_req,
4998 	.get_nvmd_req		= pm8001_chip_get_nvmd_req,
4999 	.set_nvmd_req		= pm8001_chip_set_nvmd_req,
5000 	.fw_flash_update_req	= pm8001_chip_fw_flash_update_req,
5001 	.set_dev_state_req	= pm8001_chip_set_dev_state_req,
5002 	.sas_re_init_req	= pm8001_chip_sas_re_initialization,
5003 };
5004