1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
3 *
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Lorenzo Bianconi <lorenzo@kernel.org>
7 * Felix Fietkau <nbd@nbd.name>
8 */
9
10 #include "mt7615.h"
11 #include "../dma.h"
12 #include "mac.h"
13
14 static int
mt7615_init_tx_queue(struct mt7615_dev * dev,int qid,int idx,int n_desc)15 mt7615_init_tx_queue(struct mt7615_dev *dev, int qid, int idx, int n_desc)
16 {
17 struct mt76_queue *hwq;
18 int err;
19
20 hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
21 if (!hwq)
22 return -ENOMEM;
23
24 err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE);
25 if (err < 0)
26 return err;
27
28 dev->mt76.q_tx[qid] = hwq;
29
30 return 0;
31 }
32
33 static int
mt7622_init_tx_queues_multi(struct mt7615_dev * dev)34 mt7622_init_tx_queues_multi(struct mt7615_dev *dev)
35 {
36 static const u8 wmm_queue_map[] = {
37 [IEEE80211_AC_BK] = MT7622_TXQ_AC0,
38 [IEEE80211_AC_BE] = MT7622_TXQ_AC1,
39 [IEEE80211_AC_VI] = MT7622_TXQ_AC2,
40 [IEEE80211_AC_VO] = MT7622_TXQ_AC3,
41 };
42 int ret;
43 int i;
44
45 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
46 ret = mt7615_init_tx_queue(dev, i, wmm_queue_map[i],
47 MT7615_TX_RING_SIZE / 2);
48 if (ret)
49 return ret;
50 }
51
52 ret = mt7615_init_tx_queue(dev, MT_TXQ_PSD,
53 MT7622_TXQ_MGMT, MT7615_TX_MGMT_RING_SIZE);
54 if (ret)
55 return ret;
56
57 ret = mt7615_init_tx_queue(dev, MT_TXQ_MCU,
58 MT7622_TXQ_MCU, MT7615_TX_MCU_RING_SIZE);
59 return ret;
60 }
61
62 static int
mt7615_init_tx_queues(struct mt7615_dev * dev)63 mt7615_init_tx_queues(struct mt7615_dev *dev)
64 {
65 int ret, i;
66
67 ret = mt7615_init_tx_queue(dev, MT_TXQ_FWDL,
68 MT7615_TXQ_FWDL,
69 MT7615_TX_FWDL_RING_SIZE);
70 if (ret)
71 return ret;
72
73 if (!is_mt7615(&dev->mt76))
74 return mt7622_init_tx_queues_multi(dev);
75
76 ret = mt7615_init_tx_queue(dev, 0, 0, MT7615_TX_RING_SIZE);
77 if (ret)
78 return ret;
79
80 for (i = 1; i < MT_TXQ_MCU; i++)
81 dev->mt76.q_tx[i] = dev->mt76.q_tx[0];
82
83 ret = mt7615_init_tx_queue(dev, MT_TXQ_MCU, MT7615_TXQ_MCU,
84 MT7615_TX_MCU_RING_SIZE);
85 return 0;
86 }
87
mt7615_poll_tx(struct napi_struct * napi,int budget)88 static int mt7615_poll_tx(struct napi_struct *napi, int budget)
89 {
90 struct mt7615_dev *dev;
91
92 dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
93
94 mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false);
95
96 if (napi_complete_done(napi, 0))
97 mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev));
98
99 return 0;
100 }
101
mt7615_wait_pdma_busy(struct mt7615_dev * dev)102 int mt7615_wait_pdma_busy(struct mt7615_dev *dev)
103 {
104 struct mt76_dev *mdev = &dev->mt76;
105
106 if (!is_mt7663(mdev)) {
107 u32 mask = MT_PDMA_TX_BUSY | MT_PDMA_RX_BUSY;
108 u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY);
109
110 if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) {
111 dev_err(mdev->dev, "PDMA engine busy\n");
112 return -EIO;
113 }
114
115 return 0;
116 }
117
118 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
119 MT_PDMA_TX_IDX_BUSY, 0, 1000)) {
120 dev_err(mdev->dev, "PDMA engine tx busy\n");
121 return -EIO;
122 }
123
124 if (!mt76_poll_msec(dev, MT_PSE_PG_INFO,
125 MT_PSE_SRC_CNT, 0, 1000)) {
126 dev_err(mdev->dev, "PSE engine busy\n");
127 return -EIO;
128 }
129
130 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
131 MT_PDMA_BUSY_IDX, 0, 1000)) {
132 dev_err(mdev->dev, "PDMA engine busy\n");
133 return -EIO;
134 }
135
136 return 0;
137 }
138
mt7622_dma_sched_init(struct mt7615_dev * dev)139 static void mt7622_dma_sched_init(struct mt7615_dev *dev)
140 {
141 u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE);
142 int i;
143
144 mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE,
145 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
146 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
147 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
148
149 for (i = 0; i <= 5; i++)
150 mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i),
151 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) |
152 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
153
154 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210);
155 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210);
156 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5);
157 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0);
158
159 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f);
160 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987);
161 }
162
mt7663_dma_sched_init(struct mt7615_dev * dev)163 static void mt7663_dma_sched_init(struct mt7615_dev *dev)
164 {
165 int i;
166
167 mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),
168 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
169 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
170 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
171
172 /* enable refill control group 0, 1, 2, 4, 5 */
173 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000);
174 /* enable group 0, 1, 2, 4, 5, 15 */
175 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037);
176
177 /* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */
178 for (i = 0; i < 5; i++)
179 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)),
180 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
181 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
182 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)),
183 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
184 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40));
185 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)),
186 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) |
187 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20));
188
189 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210);
190 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210);
191 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005);
192 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0);
193 /* ALTX0 and ALTX1 QID mapping to group 5 */
194 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f);
195 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987);
196 }
197
mt7615_dma_init(struct mt7615_dev * dev)198 int mt7615_dma_init(struct mt7615_dev *dev)
199 {
200 int rx_ring_size = MT7615_RX_RING_SIZE;
201 int rx_buf_size = MT_RX_BUF_SIZE;
202 int ret;
203
204 /* Increase buffer size to receive large VHT MPDUs */
205 if (dev->mt76.cap.has_5ghz)
206 rx_buf_size *= 2;
207
208 mt76_dma_attach(&dev->mt76);
209
210 mt76_wr(dev, MT_WPDMA_GLO_CFG,
211 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE |
212 MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN |
213 MT_WPDMA_GLO_CFG_OMIT_TX_INFO);
214
215 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
216 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);
217
218 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
219 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1);
220
221 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
222 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3);
223
224 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
225 MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);
226
227 if (is_mt7615(&dev->mt76)) {
228 mt76_set(dev, MT_WPDMA_GLO_CFG,
229 MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY);
230
231 mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);
232 mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);
233 mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
234 mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);
235 mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);
236 mt76_set(dev, 0x7158, BIT(16));
237 mt76_clear(dev, 0x7000, BIT(23));
238 }
239
240 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
241
242 ret = mt7615_init_tx_queues(dev);
243 if (ret)
244 return ret;
245
246 /* init rx queues */
247 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
248 MT7615_RX_MCU_RING_SIZE, rx_buf_size,
249 MT_RX_RING_BASE);
250 if (ret)
251 return ret;
252
253 if (!is_mt7615(&dev->mt76))
254 rx_ring_size /= 2;
255
256 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
257 rx_ring_size, rx_buf_size, MT_RX_RING_BASE);
258 if (ret)
259 return ret;
260
261 mt76_wr(dev, MT_DELAY_INT_CFG, 0);
262
263 ret = mt76_init_queues(dev);
264 if (ret < 0)
265 return ret;
266
267 netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi,
268 mt7615_poll_tx, NAPI_POLL_WEIGHT);
269 napi_enable(&dev->mt76.tx_napi);
270
271 mt76_poll(dev, MT_WPDMA_GLO_CFG,
272 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
273 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000);
274
275 /* start dma engine */
276 mt76_set(dev, MT_WPDMA_GLO_CFG,
277 MT_WPDMA_GLO_CFG_TX_DMA_EN |
278 MT_WPDMA_GLO_CFG_RX_DMA_EN);
279
280 /* enable interrupts for TX/RX rings */
281 mt7615_irq_enable(dev, MT_INT_RX_DONE_ALL | mt7615_tx_mcu_int_mask(dev) |
282 MT_INT_MCU_CMD);
283
284 if (is_mt7622(&dev->mt76))
285 mt7622_dma_sched_init(dev);
286
287 if (is_mt7663(&dev->mt76))
288 mt7663_dma_sched_init(dev);
289
290 return 0;
291 }
292
mt7615_dma_cleanup(struct mt7615_dev * dev)293 void mt7615_dma_cleanup(struct mt7615_dev *dev)
294 {
295 mt76_clear(dev, MT_WPDMA_GLO_CFG,
296 MT_WPDMA_GLO_CFG_TX_DMA_EN |
297 MT_WPDMA_GLO_CFG_RX_DMA_EN);
298 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
299
300 mt76_dma_cleanup(&dev->mt76);
301 }
302