1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include "mt7915.h"
5 #include "../dma.h"
6 #include "mac.h"
7
8 static int
mt7915_init_tx_queues(struct mt7915_dev * dev,int n_desc)9 mt7915_init_tx_queues(struct mt7915_dev *dev, int n_desc)
10 {
11 struct mt76_queue *hwq;
12 int err, i;
13
14 hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
15 if (!hwq)
16 return -ENOMEM;
17
18 err = mt76_queue_alloc(dev, hwq, MT7915_TXQ_BAND0, n_desc, 0,
19 MT_TX_RING_BASE);
20 if (err < 0)
21 return err;
22
23 for (i = 0; i < MT_TXQ_MCU; i++)
24 dev->mt76.q_tx[i] = hwq;
25
26 return 0;
27 }
28
29 static int
mt7915_init_mcu_queue(struct mt7915_dev * dev,int qid,int idx,int n_desc)30 mt7915_init_mcu_queue(struct mt7915_dev *dev, int qid, int idx, int n_desc)
31 {
32 struct mt76_queue *hwq;
33 int err;
34
35 hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
36 if (!hwq)
37 return -ENOMEM;
38
39 err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE);
40 if (err < 0)
41 return err;
42
43 dev->mt76.q_tx[qid] = hwq;
44
45 return 0;
46 }
47
mt7915_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb)48 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
49 struct sk_buff *skb)
50 {
51 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
52 __le32 *rxd = (__le32 *)skb->data;
53 enum rx_pkt_type type;
54
55 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
56
57 switch (type) {
58 case PKT_TYPE_TXRX_NOTIFY:
59 mt7915_mac_tx_free(dev, skb);
60 break;
61 case PKT_TYPE_RX_EVENT:
62 mt7915_mcu_rx_event(dev, skb);
63 break;
64 case PKT_TYPE_NORMAL:
65 if (!mt7915_mac_fill_rx(dev, skb)) {
66 mt76_rx(&dev->mt76, q, skb);
67 return;
68 }
69 fallthrough;
70 default:
71 dev_kfree_skb(skb);
72 break;
73 }
74 }
75
76 static void
mt7915_tx_cleanup(struct mt7915_dev * dev)77 mt7915_tx_cleanup(struct mt7915_dev *dev)
78 {
79 mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false);
80 mt76_queue_tx_cleanup(dev, MT_TXQ_MCU_WA, false);
81 }
82
mt7915_poll_tx(struct napi_struct * napi,int budget)83 static int mt7915_poll_tx(struct napi_struct *napi, int budget)
84 {
85 struct mt7915_dev *dev;
86
87 dev = container_of(napi, struct mt7915_dev, mt76.tx_napi);
88
89 mt7915_tx_cleanup(dev);
90
91 if (napi_complete_done(napi, 0))
92 mt7915_irq_enable(dev, MT_INT_TX_DONE_MCU);
93
94 return 0;
95 }
96
mt7915_dma_prefetch(struct mt7915_dev * dev)97 void mt7915_dma_prefetch(struct mt7915_dev *dev)
98 {
99 #define PREFETCH(base, depth) ((base) << 16 | (depth))
100
101 mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4));
102 mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x40, 0x4));
103 mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x80, 0x0));
104
105 mt76_wr(dev, MT_WFDMA1_TX_RING0_EXT_CTRL, PREFETCH(0x80, 0x4));
106 mt76_wr(dev, MT_WFDMA1_TX_RING1_EXT_CTRL, PREFETCH(0xc0, 0x4));
107 mt76_wr(dev, MT_WFDMA1_TX_RING2_EXT_CTRL, PREFETCH(0x100, 0x4));
108 mt76_wr(dev, MT_WFDMA1_TX_RING3_EXT_CTRL, PREFETCH(0x140, 0x4));
109 mt76_wr(dev, MT_WFDMA1_TX_RING4_EXT_CTRL, PREFETCH(0x180, 0x4));
110 mt76_wr(dev, MT_WFDMA1_TX_RING5_EXT_CTRL, PREFETCH(0x1c0, 0x4));
111 mt76_wr(dev, MT_WFDMA1_TX_RING6_EXT_CTRL, PREFETCH(0x200, 0x4));
112 mt76_wr(dev, MT_WFDMA1_TX_RING7_EXT_CTRL, PREFETCH(0x240, 0x4));
113
114 mt76_wr(dev, MT_WFDMA1_TX_RING16_EXT_CTRL, PREFETCH(0x280, 0x4));
115 mt76_wr(dev, MT_WFDMA1_TX_RING17_EXT_CTRL, PREFETCH(0x2c0, 0x4));
116 mt76_wr(dev, MT_WFDMA1_TX_RING18_EXT_CTRL, PREFETCH(0x300, 0x4));
117 mt76_wr(dev, MT_WFDMA1_TX_RING19_EXT_CTRL, PREFETCH(0x340, 0x4));
118 mt76_wr(dev, MT_WFDMA1_TX_RING20_EXT_CTRL, PREFETCH(0x380, 0x4));
119 mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL, PREFETCH(0x3c0, 0x0));
120
121 mt76_wr(dev, MT_WFDMA1_RX_RING0_EXT_CTRL, PREFETCH(0x3c0, 0x4));
122 mt76_wr(dev, MT_WFDMA1_RX_RING1_EXT_CTRL, PREFETCH(0x400, 0x4));
123 mt76_wr(dev, MT_WFDMA1_RX_RING2_EXT_CTRL, PREFETCH(0x440, 0x4));
124 mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL, PREFETCH(0x480, 0x0));
125 }
126
__mt7915_reg_addr(struct mt7915_dev * dev,u32 addr)127 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
128 {
129 static const struct {
130 u32 phys;
131 u32 mapped;
132 u32 size;
133 } fixed_map[] = {
134 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
135 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
136 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
137 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
138 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
139 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
140 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
141 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
142 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
143 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
144 { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
145 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
146 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
147 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
148 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
149 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
150 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
151 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
152 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
153 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
154 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
155 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
156 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
157 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
158 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
159 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
160 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
161 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
162 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
163 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
164 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
165 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
166 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
167 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
168 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
169 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
170 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
171 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
172 };
173 int i;
174
175 if (addr < 0x100000)
176 return addr;
177
178 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
179 u32 ofs;
180
181 if (addr < fixed_map[i].phys)
182 continue;
183
184 ofs = addr - fixed_map[i].phys;
185 if (ofs > fixed_map[i].size)
186 continue;
187
188 return fixed_map[i].mapped + ofs;
189 }
190
191 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
192 (addr >= 0x70000000 && addr < 0x78000000) ||
193 (addr >= 0x7c000000 && addr < 0x7c400000))
194 return mt7915_reg_map_l1(dev, addr);
195
196 return mt7915_reg_map_l2(dev, addr);
197 }
198
mt7915_rr(struct mt76_dev * mdev,u32 offset)199 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset)
200 {
201 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
202 u32 addr = __mt7915_reg_addr(dev, offset);
203
204 return dev->bus_ops->rr(mdev, addr);
205 }
206
mt7915_wr(struct mt76_dev * mdev,u32 offset,u32 val)207 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val)
208 {
209 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
210 u32 addr = __mt7915_reg_addr(dev, offset);
211
212 dev->bus_ops->wr(mdev, addr, val);
213 }
214
mt7915_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)215 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
216 {
217 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
218 u32 addr = __mt7915_reg_addr(dev, offset);
219
220 return dev->bus_ops->rmw(mdev, addr, mask, val);
221 }
222
mt7915_dma_init(struct mt7915_dev * dev)223 int mt7915_dma_init(struct mt7915_dev *dev)
224 {
225 /* Increase buffer size to receive large VHT/HE MPDUs */
226 struct mt76_bus_ops *bus_ops;
227 int rx_buf_size = MT_RX_BUF_SIZE * 2;
228 int ret;
229
230 dev->bus_ops = dev->mt76.bus;
231 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
232 GFP_KERNEL);
233 if (!bus_ops)
234 return -ENOMEM;
235
236 bus_ops->rr = mt7915_rr;
237 bus_ops->wr = mt7915_wr;
238 bus_ops->rmw = mt7915_rmw;
239 dev->mt76.bus = bus_ops;
240
241 mt76_dma_attach(&dev->mt76);
242
243 /* configure global setting */
244 mt76_set(dev, MT_WFDMA1_GLO_CFG,
245 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
246 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
247
248 /* configure perfetch settings */
249 mt7915_dma_prefetch(dev);
250
251 /* reset dma idx */
252 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
253 mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0);
254
255 /* configure delay interrupt */
256 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
257 mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0);
258
259 /* init tx queue */
260 ret = mt7915_init_tx_queues(dev, MT7915_TX_RING_SIZE);
261 if (ret)
262 return ret;
263
264 /* command to WM */
265 ret = mt7915_init_mcu_queue(dev, MT_TXQ_MCU, MT7915_TXQ_MCU_WM,
266 MT7915_TX_MCU_RING_SIZE);
267 if (ret)
268 return ret;
269
270 /* command to WA */
271 ret = mt7915_init_mcu_queue(dev, MT_TXQ_MCU_WA, MT7915_TXQ_MCU_WA,
272 MT7915_TX_MCU_RING_SIZE);
273 if (ret)
274 return ret;
275
276 /* firmware download */
277 ret = mt7915_init_mcu_queue(dev, MT_TXQ_FWDL, MT7915_TXQ_FWDL,
278 MT7915_TX_FWDL_RING_SIZE);
279 if (ret)
280 return ret;
281
282 /* event from WM */
283 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
284 MT7915_RXQ_MCU_WM, MT7915_RX_MCU_RING_SIZE,
285 rx_buf_size, MT_RX_EVENT_RING_BASE);
286 if (ret)
287 return ret;
288
289 /* event from WA */
290 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
291 MT7915_RXQ_MCU_WA, MT7915_RX_MCU_RING_SIZE,
292 rx_buf_size, MT_RX_EVENT_RING_BASE);
293 if (ret)
294 return ret;
295
296 /* rx data */
297 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
298 MT7915_RX_RING_SIZE, rx_buf_size,
299 MT_RX_DATA_RING_BASE);
300 if (ret)
301 return ret;
302
303 ret = mt76_init_queues(dev);
304 if (ret < 0)
305 return ret;
306
307 netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi,
308 mt7915_poll_tx, NAPI_POLL_WEIGHT);
309 napi_enable(&dev->mt76.tx_napi);
310
311 /* hif wait WFDMA idle */
312 mt76_set(dev, MT_WFDMA0_BUSY_ENA,
313 MT_WFDMA0_BUSY_ENA_TX_FIFO0 |
314 MT_WFDMA0_BUSY_ENA_TX_FIFO1 |
315 MT_WFDMA0_BUSY_ENA_RX_FIFO);
316
317 mt76_set(dev, MT_WFDMA1_BUSY_ENA,
318 MT_WFDMA1_BUSY_ENA_TX_FIFO0 |
319 MT_WFDMA1_BUSY_ENA_TX_FIFO1 |
320 MT_WFDMA1_BUSY_ENA_RX_FIFO);
321
322 mt76_set(dev, MT_WFDMA0_PCIE1_BUSY_ENA,
323 MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 |
324 MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 |
325 MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO);
326
327 mt76_set(dev, MT_WFDMA1_PCIE1_BUSY_ENA,
328 MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 |
329 MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 |
330 MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO);
331
332 mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC,
333 MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000);
334
335 /* set WFDMA Tx/Rx */
336 mt76_set(dev, MT_WFDMA0_GLO_CFG,
337 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
338 mt76_set(dev, MT_WFDMA1_GLO_CFG,
339 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
340
341 /* enable interrupts for TX/RX rings */
342 mt7915_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_MCU |
343 MT_INT_MCU_CMD);
344
345 return 0;
346 }
347
mt7915_dma_cleanup(struct mt7915_dev * dev)348 void mt7915_dma_cleanup(struct mt7915_dev *dev)
349 {
350 /* disable */
351 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
352 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
353 MT_WFDMA0_GLO_CFG_RX_DMA_EN);
354 mt76_clear(dev, MT_WFDMA1_GLO_CFG,
355 MT_WFDMA1_GLO_CFG_TX_DMA_EN |
356 MT_WFDMA1_GLO_CFG_RX_DMA_EN);
357
358 /* reset */
359 mt76_clear(dev, MT_WFDMA1_RST,
360 MT_WFDMA1_RST_DMASHDL_ALL_RST |
361 MT_WFDMA1_RST_LOGIC_RST);
362
363 mt76_set(dev, MT_WFDMA1_RST,
364 MT_WFDMA1_RST_DMASHDL_ALL_RST |
365 MT_WFDMA1_RST_LOGIC_RST);
366
367 mt76_clear(dev, MT_WFDMA0_RST,
368 MT_WFDMA0_RST_DMASHDL_ALL_RST |
369 MT_WFDMA0_RST_LOGIC_RST);
370
371 mt76_set(dev, MT_WFDMA0_RST,
372 MT_WFDMA0_RST_DMASHDL_ALL_RST |
373 MT_WFDMA0_RST_LOGIC_RST);
374
375 mt76_dma_cleanup(&dev->mt76);
376 }
377