1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * nicstar.c
4 *
5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
6 *
7 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
8 * It was taken from the frle-0.22 device driver.
9 * As the file doesn't have a copyright notice, in the file
10 * nicstarmac.copyright I put the copyright notice from the
11 * frle-0.22 device driver.
12 * Some code is based on the nicstar driver by M. Welsh.
13 *
14 * Author: Rui Prior (rprior@inescn.pt)
15 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
16 *
17 *
18 * (C) INESC 1999
19 */
20
21 /*
22 * IMPORTANT INFORMATION
23 *
24 * There are currently three types of spinlocks:
25 *
26 * 1 - Per card interrupt spinlock (to protect structures and such)
27 * 2 - Per SCQ scq spinlock
28 * 3 - Per card resource spinlock (to access registers, etc.)
29 *
30 * These must NEVER be grabbed in reverse order.
31 *
32 */
33
34 /* Header files */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/skbuff.h>
39 #include <linux/atmdev.h>
40 #include <linux/atm.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/types.h>
44 #include <linux/string.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/sched.h>
48 #include <linux/timer.h>
49 #include <linux/interrupt.h>
50 #include <linux/bitops.h>
51 #include <linux/slab.h>
52 #include <linux/idr.h>
53 #include <asm/io.h>
54 #include <linux/uaccess.h>
55 #include <linux/atomic.h>
56 #include <linux/etherdevice.h>
57 #include "nicstar.h"
58 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
59 #include "suni.h"
60 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
61 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
62 #include "idt77105.h"
63 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
64
65 /* Additional code */
66
67 #include "nicstarmac.c"
68
69 /* Configurable parameters */
70
71 #undef PHY_LOOPBACK
72 #undef TX_DEBUG
73 #undef RX_DEBUG
74 #undef GENERAL_DEBUG
75 #undef EXTRA_DEBUG
76
77 /* Do not touch these */
78
79 #ifdef TX_DEBUG
80 #define TXPRINTK(args...) printk(args)
81 #else
82 #define TXPRINTK(args...)
83 #endif /* TX_DEBUG */
84
85 #ifdef RX_DEBUG
86 #define RXPRINTK(args...) printk(args)
87 #else
88 #define RXPRINTK(args...)
89 #endif /* RX_DEBUG */
90
91 #ifdef GENERAL_DEBUG
92 #define PRINTK(args...) printk(args)
93 #else
94 #define PRINTK(args...) do {} while (0)
95 #endif /* GENERAL_DEBUG */
96
97 #ifdef EXTRA_DEBUG
98 #define XPRINTK(args...) printk(args)
99 #else
100 #define XPRINTK(args...)
101 #endif /* EXTRA_DEBUG */
102
103 /* Macros */
104
105 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
106
107 #define NS_DELAY mdelay(1)
108
109 #define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
110
111 #ifndef ATM_SKB
112 #define ATM_SKB(s) (&(s)->atm)
113 #endif
114
115 #define scq_virt_to_bus(scq, p) \
116 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
117
118 /* Function declarations */
119
120 static u32 ns_read_sram(ns_dev * card, u32 sram_address);
121 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
122 int count);
123 static int ns_init_card(int i, struct pci_dev *pcidev);
124 static void ns_init_card_error(ns_dev * card, int error);
125 static scq_info *get_scq(ns_dev *card, int size, u32 scd);
126 static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
127 static void push_rxbufs(ns_dev *, struct sk_buff *);
128 static irqreturn_t ns_irq_handler(int irq, void *dev_id);
129 static int ns_open(struct atm_vcc *vcc);
130 static void ns_close(struct atm_vcc *vcc);
131 static void fill_tst(ns_dev * card, int n, vc_map * vc);
132 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
133 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
134 struct sk_buff *skb);
135 static void process_tsq(ns_dev * card);
136 static void drain_scq(ns_dev * card, scq_info * scq, int pos);
137 static void process_rsq(ns_dev * card);
138 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
139 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
140 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
141 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
142 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
143 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
144 static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
145 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
146 #ifdef EXTRA_DEBUG
147 static void which_list(ns_dev * card, struct sk_buff *skb);
148 #endif
149 static void ns_poll(struct timer_list *unused);
150 static void ns_phy_put(struct atm_dev *dev, unsigned char value,
151 unsigned long addr);
152 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
153
154 /* Global variables */
155
156 static struct ns_dev *cards[NS_MAX_CARDS];
157 static unsigned num_cards;
158 static const struct atmdev_ops atm_ops = {
159 .open = ns_open,
160 .close = ns_close,
161 .ioctl = ns_ioctl,
162 .send = ns_send,
163 .phy_put = ns_phy_put,
164 .phy_get = ns_phy_get,
165 .proc_read = ns_proc_read,
166 .owner = THIS_MODULE,
167 };
168
169 static struct timer_list ns_timer;
170 static char *mac[NS_MAX_CARDS];
171 module_param_array(mac, charp, NULL, 0);
172 MODULE_LICENSE("GPL");
173
174 /* Functions */
175
nicstar_init_one(struct pci_dev * pcidev,const struct pci_device_id * ent)176 static int nicstar_init_one(struct pci_dev *pcidev,
177 const struct pci_device_id *ent)
178 {
179 static int index = -1;
180 unsigned int error;
181
182 index++;
183 cards[index] = NULL;
184
185 error = ns_init_card(index, pcidev);
186 if (error) {
187 cards[index--] = NULL; /* don't increment index */
188 goto err_out;
189 }
190
191 return 0;
192 err_out:
193 return -ENODEV;
194 }
195
nicstar_remove_one(struct pci_dev * pcidev)196 static void nicstar_remove_one(struct pci_dev *pcidev)
197 {
198 int i, j;
199 ns_dev *card = pci_get_drvdata(pcidev);
200 struct sk_buff *hb;
201 struct sk_buff *iovb;
202 struct sk_buff *lb;
203 struct sk_buff *sb;
204
205 i = card->index;
206
207 if (cards[i] == NULL)
208 return;
209
210 if (card->atmdev->phy && card->atmdev->phy->stop)
211 card->atmdev->phy->stop(card->atmdev);
212
213 /* Stop everything */
214 writel(0x00000000, card->membase + CFG);
215
216 /* De-register device */
217 atm_dev_deregister(card->atmdev);
218
219 /* Disable PCI device */
220 pci_disable_device(pcidev);
221
222 /* Free up resources */
223 j = 0;
224 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
225 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
226 dev_kfree_skb_any(hb);
227 j++;
228 }
229 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
230 j = 0;
231 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
232 card->iovpool.count);
233 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
234 dev_kfree_skb_any(iovb);
235 j++;
236 }
237 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
238 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
239 dev_kfree_skb_any(lb);
240 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
241 dev_kfree_skb_any(sb);
242 free_scq(card, card->scq0, NULL);
243 for (j = 0; j < NS_FRSCD_NUM; j++) {
244 if (card->scd2vc[j] != NULL)
245 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
246 }
247 idr_destroy(&card->idr);
248 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
249 card->rsq.org, card->rsq.dma);
250 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
251 card->tsq.org, card->tsq.dma);
252 free_irq(card->pcidev->irq, card);
253 iounmap(card->membase);
254 kfree(card);
255 }
256
257 static const struct pci_device_id nicstar_pci_tbl[] = {
258 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
259 {0,} /* terminate list */
260 };
261
262 MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
263
264 static struct pci_driver nicstar_driver = {
265 .name = "nicstar",
266 .id_table = nicstar_pci_tbl,
267 .probe = nicstar_init_one,
268 .remove = nicstar_remove_one,
269 };
270
nicstar_init(void)271 static int __init nicstar_init(void)
272 {
273 unsigned error = 0; /* Initialized to remove compile warning */
274
275 XPRINTK("nicstar: nicstar_init() called.\n");
276
277 error = pci_register_driver(&nicstar_driver);
278
279 TXPRINTK("nicstar: TX debug enabled.\n");
280 RXPRINTK("nicstar: RX debug enabled.\n");
281 PRINTK("nicstar: General debug enabled.\n");
282 #ifdef PHY_LOOPBACK
283 printk("nicstar: using PHY loopback.\n");
284 #endif /* PHY_LOOPBACK */
285 XPRINTK("nicstar: nicstar_init() returned.\n");
286
287 if (!error) {
288 timer_setup(&ns_timer, ns_poll, 0);
289 ns_timer.expires = jiffies + NS_POLL_PERIOD;
290 add_timer(&ns_timer);
291 }
292
293 return error;
294 }
295
nicstar_cleanup(void)296 static void __exit nicstar_cleanup(void)
297 {
298 XPRINTK("nicstar: nicstar_cleanup() called.\n");
299
300 del_timer_sync(&ns_timer);
301
302 pci_unregister_driver(&nicstar_driver);
303
304 XPRINTK("nicstar: nicstar_cleanup() returned.\n");
305 }
306
ns_read_sram(ns_dev * card,u32 sram_address)307 static u32 ns_read_sram(ns_dev * card, u32 sram_address)
308 {
309 unsigned long flags;
310 u32 data;
311 sram_address <<= 2;
312 sram_address &= 0x0007FFFC; /* address must be dword aligned */
313 sram_address |= 0x50000000; /* SRAM read command */
314 spin_lock_irqsave(&card->res_lock, flags);
315 while (CMD_BUSY(card)) ;
316 writel(sram_address, card->membase + CMD);
317 while (CMD_BUSY(card)) ;
318 data = readl(card->membase + DR0);
319 spin_unlock_irqrestore(&card->res_lock, flags);
320 return data;
321 }
322
ns_write_sram(ns_dev * card,u32 sram_address,u32 * value,int count)323 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
324 int count)
325 {
326 unsigned long flags;
327 int i, c;
328 count--; /* count range now is 0..3 instead of 1..4 */
329 c = count;
330 c <<= 2; /* to use increments of 4 */
331 spin_lock_irqsave(&card->res_lock, flags);
332 while (CMD_BUSY(card)) ;
333 for (i = 0; i <= c; i += 4)
334 writel(*(value++), card->membase + i);
335 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
336 so card->membase + DR0 == card->membase */
337 sram_address <<= 2;
338 sram_address &= 0x0007FFFC;
339 sram_address |= (0x40000000 | count);
340 writel(sram_address, card->membase + CMD);
341 spin_unlock_irqrestore(&card->res_lock, flags);
342 }
343
ns_init_card(int i,struct pci_dev * pcidev)344 static int ns_init_card(int i, struct pci_dev *pcidev)
345 {
346 int j;
347 struct ns_dev *card = NULL;
348 unsigned char pci_latency;
349 unsigned error;
350 u32 data;
351 u32 u32d[4];
352 u32 ns_cfg_rctsize;
353 int bcount;
354 unsigned long membase;
355
356 error = 0;
357
358 if (pci_enable_device(pcidev)) {
359 printk("nicstar%d: can't enable PCI device\n", i);
360 error = 2;
361 ns_init_card_error(card, error);
362 return error;
363 }
364 if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) {
365 printk(KERN_WARNING
366 "nicstar%d: No suitable DMA available.\n", i);
367 error = 2;
368 ns_init_card_error(card, error);
369 return error;
370 }
371
372 card = kmalloc(sizeof(*card), GFP_KERNEL);
373 if (!card) {
374 printk
375 ("nicstar%d: can't allocate memory for device structure.\n",
376 i);
377 error = 2;
378 ns_init_card_error(card, error);
379 return error;
380 }
381 cards[i] = card;
382 spin_lock_init(&card->int_lock);
383 spin_lock_init(&card->res_lock);
384
385 pci_set_drvdata(pcidev, card);
386
387 card->index = i;
388 card->atmdev = NULL;
389 card->pcidev = pcidev;
390 membase = pci_resource_start(pcidev, 1);
391 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
392 if (!card->membase) {
393 printk("nicstar%d: can't ioremap() membase.\n", i);
394 error = 3;
395 ns_init_card_error(card, error);
396 return error;
397 }
398 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
399
400 pci_set_master(pcidev);
401
402 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
403 printk("nicstar%d: can't read PCI latency timer.\n", i);
404 error = 6;
405 ns_init_card_error(card, error);
406 return error;
407 }
408 #ifdef NS_PCI_LATENCY
409 if (pci_latency < NS_PCI_LATENCY) {
410 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
411 NS_PCI_LATENCY);
412 for (j = 1; j < 4; j++) {
413 if (pci_write_config_byte
414 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
415 break;
416 }
417 if (j == 4) {
418 printk
419 ("nicstar%d: can't set PCI latency timer to %d.\n",
420 i, NS_PCI_LATENCY);
421 error = 7;
422 ns_init_card_error(card, error);
423 return error;
424 }
425 }
426 #endif /* NS_PCI_LATENCY */
427
428 /* Clear timer overflow */
429 data = readl(card->membase + STAT);
430 if (data & NS_STAT_TMROF)
431 writel(NS_STAT_TMROF, card->membase + STAT);
432
433 /* Software reset */
434 writel(NS_CFG_SWRST, card->membase + CFG);
435 NS_DELAY;
436 writel(0x00000000, card->membase + CFG);
437
438 /* PHY reset */
439 writel(0x00000008, card->membase + GP);
440 NS_DELAY;
441 writel(0x00000001, card->membase + GP);
442 NS_DELAY;
443 while (CMD_BUSY(card)) ;
444 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
445 NS_DELAY;
446
447 /* Detect PHY type */
448 while (CMD_BUSY(card)) ;
449 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
450 while (CMD_BUSY(card)) ;
451 data = readl(card->membase + DR0);
452 switch (data) {
453 case 0x00000009:
454 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
455 card->max_pcr = ATM_25_PCR;
456 while (CMD_BUSY(card)) ;
457 writel(0x00000008, card->membase + DR0);
458 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
459 /* Clear an eventual pending interrupt */
460 writel(NS_STAT_SFBQF, card->membase + STAT);
461 #ifdef PHY_LOOPBACK
462 while (CMD_BUSY(card)) ;
463 writel(0x00000022, card->membase + DR0);
464 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
465 #endif /* PHY_LOOPBACK */
466 break;
467 case 0x00000030:
468 case 0x00000031:
469 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
470 card->max_pcr = ATM_OC3_PCR;
471 #ifdef PHY_LOOPBACK
472 while (CMD_BUSY(card)) ;
473 writel(0x00000002, card->membase + DR0);
474 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
475 #endif /* PHY_LOOPBACK */
476 break;
477 default:
478 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
479 error = 8;
480 ns_init_card_error(card, error);
481 return error;
482 }
483 writel(0x00000000, card->membase + GP);
484
485 /* Determine SRAM size */
486 data = 0x76543210;
487 ns_write_sram(card, 0x1C003, &data, 1);
488 data = 0x89ABCDEF;
489 ns_write_sram(card, 0x14003, &data, 1);
490 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
491 ns_read_sram(card, 0x1C003) == 0x76543210)
492 card->sram_size = 128;
493 else
494 card->sram_size = 32;
495 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
496
497 card->rct_size = NS_MAX_RCTSIZE;
498
499 #if (NS_MAX_RCTSIZE == 4096)
500 if (card->sram_size == 128)
501 printk
502 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
503 i);
504 #elif (NS_MAX_RCTSIZE == 16384)
505 if (card->sram_size == 32) {
506 printk
507 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
508 i);
509 card->rct_size = 4096;
510 }
511 #else
512 #error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
513 #endif
514
515 card->vpibits = NS_VPIBITS;
516 if (card->rct_size == 4096)
517 card->vcibits = 12 - NS_VPIBITS;
518 else /* card->rct_size == 16384 */
519 card->vcibits = 14 - NS_VPIBITS;
520
521 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
522 if (mac[i] == NULL)
523 nicstar_init_eprom(card->membase);
524
525 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
526 writel(0x00000000, card->membase + VPM);
527
528 card->intcnt = 0;
529 if (request_irq
530 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
531 pr_err("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
532 error = 9;
533 ns_init_card_error(card, error);
534 return error;
535 }
536
537 /* Initialize TSQ */
538 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
539 NS_TSQSIZE + NS_TSQ_ALIGNMENT,
540 &card->tsq.dma, GFP_KERNEL);
541 if (card->tsq.org == NULL) {
542 printk("nicstar%d: can't allocate TSQ.\n", i);
543 error = 10;
544 ns_init_card_error(card, error);
545 return error;
546 }
547 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
548 card->tsq.next = card->tsq.base;
549 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
550 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
551 ns_tsi_init(card->tsq.base + j);
552 writel(0x00000000, card->membase + TSQH);
553 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
554 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
555
556 /* Initialize RSQ */
557 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev,
558 NS_RSQSIZE + NS_RSQ_ALIGNMENT,
559 &card->rsq.dma, GFP_KERNEL);
560 if (card->rsq.org == NULL) {
561 printk("nicstar%d: can't allocate RSQ.\n", i);
562 error = 11;
563 ns_init_card_error(card, error);
564 return error;
565 }
566 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
567 card->rsq.next = card->rsq.base;
568 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
569 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
570 ns_rsqe_init(card->rsq.base + j);
571 writel(0x00000000, card->membase + RSQH);
572 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
573 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
574
575 /* Initialize SCQ0, the only VBR SCQ used */
576 card->scq1 = NULL;
577 card->scq2 = NULL;
578 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
579 if (card->scq0 == NULL) {
580 printk("nicstar%d: can't get SCQ0.\n", i);
581 error = 12;
582 ns_init_card_error(card, error);
583 return error;
584 }
585 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
586 u32d[1] = (u32) 0x00000000;
587 u32d[2] = (u32) 0xffffffff;
588 u32d[3] = (u32) 0x00000000;
589 ns_write_sram(card, NS_VRSCD0, u32d, 4);
590 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
591 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
592 card->scq0->scd = NS_VRSCD0;
593 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
594
595 /* Initialize TSTs */
596 card->tst_addr = NS_TST0;
597 card->tst_free_entries = NS_TST_NUM_ENTRIES;
598 data = NS_TST_OPCODE_VARIABLE;
599 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
600 ns_write_sram(card, NS_TST0 + j, &data, 1);
601 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
602 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
603 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
604 ns_write_sram(card, NS_TST1 + j, &data, 1);
605 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
606 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
607 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
608 card->tste2vc[j] = NULL;
609 writel(NS_TST0 << 2, card->membase + TSTB);
610
611 /* Initialize RCT. AAL type is set on opening the VC. */
612 #ifdef RCQ_SUPPORT
613 u32d[0] = NS_RCTE_RAWCELLINTEN;
614 #else
615 u32d[0] = 0x00000000;
616 #endif /* RCQ_SUPPORT */
617 u32d[1] = 0x00000000;
618 u32d[2] = 0x00000000;
619 u32d[3] = 0xFFFFFFFF;
620 for (j = 0; j < card->rct_size; j++)
621 ns_write_sram(card, j * 4, u32d, 4);
622
623 memset(card->vcmap, 0, sizeof(card->vcmap));
624
625 for (j = 0; j < NS_FRSCD_NUM; j++)
626 card->scd2vc[j] = NULL;
627
628 /* Initialize buffer levels */
629 card->sbnr.min = MIN_SB;
630 card->sbnr.init = NUM_SB;
631 card->sbnr.max = MAX_SB;
632 card->lbnr.min = MIN_LB;
633 card->lbnr.init = NUM_LB;
634 card->lbnr.max = MAX_LB;
635 card->iovnr.min = MIN_IOVB;
636 card->iovnr.init = NUM_IOVB;
637 card->iovnr.max = MAX_IOVB;
638 card->hbnr.min = MIN_HB;
639 card->hbnr.init = NUM_HB;
640 card->hbnr.max = MAX_HB;
641
642 card->sm_handle = NULL;
643 card->sm_addr = 0x00000000;
644 card->lg_handle = NULL;
645 card->lg_addr = 0x00000000;
646
647 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
648
649 idr_init(&card->idr);
650
651 /* Pre-allocate some huge buffers */
652 skb_queue_head_init(&card->hbpool.queue);
653 card->hbpool.count = 0;
654 for (j = 0; j < NUM_HB; j++) {
655 struct sk_buff *hb;
656 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
657 if (hb == NULL) {
658 printk
659 ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
660 i, j, NUM_HB);
661 error = 13;
662 ns_init_card_error(card, error);
663 return error;
664 }
665 NS_PRV_BUFTYPE(hb) = BUF_NONE;
666 skb_queue_tail(&card->hbpool.queue, hb);
667 card->hbpool.count++;
668 }
669
670 /* Allocate large buffers */
671 skb_queue_head_init(&card->lbpool.queue);
672 card->lbpool.count = 0; /* Not used */
673 for (j = 0; j < NUM_LB; j++) {
674 struct sk_buff *lb;
675 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
676 if (lb == NULL) {
677 printk
678 ("nicstar%d: can't allocate %dth of %d large buffers.\n",
679 i, j, NUM_LB);
680 error = 14;
681 ns_init_card_error(card, error);
682 return error;
683 }
684 NS_PRV_BUFTYPE(lb) = BUF_LG;
685 skb_queue_tail(&card->lbpool.queue, lb);
686 skb_reserve(lb, NS_SMBUFSIZE);
687 push_rxbufs(card, lb);
688 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
689 if (j == 1) {
690 card->rcbuf = lb;
691 card->rawcell = (struct ns_rcqe *) lb->data;
692 card->rawch = NS_PRV_DMA(lb);
693 }
694 }
695 /* Test for strange behaviour which leads to crashes */
696 if ((bcount =
697 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
698 printk
699 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
700 i, j, bcount);
701 error = 14;
702 ns_init_card_error(card, error);
703 return error;
704 }
705
706 /* Allocate small buffers */
707 skb_queue_head_init(&card->sbpool.queue);
708 card->sbpool.count = 0; /* Not used */
709 for (j = 0; j < NUM_SB; j++) {
710 struct sk_buff *sb;
711 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
712 if (sb == NULL) {
713 printk
714 ("nicstar%d: can't allocate %dth of %d small buffers.\n",
715 i, j, NUM_SB);
716 error = 15;
717 ns_init_card_error(card, error);
718 return error;
719 }
720 NS_PRV_BUFTYPE(sb) = BUF_SM;
721 skb_queue_tail(&card->sbpool.queue, sb);
722 skb_reserve(sb, NS_AAL0_HEADER);
723 push_rxbufs(card, sb);
724 }
725 /* Test for strange behaviour which leads to crashes */
726 if ((bcount =
727 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
728 printk
729 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
730 i, j, bcount);
731 error = 15;
732 ns_init_card_error(card, error);
733 return error;
734 }
735
736 /* Allocate iovec buffers */
737 skb_queue_head_init(&card->iovpool.queue);
738 card->iovpool.count = 0;
739 for (j = 0; j < NUM_IOVB; j++) {
740 struct sk_buff *iovb;
741 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
742 if (iovb == NULL) {
743 printk
744 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
745 i, j, NUM_IOVB);
746 error = 16;
747 ns_init_card_error(card, error);
748 return error;
749 }
750 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
751 skb_queue_tail(&card->iovpool.queue, iovb);
752 card->iovpool.count++;
753 }
754
755 /* Configure NICStAR */
756 if (card->rct_size == 4096)
757 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
758 else /* (card->rct_size == 16384) */
759 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
760
761 card->efbie = 1;
762
763 /* Register device */
764 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
765 -1, NULL);
766 if (card->atmdev == NULL) {
767 printk("nicstar%d: can't register device.\n", i);
768 error = 17;
769 ns_init_card_error(card, error);
770 return error;
771 }
772
773 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
774 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
775 card->atmdev->esi, 6);
776 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
777 nicstar_read_eprom(card->membase,
778 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
779 card->atmdev->esi, 6);
780 }
781 }
782
783 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
784
785 card->atmdev->dev_data = card;
786 card->atmdev->ci_range.vpi_bits = card->vpibits;
787 card->atmdev->ci_range.vci_bits = card->vcibits;
788 card->atmdev->link_rate = card->max_pcr;
789 card->atmdev->phy = NULL;
790
791 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
792 if (card->max_pcr == ATM_OC3_PCR)
793 suni_init(card->atmdev);
794 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
795
796 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
797 if (card->max_pcr == ATM_25_PCR)
798 idt77105_init(card->atmdev);
799 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
800
801 if (card->atmdev->phy && card->atmdev->phy->start)
802 card->atmdev->phy->start(card->atmdev);
803
804 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
805 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
806 NS_CFG_PHYIE, card->membase + CFG);
807
808 num_cards++;
809
810 return error;
811 }
812
ns_init_card_error(ns_dev * card,int error)813 static void ns_init_card_error(ns_dev *card, int error)
814 {
815 if (error >= 17) {
816 writel(0x00000000, card->membase + CFG);
817 }
818 if (error >= 16) {
819 struct sk_buff *iovb;
820 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
821 dev_kfree_skb_any(iovb);
822 }
823 if (error >= 15) {
824 struct sk_buff *sb;
825 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
826 dev_kfree_skb_any(sb);
827 free_scq(card, card->scq0, NULL);
828 }
829 if (error >= 14) {
830 struct sk_buff *lb;
831 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
832 dev_kfree_skb_any(lb);
833 }
834 if (error >= 13) {
835 struct sk_buff *hb;
836 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
837 dev_kfree_skb_any(hb);
838 }
839 if (error >= 12) {
840 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
841 card->rsq.org, card->rsq.dma);
842 }
843 if (error >= 11) {
844 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
845 card->tsq.org, card->tsq.dma);
846 }
847 if (error >= 10) {
848 free_irq(card->pcidev->irq, card);
849 }
850 if (error >= 4) {
851 iounmap(card->membase);
852 }
853 if (error >= 3) {
854 pci_disable_device(card->pcidev);
855 kfree(card);
856 }
857 }
858
get_scq(ns_dev * card,int size,u32 scd)859 static scq_info *get_scq(ns_dev *card, int size, u32 scd)
860 {
861 scq_info *scq;
862 int i;
863
864 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
865 return NULL;
866
867 scq = kmalloc(sizeof(*scq), GFP_KERNEL);
868 if (!scq)
869 return NULL;
870 scq->org = dma_alloc_coherent(&card->pcidev->dev,
871 2 * size, &scq->dma, GFP_KERNEL);
872 if (!scq->org) {
873 kfree(scq);
874 return NULL;
875 }
876 scq->skb = kmalloc_array(size / NS_SCQE_SIZE,
877 sizeof(*scq->skb),
878 GFP_KERNEL);
879 if (!scq->skb) {
880 dma_free_coherent(&card->pcidev->dev,
881 2 * size, scq->org, scq->dma);
882 kfree(scq);
883 return NULL;
884 }
885 scq->num_entries = size / NS_SCQE_SIZE;
886 scq->base = PTR_ALIGN(scq->org, size);
887 scq->next = scq->base;
888 scq->last = scq->base + (scq->num_entries - 1);
889 scq->tail = scq->last;
890 scq->scd = scd;
891 scq->num_entries = size / NS_SCQE_SIZE;
892 scq->tbd_count = 0;
893 init_waitqueue_head(&scq->scqfull_waitq);
894 scq->full = 0;
895 spin_lock_init(&scq->lock);
896
897 for (i = 0; i < scq->num_entries; i++)
898 scq->skb[i] = NULL;
899
900 return scq;
901 }
902
903 /* For variable rate SCQ vcc must be NULL */
free_scq(ns_dev * card,scq_info * scq,struct atm_vcc * vcc)904 static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
905 {
906 int i;
907
908 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
909 for (i = 0; i < scq->num_entries; i++) {
910 if (scq->skb[i] != NULL) {
911 vcc = ATM_SKB(scq->skb[i])->vcc;
912 if (vcc->pop != NULL)
913 vcc->pop(vcc, scq->skb[i]);
914 else
915 dev_kfree_skb_any(scq->skb[i]);
916 }
917 } else { /* vcc must be != NULL */
918
919 if (vcc == NULL) {
920 printk
921 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
922 for (i = 0; i < scq->num_entries; i++)
923 dev_kfree_skb_any(scq->skb[i]);
924 } else
925 for (i = 0; i < scq->num_entries; i++) {
926 if (scq->skb[i] != NULL) {
927 if (vcc->pop != NULL)
928 vcc->pop(vcc, scq->skb[i]);
929 else
930 dev_kfree_skb_any(scq->skb[i]);
931 }
932 }
933 }
934 kfree(scq->skb);
935 dma_free_coherent(&card->pcidev->dev,
936 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
937 VBR_SCQSIZE : CBR_SCQSIZE),
938 scq->org, scq->dma);
939 kfree(scq);
940 }
941
942 /* The handles passed must be pointers to the sk_buff containing the small
943 or large buffer(s) cast to u32. */
push_rxbufs(ns_dev * card,struct sk_buff * skb)944 static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
945 {
946 struct sk_buff *handle1, *handle2;
947 int id1, id2;
948 u32 addr1, addr2;
949 u32 stat;
950 unsigned long flags;
951
952 /* *BARF* */
953 handle2 = NULL;
954 addr2 = 0;
955 handle1 = skb;
956 addr1 = dma_map_single(&card->pcidev->dev,
957 skb->data,
958 (NS_PRV_BUFTYPE(skb) == BUF_SM
959 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
960 DMA_TO_DEVICE);
961 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
962
963 #ifdef GENERAL_DEBUG
964 if (!addr1)
965 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
966 card->index);
967 #endif /* GENERAL_DEBUG */
968
969 stat = readl(card->membase + STAT);
970 card->sbfqc = ns_stat_sfbqc_get(stat);
971 card->lbfqc = ns_stat_lfbqc_get(stat);
972 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
973 if (!addr2) {
974 if (card->sm_addr) {
975 addr2 = card->sm_addr;
976 handle2 = card->sm_handle;
977 card->sm_addr = 0x00000000;
978 card->sm_handle = NULL;
979 } else { /* (!sm_addr) */
980
981 card->sm_addr = addr1;
982 card->sm_handle = handle1;
983 }
984 }
985 } else { /* buf_type == BUF_LG */
986
987 if (!addr2) {
988 if (card->lg_addr) {
989 addr2 = card->lg_addr;
990 handle2 = card->lg_handle;
991 card->lg_addr = 0x00000000;
992 card->lg_handle = NULL;
993 } else { /* (!lg_addr) */
994
995 card->lg_addr = addr1;
996 card->lg_handle = handle1;
997 }
998 }
999 }
1000
1001 if (addr2) {
1002 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
1003 if (card->sbfqc >= card->sbnr.max) {
1004 skb_unlink(handle1, &card->sbpool.queue);
1005 dev_kfree_skb_any(handle1);
1006 skb_unlink(handle2, &card->sbpool.queue);
1007 dev_kfree_skb_any(handle2);
1008 return;
1009 } else
1010 card->sbfqc += 2;
1011 } else { /* (buf_type == BUF_LG) */
1012
1013 if (card->lbfqc >= card->lbnr.max) {
1014 skb_unlink(handle1, &card->lbpool.queue);
1015 dev_kfree_skb_any(handle1);
1016 skb_unlink(handle2, &card->lbpool.queue);
1017 dev_kfree_skb_any(handle2);
1018 return;
1019 } else
1020 card->lbfqc += 2;
1021 }
1022
1023 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
1024 if (id1 < 0)
1025 goto out;
1026
1027 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
1028 if (id2 < 0)
1029 goto out;
1030
1031 spin_lock_irqsave(&card->res_lock, flags);
1032 while (CMD_BUSY(card)) ;
1033 writel(addr2, card->membase + DR3);
1034 writel(id2, card->membase + DR2);
1035 writel(addr1, card->membase + DR1);
1036 writel(id1, card->membase + DR0);
1037 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
1038 card->membase + CMD);
1039 spin_unlock_irqrestore(&card->res_lock, flags);
1040
1041 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1042 card->index,
1043 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
1044 addr1, addr2);
1045 }
1046
1047 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1048 card->lbfqc >= card->lbnr.min) {
1049 card->efbie = 1;
1050 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1051 card->membase + CFG);
1052 }
1053
1054 out:
1055 return;
1056 }
1057
ns_irq_handler(int irq,void * dev_id)1058 static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1059 {
1060 u32 stat_r;
1061 ns_dev *card;
1062 struct atm_dev *dev;
1063 unsigned long flags;
1064
1065 card = (ns_dev *) dev_id;
1066 dev = card->atmdev;
1067 card->intcnt++;
1068
1069 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1070
1071 spin_lock_irqsave(&card->int_lock, flags);
1072
1073 stat_r = readl(card->membase + STAT);
1074
1075 /* Transmit Status Indicator has been written to T. S. Queue */
1076 if (stat_r & NS_STAT_TSIF) {
1077 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1078 process_tsq(card);
1079 writel(NS_STAT_TSIF, card->membase + STAT);
1080 }
1081
1082 /* Incomplete CS-PDU has been transmitted */
1083 if (stat_r & NS_STAT_TXICP) {
1084 writel(NS_STAT_TXICP, card->membase + STAT);
1085 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1086 card->index);
1087 }
1088
1089 /* Transmit Status Queue 7/8 full */
1090 if (stat_r & NS_STAT_TSQF) {
1091 writel(NS_STAT_TSQF, card->membase + STAT);
1092 PRINTK("nicstar%d: TSQ full.\n", card->index);
1093 process_tsq(card);
1094 }
1095
1096 /* Timer overflow */
1097 if (stat_r & NS_STAT_TMROF) {
1098 writel(NS_STAT_TMROF, card->membase + STAT);
1099 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1100 }
1101
1102 /* PHY device interrupt signal active */
1103 if (stat_r & NS_STAT_PHYI) {
1104 writel(NS_STAT_PHYI, card->membase + STAT);
1105 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1106 if (dev->phy && dev->phy->interrupt) {
1107 dev->phy->interrupt(dev);
1108 }
1109 }
1110
1111 /* Small Buffer Queue is full */
1112 if (stat_r & NS_STAT_SFBQF) {
1113 writel(NS_STAT_SFBQF, card->membase + STAT);
1114 printk("nicstar%d: Small free buffer queue is full.\n",
1115 card->index);
1116 }
1117
1118 /* Large Buffer Queue is full */
1119 if (stat_r & NS_STAT_LFBQF) {
1120 writel(NS_STAT_LFBQF, card->membase + STAT);
1121 printk("nicstar%d: Large free buffer queue is full.\n",
1122 card->index);
1123 }
1124
1125 /* Receive Status Queue is full */
1126 if (stat_r & NS_STAT_RSQF) {
1127 writel(NS_STAT_RSQF, card->membase + STAT);
1128 printk("nicstar%d: RSQ full.\n", card->index);
1129 process_rsq(card);
1130 }
1131
1132 /* Complete CS-PDU received */
1133 if (stat_r & NS_STAT_EOPDU) {
1134 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1135 process_rsq(card);
1136 writel(NS_STAT_EOPDU, card->membase + STAT);
1137 }
1138
1139 /* Raw cell received */
1140 if (stat_r & NS_STAT_RAWCF) {
1141 writel(NS_STAT_RAWCF, card->membase + STAT);
1142 #ifndef RCQ_SUPPORT
1143 printk("nicstar%d: Raw cell received and no support yet...\n",
1144 card->index);
1145 #endif /* RCQ_SUPPORT */
1146 /* NOTE: the following procedure may keep a raw cell pending until the
1147 next interrupt. As this preliminary support is only meant to
1148 avoid buffer leakage, this is not an issue. */
1149 while (readl(card->membase + RAWCT) != card->rawch) {
1150
1151 if (ns_rcqe_islast(card->rawcell)) {
1152 struct sk_buff *oldbuf;
1153
1154 oldbuf = card->rcbuf;
1155 card->rcbuf = idr_find(&card->idr,
1156 ns_rcqe_nextbufhandle(card->rawcell));
1157 card->rawch = NS_PRV_DMA(card->rcbuf);
1158 card->rawcell = (struct ns_rcqe *)
1159 card->rcbuf->data;
1160 recycle_rx_buf(card, oldbuf);
1161 } else {
1162 card->rawch += NS_RCQE_SIZE;
1163 card->rawcell++;
1164 }
1165 }
1166 }
1167
1168 /* Small buffer queue is empty */
1169 if (stat_r & NS_STAT_SFBQE) {
1170 int i;
1171 struct sk_buff *sb;
1172
1173 writel(NS_STAT_SFBQE, card->membase + STAT);
1174 printk("nicstar%d: Small free buffer queue empty.\n",
1175 card->index);
1176 for (i = 0; i < card->sbnr.min; i++) {
1177 sb = dev_alloc_skb(NS_SMSKBSIZE);
1178 if (sb == NULL) {
1179 writel(readl(card->membase + CFG) &
1180 ~NS_CFG_EFBIE, card->membase + CFG);
1181 card->efbie = 0;
1182 break;
1183 }
1184 NS_PRV_BUFTYPE(sb) = BUF_SM;
1185 skb_queue_tail(&card->sbpool.queue, sb);
1186 skb_reserve(sb, NS_AAL0_HEADER);
1187 push_rxbufs(card, sb);
1188 }
1189 card->sbfqc = i;
1190 process_rsq(card);
1191 }
1192
1193 /* Large buffer queue empty */
1194 if (stat_r & NS_STAT_LFBQE) {
1195 int i;
1196 struct sk_buff *lb;
1197
1198 writel(NS_STAT_LFBQE, card->membase + STAT);
1199 printk("nicstar%d: Large free buffer queue empty.\n",
1200 card->index);
1201 for (i = 0; i < card->lbnr.min; i++) {
1202 lb = dev_alloc_skb(NS_LGSKBSIZE);
1203 if (lb == NULL) {
1204 writel(readl(card->membase + CFG) &
1205 ~NS_CFG_EFBIE, card->membase + CFG);
1206 card->efbie = 0;
1207 break;
1208 }
1209 NS_PRV_BUFTYPE(lb) = BUF_LG;
1210 skb_queue_tail(&card->lbpool.queue, lb);
1211 skb_reserve(lb, NS_SMBUFSIZE);
1212 push_rxbufs(card, lb);
1213 }
1214 card->lbfqc = i;
1215 process_rsq(card);
1216 }
1217
1218 /* Receive Status Queue is 7/8 full */
1219 if (stat_r & NS_STAT_RSQAF) {
1220 writel(NS_STAT_RSQAF, card->membase + STAT);
1221 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1222 process_rsq(card);
1223 }
1224
1225 spin_unlock_irqrestore(&card->int_lock, flags);
1226 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1227 return IRQ_HANDLED;
1228 }
1229
ns_open(struct atm_vcc * vcc)1230 static int ns_open(struct atm_vcc *vcc)
1231 {
1232 ns_dev *card;
1233 vc_map *vc;
1234 unsigned long tmpl, modl;
1235 int tcr, tcra; /* target cell rate, and absolute value */
1236 int n = 0; /* Number of entries in the TST. Initialized to remove
1237 the compiler warning. */
1238 u32 u32d[4];
1239 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1240 warning. How I wish compilers were clever enough to
1241 tell which variables can truly be used
1242 uninitialized... */
1243 int inuse; /* tx or rx vc already in use by another vcc */
1244 short vpi = vcc->vpi;
1245 int vci = vcc->vci;
1246
1247 card = (ns_dev *) vcc->dev->dev_data;
1248 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1249 vci);
1250 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1251 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1252 return -EINVAL;
1253 }
1254
1255 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1256 vcc->dev_data = vc;
1257
1258 inuse = 0;
1259 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1260 inuse = 1;
1261 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1262 inuse += 2;
1263 if (inuse) {
1264 printk("nicstar%d: %s vci already in use.\n", card->index,
1265 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1266 return -EINVAL;
1267 }
1268
1269 set_bit(ATM_VF_ADDR, &vcc->flags);
1270
1271 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1272 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1273 needed to do that. */
1274 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1275 scq_info *scq;
1276
1277 set_bit(ATM_VF_PARTIAL, &vcc->flags);
1278 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1279 /* Check requested cell rate and availability of SCD */
1280 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1281 && vcc->qos.txtp.min_pcr == 0) {
1282 PRINTK
1283 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1284 card->index);
1285 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1286 clear_bit(ATM_VF_ADDR, &vcc->flags);
1287 return -EINVAL;
1288 }
1289
1290 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1291 tcra = tcr >= 0 ? tcr : -tcr;
1292
1293 PRINTK("nicstar%d: target cell rate = %d.\n",
1294 card->index, vcc->qos.txtp.max_pcr);
1295
1296 tmpl =
1297 (unsigned long)tcra *(unsigned long)
1298 NS_TST_NUM_ENTRIES;
1299 modl = tmpl % card->max_pcr;
1300
1301 n = (int)(tmpl / card->max_pcr);
1302 if (tcr > 0) {
1303 if (modl > 0)
1304 n++;
1305 } else if (tcr == 0) {
1306 if ((n =
1307 (card->tst_free_entries -
1308 NS_TST_RESERVED)) <= 0) {
1309 PRINTK
1310 ("nicstar%d: no CBR bandwidth free.\n",
1311 card->index);
1312 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1313 clear_bit(ATM_VF_ADDR, &vcc->flags);
1314 return -EINVAL;
1315 }
1316 }
1317
1318 if (n == 0) {
1319 printk
1320 ("nicstar%d: selected bandwidth < granularity.\n",
1321 card->index);
1322 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1323 clear_bit(ATM_VF_ADDR, &vcc->flags);
1324 return -EINVAL;
1325 }
1326
1327 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1328 PRINTK
1329 ("nicstar%d: not enough free CBR bandwidth.\n",
1330 card->index);
1331 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1332 clear_bit(ATM_VF_ADDR, &vcc->flags);
1333 return -EINVAL;
1334 } else
1335 card->tst_free_entries -= n;
1336
1337 XPRINTK("nicstar%d: writing %d tst entries.\n",
1338 card->index, n);
1339 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1340 if (card->scd2vc[frscdi] == NULL) {
1341 card->scd2vc[frscdi] = vc;
1342 break;
1343 }
1344 }
1345 if (frscdi == NS_FRSCD_NUM) {
1346 PRINTK
1347 ("nicstar%d: no SCD available for CBR channel.\n",
1348 card->index);
1349 card->tst_free_entries += n;
1350 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1351 clear_bit(ATM_VF_ADDR, &vcc->flags);
1352 return -EBUSY;
1353 }
1354
1355 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1356
1357 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1358 if (scq == NULL) {
1359 PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1360 card->index);
1361 card->scd2vc[frscdi] = NULL;
1362 card->tst_free_entries += n;
1363 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1364 clear_bit(ATM_VF_ADDR, &vcc->flags);
1365 return -ENOMEM;
1366 }
1367 vc->scq = scq;
1368 u32d[0] = scq_virt_to_bus(scq, scq->base);
1369 u32d[1] = (u32) 0x00000000;
1370 u32d[2] = (u32) 0xffffffff;
1371 u32d[3] = (u32) 0x00000000;
1372 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1373
1374 fill_tst(card, n, vc);
1375 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1376 vc->cbr_scd = 0x00000000;
1377 vc->scq = card->scq0;
1378 }
1379
1380 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1381 vc->tx = 1;
1382 vc->tx_vcc = vcc;
1383 vc->tbd_count = 0;
1384 }
1385 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1386 u32 status;
1387
1388 vc->rx = 1;
1389 vc->rx_vcc = vcc;
1390 vc->rx_iov = NULL;
1391
1392 /* Open the connection in hardware */
1393 if (vcc->qos.aal == ATM_AAL5)
1394 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1395 else /* vcc->qos.aal == ATM_AAL0 */
1396 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1397 #ifdef RCQ_SUPPORT
1398 status |= NS_RCTE_RAWCELLINTEN;
1399 #endif /* RCQ_SUPPORT */
1400 ns_write_sram(card,
1401 NS_RCT +
1402 (vpi << card->vcibits | vci) *
1403 NS_RCT_ENTRY_SIZE, &status, 1);
1404 }
1405
1406 }
1407
1408 set_bit(ATM_VF_READY, &vcc->flags);
1409 return 0;
1410 }
1411
ns_close(struct atm_vcc * vcc)1412 static void ns_close(struct atm_vcc *vcc)
1413 {
1414 vc_map *vc;
1415 ns_dev *card;
1416 u32 data;
1417 int i;
1418
1419 vc = vcc->dev_data;
1420 card = vcc->dev->dev_data;
1421 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1422 (int)vcc->vpi, vcc->vci);
1423
1424 clear_bit(ATM_VF_READY, &vcc->flags);
1425
1426 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1427 u32 addr;
1428 unsigned long flags;
1429
1430 addr =
1431 NS_RCT +
1432 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1433 spin_lock_irqsave(&card->res_lock, flags);
1434 while (CMD_BUSY(card)) ;
1435 writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1436 card->membase + CMD);
1437 spin_unlock_irqrestore(&card->res_lock, flags);
1438
1439 vc->rx = 0;
1440 if (vc->rx_iov != NULL) {
1441 struct sk_buff *iovb;
1442 u32 stat;
1443
1444 stat = readl(card->membase + STAT);
1445 card->sbfqc = ns_stat_sfbqc_get(stat);
1446 card->lbfqc = ns_stat_lfbqc_get(stat);
1447
1448 PRINTK
1449 ("nicstar%d: closing a VC with pending rx buffers.\n",
1450 card->index);
1451 iovb = vc->rx_iov;
1452 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1453 NS_PRV_IOVCNT(iovb));
1454 NS_PRV_IOVCNT(iovb) = 0;
1455 spin_lock_irqsave(&card->int_lock, flags);
1456 recycle_iov_buf(card, iovb);
1457 spin_unlock_irqrestore(&card->int_lock, flags);
1458 vc->rx_iov = NULL;
1459 }
1460 }
1461
1462 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1463 vc->tx = 0;
1464 }
1465
1466 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1467 unsigned long flags;
1468 ns_scqe *scqep;
1469 scq_info *scq;
1470
1471 scq = vc->scq;
1472
1473 for (;;) {
1474 spin_lock_irqsave(&scq->lock, flags);
1475 scqep = scq->next;
1476 if (scqep == scq->base)
1477 scqep = scq->last;
1478 else
1479 scqep--;
1480 if (scqep == scq->tail) {
1481 spin_unlock_irqrestore(&scq->lock, flags);
1482 break;
1483 }
1484 /* If the last entry is not a TSR, place one in the SCQ in order to
1485 be able to completely drain it and then close. */
1486 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1487 ns_scqe tsr;
1488 u32 scdi, scqi;
1489 u32 data;
1490 int index;
1491
1492 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1493 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1494 scqi = scq->next - scq->base;
1495 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1496 tsr.word_3 = 0x00000000;
1497 tsr.word_4 = 0x00000000;
1498 *scq->next = tsr;
1499 index = (int)scqi;
1500 scq->skb[index] = NULL;
1501 if (scq->next == scq->last)
1502 scq->next = scq->base;
1503 else
1504 scq->next++;
1505 data = scq_virt_to_bus(scq, scq->next);
1506 ns_write_sram(card, scq->scd, &data, 1);
1507 }
1508 spin_unlock_irqrestore(&scq->lock, flags);
1509 schedule();
1510 }
1511
1512 /* Free all TST entries */
1513 data = NS_TST_OPCODE_VARIABLE;
1514 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1515 if (card->tste2vc[i] == vc) {
1516 ns_write_sram(card, card->tst_addr + i, &data,
1517 1);
1518 card->tste2vc[i] = NULL;
1519 card->tst_free_entries++;
1520 }
1521 }
1522
1523 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1524 free_scq(card, vc->scq, vcc);
1525 }
1526
1527 /* remove all references to vcc before deleting it */
1528 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1529 unsigned long flags;
1530 scq_info *scq = card->scq0;
1531
1532 spin_lock_irqsave(&scq->lock, flags);
1533
1534 for (i = 0; i < scq->num_entries; i++) {
1535 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1536 ATM_SKB(scq->skb[i])->vcc = NULL;
1537 atm_return(vcc, scq->skb[i]->truesize);
1538 PRINTK
1539 ("nicstar: deleted pending vcc mapping\n");
1540 }
1541 }
1542
1543 spin_unlock_irqrestore(&scq->lock, flags);
1544 }
1545
1546 vcc->dev_data = NULL;
1547 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1548 clear_bit(ATM_VF_ADDR, &vcc->flags);
1549
1550 #ifdef RX_DEBUG
1551 {
1552 u32 stat, cfg;
1553 stat = readl(card->membase + STAT);
1554 cfg = readl(card->membase + CFG);
1555 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1556 printk
1557 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
1558 card->tsq.base, card->tsq.next,
1559 card->tsq.last, readl(card->membase + TSQT));
1560 printk
1561 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
1562 card->rsq.base, card->rsq.next,
1563 card->rsq.last, readl(card->membase + RSQT));
1564 printk("Empty free buffer queue interrupt %s \n",
1565 card->efbie ? "enabled" : "disabled");
1566 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1567 ns_stat_sfbqc_get(stat), card->sbpool.count,
1568 ns_stat_lfbqc_get(stat), card->lbpool.count);
1569 printk("hbpool.count = %d iovpool.count = %d \n",
1570 card->hbpool.count, card->iovpool.count);
1571 }
1572 #endif /* RX_DEBUG */
1573 }
1574
fill_tst(ns_dev * card,int n,vc_map * vc)1575 static void fill_tst(ns_dev * card, int n, vc_map * vc)
1576 {
1577 u32 new_tst;
1578 unsigned long cl;
1579 int e, r;
1580 u32 data;
1581
1582 /* It would be very complicated to keep the two TSTs synchronized while
1583 assuring that writes are only made to the inactive TST. So, for now I
1584 will use only one TST. If problems occur, I will change this again */
1585
1586 new_tst = card->tst_addr;
1587
1588 /* Fill procedure */
1589
1590 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1591 if (card->tste2vc[e] == NULL)
1592 break;
1593 }
1594 if (e == NS_TST_NUM_ENTRIES) {
1595 printk("nicstar%d: No free TST entries found. \n", card->index);
1596 return;
1597 }
1598
1599 r = n;
1600 cl = NS_TST_NUM_ENTRIES;
1601 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1602
1603 while (r > 0) {
1604 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1605 card->tste2vc[e] = vc;
1606 ns_write_sram(card, new_tst + e, &data, 1);
1607 cl -= NS_TST_NUM_ENTRIES;
1608 r--;
1609 }
1610
1611 if (++e == NS_TST_NUM_ENTRIES) {
1612 e = 0;
1613 }
1614 cl += n;
1615 }
1616
1617 /* End of fill procedure */
1618
1619 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1620 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1621 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1622 card->tst_addr = new_tst;
1623 }
1624
ns_send(struct atm_vcc * vcc,struct sk_buff * skb)1625 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1626 {
1627 ns_dev *card;
1628 vc_map *vc;
1629 scq_info *scq;
1630 unsigned long buflen;
1631 ns_scqe scqe;
1632 u32 flags; /* TBD flags, not CPU flags */
1633
1634 card = vcc->dev->dev_data;
1635 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1636 if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1637 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1638 card->index);
1639 atomic_inc(&vcc->stats->tx_err);
1640 dev_kfree_skb_any(skb);
1641 return -EINVAL;
1642 }
1643
1644 if (!vc->tx) {
1645 printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1646 card->index);
1647 atomic_inc(&vcc->stats->tx_err);
1648 dev_kfree_skb_any(skb);
1649 return -EINVAL;
1650 }
1651
1652 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1653 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1654 card->index);
1655 atomic_inc(&vcc->stats->tx_err);
1656 dev_kfree_skb_any(skb);
1657 return -EINVAL;
1658 }
1659
1660 if (skb_shinfo(skb)->nr_frags != 0) {
1661 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1662 atomic_inc(&vcc->stats->tx_err);
1663 dev_kfree_skb_any(skb);
1664 return -EINVAL;
1665 }
1666
1667 ATM_SKB(skb)->vcc = vcc;
1668
1669 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
1670 skb->len, DMA_TO_DEVICE);
1671
1672 if (vcc->qos.aal == ATM_AAL5) {
1673 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1674 flags = NS_TBD_AAL5;
1675 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
1676 scqe.word_3 = cpu_to_le32(skb->len);
1677 scqe.word_4 =
1678 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1679 ATM_SKB(skb)->
1680 atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1681 flags |= NS_TBD_EOPDU;
1682 } else { /* (vcc->qos.aal == ATM_AAL0) */
1683
1684 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1685 flags = NS_TBD_AAL0;
1686 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
1687 scqe.word_3 = cpu_to_le32(0x00000000);
1688 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1689 flags |= NS_TBD_EOPDU;
1690 scqe.word_4 =
1691 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1692 /* Force the VPI/VCI to be the same as in VCC struct */
1693 scqe.word_4 |=
1694 cpu_to_le32((((u32) vcc->
1695 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1696 vci) <<
1697 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1698 }
1699
1700 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1701 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1702 scq = ((vc_map *) vcc->dev_data)->scq;
1703 } else {
1704 scqe.word_1 =
1705 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1706 scq = card->scq0;
1707 }
1708
1709 if (push_scqe(card, vc, scq, &scqe, skb) != 0) {
1710 atomic_inc(&vcc->stats->tx_err);
1711 dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
1712 DMA_TO_DEVICE);
1713 dev_kfree_skb_any(skb);
1714 return -EIO;
1715 }
1716 atomic_inc(&vcc->stats->tx);
1717
1718 return 0;
1719 }
1720
push_scqe(ns_dev * card,vc_map * vc,scq_info * scq,ns_scqe * tbd,struct sk_buff * skb)1721 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1722 struct sk_buff *skb)
1723 {
1724 unsigned long flags;
1725 ns_scqe tsr;
1726 u32 scdi, scqi;
1727 int scq_is_vbr;
1728 u32 data;
1729 int index;
1730
1731 spin_lock_irqsave(&scq->lock, flags);
1732 while (scq->tail == scq->next) {
1733 if (in_interrupt()) {
1734 spin_unlock_irqrestore(&scq->lock, flags);
1735 printk("nicstar%d: Error pushing TBD.\n", card->index);
1736 return 1;
1737 }
1738
1739 scq->full = 1;
1740 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1741 scq->tail != scq->next,
1742 scq->lock,
1743 SCQFULL_TIMEOUT);
1744
1745 if (scq->full) {
1746 spin_unlock_irqrestore(&scq->lock, flags);
1747 printk("nicstar%d: Timeout pushing TBD.\n",
1748 card->index);
1749 return 1;
1750 }
1751 }
1752 *scq->next = *tbd;
1753 index = (int)(scq->next - scq->base);
1754 scq->skb[index] = skb;
1755 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
1756 card->index, skb, index);
1757 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1758 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1759 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1760 scq->next);
1761 if (scq->next == scq->last)
1762 scq->next = scq->base;
1763 else
1764 scq->next++;
1765
1766 vc->tbd_count++;
1767 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1768 scq->tbd_count++;
1769 scq_is_vbr = 1;
1770 } else
1771 scq_is_vbr = 0;
1772
1773 if (vc->tbd_count >= MAX_TBD_PER_VC
1774 || scq->tbd_count >= MAX_TBD_PER_SCQ) {
1775 int has_run = 0;
1776
1777 while (scq->tail == scq->next) {
1778 if (in_interrupt()) {
1779 data = scq_virt_to_bus(scq, scq->next);
1780 ns_write_sram(card, scq->scd, &data, 1);
1781 spin_unlock_irqrestore(&scq->lock, flags);
1782 printk("nicstar%d: Error pushing TSR.\n",
1783 card->index);
1784 return 0;
1785 }
1786
1787 scq->full = 1;
1788 if (has_run++)
1789 break;
1790 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1791 scq->tail != scq->next,
1792 scq->lock,
1793 SCQFULL_TIMEOUT);
1794 }
1795
1796 if (!scq->full) {
1797 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1798 if (scq_is_vbr)
1799 scdi = NS_TSR_SCDISVBR;
1800 else
1801 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1802 scqi = scq->next - scq->base;
1803 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1804 tsr.word_3 = 0x00000000;
1805 tsr.word_4 = 0x00000000;
1806
1807 *scq->next = tsr;
1808 index = (int)scqi;
1809 scq->skb[index] = NULL;
1810 XPRINTK
1811 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1812 card->index, le32_to_cpu(tsr.word_1),
1813 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1814 le32_to_cpu(tsr.word_4), scq->next);
1815 if (scq->next == scq->last)
1816 scq->next = scq->base;
1817 else
1818 scq->next++;
1819 vc->tbd_count = 0;
1820 scq->tbd_count = 0;
1821 } else
1822 PRINTK("nicstar%d: Timeout pushing TSR.\n",
1823 card->index);
1824 }
1825 data = scq_virt_to_bus(scq, scq->next);
1826 ns_write_sram(card, scq->scd, &data, 1);
1827
1828 spin_unlock_irqrestore(&scq->lock, flags);
1829
1830 return 0;
1831 }
1832
process_tsq(ns_dev * card)1833 static void process_tsq(ns_dev * card)
1834 {
1835 u32 scdi;
1836 scq_info *scq;
1837 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
1838 int serviced_entries; /* flag indicating at least on entry was serviced */
1839
1840 serviced_entries = 0;
1841
1842 if (card->tsq.next == card->tsq.last)
1843 one_ahead = card->tsq.base;
1844 else
1845 one_ahead = card->tsq.next + 1;
1846
1847 if (one_ahead == card->tsq.last)
1848 two_ahead = card->tsq.base;
1849 else
1850 two_ahead = one_ahead + 1;
1851
1852 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1853 !ns_tsi_isempty(two_ahead))
1854 /* At most two empty, as stated in the 77201 errata */
1855 {
1856 serviced_entries = 1;
1857
1858 /* Skip the one or two possible empty entries */
1859 while (ns_tsi_isempty(card->tsq.next)) {
1860 if (card->tsq.next == card->tsq.last)
1861 card->tsq.next = card->tsq.base;
1862 else
1863 card->tsq.next++;
1864 }
1865
1866 if (!ns_tsi_tmrof(card->tsq.next)) {
1867 scdi = ns_tsi_getscdindex(card->tsq.next);
1868 if (scdi == NS_TSI_SCDISVBR)
1869 scq = card->scq0;
1870 else {
1871 if (card->scd2vc[scdi] == NULL) {
1872 printk
1873 ("nicstar%d: could not find VC from SCD index.\n",
1874 card->index);
1875 ns_tsi_init(card->tsq.next);
1876 return;
1877 }
1878 scq = card->scd2vc[scdi]->scq;
1879 }
1880 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1881 scq->full = 0;
1882 wake_up_interruptible(&(scq->scqfull_waitq));
1883 }
1884
1885 ns_tsi_init(card->tsq.next);
1886 previous = card->tsq.next;
1887 if (card->tsq.next == card->tsq.last)
1888 card->tsq.next = card->tsq.base;
1889 else
1890 card->tsq.next++;
1891
1892 if (card->tsq.next == card->tsq.last)
1893 one_ahead = card->tsq.base;
1894 else
1895 one_ahead = card->tsq.next + 1;
1896
1897 if (one_ahead == card->tsq.last)
1898 two_ahead = card->tsq.base;
1899 else
1900 two_ahead = one_ahead + 1;
1901 }
1902
1903 if (serviced_entries)
1904 writel(PTR_DIFF(previous, card->tsq.base),
1905 card->membase + TSQH);
1906 }
1907
drain_scq(ns_dev * card,scq_info * scq,int pos)1908 static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1909 {
1910 struct atm_vcc *vcc;
1911 struct sk_buff *skb;
1912 int i;
1913 unsigned long flags;
1914
1915 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
1916 card->index, scq, pos);
1917 if (pos >= scq->num_entries) {
1918 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1919 return;
1920 }
1921
1922 spin_lock_irqsave(&scq->lock, flags);
1923 i = (int)(scq->tail - scq->base);
1924 if (++i == scq->num_entries)
1925 i = 0;
1926 while (i != pos) {
1927 skb = scq->skb[i];
1928 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
1929 card->index, skb, i);
1930 if (skb != NULL) {
1931 dma_unmap_single(&card->pcidev->dev,
1932 NS_PRV_DMA(skb),
1933 skb->len,
1934 DMA_TO_DEVICE);
1935 vcc = ATM_SKB(skb)->vcc;
1936 if (vcc && vcc->pop != NULL) {
1937 vcc->pop(vcc, skb);
1938 } else {
1939 dev_kfree_skb_irq(skb);
1940 }
1941 scq->skb[i] = NULL;
1942 }
1943 if (++i == scq->num_entries)
1944 i = 0;
1945 }
1946 scq->tail = scq->base + pos;
1947 spin_unlock_irqrestore(&scq->lock, flags);
1948 }
1949
process_rsq(ns_dev * card)1950 static void process_rsq(ns_dev * card)
1951 {
1952 ns_rsqe *previous;
1953
1954 if (!ns_rsqe_valid(card->rsq.next))
1955 return;
1956 do {
1957 dequeue_rx(card, card->rsq.next);
1958 ns_rsqe_init(card->rsq.next);
1959 previous = card->rsq.next;
1960 if (card->rsq.next == card->rsq.last)
1961 card->rsq.next = card->rsq.base;
1962 else
1963 card->rsq.next++;
1964 } while (ns_rsqe_valid(card->rsq.next));
1965 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1966 }
1967
dequeue_rx(ns_dev * card,ns_rsqe * rsqe)1968 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1969 {
1970 u32 vpi, vci;
1971 vc_map *vc;
1972 struct sk_buff *iovb;
1973 struct iovec *iov;
1974 struct atm_vcc *vcc;
1975 struct sk_buff *skb;
1976 unsigned short aal5_len;
1977 int len;
1978 u32 stat;
1979 u32 id;
1980
1981 stat = readl(card->membase + STAT);
1982 card->sbfqc = ns_stat_sfbqc_get(stat);
1983 card->lbfqc = ns_stat_lfbqc_get(stat);
1984
1985 id = le32_to_cpu(rsqe->buffer_handle);
1986 skb = idr_remove(&card->idr, id);
1987 if (!skb) {
1988 RXPRINTK(KERN_ERR
1989 "nicstar%d: skb not found!\n", card->index);
1990 return;
1991 }
1992 dma_sync_single_for_cpu(&card->pcidev->dev,
1993 NS_PRV_DMA(skb),
1994 (NS_PRV_BUFTYPE(skb) == BUF_SM
1995 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
1996 DMA_FROM_DEVICE);
1997 dma_unmap_single(&card->pcidev->dev,
1998 NS_PRV_DMA(skb),
1999 (NS_PRV_BUFTYPE(skb) == BUF_SM
2000 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2001 DMA_FROM_DEVICE);
2002 vpi = ns_rsqe_vpi(rsqe);
2003 vci = ns_rsqe_vci(rsqe);
2004 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2005 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2006 card->index, vpi, vci);
2007 recycle_rx_buf(card, skb);
2008 return;
2009 }
2010
2011 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2012 if (!vc->rx) {
2013 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2014 card->index, vpi, vci);
2015 recycle_rx_buf(card, skb);
2016 return;
2017 }
2018
2019 vcc = vc->rx_vcc;
2020
2021 if (vcc->qos.aal == ATM_AAL0) {
2022 struct sk_buff *sb;
2023 unsigned char *cell;
2024 int i;
2025
2026 cell = skb->data;
2027 for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2028 sb = dev_alloc_skb(NS_SMSKBSIZE);
2029 if (!sb) {
2030 printk
2031 ("nicstar%d: Can't allocate buffers for aal0.\n",
2032 card->index);
2033 atomic_add(i, &vcc->stats->rx_drop);
2034 break;
2035 }
2036 if (!atm_charge(vcc, sb->truesize)) {
2037 RXPRINTK
2038 ("nicstar%d: atm_charge() dropped aal0 packets.\n",
2039 card->index);
2040 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
2041 dev_kfree_skb_any(sb);
2042 break;
2043 }
2044 /* Rebuild the header */
2045 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2046 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2047 if (i == 1 && ns_rsqe_eopdu(rsqe))
2048 *((u32 *) sb->data) |= 0x00000002;
2049 skb_put(sb, NS_AAL0_HEADER);
2050 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2051 skb_put(sb, ATM_CELL_PAYLOAD);
2052 ATM_SKB(sb)->vcc = vcc;
2053 __net_timestamp(sb);
2054 vcc->push(vcc, sb);
2055 atomic_inc(&vcc->stats->rx);
2056 cell += ATM_CELL_PAYLOAD;
2057 }
2058
2059 recycle_rx_buf(card, skb);
2060 return;
2061 }
2062
2063 /* To reach this point, the AAL layer can only be AAL5 */
2064
2065 if ((iovb = vc->rx_iov) == NULL) {
2066 iovb = skb_dequeue(&(card->iovpool.queue));
2067 if (iovb == NULL) { /* No buffers in the queue */
2068 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2069 if (iovb == NULL) {
2070 printk("nicstar%d: Out of iovec buffers.\n",
2071 card->index);
2072 atomic_inc(&vcc->stats->rx_drop);
2073 recycle_rx_buf(card, skb);
2074 return;
2075 }
2076 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2077 } else if (--card->iovpool.count < card->iovnr.min) {
2078 struct sk_buff *new_iovb;
2079 if ((new_iovb =
2080 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2081 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2082 skb_queue_tail(&card->iovpool.queue, new_iovb);
2083 card->iovpool.count++;
2084 }
2085 }
2086 vc->rx_iov = iovb;
2087 NS_PRV_IOVCNT(iovb) = 0;
2088 iovb->len = 0;
2089 iovb->data = iovb->head;
2090 skb_reset_tail_pointer(iovb);
2091 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2092 buffer is stored as iovec base, NOT a pointer to the
2093 small or large buffer itself. */
2094 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
2095 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2096 atomic_inc(&vcc->stats->rx_err);
2097 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2098 NS_MAX_IOVECS);
2099 NS_PRV_IOVCNT(iovb) = 0;
2100 iovb->len = 0;
2101 iovb->data = iovb->head;
2102 skb_reset_tail_pointer(iovb);
2103 }
2104 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
2105 iov->iov_base = (void *)skb;
2106 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2107 iovb->len += iov->iov_len;
2108
2109 #ifdef EXTRA_DEBUG
2110 if (NS_PRV_IOVCNT(iovb) == 1) {
2111 if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
2112 printk
2113 ("nicstar%d: Expected a small buffer, and this is not one.\n",
2114 card->index);
2115 which_list(card, skb);
2116 atomic_inc(&vcc->stats->rx_err);
2117 recycle_rx_buf(card, skb);
2118 vc->rx_iov = NULL;
2119 recycle_iov_buf(card, iovb);
2120 return;
2121 }
2122 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
2123
2124 if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
2125 printk
2126 ("nicstar%d: Expected a large buffer, and this is not one.\n",
2127 card->index);
2128 which_list(card, skb);
2129 atomic_inc(&vcc->stats->rx_err);
2130 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2131 NS_PRV_IOVCNT(iovb));
2132 vc->rx_iov = NULL;
2133 recycle_iov_buf(card, iovb);
2134 return;
2135 }
2136 }
2137 #endif /* EXTRA_DEBUG */
2138
2139 if (ns_rsqe_eopdu(rsqe)) {
2140 /* This works correctly regardless of the endianness of the host */
2141 unsigned char *L1L2 = (unsigned char *)
2142 (skb->data + iov->iov_len - 6);
2143 aal5_len = L1L2[0] << 8 | L1L2[1];
2144 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2145 if (ns_rsqe_crcerr(rsqe) ||
2146 len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2147 printk("nicstar%d: AAL5 CRC error", card->index);
2148 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2149 printk(" - PDU size mismatch.\n");
2150 else
2151 printk(".\n");
2152 atomic_inc(&vcc->stats->rx_err);
2153 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2154 NS_PRV_IOVCNT(iovb));
2155 vc->rx_iov = NULL;
2156 recycle_iov_buf(card, iovb);
2157 return;
2158 }
2159
2160 /* By this point we (hopefully) have a complete SDU without errors. */
2161
2162 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
2163 /* skb points to a small buffer */
2164 if (!atm_charge(vcc, skb->truesize)) {
2165 push_rxbufs(card, skb);
2166 atomic_inc(&vcc->stats->rx_drop);
2167 } else {
2168 skb_put(skb, len);
2169 dequeue_sm_buf(card, skb);
2170 ATM_SKB(skb)->vcc = vcc;
2171 __net_timestamp(skb);
2172 vcc->push(vcc, skb);
2173 atomic_inc(&vcc->stats->rx);
2174 }
2175 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
2176 struct sk_buff *sb;
2177
2178 sb = (struct sk_buff *)(iov - 1)->iov_base;
2179 /* skb points to a large buffer */
2180
2181 if (len <= NS_SMBUFSIZE) {
2182 if (!atm_charge(vcc, sb->truesize)) {
2183 push_rxbufs(card, sb);
2184 atomic_inc(&vcc->stats->rx_drop);
2185 } else {
2186 skb_put(sb, len);
2187 dequeue_sm_buf(card, sb);
2188 ATM_SKB(sb)->vcc = vcc;
2189 __net_timestamp(sb);
2190 vcc->push(vcc, sb);
2191 atomic_inc(&vcc->stats->rx);
2192 }
2193
2194 push_rxbufs(card, skb);
2195
2196 } else { /* len > NS_SMBUFSIZE, the usual case */
2197
2198 if (!atm_charge(vcc, skb->truesize)) {
2199 push_rxbufs(card, skb);
2200 atomic_inc(&vcc->stats->rx_drop);
2201 } else {
2202 dequeue_lg_buf(card, skb);
2203 skb_push(skb, NS_SMBUFSIZE);
2204 skb_copy_from_linear_data(sb, skb->data,
2205 NS_SMBUFSIZE);
2206 skb_put(skb, len - NS_SMBUFSIZE);
2207 ATM_SKB(skb)->vcc = vcc;
2208 __net_timestamp(skb);
2209 vcc->push(vcc, skb);
2210 atomic_inc(&vcc->stats->rx);
2211 }
2212
2213 push_rxbufs(card, sb);
2214
2215 }
2216
2217 } else { /* Must push a huge buffer */
2218
2219 struct sk_buff *hb, *sb, *lb;
2220 int remaining, tocopy;
2221 int j;
2222
2223 hb = skb_dequeue(&(card->hbpool.queue));
2224 if (hb == NULL) { /* No buffers in the queue */
2225
2226 hb = dev_alloc_skb(NS_HBUFSIZE);
2227 if (hb == NULL) {
2228 printk
2229 ("nicstar%d: Out of huge buffers.\n",
2230 card->index);
2231 atomic_inc(&vcc->stats->rx_drop);
2232 recycle_iovec_rx_bufs(card,
2233 (struct iovec *)
2234 iovb->data,
2235 NS_PRV_IOVCNT(iovb));
2236 vc->rx_iov = NULL;
2237 recycle_iov_buf(card, iovb);
2238 return;
2239 } else if (card->hbpool.count < card->hbnr.min) {
2240 struct sk_buff *new_hb;
2241 if ((new_hb =
2242 dev_alloc_skb(NS_HBUFSIZE)) !=
2243 NULL) {
2244 skb_queue_tail(&card->hbpool.
2245 queue, new_hb);
2246 card->hbpool.count++;
2247 }
2248 }
2249 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2250 } else if (--card->hbpool.count < card->hbnr.min) {
2251 struct sk_buff *new_hb;
2252 if ((new_hb =
2253 dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2254 NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
2255 skb_queue_tail(&card->hbpool.queue,
2256 new_hb);
2257 card->hbpool.count++;
2258 }
2259 if (card->hbpool.count < card->hbnr.min) {
2260 if ((new_hb =
2261 dev_alloc_skb(NS_HBUFSIZE)) !=
2262 NULL) {
2263 NS_PRV_BUFTYPE(new_hb) =
2264 BUF_NONE;
2265 skb_queue_tail(&card->hbpool.
2266 queue, new_hb);
2267 card->hbpool.count++;
2268 }
2269 }
2270 }
2271
2272 iov = (struct iovec *)iovb->data;
2273
2274 if (!atm_charge(vcc, hb->truesize)) {
2275 recycle_iovec_rx_bufs(card, iov,
2276 NS_PRV_IOVCNT(iovb));
2277 if (card->hbpool.count < card->hbnr.max) {
2278 skb_queue_tail(&card->hbpool.queue, hb);
2279 card->hbpool.count++;
2280 } else
2281 dev_kfree_skb_any(hb);
2282 atomic_inc(&vcc->stats->rx_drop);
2283 } else {
2284 /* Copy the small buffer to the huge buffer */
2285 sb = (struct sk_buff *)iov->iov_base;
2286 skb_copy_from_linear_data(sb, hb->data,
2287 iov->iov_len);
2288 skb_put(hb, iov->iov_len);
2289 remaining = len - iov->iov_len;
2290 iov++;
2291 /* Free the small buffer */
2292 push_rxbufs(card, sb);
2293
2294 /* Copy all large buffers to the huge buffer and free them */
2295 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
2296 lb = (struct sk_buff *)iov->iov_base;
2297 tocopy =
2298 min_t(int, remaining, iov->iov_len);
2299 skb_copy_from_linear_data(lb,
2300 skb_tail_pointer
2301 (hb), tocopy);
2302 skb_put(hb, tocopy);
2303 iov++;
2304 remaining -= tocopy;
2305 push_rxbufs(card, lb);
2306 }
2307 #ifdef EXTRA_DEBUG
2308 if (remaining != 0 || hb->len != len)
2309 printk
2310 ("nicstar%d: Huge buffer len mismatch.\n",
2311 card->index);
2312 #endif /* EXTRA_DEBUG */
2313 ATM_SKB(hb)->vcc = vcc;
2314 __net_timestamp(hb);
2315 vcc->push(vcc, hb);
2316 atomic_inc(&vcc->stats->rx);
2317 }
2318 }
2319
2320 vc->rx_iov = NULL;
2321 recycle_iov_buf(card, iovb);
2322 }
2323
2324 }
2325
recycle_rx_buf(ns_dev * card,struct sk_buff * skb)2326 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2327 {
2328 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
2329 printk("nicstar%d: What kind of rx buffer is this?\n",
2330 card->index);
2331 dev_kfree_skb_any(skb);
2332 } else
2333 push_rxbufs(card, skb);
2334 }
2335
recycle_iovec_rx_bufs(ns_dev * card,struct iovec * iov,int count)2336 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2337 {
2338 while (count-- > 0)
2339 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2340 }
2341
recycle_iov_buf(ns_dev * card,struct sk_buff * iovb)2342 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2343 {
2344 if (card->iovpool.count < card->iovnr.max) {
2345 skb_queue_tail(&card->iovpool.queue, iovb);
2346 card->iovpool.count++;
2347 } else
2348 dev_kfree_skb_any(iovb);
2349 }
2350
dequeue_sm_buf(ns_dev * card,struct sk_buff * sb)2351 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2352 {
2353 skb_unlink(sb, &card->sbpool.queue);
2354 if (card->sbfqc < card->sbnr.init) {
2355 struct sk_buff *new_sb;
2356 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2357 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2358 skb_queue_tail(&card->sbpool.queue, new_sb);
2359 skb_reserve(new_sb, NS_AAL0_HEADER);
2360 push_rxbufs(card, new_sb);
2361 }
2362 }
2363 if (card->sbfqc < card->sbnr.init)
2364 {
2365 struct sk_buff *new_sb;
2366 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2367 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2368 skb_queue_tail(&card->sbpool.queue, new_sb);
2369 skb_reserve(new_sb, NS_AAL0_HEADER);
2370 push_rxbufs(card, new_sb);
2371 }
2372 }
2373 }
2374
dequeue_lg_buf(ns_dev * card,struct sk_buff * lb)2375 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2376 {
2377 skb_unlink(lb, &card->lbpool.queue);
2378 if (card->lbfqc < card->lbnr.init) {
2379 struct sk_buff *new_lb;
2380 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2381 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2382 skb_queue_tail(&card->lbpool.queue, new_lb);
2383 skb_reserve(new_lb, NS_SMBUFSIZE);
2384 push_rxbufs(card, new_lb);
2385 }
2386 }
2387 if (card->lbfqc < card->lbnr.init)
2388 {
2389 struct sk_buff *new_lb;
2390 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2391 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2392 skb_queue_tail(&card->lbpool.queue, new_lb);
2393 skb_reserve(new_lb, NS_SMBUFSIZE);
2394 push_rxbufs(card, new_lb);
2395 }
2396 }
2397 }
2398
ns_proc_read(struct atm_dev * dev,loff_t * pos,char * page)2399 static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2400 {
2401 u32 stat;
2402 ns_dev *card;
2403 int left;
2404
2405 left = (int)*pos;
2406 card = (ns_dev *) dev->dev_data;
2407 stat = readl(card->membase + STAT);
2408 if (!left--)
2409 return sprintf(page, "Pool count min init max \n");
2410 if (!left--)
2411 return sprintf(page, "Small %5d %5d %5d %5d \n",
2412 ns_stat_sfbqc_get(stat), card->sbnr.min,
2413 card->sbnr.init, card->sbnr.max);
2414 if (!left--)
2415 return sprintf(page, "Large %5d %5d %5d %5d \n",
2416 ns_stat_lfbqc_get(stat), card->lbnr.min,
2417 card->lbnr.init, card->lbnr.max);
2418 if (!left--)
2419 return sprintf(page, "Huge %5d %5d %5d %5d \n",
2420 card->hbpool.count, card->hbnr.min,
2421 card->hbnr.init, card->hbnr.max);
2422 if (!left--)
2423 return sprintf(page, "Iovec %5d %5d %5d %5d \n",
2424 card->iovpool.count, card->iovnr.min,
2425 card->iovnr.init, card->iovnr.max);
2426 if (!left--) {
2427 int retval;
2428 retval =
2429 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2430 card->intcnt = 0;
2431 return retval;
2432 }
2433 #if 0
2434 /* Dump 25.6 Mbps PHY registers */
2435 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2436 here just in case it's needed for debugging. */
2437 if (card->max_pcr == ATM_25_PCR && !left--) {
2438 u32 phy_regs[4];
2439 u32 i;
2440
2441 for (i = 0; i < 4; i++) {
2442 while (CMD_BUSY(card)) ;
2443 writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2444 card->membase + CMD);
2445 while (CMD_BUSY(card)) ;
2446 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2447 }
2448
2449 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2450 phy_regs[0], phy_regs[1], phy_regs[2],
2451 phy_regs[3]);
2452 }
2453 #endif /* 0 - Dump 25.6 Mbps PHY registers */
2454 #if 0
2455 /* Dump TST */
2456 if (left-- < NS_TST_NUM_ENTRIES) {
2457 if (card->tste2vc[left + 1] == NULL)
2458 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2459 else
2460 return sprintf(page, "%5d - %d %d \n", left + 1,
2461 card->tste2vc[left + 1]->tx_vcc->vpi,
2462 card->tste2vc[left + 1]->tx_vcc->vci);
2463 }
2464 #endif /* 0 */
2465 return 0;
2466 }
2467
ns_ioctl(struct atm_dev * dev,unsigned int cmd,void __user * arg)2468 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2469 {
2470 ns_dev *card;
2471 pool_levels pl;
2472 long btype;
2473 unsigned long flags;
2474
2475 card = dev->dev_data;
2476 switch (cmd) {
2477 case NS_GETPSTAT:
2478 if (get_user
2479 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2480 return -EFAULT;
2481 switch (pl.buftype) {
2482 case NS_BUFTYPE_SMALL:
2483 pl.count =
2484 ns_stat_sfbqc_get(readl(card->membase + STAT));
2485 pl.level.min = card->sbnr.min;
2486 pl.level.init = card->sbnr.init;
2487 pl.level.max = card->sbnr.max;
2488 break;
2489
2490 case NS_BUFTYPE_LARGE:
2491 pl.count =
2492 ns_stat_lfbqc_get(readl(card->membase + STAT));
2493 pl.level.min = card->lbnr.min;
2494 pl.level.init = card->lbnr.init;
2495 pl.level.max = card->lbnr.max;
2496 break;
2497
2498 case NS_BUFTYPE_HUGE:
2499 pl.count = card->hbpool.count;
2500 pl.level.min = card->hbnr.min;
2501 pl.level.init = card->hbnr.init;
2502 pl.level.max = card->hbnr.max;
2503 break;
2504
2505 case NS_BUFTYPE_IOVEC:
2506 pl.count = card->iovpool.count;
2507 pl.level.min = card->iovnr.min;
2508 pl.level.init = card->iovnr.init;
2509 pl.level.max = card->iovnr.max;
2510 break;
2511
2512 default:
2513 return -ENOIOCTLCMD;
2514
2515 }
2516 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
2517 return (sizeof(pl));
2518 else
2519 return -EFAULT;
2520
2521 case NS_SETBUFLEV:
2522 if (!capable(CAP_NET_ADMIN))
2523 return -EPERM;
2524 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
2525 return -EFAULT;
2526 if (pl.level.min >= pl.level.init
2527 || pl.level.init >= pl.level.max)
2528 return -EINVAL;
2529 if (pl.level.min == 0)
2530 return -EINVAL;
2531 switch (pl.buftype) {
2532 case NS_BUFTYPE_SMALL:
2533 if (pl.level.max > TOP_SB)
2534 return -EINVAL;
2535 card->sbnr.min = pl.level.min;
2536 card->sbnr.init = pl.level.init;
2537 card->sbnr.max = pl.level.max;
2538 break;
2539
2540 case NS_BUFTYPE_LARGE:
2541 if (pl.level.max > TOP_LB)
2542 return -EINVAL;
2543 card->lbnr.min = pl.level.min;
2544 card->lbnr.init = pl.level.init;
2545 card->lbnr.max = pl.level.max;
2546 break;
2547
2548 case NS_BUFTYPE_HUGE:
2549 if (pl.level.max > TOP_HB)
2550 return -EINVAL;
2551 card->hbnr.min = pl.level.min;
2552 card->hbnr.init = pl.level.init;
2553 card->hbnr.max = pl.level.max;
2554 break;
2555
2556 case NS_BUFTYPE_IOVEC:
2557 if (pl.level.max > TOP_IOVB)
2558 return -EINVAL;
2559 card->iovnr.min = pl.level.min;
2560 card->iovnr.init = pl.level.init;
2561 card->iovnr.max = pl.level.max;
2562 break;
2563
2564 default:
2565 return -EINVAL;
2566
2567 }
2568 return 0;
2569
2570 case NS_ADJBUFLEV:
2571 if (!capable(CAP_NET_ADMIN))
2572 return -EPERM;
2573 btype = (long)arg; /* a long is the same size as a pointer or bigger */
2574 switch (btype) {
2575 case NS_BUFTYPE_SMALL:
2576 while (card->sbfqc < card->sbnr.init) {
2577 struct sk_buff *sb;
2578
2579 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2580 if (sb == NULL)
2581 return -ENOMEM;
2582 NS_PRV_BUFTYPE(sb) = BUF_SM;
2583 skb_queue_tail(&card->sbpool.queue, sb);
2584 skb_reserve(sb, NS_AAL0_HEADER);
2585 push_rxbufs(card, sb);
2586 }
2587 break;
2588
2589 case NS_BUFTYPE_LARGE:
2590 while (card->lbfqc < card->lbnr.init) {
2591 struct sk_buff *lb;
2592
2593 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2594 if (lb == NULL)
2595 return -ENOMEM;
2596 NS_PRV_BUFTYPE(lb) = BUF_LG;
2597 skb_queue_tail(&card->lbpool.queue, lb);
2598 skb_reserve(lb, NS_SMBUFSIZE);
2599 push_rxbufs(card, lb);
2600 }
2601 break;
2602
2603 case NS_BUFTYPE_HUGE:
2604 while (card->hbpool.count > card->hbnr.init) {
2605 struct sk_buff *hb;
2606
2607 spin_lock_irqsave(&card->int_lock, flags);
2608 hb = skb_dequeue(&card->hbpool.queue);
2609 card->hbpool.count--;
2610 spin_unlock_irqrestore(&card->int_lock, flags);
2611 if (hb == NULL)
2612 printk
2613 ("nicstar%d: huge buffer count inconsistent.\n",
2614 card->index);
2615 else
2616 dev_kfree_skb_any(hb);
2617
2618 }
2619 while (card->hbpool.count < card->hbnr.init) {
2620 struct sk_buff *hb;
2621
2622 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2623 if (hb == NULL)
2624 return -ENOMEM;
2625 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2626 spin_lock_irqsave(&card->int_lock, flags);
2627 skb_queue_tail(&card->hbpool.queue, hb);
2628 card->hbpool.count++;
2629 spin_unlock_irqrestore(&card->int_lock, flags);
2630 }
2631 break;
2632
2633 case NS_BUFTYPE_IOVEC:
2634 while (card->iovpool.count > card->iovnr.init) {
2635 struct sk_buff *iovb;
2636
2637 spin_lock_irqsave(&card->int_lock, flags);
2638 iovb = skb_dequeue(&card->iovpool.queue);
2639 card->iovpool.count--;
2640 spin_unlock_irqrestore(&card->int_lock, flags);
2641 if (iovb == NULL)
2642 printk
2643 ("nicstar%d: iovec buffer count inconsistent.\n",
2644 card->index);
2645 else
2646 dev_kfree_skb_any(iovb);
2647
2648 }
2649 while (card->iovpool.count < card->iovnr.init) {
2650 struct sk_buff *iovb;
2651
2652 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2653 if (iovb == NULL)
2654 return -ENOMEM;
2655 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2656 spin_lock_irqsave(&card->int_lock, flags);
2657 skb_queue_tail(&card->iovpool.queue, iovb);
2658 card->iovpool.count++;
2659 spin_unlock_irqrestore(&card->int_lock, flags);
2660 }
2661 break;
2662
2663 default:
2664 return -EINVAL;
2665
2666 }
2667 return 0;
2668
2669 default:
2670 if (dev->phy && dev->phy->ioctl) {
2671 return dev->phy->ioctl(dev, cmd, arg);
2672 } else {
2673 printk("nicstar%d: %s == NULL \n", card->index,
2674 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2675 return -ENOIOCTLCMD;
2676 }
2677 }
2678 }
2679
2680 #ifdef EXTRA_DEBUG
which_list(ns_dev * card,struct sk_buff * skb)2681 static void which_list(ns_dev * card, struct sk_buff *skb)
2682 {
2683 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
2684 }
2685 #endif /* EXTRA_DEBUG */
2686
ns_poll(struct timer_list * unused)2687 static void ns_poll(struct timer_list *unused)
2688 {
2689 int i;
2690 ns_dev *card;
2691 unsigned long flags;
2692 u32 stat_r, stat_w;
2693
2694 PRINTK("nicstar: Entering ns_poll().\n");
2695 for (i = 0; i < num_cards; i++) {
2696 card = cards[i];
2697 if (!spin_trylock_irqsave(&card->int_lock, flags)) {
2698 /* Probably it isn't worth spinning */
2699 continue;
2700 }
2701
2702 stat_w = 0;
2703 stat_r = readl(card->membase + STAT);
2704 if (stat_r & NS_STAT_TSIF)
2705 stat_w |= NS_STAT_TSIF;
2706 if (stat_r & NS_STAT_EOPDU)
2707 stat_w |= NS_STAT_EOPDU;
2708
2709 process_tsq(card);
2710 process_rsq(card);
2711
2712 writel(stat_w, card->membase + STAT);
2713 spin_unlock_irqrestore(&card->int_lock, flags);
2714 }
2715 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
2716 PRINTK("nicstar: Leaving ns_poll().\n");
2717 }
2718
ns_phy_put(struct atm_dev * dev,unsigned char value,unsigned long addr)2719 static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2720 unsigned long addr)
2721 {
2722 ns_dev *card;
2723 unsigned long flags;
2724
2725 card = dev->dev_data;
2726 spin_lock_irqsave(&card->res_lock, flags);
2727 while (CMD_BUSY(card)) ;
2728 writel((u32) value, card->membase + DR0);
2729 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2730 card->membase + CMD);
2731 spin_unlock_irqrestore(&card->res_lock, flags);
2732 }
2733
ns_phy_get(struct atm_dev * dev,unsigned long addr)2734 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2735 {
2736 ns_dev *card;
2737 unsigned long flags;
2738 u32 data;
2739
2740 card = dev->dev_data;
2741 spin_lock_irqsave(&card->res_lock, flags);
2742 while (CMD_BUSY(card)) ;
2743 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
2744 card->membase + CMD);
2745 while (CMD_BUSY(card)) ;
2746 data = readl(card->membase + DR0) & 0x000000FF;
2747 spin_unlock_irqrestore(&card->res_lock, flags);
2748 return (unsigned char)data;
2749 }
2750
2751 module_init(nicstar_init);
2752 module_exit(nicstar_cleanup);
2753