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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * NVM Express device driver
4  * Copyright (c) 2011-2014, Intel Corporation.
5  */
6 
7 #include <linux/acpi.h>
8 #include <linux/aer.h>
9 #include <linux/async.h>
10 #include <linux/blkdev.h>
11 #include <linux/blk-mq.h>
12 #include <linux/blk-mq-pci.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/mm.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/once.h>
21 #include <linux/pci.h>
22 #include <linux/suspend.h>
23 #include <linux/t10-pi.h>
24 #include <linux/types.h>
25 #include <linux/io-64-nonatomic-lo-hi.h>
26 #include <linux/io-64-nonatomic-hi-lo.h>
27 #include <linux/sed-opal.h>
28 #include <linux/pci-p2pdma.h>
29 
30 #include "trace.h"
31 #include "nvme.h"
32 
33 #define SQ_SIZE(q)	((q)->q_depth << (q)->sqes)
34 #define CQ_SIZE(q)	((q)->q_depth * sizeof(struct nvme_completion))
35 
36 #define SGES_PER_PAGE	(PAGE_SIZE / sizeof(struct nvme_sgl_desc))
37 
38 /*
39  * These can be higher, but we need to ensure that any command doesn't
40  * require an sg allocation that needs more than a page of data.
41  */
42 #define NVME_MAX_KB_SZ	4096
43 #define NVME_MAX_SEGS	127
44 
45 static int use_threaded_interrupts;
46 module_param(use_threaded_interrupts, int, 0);
47 
48 static bool use_cmb_sqes = true;
49 module_param(use_cmb_sqes, bool, 0444);
50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
51 
52 static unsigned int max_host_mem_size_mb = 128;
53 module_param(max_host_mem_size_mb, uint, 0444);
54 MODULE_PARM_DESC(max_host_mem_size_mb,
55 	"Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
56 
57 static unsigned int sgl_threshold = SZ_32K;
58 module_param(sgl_threshold, uint, 0644);
59 MODULE_PARM_DESC(sgl_threshold,
60 		"Use SGLs when average request segment size is larger or equal to "
61 		"this size. Use 0 to disable SGLs.");
62 
63 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
64 static const struct kernel_param_ops io_queue_depth_ops = {
65 	.set = io_queue_depth_set,
66 	.get = param_get_uint,
67 };
68 
69 static unsigned int io_queue_depth = 1024;
70 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
71 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
72 
io_queue_count_set(const char * val,const struct kernel_param * kp)73 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
74 {
75 	unsigned int n;
76 	int ret;
77 
78 	ret = kstrtouint(val, 10, &n);
79 	if (ret != 0 || n > num_possible_cpus())
80 		return -EINVAL;
81 	return param_set_uint(val, kp);
82 }
83 
84 static const struct kernel_param_ops io_queue_count_ops = {
85 	.set = io_queue_count_set,
86 	.get = param_get_uint,
87 };
88 
89 static unsigned int write_queues;
90 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
91 MODULE_PARM_DESC(write_queues,
92 	"Number of queues to use for writes. If not set, reads and writes "
93 	"will share a queue set.");
94 
95 static unsigned int poll_queues;
96 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
97 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
98 
99 static bool noacpi;
100 module_param(noacpi, bool, 0444);
101 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
102 
103 struct nvme_dev;
104 struct nvme_queue;
105 
106 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
107 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
108 
109 /*
110  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
111  */
112 struct nvme_dev {
113 	struct nvme_queue *queues;
114 	struct blk_mq_tag_set tagset;
115 	struct blk_mq_tag_set admin_tagset;
116 	u32 __iomem *dbs;
117 	struct device *dev;
118 	struct dma_pool *prp_page_pool;
119 	struct dma_pool *prp_small_pool;
120 	unsigned online_queues;
121 	unsigned max_qid;
122 	unsigned io_queues[HCTX_MAX_TYPES];
123 	unsigned int num_vecs;
124 	u32 q_depth;
125 	int io_sqes;
126 	u32 db_stride;
127 	void __iomem *bar;
128 	unsigned long bar_mapped_size;
129 	struct work_struct remove_work;
130 	struct mutex shutdown_lock;
131 	bool subsystem;
132 	u64 cmb_size;
133 	bool cmb_use_sqes;
134 	u32 cmbsz;
135 	u32 cmbloc;
136 	struct nvme_ctrl ctrl;
137 	u32 last_ps;
138 
139 	mempool_t *iod_mempool;
140 
141 	/* shadow doorbell buffer support: */
142 	u32 *dbbuf_dbs;
143 	dma_addr_t dbbuf_dbs_dma_addr;
144 	u32 *dbbuf_eis;
145 	dma_addr_t dbbuf_eis_dma_addr;
146 
147 	/* host memory buffer support: */
148 	u64 host_mem_size;
149 	u32 nr_host_mem_descs;
150 	dma_addr_t host_mem_descs_dma;
151 	struct nvme_host_mem_buf_desc *host_mem_descs;
152 	void **host_mem_desc_bufs;
153 	unsigned int nr_allocated_queues;
154 	unsigned int nr_write_queues;
155 	unsigned int nr_poll_queues;
156 };
157 
io_queue_depth_set(const char * val,const struct kernel_param * kp)158 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
159 {
160 	int ret;
161 	u32 n;
162 
163 	ret = kstrtou32(val, 10, &n);
164 	if (ret != 0 || n < 2)
165 		return -EINVAL;
166 
167 	return param_set_uint(val, kp);
168 }
169 
sq_idx(unsigned int qid,u32 stride)170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171 {
172 	return qid * 2 * stride;
173 }
174 
cq_idx(unsigned int qid,u32 stride)175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176 {
177 	return (qid * 2 + 1) * stride;
178 }
179 
to_nvme_dev(struct nvme_ctrl * ctrl)180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181 {
182 	return container_of(ctrl, struct nvme_dev, ctrl);
183 }
184 
185 /*
186  * An NVM Express queue.  Each device has at least two (one for admin
187  * commands and one for I/O commands).
188  */
189 struct nvme_queue {
190 	struct nvme_dev *dev;
191 	spinlock_t sq_lock;
192 	void *sq_cmds;
193 	 /* only used for poll queues: */
194 	spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
195 	struct nvme_completion *cqes;
196 	dma_addr_t sq_dma_addr;
197 	dma_addr_t cq_dma_addr;
198 	u32 __iomem *q_db;
199 	u32 q_depth;
200 	u16 cq_vector;
201 	u16 sq_tail;
202 	u16 last_sq_tail;
203 	u16 cq_head;
204 	u16 qid;
205 	u8 cq_phase;
206 	u8 sqes;
207 	unsigned long flags;
208 #define NVMEQ_ENABLED		0
209 #define NVMEQ_SQ_CMB		1
210 #define NVMEQ_DELETE_ERROR	2
211 #define NVMEQ_POLLED		3
212 	u32 *dbbuf_sq_db;
213 	u32 *dbbuf_cq_db;
214 	u32 *dbbuf_sq_ei;
215 	u32 *dbbuf_cq_ei;
216 	struct completion delete_done;
217 };
218 
219 /*
220  * The nvme_iod describes the data in an I/O.
221  *
222  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
223  * to the actual struct scatterlist.
224  */
225 struct nvme_iod {
226 	struct nvme_request req;
227 	struct nvme_queue *nvmeq;
228 	bool use_sgl;
229 	int aborted;
230 	int npages;		/* In the PRP list. 0 means small pool in use */
231 	int nents;		/* Used in scatterlist */
232 	dma_addr_t first_dma;
233 	unsigned int dma_len;	/* length of single DMA segment mapping */
234 	dma_addr_t meta_dma;
235 	struct scatterlist *sg;
236 };
237 
nvme_dbbuf_size(struct nvme_dev * dev)238 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
239 {
240 	return dev->nr_allocated_queues * 8 * dev->db_stride;
241 }
242 
nvme_dbbuf_dma_alloc(struct nvme_dev * dev)243 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
244 {
245 	unsigned int mem_size = nvme_dbbuf_size(dev);
246 
247 	if (dev->dbbuf_dbs)
248 		return 0;
249 
250 	dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
251 					    &dev->dbbuf_dbs_dma_addr,
252 					    GFP_KERNEL);
253 	if (!dev->dbbuf_dbs)
254 		return -ENOMEM;
255 	dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
256 					    &dev->dbbuf_eis_dma_addr,
257 					    GFP_KERNEL);
258 	if (!dev->dbbuf_eis) {
259 		dma_free_coherent(dev->dev, mem_size,
260 				  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
261 		dev->dbbuf_dbs = NULL;
262 		return -ENOMEM;
263 	}
264 
265 	return 0;
266 }
267 
nvme_dbbuf_dma_free(struct nvme_dev * dev)268 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
269 {
270 	unsigned int mem_size = nvme_dbbuf_size(dev);
271 
272 	if (dev->dbbuf_dbs) {
273 		dma_free_coherent(dev->dev, mem_size,
274 				  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
275 		dev->dbbuf_dbs = NULL;
276 	}
277 	if (dev->dbbuf_eis) {
278 		dma_free_coherent(dev->dev, mem_size,
279 				  dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
280 		dev->dbbuf_eis = NULL;
281 	}
282 }
283 
nvme_dbbuf_init(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)284 static void nvme_dbbuf_init(struct nvme_dev *dev,
285 			    struct nvme_queue *nvmeq, int qid)
286 {
287 	if (!dev->dbbuf_dbs || !qid)
288 		return;
289 
290 	nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
291 	nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
292 	nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
293 	nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
294 }
295 
nvme_dbbuf_free(struct nvme_queue * nvmeq)296 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
297 {
298 	if (!nvmeq->qid)
299 		return;
300 
301 	nvmeq->dbbuf_sq_db = NULL;
302 	nvmeq->dbbuf_cq_db = NULL;
303 	nvmeq->dbbuf_sq_ei = NULL;
304 	nvmeq->dbbuf_cq_ei = NULL;
305 }
306 
nvme_dbbuf_set(struct nvme_dev * dev)307 static void nvme_dbbuf_set(struct nvme_dev *dev)
308 {
309 	struct nvme_command c;
310 	unsigned int i;
311 
312 	if (!dev->dbbuf_dbs)
313 		return;
314 
315 	memset(&c, 0, sizeof(c));
316 	c.dbbuf.opcode = nvme_admin_dbbuf;
317 	c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
318 	c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
319 
320 	if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
321 		dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
322 		/* Free memory and continue on */
323 		nvme_dbbuf_dma_free(dev);
324 
325 		for (i = 1; i <= dev->online_queues; i++)
326 			nvme_dbbuf_free(&dev->queues[i]);
327 	}
328 }
329 
nvme_dbbuf_need_event(u16 event_idx,u16 new_idx,u16 old)330 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
331 {
332 	return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
333 }
334 
335 /* Update dbbuf and return true if an MMIO is required */
nvme_dbbuf_update_and_check_event(u16 value,u32 * dbbuf_db,volatile u32 * dbbuf_ei)336 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
337 					      volatile u32 *dbbuf_ei)
338 {
339 	if (dbbuf_db) {
340 		u16 old_value;
341 
342 		/*
343 		 * Ensure that the queue is written before updating
344 		 * the doorbell in memory
345 		 */
346 		wmb();
347 
348 		old_value = *dbbuf_db;
349 		*dbbuf_db = value;
350 
351 		/*
352 		 * Ensure that the doorbell is updated before reading the event
353 		 * index from memory.  The controller needs to provide similar
354 		 * ordering to ensure the envent index is updated before reading
355 		 * the doorbell.
356 		 */
357 		mb();
358 
359 		if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
360 			return false;
361 	}
362 
363 	return true;
364 }
365 
366 /*
367  * Will slightly overestimate the number of pages needed.  This is OK
368  * as it only leads to a small amount of wasted memory for the lifetime of
369  * the I/O.
370  */
nvme_pci_npages_prp(void)371 static int nvme_pci_npages_prp(void)
372 {
373 	unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
374 				      NVME_CTRL_PAGE_SIZE);
375 	return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
376 }
377 
378 /*
379  * Calculates the number of pages needed for the SGL segments. For example a 4k
380  * page can accommodate 256 SGL descriptors.
381  */
nvme_pci_npages_sgl(void)382 static int nvme_pci_npages_sgl(void)
383 {
384 	return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
385 			PAGE_SIZE);
386 }
387 
nvme_pci_iod_alloc_size(void)388 static size_t nvme_pci_iod_alloc_size(void)
389 {
390 	size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
391 
392 	return sizeof(__le64 *) * npages +
393 		sizeof(struct scatterlist) * NVME_MAX_SEGS;
394 }
395 
nvme_admin_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)396 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
397 				unsigned int hctx_idx)
398 {
399 	struct nvme_dev *dev = data;
400 	struct nvme_queue *nvmeq = &dev->queues[0];
401 
402 	WARN_ON(hctx_idx != 0);
403 	WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
404 
405 	hctx->driver_data = nvmeq;
406 	return 0;
407 }
408 
nvme_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)409 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
410 			  unsigned int hctx_idx)
411 {
412 	struct nvme_dev *dev = data;
413 	struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
414 
415 	WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
416 	hctx->driver_data = nvmeq;
417 	return 0;
418 }
419 
nvme_init_request(struct blk_mq_tag_set * set,struct request * req,unsigned int hctx_idx,unsigned int numa_node)420 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
421 		unsigned int hctx_idx, unsigned int numa_node)
422 {
423 	struct nvme_dev *dev = set->driver_data;
424 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
425 	int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
426 	struct nvme_queue *nvmeq = &dev->queues[queue_idx];
427 
428 	BUG_ON(!nvmeq);
429 	iod->nvmeq = nvmeq;
430 
431 	nvme_req(req)->ctrl = &dev->ctrl;
432 	return 0;
433 }
434 
queue_irq_offset(struct nvme_dev * dev)435 static int queue_irq_offset(struct nvme_dev *dev)
436 {
437 	/* if we have more than 1 vec, admin queue offsets us by 1 */
438 	if (dev->num_vecs > 1)
439 		return 1;
440 
441 	return 0;
442 }
443 
nvme_pci_map_queues(struct blk_mq_tag_set * set)444 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
445 {
446 	struct nvme_dev *dev = set->driver_data;
447 	int i, qoff, offset;
448 
449 	offset = queue_irq_offset(dev);
450 	for (i = 0, qoff = 0; i < set->nr_maps; i++) {
451 		struct blk_mq_queue_map *map = &set->map[i];
452 
453 		map->nr_queues = dev->io_queues[i];
454 		if (!map->nr_queues) {
455 			BUG_ON(i == HCTX_TYPE_DEFAULT);
456 			continue;
457 		}
458 
459 		/*
460 		 * The poll queue(s) doesn't have an IRQ (and hence IRQ
461 		 * affinity), so use the regular blk-mq cpu mapping
462 		 */
463 		map->queue_offset = qoff;
464 		if (i != HCTX_TYPE_POLL && offset)
465 			blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
466 		else
467 			blk_mq_map_queues(map);
468 		qoff += map->nr_queues;
469 		offset += map->nr_queues;
470 	}
471 
472 	return 0;
473 }
474 
475 /*
476  * Write sq tail if we are asked to, or if the next command would wrap.
477  */
nvme_write_sq_db(struct nvme_queue * nvmeq,bool write_sq)478 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
479 {
480 	if (!write_sq) {
481 		u16 next_tail = nvmeq->sq_tail + 1;
482 
483 		if (next_tail == nvmeq->q_depth)
484 			next_tail = 0;
485 		if (next_tail != nvmeq->last_sq_tail)
486 			return;
487 	}
488 
489 	if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
490 			nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
491 		writel(nvmeq->sq_tail, nvmeq->q_db);
492 	nvmeq->last_sq_tail = nvmeq->sq_tail;
493 }
494 
495 /**
496  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
497  * @nvmeq: The queue to use
498  * @cmd: The command to send
499  * @write_sq: whether to write to the SQ doorbell
500  */
nvme_submit_cmd(struct nvme_queue * nvmeq,struct nvme_command * cmd,bool write_sq)501 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
502 			    bool write_sq)
503 {
504 	spin_lock(&nvmeq->sq_lock);
505 	memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
506 	       cmd, sizeof(*cmd));
507 	if (++nvmeq->sq_tail == nvmeq->q_depth)
508 		nvmeq->sq_tail = 0;
509 	nvme_write_sq_db(nvmeq, write_sq);
510 	spin_unlock(&nvmeq->sq_lock);
511 }
512 
nvme_commit_rqs(struct blk_mq_hw_ctx * hctx)513 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
514 {
515 	struct nvme_queue *nvmeq = hctx->driver_data;
516 
517 	spin_lock(&nvmeq->sq_lock);
518 	if (nvmeq->sq_tail != nvmeq->last_sq_tail)
519 		nvme_write_sq_db(nvmeq, true);
520 	spin_unlock(&nvmeq->sq_lock);
521 }
522 
nvme_pci_iod_list(struct request * req)523 static void **nvme_pci_iod_list(struct request *req)
524 {
525 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
526 	return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
527 }
528 
nvme_pci_use_sgls(struct nvme_dev * dev,struct request * req)529 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
530 {
531 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
532 	int nseg = blk_rq_nr_phys_segments(req);
533 	unsigned int avg_seg_size;
534 
535 	avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
536 
537 	if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
538 		return false;
539 	if (!iod->nvmeq->qid)
540 		return false;
541 	if (!sgl_threshold || avg_seg_size < sgl_threshold)
542 		return false;
543 	return true;
544 }
545 
nvme_free_prps(struct nvme_dev * dev,struct request * req)546 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
547 {
548 	const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
549 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
550 	dma_addr_t dma_addr = iod->first_dma;
551 	int i;
552 
553 	for (i = 0; i < iod->npages; i++) {
554 		__le64 *prp_list = nvme_pci_iod_list(req)[i];
555 		dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
556 
557 		dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
558 		dma_addr = next_dma_addr;
559 	}
560 
561 }
562 
nvme_free_sgls(struct nvme_dev * dev,struct request * req)563 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
564 {
565 	const int last_sg = SGES_PER_PAGE - 1;
566 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
567 	dma_addr_t dma_addr = iod->first_dma;
568 	int i;
569 
570 	for (i = 0; i < iod->npages; i++) {
571 		struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
572 		dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
573 
574 		dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
575 		dma_addr = next_dma_addr;
576 	}
577 
578 }
579 
nvme_unmap_sg(struct nvme_dev * dev,struct request * req)580 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
581 {
582 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
583 
584 	if (is_pci_p2pdma_page(sg_page(iod->sg)))
585 		pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
586 				    rq_dma_dir(req));
587 	else
588 		dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
589 }
590 
nvme_unmap_data(struct nvme_dev * dev,struct request * req)591 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
592 {
593 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
594 
595 	if (iod->dma_len) {
596 		dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
597 			       rq_dma_dir(req));
598 		return;
599 	}
600 
601 	WARN_ON_ONCE(!iod->nents);
602 
603 	nvme_unmap_sg(dev, req);
604 	if (iod->npages == 0)
605 		dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
606 			      iod->first_dma);
607 	else if (iod->use_sgl)
608 		nvme_free_sgls(dev, req);
609 	else
610 		nvme_free_prps(dev, req);
611 	mempool_free(iod->sg, dev->iod_mempool);
612 }
613 
nvme_print_sgl(struct scatterlist * sgl,int nents)614 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
615 {
616 	int i;
617 	struct scatterlist *sg;
618 
619 	for_each_sg(sgl, sg, nents, i) {
620 		dma_addr_t phys = sg_phys(sg);
621 		pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
622 			"dma_address:%pad dma_length:%d\n",
623 			i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
624 			sg_dma_len(sg));
625 	}
626 }
627 
nvme_pci_setup_prps(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd)628 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
629 		struct request *req, struct nvme_rw_command *cmnd)
630 {
631 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
632 	struct dma_pool *pool;
633 	int length = blk_rq_payload_bytes(req);
634 	struct scatterlist *sg = iod->sg;
635 	int dma_len = sg_dma_len(sg);
636 	u64 dma_addr = sg_dma_address(sg);
637 	int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
638 	__le64 *prp_list;
639 	void **list = nvme_pci_iod_list(req);
640 	dma_addr_t prp_dma;
641 	int nprps, i;
642 
643 	length -= (NVME_CTRL_PAGE_SIZE - offset);
644 	if (length <= 0) {
645 		iod->first_dma = 0;
646 		goto done;
647 	}
648 
649 	dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
650 	if (dma_len) {
651 		dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
652 	} else {
653 		sg = sg_next(sg);
654 		dma_addr = sg_dma_address(sg);
655 		dma_len = sg_dma_len(sg);
656 	}
657 
658 	if (length <= NVME_CTRL_PAGE_SIZE) {
659 		iod->first_dma = dma_addr;
660 		goto done;
661 	}
662 
663 	nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
664 	if (nprps <= (256 / 8)) {
665 		pool = dev->prp_small_pool;
666 		iod->npages = 0;
667 	} else {
668 		pool = dev->prp_page_pool;
669 		iod->npages = 1;
670 	}
671 
672 	prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
673 	if (!prp_list) {
674 		iod->first_dma = dma_addr;
675 		iod->npages = -1;
676 		return BLK_STS_RESOURCE;
677 	}
678 	list[0] = prp_list;
679 	iod->first_dma = prp_dma;
680 	i = 0;
681 	for (;;) {
682 		if (i == NVME_CTRL_PAGE_SIZE >> 3) {
683 			__le64 *old_prp_list = prp_list;
684 			prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
685 			if (!prp_list)
686 				goto free_prps;
687 			list[iod->npages++] = prp_list;
688 			prp_list[0] = old_prp_list[i - 1];
689 			old_prp_list[i - 1] = cpu_to_le64(prp_dma);
690 			i = 1;
691 		}
692 		prp_list[i++] = cpu_to_le64(dma_addr);
693 		dma_len -= NVME_CTRL_PAGE_SIZE;
694 		dma_addr += NVME_CTRL_PAGE_SIZE;
695 		length -= NVME_CTRL_PAGE_SIZE;
696 		if (length <= 0)
697 			break;
698 		if (dma_len > 0)
699 			continue;
700 		if (unlikely(dma_len < 0))
701 			goto bad_sgl;
702 		sg = sg_next(sg);
703 		dma_addr = sg_dma_address(sg);
704 		dma_len = sg_dma_len(sg);
705 	}
706 done:
707 	cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
708 	cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
709 	return BLK_STS_OK;
710 free_prps:
711 	nvme_free_prps(dev, req);
712 	return BLK_STS_RESOURCE;
713 bad_sgl:
714 	WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
715 			"Invalid SGL for payload:%d nents:%d\n",
716 			blk_rq_payload_bytes(req), iod->nents);
717 	return BLK_STS_IOERR;
718 }
719 
nvme_pci_sgl_set_data(struct nvme_sgl_desc * sge,struct scatterlist * sg)720 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
721 		struct scatterlist *sg)
722 {
723 	sge->addr = cpu_to_le64(sg_dma_address(sg));
724 	sge->length = cpu_to_le32(sg_dma_len(sg));
725 	sge->type = NVME_SGL_FMT_DATA_DESC << 4;
726 }
727 
nvme_pci_sgl_set_seg(struct nvme_sgl_desc * sge,dma_addr_t dma_addr,int entries)728 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
729 		dma_addr_t dma_addr, int entries)
730 {
731 	sge->addr = cpu_to_le64(dma_addr);
732 	if (entries < SGES_PER_PAGE) {
733 		sge->length = cpu_to_le32(entries * sizeof(*sge));
734 		sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
735 	} else {
736 		sge->length = cpu_to_le32(PAGE_SIZE);
737 		sge->type = NVME_SGL_FMT_SEG_DESC << 4;
738 	}
739 }
740 
nvme_pci_setup_sgls(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmd,int entries)741 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
742 		struct request *req, struct nvme_rw_command *cmd, int entries)
743 {
744 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
745 	struct dma_pool *pool;
746 	struct nvme_sgl_desc *sg_list;
747 	struct scatterlist *sg = iod->sg;
748 	dma_addr_t sgl_dma;
749 	int i = 0;
750 
751 	/* setting the transfer type as SGL */
752 	cmd->flags = NVME_CMD_SGL_METABUF;
753 
754 	if (entries == 1) {
755 		nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
756 		return BLK_STS_OK;
757 	}
758 
759 	if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
760 		pool = dev->prp_small_pool;
761 		iod->npages = 0;
762 	} else {
763 		pool = dev->prp_page_pool;
764 		iod->npages = 1;
765 	}
766 
767 	sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
768 	if (!sg_list) {
769 		iod->npages = -1;
770 		return BLK_STS_RESOURCE;
771 	}
772 
773 	nvme_pci_iod_list(req)[0] = sg_list;
774 	iod->first_dma = sgl_dma;
775 
776 	nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
777 
778 	do {
779 		if (i == SGES_PER_PAGE) {
780 			struct nvme_sgl_desc *old_sg_desc = sg_list;
781 			struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
782 
783 			sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
784 			if (!sg_list)
785 				goto free_sgls;
786 
787 			i = 0;
788 			nvme_pci_iod_list(req)[iod->npages++] = sg_list;
789 			sg_list[i++] = *link;
790 			nvme_pci_sgl_set_seg(link, sgl_dma, entries);
791 		}
792 
793 		nvme_pci_sgl_set_data(&sg_list[i++], sg);
794 		sg = sg_next(sg);
795 	} while (--entries > 0);
796 
797 	return BLK_STS_OK;
798 free_sgls:
799 	nvme_free_sgls(dev, req);
800 	return BLK_STS_RESOURCE;
801 }
802 
nvme_setup_prp_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)803 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
804 		struct request *req, struct nvme_rw_command *cmnd,
805 		struct bio_vec *bv)
806 {
807 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
808 	unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
809 	unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
810 
811 	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
812 	if (dma_mapping_error(dev->dev, iod->first_dma))
813 		return BLK_STS_RESOURCE;
814 	iod->dma_len = bv->bv_len;
815 
816 	cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
817 	if (bv->bv_len > first_prp_len)
818 		cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
819 	return BLK_STS_OK;
820 }
821 
nvme_setup_sgl_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)822 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
823 		struct request *req, struct nvme_rw_command *cmnd,
824 		struct bio_vec *bv)
825 {
826 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
827 
828 	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
829 	if (dma_mapping_error(dev->dev, iod->first_dma))
830 		return BLK_STS_RESOURCE;
831 	iod->dma_len = bv->bv_len;
832 
833 	cmnd->flags = NVME_CMD_SGL_METABUF;
834 	cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
835 	cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
836 	cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
837 	return BLK_STS_OK;
838 }
839 
nvme_map_data(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)840 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
841 		struct nvme_command *cmnd)
842 {
843 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
844 	blk_status_t ret = BLK_STS_RESOURCE;
845 	int nr_mapped;
846 
847 	if (blk_rq_nr_phys_segments(req) == 1) {
848 		struct bio_vec bv = req_bvec(req);
849 
850 		if (!is_pci_p2pdma_page(bv.bv_page)) {
851 			if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
852 				return nvme_setup_prp_simple(dev, req,
853 							     &cmnd->rw, &bv);
854 
855 			if (iod->nvmeq->qid && sgl_threshold &&
856 			    dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
857 				return nvme_setup_sgl_simple(dev, req,
858 							     &cmnd->rw, &bv);
859 		}
860 	}
861 
862 	iod->dma_len = 0;
863 	iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
864 	if (!iod->sg)
865 		return BLK_STS_RESOURCE;
866 	sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
867 	iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
868 	if (!iod->nents)
869 		goto out_free_sg;
870 
871 	if (is_pci_p2pdma_page(sg_page(iod->sg)))
872 		nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
873 				iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
874 	else
875 		nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
876 					     rq_dma_dir(req), DMA_ATTR_NO_WARN);
877 	if (!nr_mapped)
878 		goto out_free_sg;
879 
880 	iod->use_sgl = nvme_pci_use_sgls(dev, req);
881 	if (iod->use_sgl)
882 		ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
883 	else
884 		ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
885 	if (ret != BLK_STS_OK)
886 		goto out_unmap_sg;
887 	return BLK_STS_OK;
888 
889 out_unmap_sg:
890 	nvme_unmap_sg(dev, req);
891 out_free_sg:
892 	mempool_free(iod->sg, dev->iod_mempool);
893 	return ret;
894 }
895 
nvme_map_metadata(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)896 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
897 		struct nvme_command *cmnd)
898 {
899 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
900 
901 	iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
902 			rq_dma_dir(req), 0);
903 	if (dma_mapping_error(dev->dev, iod->meta_dma))
904 		return BLK_STS_IOERR;
905 	cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
906 	return BLK_STS_OK;
907 }
908 
909 /*
910  * NOTE: ns is NULL when called on the admin queue.
911  */
nvme_queue_rq(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * bd)912 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
913 			 const struct blk_mq_queue_data *bd)
914 {
915 	struct nvme_ns *ns = hctx->queue->queuedata;
916 	struct nvme_queue *nvmeq = hctx->driver_data;
917 	struct nvme_dev *dev = nvmeq->dev;
918 	struct request *req = bd->rq;
919 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
920 	struct nvme_command cmnd;
921 	blk_status_t ret;
922 
923 	iod->aborted = 0;
924 	iod->npages = -1;
925 	iod->nents = 0;
926 
927 	/*
928 	 * We should not need to do this, but we're still using this to
929 	 * ensure we can drain requests on a dying queue.
930 	 */
931 	if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
932 		return BLK_STS_IOERR;
933 
934 	ret = nvme_setup_cmd(ns, req, &cmnd);
935 	if (ret)
936 		return ret;
937 
938 	if (blk_rq_nr_phys_segments(req)) {
939 		ret = nvme_map_data(dev, req, &cmnd);
940 		if (ret)
941 			goto out_free_cmd;
942 	}
943 
944 	if (blk_integrity_rq(req)) {
945 		ret = nvme_map_metadata(dev, req, &cmnd);
946 		if (ret)
947 			goto out_unmap_data;
948 	}
949 
950 	blk_mq_start_request(req);
951 	nvme_submit_cmd(nvmeq, &cmnd, bd->last);
952 	return BLK_STS_OK;
953 out_unmap_data:
954 	nvme_unmap_data(dev, req);
955 out_free_cmd:
956 	nvme_cleanup_cmd(req);
957 	return ret;
958 }
959 
nvme_pci_complete_rq(struct request * req)960 static void nvme_pci_complete_rq(struct request *req)
961 {
962 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
963 	struct nvme_dev *dev = iod->nvmeq->dev;
964 
965 	if (blk_integrity_rq(req))
966 		dma_unmap_page(dev->dev, iod->meta_dma,
967 			       rq_integrity_vec(req)->bv_len, rq_data_dir(req));
968 	if (blk_rq_nr_phys_segments(req))
969 		nvme_unmap_data(dev, req);
970 	nvme_complete_rq(req);
971 }
972 
973 /* We read the CQE phase first to check if the rest of the entry is valid */
nvme_cqe_pending(struct nvme_queue * nvmeq)974 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
975 {
976 	struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
977 
978 	return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
979 }
980 
nvme_ring_cq_doorbell(struct nvme_queue * nvmeq)981 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
982 {
983 	u16 head = nvmeq->cq_head;
984 
985 	if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
986 					      nvmeq->dbbuf_cq_ei))
987 		writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
988 }
989 
nvme_queue_tagset(struct nvme_queue * nvmeq)990 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
991 {
992 	if (!nvmeq->qid)
993 		return nvmeq->dev->admin_tagset.tags[0];
994 	return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
995 }
996 
nvme_handle_cqe(struct nvme_queue * nvmeq,u16 idx)997 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
998 {
999 	struct nvme_completion *cqe = &nvmeq->cqes[idx];
1000 	__u16 command_id = READ_ONCE(cqe->command_id);
1001 	struct request *req;
1002 
1003 	/*
1004 	 * AEN requests are special as they don't time out and can
1005 	 * survive any kind of queue freeze and often don't respond to
1006 	 * aborts.  We don't even bother to allocate a struct request
1007 	 * for them but rather special case them here.
1008 	 */
1009 	if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1010 		nvme_complete_async_event(&nvmeq->dev->ctrl,
1011 				cqe->status, &cqe->result);
1012 		return;
1013 	}
1014 
1015 	req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1016 	if (unlikely(!req)) {
1017 		dev_warn(nvmeq->dev->ctrl.device,
1018 			"invalid id %d completed on queue %d\n",
1019 			command_id, le16_to_cpu(cqe->sq_id));
1020 		return;
1021 	}
1022 
1023 	trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1024 	if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1025 		nvme_pci_complete_rq(req);
1026 }
1027 
nvme_update_cq_head(struct nvme_queue * nvmeq)1028 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1029 {
1030 	u32 tmp = nvmeq->cq_head + 1;
1031 
1032 	if (tmp == nvmeq->q_depth) {
1033 		nvmeq->cq_head = 0;
1034 		nvmeq->cq_phase ^= 1;
1035 	} else {
1036 		nvmeq->cq_head = tmp;
1037 	}
1038 }
1039 
nvme_process_cq(struct nvme_queue * nvmeq)1040 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1041 {
1042 	int found = 0;
1043 
1044 	while (nvme_cqe_pending(nvmeq)) {
1045 		found++;
1046 		/*
1047 		 * load-load control dependency between phase and the rest of
1048 		 * the cqe requires a full read memory barrier
1049 		 */
1050 		dma_rmb();
1051 		nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1052 		nvme_update_cq_head(nvmeq);
1053 	}
1054 
1055 	if (found)
1056 		nvme_ring_cq_doorbell(nvmeq);
1057 	return found;
1058 }
1059 
nvme_irq(int irq,void * data)1060 static irqreturn_t nvme_irq(int irq, void *data)
1061 {
1062 	struct nvme_queue *nvmeq = data;
1063 	irqreturn_t ret = IRQ_NONE;
1064 
1065 	/*
1066 	 * The rmb/wmb pair ensures we see all updates from a previous run of
1067 	 * the irq handler, even if that was on another CPU.
1068 	 */
1069 	rmb();
1070 	if (nvme_process_cq(nvmeq))
1071 		ret = IRQ_HANDLED;
1072 	wmb();
1073 
1074 	return ret;
1075 }
1076 
nvme_irq_check(int irq,void * data)1077 static irqreturn_t nvme_irq_check(int irq, void *data)
1078 {
1079 	struct nvme_queue *nvmeq = data;
1080 
1081 	if (nvme_cqe_pending(nvmeq))
1082 		return IRQ_WAKE_THREAD;
1083 	return IRQ_NONE;
1084 }
1085 
1086 /*
1087  * Poll for completions for any interrupt driven queue
1088  * Can be called from any context.
1089  */
nvme_poll_irqdisable(struct nvme_queue * nvmeq)1090 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1091 {
1092 	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1093 
1094 	WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1095 
1096 	disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1097 	nvme_process_cq(nvmeq);
1098 	enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1099 }
1100 
nvme_poll(struct blk_mq_hw_ctx * hctx)1101 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1102 {
1103 	struct nvme_queue *nvmeq = hctx->driver_data;
1104 	bool found;
1105 
1106 	if (!nvme_cqe_pending(nvmeq))
1107 		return 0;
1108 
1109 	spin_lock(&nvmeq->cq_poll_lock);
1110 	found = nvme_process_cq(nvmeq);
1111 	spin_unlock(&nvmeq->cq_poll_lock);
1112 
1113 	return found;
1114 }
1115 
nvme_pci_submit_async_event(struct nvme_ctrl * ctrl)1116 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1117 {
1118 	struct nvme_dev *dev = to_nvme_dev(ctrl);
1119 	struct nvme_queue *nvmeq = &dev->queues[0];
1120 	struct nvme_command c;
1121 
1122 	memset(&c, 0, sizeof(c));
1123 	c.common.opcode = nvme_admin_async_event;
1124 	c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1125 	nvme_submit_cmd(nvmeq, &c, true);
1126 }
1127 
adapter_delete_queue(struct nvme_dev * dev,u8 opcode,u16 id)1128 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1129 {
1130 	struct nvme_command c;
1131 
1132 	memset(&c, 0, sizeof(c));
1133 	c.delete_queue.opcode = opcode;
1134 	c.delete_queue.qid = cpu_to_le16(id);
1135 
1136 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1137 }
1138 
adapter_alloc_cq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq,s16 vector)1139 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1140 		struct nvme_queue *nvmeq, s16 vector)
1141 {
1142 	struct nvme_command c;
1143 	int flags = NVME_QUEUE_PHYS_CONTIG;
1144 
1145 	if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1146 		flags |= NVME_CQ_IRQ_ENABLED;
1147 
1148 	/*
1149 	 * Note: we (ab)use the fact that the prp fields survive if no data
1150 	 * is attached to the request.
1151 	 */
1152 	memset(&c, 0, sizeof(c));
1153 	c.create_cq.opcode = nvme_admin_create_cq;
1154 	c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1155 	c.create_cq.cqid = cpu_to_le16(qid);
1156 	c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1157 	c.create_cq.cq_flags = cpu_to_le16(flags);
1158 	c.create_cq.irq_vector = cpu_to_le16(vector);
1159 
1160 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1161 }
1162 
adapter_alloc_sq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq)1163 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1164 						struct nvme_queue *nvmeq)
1165 {
1166 	struct nvme_ctrl *ctrl = &dev->ctrl;
1167 	struct nvme_command c;
1168 	int flags = NVME_QUEUE_PHYS_CONTIG;
1169 
1170 	/*
1171 	 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1172 	 * set. Since URGENT priority is zeroes, it makes all queues
1173 	 * URGENT.
1174 	 */
1175 	if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1176 		flags |= NVME_SQ_PRIO_MEDIUM;
1177 
1178 	/*
1179 	 * Note: we (ab)use the fact that the prp fields survive if no data
1180 	 * is attached to the request.
1181 	 */
1182 	memset(&c, 0, sizeof(c));
1183 	c.create_sq.opcode = nvme_admin_create_sq;
1184 	c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1185 	c.create_sq.sqid = cpu_to_le16(qid);
1186 	c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1187 	c.create_sq.sq_flags = cpu_to_le16(flags);
1188 	c.create_sq.cqid = cpu_to_le16(qid);
1189 
1190 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1191 }
1192 
adapter_delete_cq(struct nvme_dev * dev,u16 cqid)1193 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1194 {
1195 	return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1196 }
1197 
adapter_delete_sq(struct nvme_dev * dev,u16 sqid)1198 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1199 {
1200 	return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1201 }
1202 
abort_endio(struct request * req,blk_status_t error)1203 static void abort_endio(struct request *req, blk_status_t error)
1204 {
1205 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1206 	struct nvme_queue *nvmeq = iod->nvmeq;
1207 
1208 	dev_warn(nvmeq->dev->ctrl.device,
1209 		 "Abort status: 0x%x", nvme_req(req)->status);
1210 	atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1211 	blk_mq_free_request(req);
1212 }
1213 
nvme_should_reset(struct nvme_dev * dev,u32 csts)1214 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1215 {
1216 	/* If true, indicates loss of adapter communication, possibly by a
1217 	 * NVMe Subsystem reset.
1218 	 */
1219 	bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1220 
1221 	/* If there is a reset/reinit ongoing, we shouldn't reset again. */
1222 	switch (dev->ctrl.state) {
1223 	case NVME_CTRL_RESETTING:
1224 	case NVME_CTRL_CONNECTING:
1225 		return false;
1226 	default:
1227 		break;
1228 	}
1229 
1230 	/* We shouldn't reset unless the controller is on fatal error state
1231 	 * _or_ if we lost the communication with it.
1232 	 */
1233 	if (!(csts & NVME_CSTS_CFS) && !nssro)
1234 		return false;
1235 
1236 	return true;
1237 }
1238 
nvme_warn_reset(struct nvme_dev * dev,u32 csts)1239 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1240 {
1241 	/* Read a config register to help see what died. */
1242 	u16 pci_status;
1243 	int result;
1244 
1245 	result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1246 				      &pci_status);
1247 	if (result == PCIBIOS_SUCCESSFUL)
1248 		dev_warn(dev->ctrl.device,
1249 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1250 			 csts, pci_status);
1251 	else
1252 		dev_warn(dev->ctrl.device,
1253 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1254 			 csts, result);
1255 }
1256 
nvme_timeout(struct request * req,bool reserved)1257 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1258 {
1259 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1260 	struct nvme_queue *nvmeq = iod->nvmeq;
1261 	struct nvme_dev *dev = nvmeq->dev;
1262 	struct request *abort_req;
1263 	struct nvme_command cmd;
1264 	u32 csts = readl(dev->bar + NVME_REG_CSTS);
1265 
1266 	/* If PCI error recovery process is happening, we cannot reset or
1267 	 * the recovery mechanism will surely fail.
1268 	 */
1269 	mb();
1270 	if (pci_channel_offline(to_pci_dev(dev->dev)))
1271 		return BLK_EH_RESET_TIMER;
1272 
1273 	/*
1274 	 * Reset immediately if the controller is failed
1275 	 */
1276 	if (nvme_should_reset(dev, csts)) {
1277 		nvme_warn_reset(dev, csts);
1278 		nvme_dev_disable(dev, false);
1279 		nvme_reset_ctrl(&dev->ctrl);
1280 		return BLK_EH_DONE;
1281 	}
1282 
1283 	/*
1284 	 * Did we miss an interrupt?
1285 	 */
1286 	if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1287 		nvme_poll(req->mq_hctx);
1288 	else
1289 		nvme_poll_irqdisable(nvmeq);
1290 
1291 	if (blk_mq_request_completed(req)) {
1292 		dev_warn(dev->ctrl.device,
1293 			 "I/O %d QID %d timeout, completion polled\n",
1294 			 req->tag, nvmeq->qid);
1295 		return BLK_EH_DONE;
1296 	}
1297 
1298 	/*
1299 	 * Shutdown immediately if controller times out while starting. The
1300 	 * reset work will see the pci device disabled when it gets the forced
1301 	 * cancellation error. All outstanding requests are completed on
1302 	 * shutdown, so we return BLK_EH_DONE.
1303 	 */
1304 	switch (dev->ctrl.state) {
1305 	case NVME_CTRL_CONNECTING:
1306 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1307 		fallthrough;
1308 	case NVME_CTRL_DELETING:
1309 		dev_warn_ratelimited(dev->ctrl.device,
1310 			 "I/O %d QID %d timeout, disable controller\n",
1311 			 req->tag, nvmeq->qid);
1312 		nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1313 		nvme_dev_disable(dev, true);
1314 		return BLK_EH_DONE;
1315 	case NVME_CTRL_RESETTING:
1316 		return BLK_EH_RESET_TIMER;
1317 	default:
1318 		break;
1319 	}
1320 
1321 	/*
1322 	 * Shutdown the controller immediately and schedule a reset if the
1323 	 * command was already aborted once before and still hasn't been
1324 	 * returned to the driver, or if this is the admin queue.
1325 	 */
1326 	if (!nvmeq->qid || iod->aborted) {
1327 		dev_warn(dev->ctrl.device,
1328 			 "I/O %d QID %d timeout, reset controller\n",
1329 			 req->tag, nvmeq->qid);
1330 		nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1331 		nvme_dev_disable(dev, false);
1332 		nvme_reset_ctrl(&dev->ctrl);
1333 
1334 		return BLK_EH_DONE;
1335 	}
1336 
1337 	if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1338 		atomic_inc(&dev->ctrl.abort_limit);
1339 		return BLK_EH_RESET_TIMER;
1340 	}
1341 	iod->aborted = 1;
1342 
1343 	memset(&cmd, 0, sizeof(cmd));
1344 	cmd.abort.opcode = nvme_admin_abort_cmd;
1345 	cmd.abort.cid = nvme_cid(req);
1346 	cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1347 
1348 	dev_warn(nvmeq->dev->ctrl.device,
1349 		"I/O %d QID %d timeout, aborting\n",
1350 		 req->tag, nvmeq->qid);
1351 
1352 	abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1353 			BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1354 	if (IS_ERR(abort_req)) {
1355 		atomic_inc(&dev->ctrl.abort_limit);
1356 		return BLK_EH_RESET_TIMER;
1357 	}
1358 
1359 	abort_req->timeout = ADMIN_TIMEOUT;
1360 	abort_req->end_io_data = NULL;
1361 	blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1362 
1363 	/*
1364 	 * The aborted req will be completed on receiving the abort req.
1365 	 * We enable the timer again. If hit twice, it'll cause a device reset,
1366 	 * as the device then is in a faulty state.
1367 	 */
1368 	return BLK_EH_RESET_TIMER;
1369 }
1370 
nvme_free_queue(struct nvme_queue * nvmeq)1371 static void nvme_free_queue(struct nvme_queue *nvmeq)
1372 {
1373 	dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1374 				(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1375 	if (!nvmeq->sq_cmds)
1376 		return;
1377 
1378 	if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1379 		pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1380 				nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1381 	} else {
1382 		dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1383 				nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1384 	}
1385 }
1386 
nvme_free_queues(struct nvme_dev * dev,int lowest)1387 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1388 {
1389 	int i;
1390 
1391 	for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1392 		dev->ctrl.queue_count--;
1393 		nvme_free_queue(&dev->queues[i]);
1394 	}
1395 }
1396 
1397 /**
1398  * nvme_suspend_queue - put queue into suspended state
1399  * @nvmeq: queue to suspend
1400  */
nvme_suspend_queue(struct nvme_queue * nvmeq)1401 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1402 {
1403 	if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1404 		return 1;
1405 
1406 	/* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1407 	mb();
1408 
1409 	nvmeq->dev->online_queues--;
1410 	if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1411 		nvme_stop_admin_queue(&nvmeq->dev->ctrl);
1412 	if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1413 		pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1414 	return 0;
1415 }
1416 
nvme_suspend_io_queues(struct nvme_dev * dev)1417 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1418 {
1419 	int i;
1420 
1421 	for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1422 		nvme_suspend_queue(&dev->queues[i]);
1423 }
1424 
nvme_disable_admin_queue(struct nvme_dev * dev,bool shutdown)1425 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1426 {
1427 	struct nvme_queue *nvmeq = &dev->queues[0];
1428 
1429 	if (shutdown)
1430 		nvme_shutdown_ctrl(&dev->ctrl);
1431 	else
1432 		nvme_disable_ctrl(&dev->ctrl);
1433 
1434 	nvme_poll_irqdisable(nvmeq);
1435 }
1436 
1437 /*
1438  * Called only on a device that has been disabled and after all other threads
1439  * that can check this device's completion queues have synced, except
1440  * nvme_poll(). This is the last chance for the driver to see a natural
1441  * completion before nvme_cancel_request() terminates all incomplete requests.
1442  */
nvme_reap_pending_cqes(struct nvme_dev * dev)1443 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1444 {
1445 	int i;
1446 
1447 	for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1448 		spin_lock(&dev->queues[i].cq_poll_lock);
1449 		nvme_process_cq(&dev->queues[i]);
1450 		spin_unlock(&dev->queues[i].cq_poll_lock);
1451 	}
1452 }
1453 
nvme_cmb_qdepth(struct nvme_dev * dev,int nr_io_queues,int entry_size)1454 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1455 				int entry_size)
1456 {
1457 	int q_depth = dev->q_depth;
1458 	unsigned q_size_aligned = roundup(q_depth * entry_size,
1459 					  NVME_CTRL_PAGE_SIZE);
1460 
1461 	if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1462 		u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1463 
1464 		mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1465 		q_depth = div_u64(mem_per_q, entry_size);
1466 
1467 		/*
1468 		 * Ensure the reduced q_depth is above some threshold where it
1469 		 * would be better to map queues in system memory with the
1470 		 * original depth
1471 		 */
1472 		if (q_depth < 64)
1473 			return -ENOMEM;
1474 	}
1475 
1476 	return q_depth;
1477 }
1478 
nvme_alloc_sq_cmds(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)1479 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1480 				int qid)
1481 {
1482 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1483 
1484 	if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1485 		nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1486 		if (nvmeq->sq_cmds) {
1487 			nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1488 							nvmeq->sq_cmds);
1489 			if (nvmeq->sq_dma_addr) {
1490 				set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1491 				return 0;
1492 			}
1493 
1494 			pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1495 		}
1496 	}
1497 
1498 	nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1499 				&nvmeq->sq_dma_addr, GFP_KERNEL);
1500 	if (!nvmeq->sq_cmds)
1501 		return -ENOMEM;
1502 	return 0;
1503 }
1504 
nvme_alloc_queue(struct nvme_dev * dev,int qid,int depth)1505 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1506 {
1507 	struct nvme_queue *nvmeq = &dev->queues[qid];
1508 
1509 	if (dev->ctrl.queue_count > qid)
1510 		return 0;
1511 
1512 	nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1513 	nvmeq->q_depth = depth;
1514 	nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1515 					 &nvmeq->cq_dma_addr, GFP_KERNEL);
1516 	if (!nvmeq->cqes)
1517 		goto free_nvmeq;
1518 
1519 	if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1520 		goto free_cqdma;
1521 
1522 	nvmeq->dev = dev;
1523 	spin_lock_init(&nvmeq->sq_lock);
1524 	spin_lock_init(&nvmeq->cq_poll_lock);
1525 	nvmeq->cq_head = 0;
1526 	nvmeq->cq_phase = 1;
1527 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1528 	nvmeq->qid = qid;
1529 	dev->ctrl.queue_count++;
1530 
1531 	return 0;
1532 
1533  free_cqdma:
1534 	dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1535 			  nvmeq->cq_dma_addr);
1536  free_nvmeq:
1537 	return -ENOMEM;
1538 }
1539 
queue_request_irq(struct nvme_queue * nvmeq)1540 static int queue_request_irq(struct nvme_queue *nvmeq)
1541 {
1542 	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1543 	int nr = nvmeq->dev->ctrl.instance;
1544 
1545 	if (use_threaded_interrupts) {
1546 		return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1547 				nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1548 	} else {
1549 		return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1550 				NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1551 	}
1552 }
1553 
nvme_init_queue(struct nvme_queue * nvmeq,u16 qid)1554 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1555 {
1556 	struct nvme_dev *dev = nvmeq->dev;
1557 
1558 	nvmeq->sq_tail = 0;
1559 	nvmeq->last_sq_tail = 0;
1560 	nvmeq->cq_head = 0;
1561 	nvmeq->cq_phase = 1;
1562 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1563 	memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1564 	nvme_dbbuf_init(dev, nvmeq, qid);
1565 	dev->online_queues++;
1566 	wmb(); /* ensure the first interrupt sees the initialization */
1567 }
1568 
nvme_create_queue(struct nvme_queue * nvmeq,int qid,bool polled)1569 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1570 {
1571 	struct nvme_dev *dev = nvmeq->dev;
1572 	int result;
1573 	u16 vector = 0;
1574 
1575 	clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1576 
1577 	/*
1578 	 * A queue's vector matches the queue identifier unless the controller
1579 	 * has only one vector available.
1580 	 */
1581 	if (!polled)
1582 		vector = dev->num_vecs == 1 ? 0 : qid;
1583 	else
1584 		set_bit(NVMEQ_POLLED, &nvmeq->flags);
1585 
1586 	result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1587 	if (result)
1588 		return result;
1589 
1590 	result = adapter_alloc_sq(dev, qid, nvmeq);
1591 	if (result < 0)
1592 		return result;
1593 	if (result)
1594 		goto release_cq;
1595 
1596 	nvmeq->cq_vector = vector;
1597 	nvme_init_queue(nvmeq, qid);
1598 
1599 	if (!polled) {
1600 		result = queue_request_irq(nvmeq);
1601 		if (result < 0)
1602 			goto release_sq;
1603 	}
1604 
1605 	set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1606 	return result;
1607 
1608 release_sq:
1609 	dev->online_queues--;
1610 	adapter_delete_sq(dev, qid);
1611 release_cq:
1612 	adapter_delete_cq(dev, qid);
1613 	return result;
1614 }
1615 
1616 static const struct blk_mq_ops nvme_mq_admin_ops = {
1617 	.queue_rq	= nvme_queue_rq,
1618 	.complete	= nvme_pci_complete_rq,
1619 	.init_hctx	= nvme_admin_init_hctx,
1620 	.init_request	= nvme_init_request,
1621 	.timeout	= nvme_timeout,
1622 };
1623 
1624 static const struct blk_mq_ops nvme_mq_ops = {
1625 	.queue_rq	= nvme_queue_rq,
1626 	.complete	= nvme_pci_complete_rq,
1627 	.commit_rqs	= nvme_commit_rqs,
1628 	.init_hctx	= nvme_init_hctx,
1629 	.init_request	= nvme_init_request,
1630 	.map_queues	= nvme_pci_map_queues,
1631 	.timeout	= nvme_timeout,
1632 	.poll		= nvme_poll,
1633 };
1634 
nvme_dev_remove_admin(struct nvme_dev * dev)1635 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1636 {
1637 	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1638 		/*
1639 		 * If the controller was reset during removal, it's possible
1640 		 * user requests may be waiting on a stopped queue. Start the
1641 		 * queue to flush these to completion.
1642 		 */
1643 		nvme_start_admin_queue(&dev->ctrl);
1644 		blk_cleanup_queue(dev->ctrl.admin_q);
1645 		blk_mq_free_tag_set(&dev->admin_tagset);
1646 	}
1647 }
1648 
nvme_alloc_admin_tags(struct nvme_dev * dev)1649 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1650 {
1651 	if (!dev->ctrl.admin_q) {
1652 		dev->admin_tagset.ops = &nvme_mq_admin_ops;
1653 		dev->admin_tagset.nr_hw_queues = 1;
1654 
1655 		dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1656 		dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1657 		dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1658 		dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1659 		dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1660 		dev->admin_tagset.driver_data = dev;
1661 
1662 		if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1663 			return -ENOMEM;
1664 		dev->ctrl.admin_tagset = &dev->admin_tagset;
1665 
1666 		dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1667 		if (IS_ERR(dev->ctrl.admin_q)) {
1668 			blk_mq_free_tag_set(&dev->admin_tagset);
1669 			return -ENOMEM;
1670 		}
1671 		if (!blk_get_queue(dev->ctrl.admin_q)) {
1672 			nvme_dev_remove_admin(dev);
1673 			dev->ctrl.admin_q = NULL;
1674 			return -ENODEV;
1675 		}
1676 	} else
1677 		nvme_start_admin_queue(&dev->ctrl);
1678 
1679 	return 0;
1680 }
1681 
db_bar_size(struct nvme_dev * dev,unsigned nr_io_queues)1682 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1683 {
1684 	return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1685 }
1686 
nvme_remap_bar(struct nvme_dev * dev,unsigned long size)1687 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1688 {
1689 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1690 
1691 	if (size <= dev->bar_mapped_size)
1692 		return 0;
1693 	if (size > pci_resource_len(pdev, 0))
1694 		return -ENOMEM;
1695 	if (dev->bar)
1696 		iounmap(dev->bar);
1697 	dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1698 	if (!dev->bar) {
1699 		dev->bar_mapped_size = 0;
1700 		return -ENOMEM;
1701 	}
1702 	dev->bar_mapped_size = size;
1703 	dev->dbs = dev->bar + NVME_REG_DBS;
1704 
1705 	return 0;
1706 }
1707 
nvme_pci_configure_admin_queue(struct nvme_dev * dev)1708 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1709 {
1710 	int result;
1711 	u32 aqa;
1712 	struct nvme_queue *nvmeq;
1713 
1714 	result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1715 	if (result < 0)
1716 		return result;
1717 
1718 	dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1719 				NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1720 
1721 	if (dev->subsystem &&
1722 	    (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1723 		writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1724 
1725 	result = nvme_disable_ctrl(&dev->ctrl);
1726 	if (result < 0)
1727 		return result;
1728 
1729 	result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1730 	if (result)
1731 		return result;
1732 
1733 	dev->ctrl.numa_node = dev_to_node(dev->dev);
1734 
1735 	nvmeq = &dev->queues[0];
1736 	aqa = nvmeq->q_depth - 1;
1737 	aqa |= aqa << 16;
1738 
1739 	writel(aqa, dev->bar + NVME_REG_AQA);
1740 	lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1741 	lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1742 
1743 	result = nvme_enable_ctrl(&dev->ctrl);
1744 	if (result)
1745 		return result;
1746 
1747 	nvmeq->cq_vector = 0;
1748 	nvme_init_queue(nvmeq, 0);
1749 	result = queue_request_irq(nvmeq);
1750 	if (result) {
1751 		dev->online_queues--;
1752 		return result;
1753 	}
1754 
1755 	set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1756 	return result;
1757 }
1758 
nvme_create_io_queues(struct nvme_dev * dev)1759 static int nvme_create_io_queues(struct nvme_dev *dev)
1760 {
1761 	unsigned i, max, rw_queues;
1762 	int ret = 0;
1763 
1764 	for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1765 		if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1766 			ret = -ENOMEM;
1767 			break;
1768 		}
1769 	}
1770 
1771 	max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1772 	if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1773 		rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1774 				dev->io_queues[HCTX_TYPE_READ];
1775 	} else {
1776 		rw_queues = max;
1777 	}
1778 
1779 	for (i = dev->online_queues; i <= max; i++) {
1780 		bool polled = i > rw_queues;
1781 
1782 		ret = nvme_create_queue(&dev->queues[i], i, polled);
1783 		if (ret)
1784 			break;
1785 	}
1786 
1787 	/*
1788 	 * Ignore failing Create SQ/CQ commands, we can continue with less
1789 	 * than the desired amount of queues, and even a controller without
1790 	 * I/O queues can still be used to issue admin commands.  This might
1791 	 * be useful to upgrade a buggy firmware for example.
1792 	 */
1793 	return ret >= 0 ? 0 : ret;
1794 }
1795 
nvme_cmb_show(struct device * dev,struct device_attribute * attr,char * buf)1796 static ssize_t nvme_cmb_show(struct device *dev,
1797 			     struct device_attribute *attr,
1798 			     char *buf)
1799 {
1800 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1801 
1802 	return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1803 		       ndev->cmbloc, ndev->cmbsz);
1804 }
1805 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1806 
nvme_cmb_size_unit(struct nvme_dev * dev)1807 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1808 {
1809 	u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1810 
1811 	return 1ULL << (12 + 4 * szu);
1812 }
1813 
nvme_cmb_size(struct nvme_dev * dev)1814 static u32 nvme_cmb_size(struct nvme_dev *dev)
1815 {
1816 	return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1817 }
1818 
nvme_map_cmb(struct nvme_dev * dev)1819 static void nvme_map_cmb(struct nvme_dev *dev)
1820 {
1821 	u64 size, offset;
1822 	resource_size_t bar_size;
1823 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1824 	int bar;
1825 
1826 	if (dev->cmb_size)
1827 		return;
1828 
1829 	if (NVME_CAP_CMBS(dev->ctrl.cap))
1830 		writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1831 
1832 	dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1833 	if (!dev->cmbsz)
1834 		return;
1835 	dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1836 
1837 	size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1838 	offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1839 	bar = NVME_CMB_BIR(dev->cmbloc);
1840 	bar_size = pci_resource_len(pdev, bar);
1841 
1842 	if (offset > bar_size)
1843 		return;
1844 
1845 	/*
1846 	 * Tell the controller about the host side address mapping the CMB,
1847 	 * and enable CMB decoding for the NVMe 1.4+ scheme:
1848 	 */
1849 	if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1850 		hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1851 			     (pci_bus_address(pdev, bar) + offset),
1852 			     dev->bar + NVME_REG_CMBMSC);
1853 	}
1854 
1855 	/*
1856 	 * Controllers may support a CMB size larger than their BAR,
1857 	 * for example, due to being behind a bridge. Reduce the CMB to
1858 	 * the reported size of the BAR
1859 	 */
1860 	if (size > bar_size - offset)
1861 		size = bar_size - offset;
1862 
1863 	if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1864 		dev_warn(dev->ctrl.device,
1865 			 "failed to register the CMB\n");
1866 		return;
1867 	}
1868 
1869 	dev->cmb_size = size;
1870 	dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1871 
1872 	if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1873 			(NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1874 		pci_p2pmem_publish(pdev, true);
1875 
1876 	if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1877 				    &dev_attr_cmb.attr, NULL))
1878 		dev_warn(dev->ctrl.device,
1879 			 "failed to add sysfs attribute for CMB\n");
1880 }
1881 
nvme_release_cmb(struct nvme_dev * dev)1882 static inline void nvme_release_cmb(struct nvme_dev *dev)
1883 {
1884 	if (dev->cmb_size) {
1885 		sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1886 					     &dev_attr_cmb.attr, NULL);
1887 		dev->cmb_size = 0;
1888 	}
1889 }
1890 
nvme_set_host_mem(struct nvme_dev * dev,u32 bits)1891 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1892 {
1893 	u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1894 	u64 dma_addr = dev->host_mem_descs_dma;
1895 	struct nvme_command c;
1896 	int ret;
1897 
1898 	memset(&c, 0, sizeof(c));
1899 	c.features.opcode	= nvme_admin_set_features;
1900 	c.features.fid		= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1901 	c.features.dword11	= cpu_to_le32(bits);
1902 	c.features.dword12	= cpu_to_le32(host_mem_size);
1903 	c.features.dword13	= cpu_to_le32(lower_32_bits(dma_addr));
1904 	c.features.dword14	= cpu_to_le32(upper_32_bits(dma_addr));
1905 	c.features.dword15	= cpu_to_le32(dev->nr_host_mem_descs);
1906 
1907 	ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1908 	if (ret) {
1909 		dev_warn(dev->ctrl.device,
1910 			 "failed to set host mem (err %d, flags %#x).\n",
1911 			 ret, bits);
1912 	}
1913 	return ret;
1914 }
1915 
nvme_free_host_mem(struct nvme_dev * dev)1916 static void nvme_free_host_mem(struct nvme_dev *dev)
1917 {
1918 	int i;
1919 
1920 	for (i = 0; i < dev->nr_host_mem_descs; i++) {
1921 		struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1922 		size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1923 
1924 		dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1925 			       le64_to_cpu(desc->addr),
1926 			       DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1927 	}
1928 
1929 	kfree(dev->host_mem_desc_bufs);
1930 	dev->host_mem_desc_bufs = NULL;
1931 	dma_free_coherent(dev->dev,
1932 			dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1933 			dev->host_mem_descs, dev->host_mem_descs_dma);
1934 	dev->host_mem_descs = NULL;
1935 	dev->nr_host_mem_descs = 0;
1936 }
1937 
__nvme_alloc_host_mem(struct nvme_dev * dev,u64 preferred,u32 chunk_size)1938 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1939 		u32 chunk_size)
1940 {
1941 	struct nvme_host_mem_buf_desc *descs;
1942 	u32 max_entries, len;
1943 	dma_addr_t descs_dma;
1944 	int i = 0;
1945 	void **bufs;
1946 	u64 size, tmp;
1947 
1948 	tmp = (preferred + chunk_size - 1);
1949 	do_div(tmp, chunk_size);
1950 	max_entries = tmp;
1951 
1952 	if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1953 		max_entries = dev->ctrl.hmmaxd;
1954 
1955 	descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1956 				   &descs_dma, GFP_KERNEL);
1957 	if (!descs)
1958 		goto out;
1959 
1960 	bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1961 	if (!bufs)
1962 		goto out_free_descs;
1963 
1964 	for (size = 0; size < preferred && i < max_entries; size += len) {
1965 		dma_addr_t dma_addr;
1966 
1967 		len = min_t(u64, chunk_size, preferred - size);
1968 		bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1969 				DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1970 		if (!bufs[i])
1971 			break;
1972 
1973 		descs[i].addr = cpu_to_le64(dma_addr);
1974 		descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1975 		i++;
1976 	}
1977 
1978 	if (!size)
1979 		goto out_free_bufs;
1980 
1981 	dev->nr_host_mem_descs = i;
1982 	dev->host_mem_size = size;
1983 	dev->host_mem_descs = descs;
1984 	dev->host_mem_descs_dma = descs_dma;
1985 	dev->host_mem_desc_bufs = bufs;
1986 	return 0;
1987 
1988 out_free_bufs:
1989 	while (--i >= 0) {
1990 		size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1991 
1992 		dma_free_attrs(dev->dev, size, bufs[i],
1993 			       le64_to_cpu(descs[i].addr),
1994 			       DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1995 	}
1996 
1997 	kfree(bufs);
1998 out_free_descs:
1999 	dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2000 			descs_dma);
2001 out:
2002 	dev->host_mem_descs = NULL;
2003 	return -ENOMEM;
2004 }
2005 
nvme_alloc_host_mem(struct nvme_dev * dev,u64 min,u64 preferred)2006 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2007 {
2008 	u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2009 	u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2010 	u64 chunk_size;
2011 
2012 	/* start big and work our way down */
2013 	for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2014 		if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2015 			if (!min || dev->host_mem_size >= min)
2016 				return 0;
2017 			nvme_free_host_mem(dev);
2018 		}
2019 	}
2020 
2021 	return -ENOMEM;
2022 }
2023 
nvme_setup_host_mem(struct nvme_dev * dev)2024 static int nvme_setup_host_mem(struct nvme_dev *dev)
2025 {
2026 	u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2027 	u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2028 	u64 min = (u64)dev->ctrl.hmmin * 4096;
2029 	u32 enable_bits = NVME_HOST_MEM_ENABLE;
2030 	int ret;
2031 
2032 	preferred = min(preferred, max);
2033 	if (min > max) {
2034 		dev_warn(dev->ctrl.device,
2035 			"min host memory (%lld MiB) above limit (%d MiB).\n",
2036 			min >> ilog2(SZ_1M), max_host_mem_size_mb);
2037 		nvme_free_host_mem(dev);
2038 		return 0;
2039 	}
2040 
2041 	/*
2042 	 * If we already have a buffer allocated check if we can reuse it.
2043 	 */
2044 	if (dev->host_mem_descs) {
2045 		if (dev->host_mem_size >= min)
2046 			enable_bits |= NVME_HOST_MEM_RETURN;
2047 		else
2048 			nvme_free_host_mem(dev);
2049 	}
2050 
2051 	if (!dev->host_mem_descs) {
2052 		if (nvme_alloc_host_mem(dev, min, preferred)) {
2053 			dev_warn(dev->ctrl.device,
2054 				"failed to allocate host memory buffer.\n");
2055 			return 0; /* controller must work without HMB */
2056 		}
2057 
2058 		dev_info(dev->ctrl.device,
2059 			"allocated %lld MiB host memory buffer.\n",
2060 			dev->host_mem_size >> ilog2(SZ_1M));
2061 	}
2062 
2063 	ret = nvme_set_host_mem(dev, enable_bits);
2064 	if (ret)
2065 		nvme_free_host_mem(dev);
2066 	return ret;
2067 }
2068 
2069 /*
2070  * nirqs is the number of interrupts available for write and read
2071  * queues. The core already reserved an interrupt for the admin queue.
2072  */
nvme_calc_irq_sets(struct irq_affinity * affd,unsigned int nrirqs)2073 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2074 {
2075 	struct nvme_dev *dev = affd->priv;
2076 	unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2077 
2078 	/*
2079 	 * If there is no interrupt available for queues, ensure that
2080 	 * the default queue is set to 1. The affinity set size is
2081 	 * also set to one, but the irq core ignores it for this case.
2082 	 *
2083 	 * If only one interrupt is available or 'write_queue' == 0, combine
2084 	 * write and read queues.
2085 	 *
2086 	 * If 'write_queues' > 0, ensure it leaves room for at least one read
2087 	 * queue.
2088 	 */
2089 	if (!nrirqs) {
2090 		nrirqs = 1;
2091 		nr_read_queues = 0;
2092 	} else if (nrirqs == 1 || !nr_write_queues) {
2093 		nr_read_queues = 0;
2094 	} else if (nr_write_queues >= nrirqs) {
2095 		nr_read_queues = 1;
2096 	} else {
2097 		nr_read_queues = nrirqs - nr_write_queues;
2098 	}
2099 
2100 	dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2101 	affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2102 	dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2103 	affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2104 	affd->nr_sets = nr_read_queues ? 2 : 1;
2105 }
2106 
nvme_setup_irqs(struct nvme_dev * dev,unsigned int nr_io_queues)2107 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2108 {
2109 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2110 	struct irq_affinity affd = {
2111 		.pre_vectors	= 1,
2112 		.calc_sets	= nvme_calc_irq_sets,
2113 		.priv		= dev,
2114 	};
2115 	unsigned int irq_queues, poll_queues;
2116 
2117 	/*
2118 	 * Poll queues don't need interrupts, but we need at least one I/O queue
2119 	 * left over for non-polled I/O.
2120 	 */
2121 	poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2122 	dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2123 
2124 	/*
2125 	 * Initialize for the single interrupt case, will be updated in
2126 	 * nvme_calc_irq_sets().
2127 	 */
2128 	dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2129 	dev->io_queues[HCTX_TYPE_READ] = 0;
2130 
2131 	/*
2132 	 * We need interrupts for the admin queue and each non-polled I/O queue,
2133 	 * but some Apple controllers require all queues to use the first
2134 	 * vector.
2135 	 */
2136 	irq_queues = 1;
2137 	if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2138 		irq_queues += (nr_io_queues - poll_queues);
2139 	return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2140 			      PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2141 }
2142 
nvme_disable_io_queues(struct nvme_dev * dev)2143 static void nvme_disable_io_queues(struct nvme_dev *dev)
2144 {
2145 	if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2146 		__nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2147 }
2148 
nvme_max_io_queues(struct nvme_dev * dev)2149 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2150 {
2151 	return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2152 }
2153 
nvme_setup_io_queues(struct nvme_dev * dev)2154 static int nvme_setup_io_queues(struct nvme_dev *dev)
2155 {
2156 	struct nvme_queue *adminq = &dev->queues[0];
2157 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2158 	unsigned int nr_io_queues;
2159 	unsigned long size;
2160 	int result;
2161 
2162 	/*
2163 	 * Sample the module parameters once at reset time so that we have
2164 	 * stable values to work with.
2165 	 */
2166 	dev->nr_write_queues = write_queues;
2167 	dev->nr_poll_queues = poll_queues;
2168 
2169 	/*
2170 	 * If tags are shared with admin queue (Apple bug), then
2171 	 * make sure we only use one IO queue.
2172 	 */
2173 	if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2174 		nr_io_queues = 1;
2175 	else
2176 		nr_io_queues = min(nvme_max_io_queues(dev),
2177 				   dev->nr_allocated_queues - 1);
2178 
2179 	result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2180 	if (result < 0)
2181 		return result;
2182 
2183 	if (nr_io_queues == 0)
2184 		return 0;
2185 
2186 	clear_bit(NVMEQ_ENABLED, &adminq->flags);
2187 
2188 	if (dev->cmb_use_sqes) {
2189 		result = nvme_cmb_qdepth(dev, nr_io_queues,
2190 				sizeof(struct nvme_command));
2191 		if (result > 0)
2192 			dev->q_depth = result;
2193 		else
2194 			dev->cmb_use_sqes = false;
2195 	}
2196 
2197 	do {
2198 		size = db_bar_size(dev, nr_io_queues);
2199 		result = nvme_remap_bar(dev, size);
2200 		if (!result)
2201 			break;
2202 		if (!--nr_io_queues)
2203 			return -ENOMEM;
2204 	} while (1);
2205 	adminq->q_db = dev->dbs;
2206 
2207  retry:
2208 	/* Deregister the admin queue's interrupt */
2209 	pci_free_irq(pdev, 0, adminq);
2210 
2211 	/*
2212 	 * If we enable msix early due to not intx, disable it again before
2213 	 * setting up the full range we need.
2214 	 */
2215 	pci_free_irq_vectors(pdev);
2216 
2217 	result = nvme_setup_irqs(dev, nr_io_queues);
2218 	if (result <= 0)
2219 		return -EIO;
2220 
2221 	dev->num_vecs = result;
2222 	result = max(result - 1, 1);
2223 	dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2224 
2225 	/*
2226 	 * Should investigate if there's a performance win from allocating
2227 	 * more queues than interrupt vectors; it might allow the submission
2228 	 * path to scale better, even if the receive path is limited by the
2229 	 * number of interrupts.
2230 	 */
2231 	result = queue_request_irq(adminq);
2232 	if (result)
2233 		return result;
2234 	set_bit(NVMEQ_ENABLED, &adminq->flags);
2235 
2236 	result = nvme_create_io_queues(dev);
2237 	if (result || dev->online_queues < 2)
2238 		return result;
2239 
2240 	if (dev->online_queues - 1 < dev->max_qid) {
2241 		nr_io_queues = dev->online_queues - 1;
2242 		nvme_disable_io_queues(dev);
2243 		nvme_suspend_io_queues(dev);
2244 		goto retry;
2245 	}
2246 	dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2247 					dev->io_queues[HCTX_TYPE_DEFAULT],
2248 					dev->io_queues[HCTX_TYPE_READ],
2249 					dev->io_queues[HCTX_TYPE_POLL]);
2250 	return 0;
2251 }
2252 
nvme_del_queue_end(struct request * req,blk_status_t error)2253 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2254 {
2255 	struct nvme_queue *nvmeq = req->end_io_data;
2256 
2257 	blk_mq_free_request(req);
2258 	complete(&nvmeq->delete_done);
2259 }
2260 
nvme_del_cq_end(struct request * req,blk_status_t error)2261 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2262 {
2263 	struct nvme_queue *nvmeq = req->end_io_data;
2264 
2265 	if (error)
2266 		set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2267 
2268 	nvme_del_queue_end(req, error);
2269 }
2270 
nvme_delete_queue(struct nvme_queue * nvmeq,u8 opcode)2271 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2272 {
2273 	struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2274 	struct request *req;
2275 	struct nvme_command cmd;
2276 
2277 	memset(&cmd, 0, sizeof(cmd));
2278 	cmd.delete_queue.opcode = opcode;
2279 	cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2280 
2281 	req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2282 	if (IS_ERR(req))
2283 		return PTR_ERR(req);
2284 
2285 	req->timeout = ADMIN_TIMEOUT;
2286 	req->end_io_data = nvmeq;
2287 
2288 	init_completion(&nvmeq->delete_done);
2289 	blk_execute_rq_nowait(q, NULL, req, false,
2290 			opcode == nvme_admin_delete_cq ?
2291 				nvme_del_cq_end : nvme_del_queue_end);
2292 	return 0;
2293 }
2294 
__nvme_disable_io_queues(struct nvme_dev * dev,u8 opcode)2295 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2296 {
2297 	int nr_queues = dev->online_queues - 1, sent = 0;
2298 	unsigned long timeout;
2299 
2300  retry:
2301 	timeout = ADMIN_TIMEOUT;
2302 	while (nr_queues > 0) {
2303 		if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2304 			break;
2305 		nr_queues--;
2306 		sent++;
2307 	}
2308 	while (sent) {
2309 		struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2310 
2311 		timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2312 				timeout);
2313 		if (timeout == 0)
2314 			return false;
2315 
2316 		sent--;
2317 		if (nr_queues)
2318 			goto retry;
2319 	}
2320 	return true;
2321 }
2322 
nvme_dev_add(struct nvme_dev * dev)2323 static void nvme_dev_add(struct nvme_dev *dev)
2324 {
2325 	int ret;
2326 
2327 	if (!dev->ctrl.tagset) {
2328 		dev->tagset.ops = &nvme_mq_ops;
2329 		dev->tagset.nr_hw_queues = dev->online_queues - 1;
2330 		dev->tagset.nr_maps = 2; /* default + read */
2331 		if (dev->io_queues[HCTX_TYPE_POLL])
2332 			dev->tagset.nr_maps++;
2333 		dev->tagset.timeout = NVME_IO_TIMEOUT;
2334 		dev->tagset.numa_node = dev->ctrl.numa_node;
2335 		dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2336 						BLK_MQ_MAX_DEPTH) - 1;
2337 		dev->tagset.cmd_size = sizeof(struct nvme_iod);
2338 		dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2339 		dev->tagset.driver_data = dev;
2340 
2341 		/*
2342 		 * Some Apple controllers requires tags to be unique
2343 		 * across admin and IO queue, so reserve the first 32
2344 		 * tags of the IO queue.
2345 		 */
2346 		if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2347 			dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2348 
2349 		ret = blk_mq_alloc_tag_set(&dev->tagset);
2350 		if (ret) {
2351 			dev_warn(dev->ctrl.device,
2352 				"IO queues tagset allocation failed %d\n", ret);
2353 			return;
2354 		}
2355 		dev->ctrl.tagset = &dev->tagset;
2356 	} else {
2357 		blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2358 
2359 		/* Free previously allocated queues that are no longer usable */
2360 		nvme_free_queues(dev, dev->online_queues);
2361 	}
2362 
2363 	nvme_dbbuf_set(dev);
2364 }
2365 
nvme_pci_enable(struct nvme_dev * dev)2366 static int nvme_pci_enable(struct nvme_dev *dev)
2367 {
2368 	int result = -ENOMEM;
2369 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2370 
2371 	if (pci_enable_device_mem(pdev))
2372 		return result;
2373 
2374 	pci_set_master(pdev);
2375 
2376 	if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2377 		goto disable;
2378 
2379 	if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2380 		result = -ENODEV;
2381 		goto disable;
2382 	}
2383 
2384 	/*
2385 	 * Some devices and/or platforms don't advertise or work with INTx
2386 	 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2387 	 * adjust this later.
2388 	 */
2389 	result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2390 	if (result < 0)
2391 		return result;
2392 
2393 	dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2394 
2395 	dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2396 				io_queue_depth);
2397 	dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2398 	dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2399 	dev->dbs = dev->bar + 4096;
2400 
2401 	/*
2402 	 * Some Apple controllers require a non-standard SQE size.
2403 	 * Interestingly they also seem to ignore the CC:IOSQES register
2404 	 * so we don't bother updating it here.
2405 	 */
2406 	if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2407 		dev->io_sqes = 7;
2408 	else
2409 		dev->io_sqes = NVME_NVM_IOSQES;
2410 
2411 	/*
2412 	 * Temporary fix for the Apple controller found in the MacBook8,1 and
2413 	 * some MacBook7,1 to avoid controller resets and data loss.
2414 	 */
2415 	if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2416 		dev->q_depth = 2;
2417 		dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2418 			"set queue depth=%u to work around controller resets\n",
2419 			dev->q_depth);
2420 	} else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2421 		   (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2422 		   NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2423 		dev->q_depth = 64;
2424 		dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2425                         "set queue depth=%u\n", dev->q_depth);
2426 	}
2427 
2428 	/*
2429 	 * Controllers with the shared tags quirk need the IO queue to be
2430 	 * big enough so that we get 32 tags for the admin queue
2431 	 */
2432 	if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2433 	    (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2434 		dev->q_depth = NVME_AQ_DEPTH + 2;
2435 		dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2436 			 dev->q_depth);
2437 	}
2438 
2439 
2440 	nvme_map_cmb(dev);
2441 
2442 	pci_enable_pcie_error_reporting(pdev);
2443 	pci_save_state(pdev);
2444 	return 0;
2445 
2446  disable:
2447 	pci_disable_device(pdev);
2448 	return result;
2449 }
2450 
nvme_dev_unmap(struct nvme_dev * dev)2451 static void nvme_dev_unmap(struct nvme_dev *dev)
2452 {
2453 	if (dev->bar)
2454 		iounmap(dev->bar);
2455 	pci_release_mem_regions(to_pci_dev(dev->dev));
2456 }
2457 
nvme_pci_disable(struct nvme_dev * dev)2458 static void nvme_pci_disable(struct nvme_dev *dev)
2459 {
2460 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2461 
2462 	pci_free_irq_vectors(pdev);
2463 
2464 	if (pci_is_enabled(pdev)) {
2465 		pci_disable_pcie_error_reporting(pdev);
2466 		pci_disable_device(pdev);
2467 	}
2468 }
2469 
nvme_dev_disable(struct nvme_dev * dev,bool shutdown)2470 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2471 {
2472 	bool dead = true, freeze = false;
2473 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2474 
2475 	mutex_lock(&dev->shutdown_lock);
2476 	if (pci_is_enabled(pdev)) {
2477 		u32 csts = readl(dev->bar + NVME_REG_CSTS);
2478 
2479 		if (dev->ctrl.state == NVME_CTRL_LIVE ||
2480 		    dev->ctrl.state == NVME_CTRL_RESETTING) {
2481 			freeze = true;
2482 			nvme_start_freeze(&dev->ctrl);
2483 		}
2484 		dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2485 			pdev->error_state  != pci_channel_io_normal);
2486 	}
2487 
2488 	/*
2489 	 * Give the controller a chance to complete all entered requests if
2490 	 * doing a safe shutdown.
2491 	 */
2492 	if (!dead && shutdown && freeze)
2493 		nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2494 
2495 	nvme_stop_queues(&dev->ctrl);
2496 
2497 	if (!dead && dev->ctrl.queue_count > 0) {
2498 		nvme_disable_io_queues(dev);
2499 		nvme_disable_admin_queue(dev, shutdown);
2500 	}
2501 	nvme_suspend_io_queues(dev);
2502 	nvme_suspend_queue(&dev->queues[0]);
2503 	nvme_pci_disable(dev);
2504 	nvme_reap_pending_cqes(dev);
2505 
2506 	blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2507 	blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2508 	blk_mq_tagset_wait_completed_request(&dev->tagset);
2509 	blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2510 
2511 	/*
2512 	 * The driver will not be starting up queues again if shutting down so
2513 	 * must flush all entered requests to their failed completion to avoid
2514 	 * deadlocking blk-mq hot-cpu notifier.
2515 	 */
2516 	if (shutdown) {
2517 		nvme_start_queues(&dev->ctrl);
2518 		if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2519 			nvme_start_admin_queue(&dev->ctrl);
2520 	}
2521 	mutex_unlock(&dev->shutdown_lock);
2522 }
2523 
nvme_disable_prepare_reset(struct nvme_dev * dev,bool shutdown)2524 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2525 {
2526 	if (!nvme_wait_reset(&dev->ctrl))
2527 		return -EBUSY;
2528 	nvme_dev_disable(dev, shutdown);
2529 	return 0;
2530 }
2531 
nvme_setup_prp_pools(struct nvme_dev * dev)2532 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2533 {
2534 	dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2535 						NVME_CTRL_PAGE_SIZE,
2536 						NVME_CTRL_PAGE_SIZE, 0);
2537 	if (!dev->prp_page_pool)
2538 		return -ENOMEM;
2539 
2540 	/* Optimisation for I/Os between 4k and 128k */
2541 	dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2542 						256, 256, 0);
2543 	if (!dev->prp_small_pool) {
2544 		dma_pool_destroy(dev->prp_page_pool);
2545 		return -ENOMEM;
2546 	}
2547 	return 0;
2548 }
2549 
nvme_release_prp_pools(struct nvme_dev * dev)2550 static void nvme_release_prp_pools(struct nvme_dev *dev)
2551 {
2552 	dma_pool_destroy(dev->prp_page_pool);
2553 	dma_pool_destroy(dev->prp_small_pool);
2554 }
2555 
nvme_free_tagset(struct nvme_dev * dev)2556 static void nvme_free_tagset(struct nvme_dev *dev)
2557 {
2558 	if (dev->tagset.tags)
2559 		blk_mq_free_tag_set(&dev->tagset);
2560 	dev->ctrl.tagset = NULL;
2561 }
2562 
nvme_pci_free_ctrl(struct nvme_ctrl * ctrl)2563 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2564 {
2565 	struct nvme_dev *dev = to_nvme_dev(ctrl);
2566 
2567 	nvme_dbbuf_dma_free(dev);
2568 	nvme_free_tagset(dev);
2569 	if (dev->ctrl.admin_q)
2570 		blk_put_queue(dev->ctrl.admin_q);
2571 	free_opal_dev(dev->ctrl.opal_dev);
2572 	mempool_destroy(dev->iod_mempool);
2573 	put_device(dev->dev);
2574 	kfree(dev->queues);
2575 	kfree(dev);
2576 }
2577 
nvme_remove_dead_ctrl(struct nvme_dev * dev)2578 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2579 {
2580 	/*
2581 	 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2582 	 * may be holding this pci_dev's device lock.
2583 	 */
2584 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2585 	nvme_get_ctrl(&dev->ctrl);
2586 	nvme_dev_disable(dev, false);
2587 	nvme_kill_queues(&dev->ctrl);
2588 	if (!queue_work(nvme_wq, &dev->remove_work))
2589 		nvme_put_ctrl(&dev->ctrl);
2590 }
2591 
nvme_reset_work(struct work_struct * work)2592 static void nvme_reset_work(struct work_struct *work)
2593 {
2594 	struct nvme_dev *dev =
2595 		container_of(work, struct nvme_dev, ctrl.reset_work);
2596 	bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2597 	int result;
2598 
2599 	if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2600 		dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2601 			 dev->ctrl.state);
2602 		result = -ENODEV;
2603 		goto out;
2604 	}
2605 
2606 	/*
2607 	 * If we're called to reset a live controller first shut it down before
2608 	 * moving on.
2609 	 */
2610 	if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2611 		nvme_dev_disable(dev, false);
2612 	nvme_sync_queues(&dev->ctrl);
2613 
2614 	mutex_lock(&dev->shutdown_lock);
2615 	result = nvme_pci_enable(dev);
2616 	if (result)
2617 		goto out_unlock;
2618 
2619 	result = nvme_pci_configure_admin_queue(dev);
2620 	if (result)
2621 		goto out_unlock;
2622 
2623 	result = nvme_alloc_admin_tags(dev);
2624 	if (result)
2625 		goto out_unlock;
2626 
2627 	/*
2628 	 * Limit the max command size to prevent iod->sg allocations going
2629 	 * over a single page.
2630 	 */
2631 	dev->ctrl.max_hw_sectors = min_t(u32,
2632 		NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2633 	dev->ctrl.max_segments = NVME_MAX_SEGS;
2634 
2635 	/*
2636 	 * Don't limit the IOMMU merged segment size.
2637 	 */
2638 	dma_set_max_seg_size(dev->dev, 0xffffffff);
2639 	dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2640 
2641 	mutex_unlock(&dev->shutdown_lock);
2642 
2643 	/*
2644 	 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2645 	 * initializing procedure here.
2646 	 */
2647 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2648 		dev_warn(dev->ctrl.device,
2649 			"failed to mark controller CONNECTING\n");
2650 		result = -EBUSY;
2651 		goto out;
2652 	}
2653 
2654 	/*
2655 	 * We do not support an SGL for metadata (yet), so we are limited to a
2656 	 * single integrity segment for the separate metadata pointer.
2657 	 */
2658 	dev->ctrl.max_integrity_segments = 1;
2659 
2660 	result = nvme_init_identify(&dev->ctrl);
2661 	if (result)
2662 		goto out;
2663 
2664 	if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2665 		if (!dev->ctrl.opal_dev)
2666 			dev->ctrl.opal_dev =
2667 				init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2668 		else if (was_suspend)
2669 			opal_unlock_from_suspend(dev->ctrl.opal_dev);
2670 	} else {
2671 		free_opal_dev(dev->ctrl.opal_dev);
2672 		dev->ctrl.opal_dev = NULL;
2673 	}
2674 
2675 	if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2676 		result = nvme_dbbuf_dma_alloc(dev);
2677 		if (result)
2678 			dev_warn(dev->dev,
2679 				 "unable to allocate dma for dbbuf\n");
2680 	}
2681 
2682 	if (dev->ctrl.hmpre) {
2683 		result = nvme_setup_host_mem(dev);
2684 		if (result < 0)
2685 			goto out;
2686 	}
2687 
2688 	result = nvme_setup_io_queues(dev);
2689 	if (result)
2690 		goto out;
2691 
2692 	/*
2693 	 * Keep the controller around but remove all namespaces if we don't have
2694 	 * any working I/O queue.
2695 	 */
2696 	if (dev->online_queues < 2) {
2697 		dev_warn(dev->ctrl.device, "IO queues not created\n");
2698 		nvme_kill_queues(&dev->ctrl);
2699 		nvme_remove_namespaces(&dev->ctrl);
2700 		nvme_free_tagset(dev);
2701 	} else {
2702 		nvme_start_queues(&dev->ctrl);
2703 		nvme_wait_freeze(&dev->ctrl);
2704 		nvme_dev_add(dev);
2705 		nvme_unfreeze(&dev->ctrl);
2706 	}
2707 
2708 	/*
2709 	 * If only admin queue live, keep it to do further investigation or
2710 	 * recovery.
2711 	 */
2712 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2713 		dev_warn(dev->ctrl.device,
2714 			"failed to mark controller live state\n");
2715 		result = -ENODEV;
2716 		goto out;
2717 	}
2718 
2719 	nvme_start_ctrl(&dev->ctrl);
2720 	return;
2721 
2722  out_unlock:
2723 	mutex_unlock(&dev->shutdown_lock);
2724  out:
2725 	if (result)
2726 		dev_warn(dev->ctrl.device,
2727 			 "Removing after probe failure status: %d\n", result);
2728 	nvme_remove_dead_ctrl(dev);
2729 }
2730 
nvme_remove_dead_ctrl_work(struct work_struct * work)2731 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2732 {
2733 	struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2734 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2735 
2736 	if (pci_get_drvdata(pdev))
2737 		device_release_driver(&pdev->dev);
2738 	nvme_put_ctrl(&dev->ctrl);
2739 }
2740 
nvme_pci_reg_read32(struct nvme_ctrl * ctrl,u32 off,u32 * val)2741 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2742 {
2743 	*val = readl(to_nvme_dev(ctrl)->bar + off);
2744 	return 0;
2745 }
2746 
nvme_pci_reg_write32(struct nvme_ctrl * ctrl,u32 off,u32 val)2747 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2748 {
2749 	writel(val, to_nvme_dev(ctrl)->bar + off);
2750 	return 0;
2751 }
2752 
nvme_pci_reg_read64(struct nvme_ctrl * ctrl,u32 off,u64 * val)2753 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2754 {
2755 	*val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2756 	return 0;
2757 }
2758 
nvme_pci_get_address(struct nvme_ctrl * ctrl,char * buf,int size)2759 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2760 {
2761 	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2762 
2763 	return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2764 }
2765 
2766 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2767 	.name			= "pcie",
2768 	.module			= THIS_MODULE,
2769 	.flags			= NVME_F_METADATA_SUPPORTED |
2770 				  NVME_F_PCI_P2PDMA,
2771 	.reg_read32		= nvme_pci_reg_read32,
2772 	.reg_write32		= nvme_pci_reg_write32,
2773 	.reg_read64		= nvme_pci_reg_read64,
2774 	.free_ctrl		= nvme_pci_free_ctrl,
2775 	.submit_async_event	= nvme_pci_submit_async_event,
2776 	.get_address		= nvme_pci_get_address,
2777 };
2778 
nvme_dev_map(struct nvme_dev * dev)2779 static int nvme_dev_map(struct nvme_dev *dev)
2780 {
2781 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2782 
2783 	if (pci_request_mem_regions(pdev, "nvme"))
2784 		return -ENODEV;
2785 
2786 	if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2787 		goto release;
2788 
2789 	return 0;
2790   release:
2791 	pci_release_mem_regions(pdev);
2792 	return -ENODEV;
2793 }
2794 
check_vendor_combination_bug(struct pci_dev * pdev)2795 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2796 {
2797 	if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2798 		/*
2799 		 * Several Samsung devices seem to drop off the PCIe bus
2800 		 * randomly when APST is on and uses the deepest sleep state.
2801 		 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2802 		 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2803 		 * 950 PRO 256GB", but it seems to be restricted to two Dell
2804 		 * laptops.
2805 		 */
2806 		if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2807 		    (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2808 		     dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2809 			return NVME_QUIRK_NO_DEEPEST_PS;
2810 	} else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2811 		/*
2812 		 * Samsung SSD 960 EVO drops off the PCIe bus after system
2813 		 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2814 		 * within few minutes after bootup on a Coffee Lake board -
2815 		 * ASUS PRIME Z370-A
2816 		 */
2817 		if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2818 		    (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2819 		     dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2820 			return NVME_QUIRK_NO_APST;
2821 	} else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2822 		    pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2823 		   (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2824 		/*
2825 		 * Forcing to use host managed nvme power settings for
2826 		 * lowest idle power with quick resume latency on
2827 		 * Samsung and Toshiba SSDs based on suspend behavior
2828 		 * on Coffee Lake board for LENOVO C640
2829 		 */
2830 		if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2831 		     dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2832 			return NVME_QUIRK_SIMPLE_SUSPEND;
2833 	}
2834 
2835 	return 0;
2836 }
2837 
2838 #ifdef CONFIG_ACPI
nvme_acpi_storage_d3(struct pci_dev * dev)2839 static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2840 {
2841 	struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
2842 	u8 val;
2843 
2844 	/*
2845 	 * Look for _DSD property specifying that the storage device on the port
2846 	 * must use D3 to support deep platform power savings during
2847 	 * suspend-to-idle.
2848 	 */
2849 
2850 	if (!adev)
2851 		return false;
2852 	if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2853 			&val))
2854 		return false;
2855 	return val == 1;
2856 }
2857 #else
nvme_acpi_storage_d3(struct pci_dev * dev)2858 static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2859 {
2860 	return false;
2861 }
2862 #endif /* CONFIG_ACPI */
2863 
nvme_async_probe(void * data,async_cookie_t cookie)2864 static void nvme_async_probe(void *data, async_cookie_t cookie)
2865 {
2866 	struct nvme_dev *dev = data;
2867 
2868 	flush_work(&dev->ctrl.reset_work);
2869 	flush_work(&dev->ctrl.scan_work);
2870 	nvme_put_ctrl(&dev->ctrl);
2871 }
2872 
nvme_probe(struct pci_dev * pdev,const struct pci_device_id * id)2873 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2874 {
2875 	int node, result = -ENOMEM;
2876 	struct nvme_dev *dev;
2877 	unsigned long quirks = id->driver_data;
2878 	size_t alloc_size;
2879 
2880 	node = dev_to_node(&pdev->dev);
2881 	if (node == NUMA_NO_NODE)
2882 		set_dev_node(&pdev->dev, first_memory_node);
2883 
2884 	dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2885 	if (!dev)
2886 		return -ENOMEM;
2887 
2888 	dev->nr_write_queues = write_queues;
2889 	dev->nr_poll_queues = poll_queues;
2890 	dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2891 	dev->queues = kcalloc_node(dev->nr_allocated_queues,
2892 			sizeof(struct nvme_queue), GFP_KERNEL, node);
2893 	if (!dev->queues)
2894 		goto free;
2895 
2896 	dev->dev = get_device(&pdev->dev);
2897 	pci_set_drvdata(pdev, dev);
2898 
2899 	result = nvme_dev_map(dev);
2900 	if (result)
2901 		goto put_pci;
2902 
2903 	INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2904 	INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2905 	mutex_init(&dev->shutdown_lock);
2906 
2907 	result = nvme_setup_prp_pools(dev);
2908 	if (result)
2909 		goto unmap;
2910 
2911 	quirks |= check_vendor_combination_bug(pdev);
2912 
2913 	if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2914 		/*
2915 		 * Some systems use a bios work around to ask for D3 on
2916 		 * platforms that support kernel managed suspend.
2917 		 */
2918 		dev_info(&pdev->dev,
2919 			 "platform quirk: setting simple suspend\n");
2920 		quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2921 	}
2922 
2923 	/*
2924 	 * Double check that our mempool alloc size will cover the biggest
2925 	 * command we support.
2926 	 */
2927 	alloc_size = nvme_pci_iod_alloc_size();
2928 	WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2929 
2930 	dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2931 						mempool_kfree,
2932 						(void *) alloc_size,
2933 						GFP_KERNEL, node);
2934 	if (!dev->iod_mempool) {
2935 		result = -ENOMEM;
2936 		goto release_pools;
2937 	}
2938 
2939 	result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2940 			quirks);
2941 	if (result)
2942 		goto release_mempool;
2943 
2944 	dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2945 
2946 	nvme_reset_ctrl(&dev->ctrl);
2947 	async_schedule(nvme_async_probe, dev);
2948 
2949 	return 0;
2950 
2951  release_mempool:
2952 	mempool_destroy(dev->iod_mempool);
2953  release_pools:
2954 	nvme_release_prp_pools(dev);
2955  unmap:
2956 	nvme_dev_unmap(dev);
2957  put_pci:
2958 	put_device(dev->dev);
2959  free:
2960 	kfree(dev->queues);
2961 	kfree(dev);
2962 	return result;
2963 }
2964 
nvme_reset_prepare(struct pci_dev * pdev)2965 static void nvme_reset_prepare(struct pci_dev *pdev)
2966 {
2967 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2968 
2969 	/*
2970 	 * We don't need to check the return value from waiting for the reset
2971 	 * state as pci_dev device lock is held, making it impossible to race
2972 	 * with ->remove().
2973 	 */
2974 	nvme_disable_prepare_reset(dev, false);
2975 	nvme_sync_queues(&dev->ctrl);
2976 }
2977 
nvme_reset_done(struct pci_dev * pdev)2978 static void nvme_reset_done(struct pci_dev *pdev)
2979 {
2980 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2981 
2982 	if (!nvme_try_sched_reset(&dev->ctrl))
2983 		flush_work(&dev->ctrl.reset_work);
2984 }
2985 
nvme_shutdown(struct pci_dev * pdev)2986 static void nvme_shutdown(struct pci_dev *pdev)
2987 {
2988 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2989 
2990 	nvme_disable_prepare_reset(dev, true);
2991 }
2992 
2993 /*
2994  * The driver's remove may be called on a device in a partially initialized
2995  * state. This function must not have any dependencies on the device state in
2996  * order to proceed.
2997  */
nvme_remove(struct pci_dev * pdev)2998 static void nvme_remove(struct pci_dev *pdev)
2999 {
3000 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3001 
3002 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3003 	pci_set_drvdata(pdev, NULL);
3004 
3005 	if (!pci_device_is_present(pdev)) {
3006 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3007 		nvme_dev_disable(dev, true);
3008 	}
3009 
3010 	flush_work(&dev->ctrl.reset_work);
3011 	nvme_stop_ctrl(&dev->ctrl);
3012 	nvme_remove_namespaces(&dev->ctrl);
3013 	nvme_dev_disable(dev, true);
3014 	nvme_release_cmb(dev);
3015 	nvme_free_host_mem(dev);
3016 	nvme_dev_remove_admin(dev);
3017 	nvme_free_queues(dev, 0);
3018 	nvme_release_prp_pools(dev);
3019 	nvme_dev_unmap(dev);
3020 	nvme_uninit_ctrl(&dev->ctrl);
3021 }
3022 
3023 #ifdef CONFIG_PM_SLEEP
nvme_get_power_state(struct nvme_ctrl * ctrl,u32 * ps)3024 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3025 {
3026 	return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3027 }
3028 
nvme_set_power_state(struct nvme_ctrl * ctrl,u32 ps)3029 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3030 {
3031 	return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3032 }
3033 
nvme_resume(struct device * dev)3034 static int nvme_resume(struct device *dev)
3035 {
3036 	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3037 	struct nvme_ctrl *ctrl = &ndev->ctrl;
3038 
3039 	if (ndev->last_ps == U32_MAX ||
3040 	    nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3041 		return nvme_try_sched_reset(&ndev->ctrl);
3042 	return 0;
3043 }
3044 
nvme_suspend(struct device * dev)3045 static int nvme_suspend(struct device *dev)
3046 {
3047 	struct pci_dev *pdev = to_pci_dev(dev);
3048 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
3049 	struct nvme_ctrl *ctrl = &ndev->ctrl;
3050 	int ret = -EBUSY;
3051 
3052 	ndev->last_ps = U32_MAX;
3053 
3054 	/*
3055 	 * The platform does not remove power for a kernel managed suspend so
3056 	 * use host managed nvme power settings for lowest idle power if
3057 	 * possible. This should have quicker resume latency than a full device
3058 	 * shutdown.  But if the firmware is involved after the suspend or the
3059 	 * device does not support any non-default power states, shut down the
3060 	 * device fully.
3061 	 *
3062 	 * If ASPM is not enabled for the device, shut down the device and allow
3063 	 * the PCI bus layer to put it into D3 in order to take the PCIe link
3064 	 * down, so as to allow the platform to achieve its minimum low-power
3065 	 * state (which may not be possible if the link is up).
3066 	 *
3067 	 * If a host memory buffer is enabled, shut down the device as the NVMe
3068 	 * specification allows the device to access the host memory buffer in
3069 	 * host DRAM from all power states, but hosts will fail access to DRAM
3070 	 * during S3.
3071 	 */
3072 	if (pm_suspend_via_firmware() || !ctrl->npss ||
3073 	    !pcie_aspm_enabled(pdev) ||
3074 	    ndev->nr_host_mem_descs ||
3075 	    (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3076 		return nvme_disable_prepare_reset(ndev, true);
3077 
3078 	nvme_start_freeze(ctrl);
3079 	nvme_wait_freeze(ctrl);
3080 	nvme_sync_queues(ctrl);
3081 
3082 	if (ctrl->state != NVME_CTRL_LIVE)
3083 		goto unfreeze;
3084 
3085 	ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3086 	if (ret < 0)
3087 		goto unfreeze;
3088 
3089 	/*
3090 	 * A saved state prevents pci pm from generically controlling the
3091 	 * device's power. If we're using protocol specific settings, we don't
3092 	 * want pci interfering.
3093 	 */
3094 	pci_save_state(pdev);
3095 
3096 	ret = nvme_set_power_state(ctrl, ctrl->npss);
3097 	if (ret < 0)
3098 		goto unfreeze;
3099 
3100 	if (ret) {
3101 		/* discard the saved state */
3102 		pci_load_saved_state(pdev, NULL);
3103 
3104 		/*
3105 		 * Clearing npss forces a controller reset on resume. The
3106 		 * correct value will be rediscovered then.
3107 		 */
3108 		ret = nvme_disable_prepare_reset(ndev, true);
3109 		ctrl->npss = 0;
3110 	}
3111 unfreeze:
3112 	nvme_unfreeze(ctrl);
3113 	return ret;
3114 }
3115 
nvme_simple_suspend(struct device * dev)3116 static int nvme_simple_suspend(struct device *dev)
3117 {
3118 	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3119 
3120 	return nvme_disable_prepare_reset(ndev, true);
3121 }
3122 
nvme_simple_resume(struct device * dev)3123 static int nvme_simple_resume(struct device *dev)
3124 {
3125 	struct pci_dev *pdev = to_pci_dev(dev);
3126 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
3127 
3128 	return nvme_try_sched_reset(&ndev->ctrl);
3129 }
3130 
3131 static const struct dev_pm_ops nvme_dev_pm_ops = {
3132 	.suspend	= nvme_suspend,
3133 	.resume		= nvme_resume,
3134 	.freeze		= nvme_simple_suspend,
3135 	.thaw		= nvme_simple_resume,
3136 	.poweroff	= nvme_simple_suspend,
3137 	.restore	= nvme_simple_resume,
3138 };
3139 #endif /* CONFIG_PM_SLEEP */
3140 
nvme_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3141 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3142 						pci_channel_state_t state)
3143 {
3144 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3145 
3146 	/*
3147 	 * A frozen channel requires a reset. When detected, this method will
3148 	 * shutdown the controller to quiesce. The controller will be restarted
3149 	 * after the slot reset through driver's slot_reset callback.
3150 	 */
3151 	switch (state) {
3152 	case pci_channel_io_normal:
3153 		return PCI_ERS_RESULT_CAN_RECOVER;
3154 	case pci_channel_io_frozen:
3155 		dev_warn(dev->ctrl.device,
3156 			"frozen state error detected, reset controller\n");
3157 		nvme_dev_disable(dev, false);
3158 		return PCI_ERS_RESULT_NEED_RESET;
3159 	case pci_channel_io_perm_failure:
3160 		dev_warn(dev->ctrl.device,
3161 			"failure state error detected, request disconnect\n");
3162 		return PCI_ERS_RESULT_DISCONNECT;
3163 	}
3164 	return PCI_ERS_RESULT_NEED_RESET;
3165 }
3166 
nvme_slot_reset(struct pci_dev * pdev)3167 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3168 {
3169 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3170 
3171 	dev_info(dev->ctrl.device, "restart after slot reset\n");
3172 	pci_restore_state(pdev);
3173 	nvme_reset_ctrl(&dev->ctrl);
3174 	return PCI_ERS_RESULT_RECOVERED;
3175 }
3176 
nvme_error_resume(struct pci_dev * pdev)3177 static void nvme_error_resume(struct pci_dev *pdev)
3178 {
3179 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3180 
3181 	flush_work(&dev->ctrl.reset_work);
3182 }
3183 
3184 static const struct pci_error_handlers nvme_err_handler = {
3185 	.error_detected	= nvme_error_detected,
3186 	.slot_reset	= nvme_slot_reset,
3187 	.resume		= nvme_error_resume,
3188 	.reset_prepare	= nvme_reset_prepare,
3189 	.reset_done	= nvme_reset_done,
3190 };
3191 
3192 static const struct pci_device_id nvme_id_table[] = {
3193 	{ PCI_VDEVICE(INTEL, 0x0953),	/* Intel 750/P3500/P3600/P3700 */
3194 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3195 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3196 	{ PCI_VDEVICE(INTEL, 0x0a53),	/* Intel P3520 */
3197 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3198 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3199 	{ PCI_VDEVICE(INTEL, 0x0a54),	/* Intel P4500/P4600 */
3200 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3201 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3202 	{ PCI_VDEVICE(INTEL, 0x0a55),	/* Dell Express Flash P4600 */
3203 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3204 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3205 	{ PCI_VDEVICE(INTEL, 0xf1a5),	/* Intel 600P/P3100 */
3206 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3207 				NVME_QUIRK_MEDIUM_PRIO_SQ |
3208 				NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3209 				NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3210 	{ PCI_VDEVICE(INTEL, 0xf1a6),	/* Intel 760p/Pro 7600p */
3211 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3212 	{ PCI_VDEVICE(INTEL, 0x5845),	/* Qemu emulated controller */
3213 		.driver_data = NVME_QUIRK_IDENTIFY_CNS |
3214 				NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3215 	{ PCI_DEVICE(0x126f, 0x2263),	/* Silicon Motion unidentified */
3216 		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3217 	{ PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3218 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3219 				NVME_QUIRK_NO_NS_DESC_LIST, },
3220 	{ PCI_DEVICE(0x1c58, 0x0003),	/* HGST adapter */
3221 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3222 	{ PCI_DEVICE(0x1c58, 0x0023),	/* WDC SN200 adapter */
3223 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3224 	{ PCI_DEVICE(0x1c5f, 0x0540),	/* Memblaze Pblaze4 adapter */
3225 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3226 	{ PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3227 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3228 	{ PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3229 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3230 				NVME_QUIRK_DISABLE_WRITE_ZEROES|
3231 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3232 	{ PCI_DEVICE(0x1987, 0x5016),	/* Phison E16 */
3233 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3234 	{ PCI_DEVICE(0x1b4b, 0x1092),	/* Lexar 256 GB SSD */
3235 		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3236 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3237 	{ PCI_DEVICE(0x1d1d, 0x1f1f),	/* LighNVM qemu device */
3238 		.driver_data = NVME_QUIRK_LIGHTNVM, },
3239 	{ PCI_DEVICE(0x1d1d, 0x2807),	/* CNEX WL */
3240 		.driver_data = NVME_QUIRK_LIGHTNVM, },
3241 	{ PCI_DEVICE(0x1d1d, 0x2601),	/* CNEX Granby */
3242 		.driver_data = NVME_QUIRK_LIGHTNVM, },
3243 	{ PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3244 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3245 	{ PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3246 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3247 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3248 	{ PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3249 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3250 	{ PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3251 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3252 	{ PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3253 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3254 	{ PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3255 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3256 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3257 		.driver_data = NVME_QUIRK_SINGLE_VECTOR },
3258 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3259 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3260 		.driver_data = NVME_QUIRK_SINGLE_VECTOR |
3261 				NVME_QUIRK_128_BYTES_SQES |
3262 				NVME_QUIRK_SHARED_TAGS |
3263 				NVME_QUIRK_SKIP_CID_GEN },
3264 
3265 	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3266 	{ 0, }
3267 };
3268 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3269 
3270 static struct pci_driver nvme_driver = {
3271 	.name		= "nvme",
3272 	.id_table	= nvme_id_table,
3273 	.probe		= nvme_probe,
3274 	.remove		= nvme_remove,
3275 	.shutdown	= nvme_shutdown,
3276 #ifdef CONFIG_PM_SLEEP
3277 	.driver		= {
3278 		.pm	= &nvme_dev_pm_ops,
3279 	},
3280 #endif
3281 	.sriov_configure = pci_sriov_configure_simple,
3282 	.err_handler	= &nvme_err_handler,
3283 };
3284 
nvme_init(void)3285 static int __init nvme_init(void)
3286 {
3287 	BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3288 	BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3289 	BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3290 	BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3291 
3292 	return pci_register_driver(&nvme_driver);
3293 }
3294 
nvme_exit(void)3295 static void __exit nvme_exit(void)
3296 {
3297 	pci_unregister_driver(&nvme_driver);
3298 	flush_workqueue(nvme_wq);
3299 }
3300 
3301 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3302 MODULE_LICENSE("GPL");
3303 MODULE_VERSION("1.0");
3304 module_init(nvme_init);
3305 module_exit(nvme_exit);
3306