1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx 4 * 5 * Copyright (C) 2011 Nokia Corporation 6 * Paul Walmsley 7 */ 8 9 #include <linux/types.h> 10 11 #include "omap_hwmod.h" 12 #include "omap_hwmod_common_data.h" 13 #include "cm-regbits-24xx.h" 14 #include "prm-regbits-24xx.h" 15 #include "wd_timer.h" 16 17 /* 18 * 'dispc' class 19 * display controller 20 */ 21 22 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = { 23 .rev_offs = 0x0000, 24 .sysc_offs = 0x0010, 25 .syss_offs = 0x0014, 26 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 27 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 29 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 30 .sysc_fields = &omap_hwmod_sysc_type1, 31 }; 32 33 struct omap_hwmod_class omap2_dispc_hwmod_class = { 34 .name = "dispc", 35 .sysc = &omap2_dispc_sysc, 36 }; 37 38 /* OMAP2xxx Timer Common */ 39 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { 40 .rev_offs = 0x0000, 41 .sysc_offs = 0x0010, 42 .syss_offs = 0x0014, 43 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 44 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 45 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 46 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 47 .sysc_fields = &omap_hwmod_sysc_type1, 48 }; 49 50 struct omap_hwmod_class omap2xxx_timer_hwmod_class = { 51 .name = "timer", 52 .sysc = &omap2xxx_timer_sysc, 53 }; 54 55 /* 56 * 'wd_timer' class 57 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 58 * overflow condition 59 */ 60 61 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = { 62 .rev_offs = 0x0000, 63 .sysc_offs = 0x0010, 64 .syss_offs = 0x0014, 65 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | 66 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 67 .sysc_fields = &omap_hwmod_sysc_type1, 68 }; 69 70 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = { 71 .name = "wd_timer", 72 .sysc = &omap2xxx_wd_timer_sysc, 73 .pre_shutdown = &omap2_wd_timer_disable, 74 .reset = &omap2_wd_timer_reset, 75 }; 76 77 /* 78 * 'gpio' class 79 * general purpose io module 80 */ 81 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = { 82 .rev_offs = 0x0000, 83 .sysc_offs = 0x0010, 84 .syss_offs = 0x0014, 85 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 86 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 87 SYSS_HAS_RESET_STATUS), 88 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 89 .sysc_fields = &omap_hwmod_sysc_type1, 90 }; 91 92 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = { 93 .name = "gpio", 94 .sysc = &omap2xxx_gpio_sysc, 95 }; 96 97 /* 98 * 'mailbox' class 99 * mailbox module allowing communication between the on-chip processors 100 * using a queued mailbox-interrupt mechanism. 101 */ 102 103 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = { 104 .rev_offs = 0x000, 105 .sysc_offs = 0x010, 106 .syss_offs = 0x014, 107 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 108 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 109 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 110 .sysc_fields = &omap_hwmod_sysc_type1, 111 }; 112 113 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = { 114 .name = "mailbox", 115 .sysc = &omap2xxx_mailbox_sysc, 116 }; 117 118 /* 119 * 'mcspi' class 120 * multichannel serial port interface (mcspi) / master/slave synchronous serial 121 * bus 122 */ 123 124 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = { 125 .rev_offs = 0x0000, 126 .sysc_offs = 0x0010, 127 .syss_offs = 0x0014, 128 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 129 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 130 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 132 .sysc_fields = &omap_hwmod_sysc_type1, 133 }; 134 135 struct omap_hwmod_class omap2xxx_mcspi_class = { 136 .name = "mcspi", 137 .sysc = &omap2xxx_mcspi_sysc, 138 }; 139 140 /* 141 * 'gpmc' class 142 * general purpose memory controller 143 */ 144 145 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = { 146 .rev_offs = 0x0000, 147 .sysc_offs = 0x0010, 148 .syss_offs = 0x0014, 149 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 150 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 152 .sysc_fields = &omap_hwmod_sysc_type1, 153 }; 154 155 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = { 156 .name = "gpmc", 157 .sysc = &omap2xxx_gpmc_sysc, 158 }; 159 160 /* 161 * IP blocks 162 */ 163 164 /* L3 */ 165 struct omap_hwmod omap2xxx_l3_main_hwmod = { 166 .name = "l3_main", 167 .class = &l3_hwmod_class, 168 .flags = HWMOD_NO_IDLEST, 169 }; 170 171 /* L4 CORE */ 172 struct omap_hwmod omap2xxx_l4_core_hwmod = { 173 .name = "l4_core", 174 .class = &l4_hwmod_class, 175 .flags = HWMOD_NO_IDLEST, 176 }; 177 178 /* L4 WKUP */ 179 struct omap_hwmod omap2xxx_l4_wkup_hwmod = { 180 .name = "l4_wkup", 181 .class = &l4_hwmod_class, 182 .flags = HWMOD_NO_IDLEST, 183 }; 184 185 /* MPU */ 186 struct omap_hwmod omap2xxx_mpu_hwmod = { 187 .name = "mpu", 188 .class = &mpu_hwmod_class, 189 .main_clk = "mpu_ck", 190 }; 191 192 /* IVA2 */ 193 struct omap_hwmod omap2xxx_iva_hwmod = { 194 .name = "iva", 195 .class = &iva_hwmod_class, 196 }; 197 198 /* timer3 */ 199 struct omap_hwmod omap2xxx_timer3_hwmod = { 200 .name = "timer3", 201 .main_clk = "gpt3_fck", 202 .prcm = { 203 .omap2 = { 204 .module_offs = CORE_MOD, 205 .idlest_reg_id = 1, 206 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, 207 }, 208 }, 209 .class = &omap2xxx_timer_hwmod_class, 210 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 211 }; 212 213 /* timer4 */ 214 struct omap_hwmod omap2xxx_timer4_hwmod = { 215 .name = "timer4", 216 .main_clk = "gpt4_fck", 217 .prcm = { 218 .omap2 = { 219 .module_offs = CORE_MOD, 220 .idlest_reg_id = 1, 221 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, 222 }, 223 }, 224 .class = &omap2xxx_timer_hwmod_class, 225 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 226 }; 227 228 /* timer5 */ 229 struct omap_hwmod omap2xxx_timer5_hwmod = { 230 .name = "timer5", 231 .main_clk = "gpt5_fck", 232 .prcm = { 233 .omap2 = { 234 .module_offs = CORE_MOD, 235 .idlest_reg_id = 1, 236 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, 237 }, 238 }, 239 .class = &omap2xxx_timer_hwmod_class, 240 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 241 }; 242 243 /* timer6 */ 244 struct omap_hwmod omap2xxx_timer6_hwmod = { 245 .name = "timer6", 246 .main_clk = "gpt6_fck", 247 .prcm = { 248 .omap2 = { 249 .module_offs = CORE_MOD, 250 .idlest_reg_id = 1, 251 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, 252 }, 253 }, 254 .class = &omap2xxx_timer_hwmod_class, 255 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 256 }; 257 258 /* timer7 */ 259 struct omap_hwmod omap2xxx_timer7_hwmod = { 260 .name = "timer7", 261 .main_clk = "gpt7_fck", 262 .prcm = { 263 .omap2 = { 264 .module_offs = CORE_MOD, 265 .idlest_reg_id = 1, 266 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, 267 }, 268 }, 269 .class = &omap2xxx_timer_hwmod_class, 270 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 271 }; 272 273 /* timer8 */ 274 struct omap_hwmod omap2xxx_timer8_hwmod = { 275 .name = "timer8", 276 .main_clk = "gpt8_fck", 277 .prcm = { 278 .omap2 = { 279 .module_offs = CORE_MOD, 280 .idlest_reg_id = 1, 281 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, 282 }, 283 }, 284 .class = &omap2xxx_timer_hwmod_class, 285 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 286 }; 287 288 /* timer9 */ 289 struct omap_hwmod omap2xxx_timer9_hwmod = { 290 .name = "timer9", 291 .main_clk = "gpt9_fck", 292 .prcm = { 293 .omap2 = { 294 .module_offs = CORE_MOD, 295 .idlest_reg_id = 1, 296 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, 297 }, 298 }, 299 .class = &omap2xxx_timer_hwmod_class, 300 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 301 }; 302 303 /* timer10 */ 304 struct omap_hwmod omap2xxx_timer10_hwmod = { 305 .name = "timer10", 306 .main_clk = "gpt10_fck", 307 .prcm = { 308 .omap2 = { 309 .module_offs = CORE_MOD, 310 .idlest_reg_id = 1, 311 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, 312 }, 313 }, 314 .class = &omap2xxx_timer_hwmod_class, 315 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 316 }; 317 318 /* timer11 */ 319 struct omap_hwmod omap2xxx_timer11_hwmod = { 320 .name = "timer11", 321 .main_clk = "gpt11_fck", 322 .prcm = { 323 .omap2 = { 324 .module_offs = CORE_MOD, 325 .idlest_reg_id = 1, 326 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, 327 }, 328 }, 329 .class = &omap2xxx_timer_hwmod_class, 330 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 331 }; 332 333 /* timer12 */ 334 struct omap_hwmod omap2xxx_timer12_hwmod = { 335 .name = "timer12", 336 .main_clk = "gpt12_fck", 337 .prcm = { 338 .omap2 = { 339 .module_offs = CORE_MOD, 340 .idlest_reg_id = 1, 341 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, 342 }, 343 }, 344 .class = &omap2xxx_timer_hwmod_class, 345 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 346 }; 347 348 /* wd_timer2 */ 349 struct omap_hwmod omap2xxx_wd_timer2_hwmod = { 350 .name = "wd_timer2", 351 .class = &omap2xxx_wd_timer_hwmod_class, 352 .main_clk = "mpu_wdt_fck", 353 .prcm = { 354 .omap2 = { 355 .module_offs = WKUP_MOD, 356 .idlest_reg_id = 1, 357 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, 358 }, 359 }, 360 }; 361 362 /* UART1 */ 363 364 struct omap_hwmod omap2xxx_uart1_hwmod = { 365 .name = "uart1", 366 .main_clk = "uart1_fck", 367 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 368 .prcm = { 369 .omap2 = { 370 .module_offs = CORE_MOD, 371 .idlest_reg_id = 1, 372 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, 373 }, 374 }, 375 .class = &omap2_uart_class, 376 }; 377 378 /* UART2 */ 379 380 struct omap_hwmod omap2xxx_uart2_hwmod = { 381 .name = "uart2", 382 .main_clk = "uart2_fck", 383 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 384 .prcm = { 385 .omap2 = { 386 .module_offs = CORE_MOD, 387 .idlest_reg_id = 1, 388 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, 389 }, 390 }, 391 .class = &omap2_uart_class, 392 }; 393 394 /* UART3 */ 395 396 struct omap_hwmod omap2xxx_uart3_hwmod = { 397 .name = "uart3", 398 .main_clk = "uart3_fck", 399 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 400 .prcm = { 401 .omap2 = { 402 .module_offs = CORE_MOD, 403 .idlest_reg_id = 2, 404 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, 405 }, 406 }, 407 .class = &omap2_uart_class, 408 }; 409 410 /* dss */ 411 412 static struct omap_hwmod_opt_clk dss_opt_clks[] = { 413 /* 414 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 415 * driver does not use these clocks. 416 */ 417 { .role = "tv_clk", .clk = "dss_54m_fck" }, 418 { .role = "sys_clk", .clk = "dss2_fck" }, 419 }; 420 421 struct omap_hwmod omap2xxx_dss_core_hwmod = { 422 .name = "dss_core", 423 .class = &omap2_dss_hwmod_class, 424 .main_clk = "dss1_fck", /* instead of dss_fck */ 425 .prcm = { 426 .omap2 = { 427 .module_offs = CORE_MOD, 428 .idlest_reg_id = 1, 429 }, 430 }, 431 .opt_clks = dss_opt_clks, 432 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 433 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 434 }; 435 436 struct omap_hwmod omap2xxx_dss_dispc_hwmod = { 437 .name = "dss_dispc", 438 .class = &omap2_dispc_hwmod_class, 439 .main_clk = "dss1_fck", 440 .prcm = { 441 .omap2 = { 442 .module_offs = CORE_MOD, 443 .idlest_reg_id = 1, 444 }, 445 }, 446 .flags = HWMOD_NO_IDLEST, 447 .dev_attr = &omap2_3_dss_dispc_dev_attr, 448 }; 449 450 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 451 { .role = "ick", .clk = "dss_ick" }, 452 }; 453 454 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = { 455 .name = "dss_rfbi", 456 .class = &omap2_rfbi_hwmod_class, 457 .main_clk = "dss1_fck", 458 .prcm = { 459 .omap2 = { 460 .module_offs = CORE_MOD, 461 }, 462 }, 463 .opt_clks = dss_rfbi_opt_clks, 464 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 465 .flags = HWMOD_NO_IDLEST, 466 }; 467 468 struct omap_hwmod omap2xxx_dss_venc_hwmod = { 469 .name = "dss_venc", 470 .class = &omap2_venc_hwmod_class, 471 .main_clk = "dss_54m_fck", 472 .prcm = { 473 .omap2 = { 474 .module_offs = CORE_MOD, 475 }, 476 }, 477 .flags = HWMOD_NO_IDLEST, 478 }; 479 480 /* gpio1 */ 481 struct omap_hwmod omap2xxx_gpio1_hwmod = { 482 .name = "gpio1", 483 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 484 .main_clk = "gpios_fck", 485 .prcm = { 486 .omap2 = { 487 .module_offs = WKUP_MOD, 488 .idlest_reg_id = 1, 489 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 490 }, 491 }, 492 .class = &omap2xxx_gpio_hwmod_class, 493 }; 494 495 /* gpio2 */ 496 struct omap_hwmod omap2xxx_gpio2_hwmod = { 497 .name = "gpio2", 498 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 499 .main_clk = "gpios_fck", 500 .prcm = { 501 .omap2 = { 502 .module_offs = WKUP_MOD, 503 .idlest_reg_id = 1, 504 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 505 }, 506 }, 507 .class = &omap2xxx_gpio_hwmod_class, 508 }; 509 510 /* gpio3 */ 511 struct omap_hwmod omap2xxx_gpio3_hwmod = { 512 .name = "gpio3", 513 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 514 .main_clk = "gpios_fck", 515 .prcm = { 516 .omap2 = { 517 .module_offs = WKUP_MOD, 518 .idlest_reg_id = 1, 519 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 520 }, 521 }, 522 .class = &omap2xxx_gpio_hwmod_class, 523 }; 524 525 /* gpio4 */ 526 struct omap_hwmod omap2xxx_gpio4_hwmod = { 527 .name = "gpio4", 528 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 529 .main_clk = "gpios_fck", 530 .prcm = { 531 .omap2 = { 532 .module_offs = WKUP_MOD, 533 .idlest_reg_id = 1, 534 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 535 }, 536 }, 537 .class = &omap2xxx_gpio_hwmod_class, 538 }; 539 540 /* mcspi1 */ 541 struct omap_hwmod omap2xxx_mcspi1_hwmod = { 542 .name = "mcspi1", 543 .main_clk = "mcspi1_fck", 544 .prcm = { 545 .omap2 = { 546 .module_offs = CORE_MOD, 547 .idlest_reg_id = 1, 548 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, 549 }, 550 }, 551 .class = &omap2xxx_mcspi_class, 552 }; 553 554 /* mcspi2 */ 555 struct omap_hwmod omap2xxx_mcspi2_hwmod = { 556 .name = "mcspi2", 557 .main_clk = "mcspi2_fck", 558 .prcm = { 559 .omap2 = { 560 .module_offs = CORE_MOD, 561 .idlest_reg_id = 1, 562 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, 563 }, 564 }, 565 .class = &omap2xxx_mcspi_class, 566 }; 567 568 /* gpmc */ 569 struct omap_hwmod omap2xxx_gpmc_hwmod = { 570 .name = "gpmc", 571 .class = &omap2xxx_gpmc_hwmod_class, 572 .main_clk = "gpmc_fck", 573 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 574 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, 575 .prcm = { 576 .omap2 = { 577 .module_offs = CORE_MOD, 578 }, 579 }, 580 }; 581 582 /* RNG */ 583 584 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = { 585 .rev_offs = 0x3c, 586 .sysc_offs = 0x40, 587 .syss_offs = 0x44, 588 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 589 SYSS_HAS_RESET_STATUS), 590 .sysc_fields = &omap_hwmod_sysc_type1, 591 }; 592 593 static struct omap_hwmod_class omap2_rng_hwmod_class = { 594 .name = "rng", 595 .sysc = &omap2_rng_sysc, 596 }; 597 598 struct omap_hwmod omap2xxx_rng_hwmod = { 599 .name = "rng", 600 .main_clk = "l4_ck", 601 .prcm = { 602 .omap2 = { 603 .module_offs = CORE_MOD, 604 .idlest_reg_id = 4, 605 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT, 606 }, 607 }, 608 /* 609 * XXX The first read from the SYSSTATUS register of the RNG 610 * after the SYSCONFIG SOFTRESET bit is set triggers an 611 * imprecise external abort. It's unclear why this happens. 612 * Until this is analyzed, skip the IP block reset. 613 */ 614 .flags = HWMOD_INIT_NO_RESET, 615 .class = &omap2_rng_hwmod_class, 616 }; 617 618 /* SHAM */ 619 620 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = { 621 .rev_offs = 0x5c, 622 .sysc_offs = 0x60, 623 .syss_offs = 0x64, 624 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 625 SYSS_HAS_RESET_STATUS), 626 .sysc_fields = &omap_hwmod_sysc_type1, 627 }; 628 629 static struct omap_hwmod_class omap2xxx_sham_class = { 630 .name = "sham", 631 .sysc = &omap2_sham_sysc, 632 }; 633 634 struct omap_hwmod omap2xxx_sham_hwmod = { 635 .name = "sham", 636 .main_clk = "l4_ck", 637 .prcm = { 638 .omap2 = { 639 .module_offs = CORE_MOD, 640 .idlest_reg_id = 4, 641 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT, 642 }, 643 }, 644 .class = &omap2xxx_sham_class, 645 }; 646 647 /* AES */ 648 649 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = { 650 .rev_offs = 0x44, 651 .sysc_offs = 0x48, 652 .syss_offs = 0x4c, 653 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 654 SYSS_HAS_RESET_STATUS), 655 .sysc_fields = &omap_hwmod_sysc_type1, 656 }; 657 658 static struct omap_hwmod_class omap2xxx_aes_class = { 659 .name = "aes", 660 .sysc = &omap2_aes_sysc, 661 }; 662 663 struct omap_hwmod omap2xxx_aes_hwmod = { 664 .name = "aes", 665 .main_clk = "l4_ck", 666 .prcm = { 667 .omap2 = { 668 .module_offs = CORE_MOD, 669 .idlest_reg_id = 4, 670 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT, 671 }, 672 }, 673 .class = &omap2xxx_aes_class, 674 }; 675