1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx 4 * 5 * Copyright (C) 2009-2011 Nokia Corporation 6 * Paul Walmsley 7 * 8 * XXX handle crossbar/shared link difference for L3? 9 * XXX these should be marked initdata for multi-OMAP kernels 10 */ 11 #include <linux/sizes.h> 12 13 #include "omap_hwmod.h" 14 #include "l3_2xxx.h" 15 #include "l4_2xxx.h" 16 #include "serial.h" 17 18 #include "omap_hwmod_common_data.h" 19 20 /* 21 * Common interconnect data 22 */ 23 24 /* L3 -> L4_CORE interface */ 25 struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = { 26 .master = &omap2xxx_l3_main_hwmod, 27 .slave = &omap2xxx_l4_core_hwmod, 28 .user = OCP_USER_MPU | OCP_USER_SDMA, 29 }; 30 31 /* MPU -> L3 interface */ 32 struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = { 33 .master = &omap2xxx_mpu_hwmod, 34 .slave = &omap2xxx_l3_main_hwmod, 35 .user = OCP_USER_MPU, 36 }; 37 38 /* DSS -> l3 */ 39 struct omap_hwmod_ocp_if omap2xxx_dss__l3 = { 40 .master = &omap2xxx_dss_core_hwmod, 41 .slave = &omap2xxx_l3_main_hwmod, 42 .fw = { 43 .omap2 = { 44 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, 45 .flags = OMAP_FIREWALL_L3, 46 }, 47 }, 48 .user = OCP_USER_MPU | OCP_USER_SDMA, 49 }; 50 51 /* L4_CORE -> L4_WKUP interface */ 52 struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = { 53 .master = &omap2xxx_l4_core_hwmod, 54 .slave = &omap2xxx_l4_wkup_hwmod, 55 .user = OCP_USER_MPU | OCP_USER_SDMA, 56 }; 57 58 /* L4 CORE -> UART1 interface */ 59 struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { 60 .master = &omap2xxx_l4_core_hwmod, 61 .slave = &omap2xxx_uart1_hwmod, 62 .clk = "uart1_ick", 63 .user = OCP_USER_MPU | OCP_USER_SDMA, 64 }; 65 66 /* L4 CORE -> UART2 interface */ 67 struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { 68 .master = &omap2xxx_l4_core_hwmod, 69 .slave = &omap2xxx_uart2_hwmod, 70 .clk = "uart2_ick", 71 .user = OCP_USER_MPU | OCP_USER_SDMA, 72 }; 73 74 /* L4 PER -> UART3 interface */ 75 struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 76 .master = &omap2xxx_l4_core_hwmod, 77 .slave = &omap2xxx_uart3_hwmod, 78 .clk = "uart3_ick", 79 .user = OCP_USER_MPU | OCP_USER_SDMA, 80 }; 81 82 /* l4 core -> mcspi1 interface */ 83 struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = { 84 .master = &omap2xxx_l4_core_hwmod, 85 .slave = &omap2xxx_mcspi1_hwmod, 86 .clk = "mcspi1_ick", 87 .user = OCP_USER_MPU | OCP_USER_SDMA, 88 }; 89 90 /* l4 core -> mcspi2 interface */ 91 struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = { 92 .master = &omap2xxx_l4_core_hwmod, 93 .slave = &omap2xxx_mcspi2_hwmod, 94 .clk = "mcspi2_ick", 95 .user = OCP_USER_MPU | OCP_USER_SDMA, 96 }; 97 98 /* l4_core -> timer3 */ 99 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = { 100 .master = &omap2xxx_l4_core_hwmod, 101 .slave = &omap2xxx_timer3_hwmod, 102 .clk = "gpt3_ick", 103 .user = OCP_USER_MPU | OCP_USER_SDMA, 104 }; 105 106 /* l4_core -> timer4 */ 107 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = { 108 .master = &omap2xxx_l4_core_hwmod, 109 .slave = &omap2xxx_timer4_hwmod, 110 .clk = "gpt4_ick", 111 .user = OCP_USER_MPU | OCP_USER_SDMA, 112 }; 113 114 /* l4_core -> timer5 */ 115 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = { 116 .master = &omap2xxx_l4_core_hwmod, 117 .slave = &omap2xxx_timer5_hwmod, 118 .clk = "gpt5_ick", 119 .user = OCP_USER_MPU | OCP_USER_SDMA, 120 }; 121 122 /* l4_core -> timer6 */ 123 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = { 124 .master = &omap2xxx_l4_core_hwmod, 125 .slave = &omap2xxx_timer6_hwmod, 126 .clk = "gpt6_ick", 127 .user = OCP_USER_MPU | OCP_USER_SDMA, 128 }; 129 130 /* l4_core -> timer7 */ 131 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = { 132 .master = &omap2xxx_l4_core_hwmod, 133 .slave = &omap2xxx_timer7_hwmod, 134 .clk = "gpt7_ick", 135 .user = OCP_USER_MPU | OCP_USER_SDMA, 136 }; 137 138 /* l4_core -> timer8 */ 139 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = { 140 .master = &omap2xxx_l4_core_hwmod, 141 .slave = &omap2xxx_timer8_hwmod, 142 .clk = "gpt8_ick", 143 .user = OCP_USER_MPU | OCP_USER_SDMA, 144 }; 145 146 /* l4_core -> timer9 */ 147 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = { 148 .master = &omap2xxx_l4_core_hwmod, 149 .slave = &omap2xxx_timer9_hwmod, 150 .clk = "gpt9_ick", 151 .user = OCP_USER_MPU | OCP_USER_SDMA, 152 }; 153 154 /* l4_core -> timer10 */ 155 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = { 156 .master = &omap2xxx_l4_core_hwmod, 157 .slave = &omap2xxx_timer10_hwmod, 158 .clk = "gpt10_ick", 159 .user = OCP_USER_MPU | OCP_USER_SDMA, 160 }; 161 162 /* l4_core -> timer11 */ 163 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = { 164 .master = &omap2xxx_l4_core_hwmod, 165 .slave = &omap2xxx_timer11_hwmod, 166 .clk = "gpt11_ick", 167 .user = OCP_USER_MPU | OCP_USER_SDMA, 168 }; 169 170 /* l4_core -> timer12 */ 171 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = { 172 .master = &omap2xxx_l4_core_hwmod, 173 .slave = &omap2xxx_timer12_hwmod, 174 .clk = "gpt12_ick", 175 .user = OCP_USER_MPU | OCP_USER_SDMA, 176 }; 177 178 /* l4_core -> dss */ 179 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = { 180 .master = &omap2xxx_l4_core_hwmod, 181 .slave = &omap2xxx_dss_core_hwmod, 182 .clk = "dss_ick", 183 .fw = { 184 .omap2 = { 185 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 186 .flags = OMAP_FIREWALL_L4, 187 }, 188 }, 189 .user = OCP_USER_MPU | OCP_USER_SDMA, 190 }; 191 192 /* l4_core -> dss_dispc */ 193 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = { 194 .master = &omap2xxx_l4_core_hwmod, 195 .slave = &omap2xxx_dss_dispc_hwmod, 196 .clk = "dss_ick", 197 .fw = { 198 .omap2 = { 199 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 200 .flags = OMAP_FIREWALL_L4, 201 }, 202 }, 203 .user = OCP_USER_MPU | OCP_USER_SDMA, 204 }; 205 206 /* l4_core -> dss_rfbi */ 207 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = { 208 .master = &omap2xxx_l4_core_hwmod, 209 .slave = &omap2xxx_dss_rfbi_hwmod, 210 .clk = "dss_ick", 211 .fw = { 212 .omap2 = { 213 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 214 .flags = OMAP_FIREWALL_L4, 215 }, 216 }, 217 .user = OCP_USER_MPU | OCP_USER_SDMA, 218 }; 219 220 /* l4_core -> dss_venc */ 221 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = { 222 .master = &omap2xxx_l4_core_hwmod, 223 .slave = &omap2xxx_dss_venc_hwmod, 224 .clk = "dss_ick", 225 .fw = { 226 .omap2 = { 227 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 228 .flags = OMAP_FIREWALL_L4, 229 }, 230 }, 231 .flags = OCPIF_SWSUP_IDLE, 232 .user = OCP_USER_MPU | OCP_USER_SDMA, 233 }; 234 235 /* l4_core -> rng */ 236 struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = { 237 .master = &omap2xxx_l4_core_hwmod, 238 .slave = &omap2xxx_rng_hwmod, 239 .clk = "rng_ick", 240 .user = OCP_USER_MPU | OCP_USER_SDMA, 241 }; 242 243 /* l4 core -> sham interface */ 244 struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = { 245 .master = &omap2xxx_l4_core_hwmod, 246 .slave = &omap2xxx_sham_hwmod, 247 .clk = "sha_ick", 248 .user = OCP_USER_MPU | OCP_USER_SDMA, 249 }; 250 251 /* l4 core -> aes interface */ 252 struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = { 253 .master = &omap2xxx_l4_core_hwmod, 254 .slave = &omap2xxx_aes_hwmod, 255 .clk = "aes_ick", 256 .user = OCP_USER_MPU | OCP_USER_SDMA, 257 }; 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