1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 RVU Physcial Function ethernet driver
3 *
4 * Copyright (C) 2020 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/etherdevice.h>
15 #include <linux/of.h>
16 #include <linux/if_vlan.h>
17 #include <linux/iommu.h>
18 #include <net/ip.h>
19
20 #include "otx2_reg.h"
21 #include "otx2_common.h"
22 #include "otx2_txrx.h"
23 #include "otx2_struct.h"
24 #include "otx2_ptp.h"
25 #include <rvu_trace.h>
26
27 #define DRV_NAME "octeontx2-nicpf"
28 #define DRV_STRING "Marvell OcteonTX2 NIC Physical Function Driver"
29
30 /* Supported devices */
31 static const struct pci_device_id otx2_pf_id_table[] = {
32 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) },
33 { 0, } /* end of table */
34 };
35
36 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
37 MODULE_DESCRIPTION(DRV_STRING);
38 MODULE_LICENSE("GPL v2");
39 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table);
40
41 enum {
42 TYPE_PFAF,
43 TYPE_PFVF,
44 };
45
46 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable);
47 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable);
48
otx2_change_mtu(struct net_device * netdev,int new_mtu)49 static int otx2_change_mtu(struct net_device *netdev, int new_mtu)
50 {
51 bool if_up = netif_running(netdev);
52 int err = 0;
53
54 if (if_up)
55 otx2_stop(netdev);
56
57 netdev_info(netdev, "Changing MTU from %d to %d\n",
58 netdev->mtu, new_mtu);
59 netdev->mtu = new_mtu;
60
61 if (if_up)
62 err = otx2_open(netdev);
63
64 return err;
65 }
66
otx2_disable_flr_me_intr(struct otx2_nic * pf)67 static void otx2_disable_flr_me_intr(struct otx2_nic *pf)
68 {
69 int irq, vfs = pf->total_vfs;
70
71 /* Disable VFs ME interrupts */
72 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
73 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0);
74 free_irq(irq, pf);
75
76 /* Disable VFs FLR interrupts */
77 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
78 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0);
79 free_irq(irq, pf);
80
81 if (vfs <= 64)
82 return;
83
84 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
85 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1);
86 free_irq(irq, pf);
87
88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1);
90 free_irq(irq, pf);
91 }
92
otx2_flr_wq_destroy(struct otx2_nic * pf)93 static void otx2_flr_wq_destroy(struct otx2_nic *pf)
94 {
95 if (!pf->flr_wq)
96 return;
97 destroy_workqueue(pf->flr_wq);
98 pf->flr_wq = NULL;
99 devm_kfree(pf->dev, pf->flr_wrk);
100 }
101
otx2_flr_handler(struct work_struct * work)102 static void otx2_flr_handler(struct work_struct *work)
103 {
104 struct flr_work *flrwork = container_of(work, struct flr_work, work);
105 struct otx2_nic *pf = flrwork->pf;
106 struct mbox *mbox = &pf->mbox;
107 struct msg_req *req;
108 int vf, reg = 0;
109
110 vf = flrwork - pf->flr_wrk;
111
112 mutex_lock(&mbox->lock);
113 req = otx2_mbox_alloc_msg_vf_flr(mbox);
114 if (!req) {
115 mutex_unlock(&mbox->lock);
116 return;
117 }
118 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK;
119 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK;
120
121 if (!otx2_sync_mbox_msg(&pf->mbox)) {
122 if (vf >= 64) {
123 reg = 1;
124 vf = vf - 64;
125 }
126 /* clear transcation pending bit */
127 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
128 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
129 }
130
131 mutex_unlock(&mbox->lock);
132 }
133
otx2_pf_flr_intr_handler(int irq,void * pf_irq)134 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq)
135 {
136 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
137 int reg, dev, vf, start_vf, num_reg = 1;
138 u64 intr;
139
140 if (pf->total_vfs > 64)
141 num_reg = 2;
142
143 for (reg = 0; reg < num_reg; reg++) {
144 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg));
145 if (!intr)
146 continue;
147 start_vf = 64 * reg;
148 for (vf = 0; vf < 64; vf++) {
149 if (!(intr & BIT_ULL(vf)))
150 continue;
151 dev = vf + start_vf;
152 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work);
153 /* Clear interrupt */
154 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
155 /* Disable the interrupt */
156 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg),
157 BIT_ULL(vf));
158 }
159 }
160 return IRQ_HANDLED;
161 }
162
otx2_pf_me_intr_handler(int irq,void * pf_irq)163 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq)
164 {
165 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
166 int vf, reg, num_reg = 1;
167 u64 intr;
168
169 if (pf->total_vfs > 64)
170 num_reg = 2;
171
172 for (reg = 0; reg < num_reg; reg++) {
173 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg));
174 if (!intr)
175 continue;
176 for (vf = 0; vf < 64; vf++) {
177 if (!(intr & BIT_ULL(vf)))
178 continue;
179 /* clear trpend bit */
180 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
181 /* clear interrupt */
182 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf));
183 }
184 }
185 return IRQ_HANDLED;
186 }
187
otx2_register_flr_me_intr(struct otx2_nic * pf,int numvfs)188 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs)
189 {
190 struct otx2_hw *hw = &pf->hw;
191 char *irq_name;
192 int ret;
193
194 /* Register ME interrupt handler*/
195 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE];
196 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc));
197 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0),
198 otx2_pf_me_intr_handler, 0, irq_name, pf);
199 if (ret) {
200 dev_err(pf->dev,
201 "RVUPF: IRQ registration failed for ME0\n");
202 }
203
204 /* Register FLR interrupt handler */
205 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE];
206 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc));
207 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0),
208 otx2_pf_flr_intr_handler, 0, irq_name, pf);
209 if (ret) {
210 dev_err(pf->dev,
211 "RVUPF: IRQ registration failed for FLR0\n");
212 return ret;
213 }
214
215 if (numvfs > 64) {
216 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE];
217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1",
218 rvu_get_pf(pf->pcifunc));
219 ret = request_irq(pci_irq_vector
220 (pf->pdev, RVU_PF_INT_VEC_VFME1),
221 otx2_pf_me_intr_handler, 0, irq_name, pf);
222 if (ret) {
223 dev_err(pf->dev,
224 "RVUPF: IRQ registration failed for ME1\n");
225 }
226 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE];
227 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1",
228 rvu_get_pf(pf->pcifunc));
229 ret = request_irq(pci_irq_vector
230 (pf->pdev, RVU_PF_INT_VEC_VFFLR1),
231 otx2_pf_flr_intr_handler, 0, irq_name, pf);
232 if (ret) {
233 dev_err(pf->dev,
234 "RVUPF: IRQ registration failed for FLR1\n");
235 return ret;
236 }
237 }
238
239 /* Enable ME interrupt for all VFs*/
240 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs));
241 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs));
242
243 /* Enable FLR interrupt for all VFs*/
244 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs));
245 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs));
246
247 if (numvfs > 64) {
248 numvfs -= 64;
249
250 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs));
251 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1),
252 INTR_MASK(numvfs));
253
254 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs));
255 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1),
256 INTR_MASK(numvfs));
257 }
258 return 0;
259 }
260
otx2_pf_flr_init(struct otx2_nic * pf,int num_vfs)261 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs)
262 {
263 int vf;
264
265 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq",
266 WQ_UNBOUND | WQ_HIGHPRI, 1);
267 if (!pf->flr_wq)
268 return -ENOMEM;
269
270 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs,
271 sizeof(struct flr_work), GFP_KERNEL);
272 if (!pf->flr_wrk) {
273 destroy_workqueue(pf->flr_wq);
274 return -ENOMEM;
275 }
276
277 for (vf = 0; vf < num_vfs; vf++) {
278 pf->flr_wrk[vf].pf = pf;
279 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler);
280 }
281
282 return 0;
283 }
284
otx2_queue_work(struct mbox * mw,struct workqueue_struct * mbox_wq,int first,int mdevs,u64 intr,int type)285 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq,
286 int first, int mdevs, u64 intr, int type)
287 {
288 struct otx2_mbox_dev *mdev;
289 struct otx2_mbox *mbox;
290 struct mbox_hdr *hdr;
291 int i;
292
293 for (i = first; i < mdevs; i++) {
294 /* start from 0 */
295 if (!(intr & BIT_ULL(i - first)))
296 continue;
297
298 mbox = &mw->mbox;
299 mdev = &mbox->dev[i];
300 if (type == TYPE_PFAF)
301 otx2_sync_mbox_bbuf(mbox, i);
302 hdr = mdev->mbase + mbox->rx_start;
303 /* The hdr->num_msgs is set to zero immediately in the interrupt
304 * handler to ensure that it holds a correct value next time
305 * when the interrupt handler is called.
306 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
307 * pf>mbox.up_num_msgs holds the data for use in
308 * pfaf_mbox_up_handler.
309 */
310 if (hdr->num_msgs) {
311 mw[i].num_msgs = hdr->num_msgs;
312 hdr->num_msgs = 0;
313 if (type == TYPE_PFAF)
314 memset(mbox->hwbase + mbox->rx_start, 0,
315 ALIGN(sizeof(struct mbox_hdr),
316 sizeof(u64)));
317
318 queue_work(mbox_wq, &mw[i].mbox_wrk);
319 }
320
321 mbox = &mw->mbox_up;
322 mdev = &mbox->dev[i];
323 if (type == TYPE_PFAF)
324 otx2_sync_mbox_bbuf(mbox, i);
325 hdr = mdev->mbase + mbox->rx_start;
326 if (hdr->num_msgs) {
327 mw[i].up_num_msgs = hdr->num_msgs;
328 hdr->num_msgs = 0;
329 if (type == TYPE_PFAF)
330 memset(mbox->hwbase + mbox->rx_start, 0,
331 ALIGN(sizeof(struct mbox_hdr),
332 sizeof(u64)));
333
334 queue_work(mbox_wq, &mw[i].mbox_up_wrk);
335 }
336 }
337 }
338
otx2_forward_msg_pfvf(struct otx2_mbox_dev * mdev,struct otx2_mbox * pfvf_mbox,void * bbuf_base,int devid)339 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev,
340 struct otx2_mbox *pfvf_mbox, void *bbuf_base,
341 int devid)
342 {
343 struct otx2_mbox_dev *src_mdev = mdev;
344 int offset;
345
346 /* Msgs are already copied, trigger VF's mbox irq */
347 smp_wmb();
348
349 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift);
350 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset);
351
352 /* Restore VF's mbox bounce buffer region address */
353 src_mdev->mbase = bbuf_base;
354 }
355
otx2_forward_vf_mbox_msgs(struct otx2_nic * pf,struct otx2_mbox * src_mbox,int dir,int vf,int num_msgs)356 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf,
357 struct otx2_mbox *src_mbox,
358 int dir, int vf, int num_msgs)
359 {
360 struct otx2_mbox_dev *src_mdev, *dst_mdev;
361 struct mbox_hdr *mbox_hdr;
362 struct mbox_hdr *req_hdr;
363 struct mbox *dst_mbox;
364 int dst_size, err;
365
366 if (dir == MBOX_DIR_PFAF) {
367 /* Set VF's mailbox memory as PF's bounce buffer memory, so
368 * that explicit copying of VF's msgs to PF=>AF mbox region
369 * and AF=>PF responses to VF's mbox region can be avoided.
370 */
371 src_mdev = &src_mbox->dev[vf];
372 mbox_hdr = src_mbox->hwbase +
373 src_mbox->rx_start + (vf * MBOX_SIZE);
374
375 dst_mbox = &pf->mbox;
376 dst_size = dst_mbox->mbox.tx_size -
377 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
378 /* Check if msgs fit into destination area and has valid size */
379 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size)
380 return -EINVAL;
381
382 dst_mdev = &dst_mbox->mbox.dev[0];
383
384 mutex_lock(&pf->mbox.lock);
385 dst_mdev->mbase = src_mdev->mbase;
386 dst_mdev->msg_size = mbox_hdr->msg_size;
387 dst_mdev->num_msgs = num_msgs;
388 err = otx2_sync_mbox_msg(dst_mbox);
389 /* Error code -EIO indicate there is a communication failure
390 * to the AF. Rest of the error codes indicate that AF processed
391 * VF messages and set the error codes in response messages
392 * (if any) so simply forward responses to VF.
393 */
394 if (err == -EIO) {
395 dev_warn(pf->dev,
396 "AF not responding to VF%d messages\n", vf);
397 /* restore PF mbase and exit */
398 dst_mdev->mbase = pf->mbox.bbuf_base;
399 mutex_unlock(&pf->mbox.lock);
400 return err;
401 }
402 /* At this point, all the VF messages sent to AF are acked
403 * with proper responses and responses are copied to VF
404 * mailbox hence raise interrupt to VF.
405 */
406 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase +
407 dst_mbox->mbox.rx_start);
408 req_hdr->num_msgs = num_msgs;
409
410 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox,
411 pf->mbox.bbuf_base, vf);
412 mutex_unlock(&pf->mbox.lock);
413 } else if (dir == MBOX_DIR_PFVF_UP) {
414 src_mdev = &src_mbox->dev[0];
415 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start;
416 req_hdr = (struct mbox_hdr *)(src_mdev->mbase +
417 src_mbox->rx_start);
418 req_hdr->num_msgs = num_msgs;
419
420 dst_mbox = &pf->mbox_pfvf[0];
421 dst_size = dst_mbox->mbox_up.tx_size -
422 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
423 /* Check if msgs fit into destination area */
424 if (mbox_hdr->msg_size > dst_size)
425 return -EINVAL;
426
427 dst_mdev = &dst_mbox->mbox_up.dev[vf];
428 dst_mdev->mbase = src_mdev->mbase;
429 dst_mdev->msg_size = mbox_hdr->msg_size;
430 dst_mdev->num_msgs = mbox_hdr->num_msgs;
431 err = otx2_sync_mbox_up_msg(dst_mbox, vf);
432 if (err) {
433 dev_warn(pf->dev,
434 "VF%d is not responding to mailbox\n", vf);
435 return err;
436 }
437 } else if (dir == MBOX_DIR_VFPF_UP) {
438 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase +
439 src_mbox->rx_start);
440 req_hdr->num_msgs = num_msgs;
441 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf],
442 &pf->mbox.mbox_up,
443 pf->mbox_pfvf[vf].bbuf_base,
444 0);
445 }
446
447 return 0;
448 }
449
otx2_pfvf_mbox_handler(struct work_struct * work)450 static void otx2_pfvf_mbox_handler(struct work_struct *work)
451 {
452 struct mbox_msghdr *msg = NULL;
453 int offset, vf_idx, id, err;
454 struct otx2_mbox_dev *mdev;
455 struct mbox_hdr *req_hdr;
456 struct otx2_mbox *mbox;
457 struct mbox *vf_mbox;
458 struct otx2_nic *pf;
459
460 vf_mbox = container_of(work, struct mbox, mbox_wrk);
461 pf = vf_mbox->pfvf;
462 vf_idx = vf_mbox - pf->mbox_pfvf;
463
464 mbox = &pf->mbox_pfvf[0].mbox;
465 mdev = &mbox->dev[vf_idx];
466 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
467
468 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
469
470 for (id = 0; id < vf_mbox->num_msgs; id++) {
471 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start +
472 offset);
473
474 if (msg->sig != OTX2_MBOX_REQ_SIG)
475 goto inval_msg;
476
477 /* Set VF's number in each of the msg */
478 msg->pcifunc &= RVU_PFVF_FUNC_MASK;
479 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK;
480 offset = msg->next_msgoff;
481 }
482 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx,
483 vf_mbox->num_msgs);
484 if (err)
485 goto inval_msg;
486 return;
487
488 inval_msg:
489 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id);
490 otx2_mbox_msg_send(mbox, vf_idx);
491 }
492
otx2_pfvf_mbox_up_handler(struct work_struct * work)493 static void otx2_pfvf_mbox_up_handler(struct work_struct *work)
494 {
495 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
496 struct otx2_nic *pf = vf_mbox->pfvf;
497 struct otx2_mbox_dev *mdev;
498 int offset, id, vf_idx = 0;
499 struct mbox_hdr *rsp_hdr;
500 struct mbox_msghdr *msg;
501 struct otx2_mbox *mbox;
502
503 vf_idx = vf_mbox - pf->mbox_pfvf;
504 mbox = &pf->mbox_pfvf[0].mbox_up;
505 mdev = &mbox->dev[vf_idx];
506
507 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
508 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
509
510 for (id = 0; id < vf_mbox->up_num_msgs; id++) {
511 msg = mdev->mbase + offset;
512
513 if (msg->id >= MBOX_MSG_MAX) {
514 dev_err(pf->dev,
515 "Mbox msg with unknown ID 0x%x\n", msg->id);
516 goto end;
517 }
518
519 if (msg->sig != OTX2_MBOX_RSP_SIG) {
520 dev_err(pf->dev,
521 "Mbox msg with wrong signature %x, ID 0x%x\n",
522 msg->sig, msg->id);
523 goto end;
524 }
525
526 switch (msg->id) {
527 case MBOX_MSG_CGX_LINK_EVENT:
528 break;
529 default:
530 if (msg->rc)
531 dev_err(pf->dev,
532 "Mbox msg response has err %d, ID 0x%x\n",
533 msg->rc, msg->id);
534 break;
535 }
536
537 end:
538 offset = mbox->rx_start + msg->next_msgoff;
539 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1))
540 __otx2_mbox_reset(mbox, 0);
541 mdev->msgs_acked++;
542 }
543 }
544
otx2_pfvf_mbox_intr_handler(int irq,void * pf_irq)545 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq)
546 {
547 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq);
548 int vfs = pf->total_vfs;
549 struct mbox *mbox;
550 u64 intr;
551
552 mbox = pf->mbox_pfvf;
553 /* Handle VF interrupts */
554 if (vfs > 64) {
555 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1));
556 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr);
557 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr,
558 TYPE_PFVF);
559 vfs -= 64;
560 }
561
562 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0));
563 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr);
564
565 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF);
566
567 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr);
568
569 return IRQ_HANDLED;
570 }
571
otx2_pfvf_mbox_init(struct otx2_nic * pf,int numvfs)572 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs)
573 {
574 void __iomem *hwbase;
575 struct mbox *mbox;
576 int err, vf;
577 u64 base;
578
579 if (!numvfs)
580 return -EINVAL;
581
582 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs,
583 sizeof(struct mbox), GFP_KERNEL);
584 if (!pf->mbox_pfvf)
585 return -ENOMEM;
586
587 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox",
588 WQ_UNBOUND | WQ_HIGHPRI |
589 WQ_MEM_RECLAIM, 1);
590 if (!pf->mbox_pfvf_wq)
591 return -ENOMEM;
592
593 base = readq((void __iomem *)((u64)pf->reg_base + RVU_PF_VF_BAR4_ADDR));
594 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs);
595
596 if (!hwbase) {
597 err = -ENOMEM;
598 goto free_wq;
599 }
600
601 mbox = &pf->mbox_pfvf[0];
602 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
603 MBOX_DIR_PFVF, numvfs);
604 if (err)
605 goto free_iomem;
606
607 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
608 MBOX_DIR_PFVF_UP, numvfs);
609 if (err)
610 goto free_iomem;
611
612 for (vf = 0; vf < numvfs; vf++) {
613 mbox->pfvf = pf;
614 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler);
615 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler);
616 mbox++;
617 }
618
619 return 0;
620
621 free_iomem:
622 if (hwbase)
623 iounmap(hwbase);
624 free_wq:
625 destroy_workqueue(pf->mbox_pfvf_wq);
626 return err;
627 }
628
otx2_pfvf_mbox_destroy(struct otx2_nic * pf)629 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf)
630 {
631 struct mbox *mbox = &pf->mbox_pfvf[0];
632
633 if (!mbox)
634 return;
635
636 if (pf->mbox_pfvf_wq) {
637 destroy_workqueue(pf->mbox_pfvf_wq);
638 pf->mbox_pfvf_wq = NULL;
639 }
640
641 if (mbox->mbox.hwbase)
642 iounmap(mbox->mbox.hwbase);
643
644 otx2_mbox_destroy(&mbox->mbox);
645 }
646
otx2_enable_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)647 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
648 {
649 /* Clear PF <=> VF mailbox IRQ */
650 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
651 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
652
653 /* Enable PF <=> VF mailbox IRQ */
654 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs));
655 if (numvfs > 64) {
656 numvfs -= 64;
657 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
658 INTR_MASK(numvfs));
659 }
660 }
661
otx2_disable_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)662 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
663 {
664 int vector;
665
666 /* Disable PF <=> VF mailbox IRQ */
667 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull);
668 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull);
669
670 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
671 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0);
672 free_irq(vector, pf);
673
674 if (numvfs > 64) {
675 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
676 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1);
677 free_irq(vector, pf);
678 }
679 }
680
otx2_register_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)681 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
682 {
683 struct otx2_hw *hw = &pf->hw;
684 char *irq_name;
685 int err;
686
687 /* Register MBOX0 interrupt handler */
688 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE];
689 if (pf->pcifunc)
690 snprintf(irq_name, NAME_SIZE,
691 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc));
692 else
693 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0");
694 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0),
695 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf);
696 if (err) {
697 dev_err(pf->dev,
698 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n");
699 return err;
700 }
701
702 if (numvfs > 64) {
703 /* Register MBOX1 interrupt handler */
704 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE];
705 if (pf->pcifunc)
706 snprintf(irq_name, NAME_SIZE,
707 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc));
708 else
709 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1");
710 err = request_irq(pci_irq_vector(pf->pdev,
711 RVU_PF_INT_VEC_VFPF_MBOX1),
712 otx2_pfvf_mbox_intr_handler,
713 0, irq_name, pf);
714 if (err) {
715 dev_err(pf->dev,
716 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n");
717 return err;
718 }
719 }
720
721 otx2_enable_pfvf_mbox_intr(pf, numvfs);
722
723 return 0;
724 }
725
otx2_process_pfaf_mbox_msg(struct otx2_nic * pf,struct mbox_msghdr * msg)726 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf,
727 struct mbox_msghdr *msg)
728 {
729 int devid;
730
731 if (msg->id >= MBOX_MSG_MAX) {
732 dev_err(pf->dev,
733 "Mbox msg with unknown ID 0x%x\n", msg->id);
734 return;
735 }
736
737 if (msg->sig != OTX2_MBOX_RSP_SIG) {
738 dev_err(pf->dev,
739 "Mbox msg with wrong signature %x, ID 0x%x\n",
740 msg->sig, msg->id);
741 return;
742 }
743
744 /* message response heading VF */
745 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
746 if (devid) {
747 struct otx2_vf_config *config = &pf->vf_configs[devid - 1];
748 struct delayed_work *dwork;
749
750 switch (msg->id) {
751 case MBOX_MSG_NIX_LF_START_RX:
752 config->intf_down = false;
753 dwork = &config->link_event_work;
754 schedule_delayed_work(dwork, msecs_to_jiffies(100));
755 break;
756 case MBOX_MSG_NIX_LF_STOP_RX:
757 config->intf_down = true;
758 break;
759 }
760
761 return;
762 }
763
764 switch (msg->id) {
765 case MBOX_MSG_READY:
766 pf->pcifunc = msg->pcifunc;
767 break;
768 case MBOX_MSG_MSIX_OFFSET:
769 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg);
770 break;
771 case MBOX_MSG_NPA_LF_ALLOC:
772 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg);
773 break;
774 case MBOX_MSG_NIX_LF_ALLOC:
775 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg);
776 break;
777 case MBOX_MSG_NIX_TXSCH_ALLOC:
778 mbox_handler_nix_txsch_alloc(pf,
779 (struct nix_txsch_alloc_rsp *)msg);
780 break;
781 case MBOX_MSG_NIX_BP_ENABLE:
782 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg);
783 break;
784 case MBOX_MSG_CGX_STATS:
785 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg);
786 break;
787 default:
788 if (msg->rc)
789 dev_err(pf->dev,
790 "Mbox msg response has err %d, ID 0x%x\n",
791 msg->rc, msg->id);
792 break;
793 }
794 }
795
otx2_pfaf_mbox_handler(struct work_struct * work)796 static void otx2_pfaf_mbox_handler(struct work_struct *work)
797 {
798 struct otx2_mbox_dev *mdev;
799 struct mbox_hdr *rsp_hdr;
800 struct mbox_msghdr *msg;
801 struct otx2_mbox *mbox;
802 struct mbox *af_mbox;
803 struct otx2_nic *pf;
804 int offset, id;
805
806 af_mbox = container_of(work, struct mbox, mbox_wrk);
807 mbox = &af_mbox->mbox;
808 mdev = &mbox->dev[0];
809 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
810
811 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
812 pf = af_mbox->pfvf;
813
814 for (id = 0; id < af_mbox->num_msgs; id++) {
815 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
816 otx2_process_pfaf_mbox_msg(pf, msg);
817 offset = mbox->rx_start + msg->next_msgoff;
818 if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
819 __otx2_mbox_reset(mbox, 0);
820 mdev->msgs_acked++;
821 }
822
823 }
824
otx2_handle_link_event(struct otx2_nic * pf)825 static void otx2_handle_link_event(struct otx2_nic *pf)
826 {
827 struct cgx_link_user_info *linfo = &pf->linfo;
828 struct net_device *netdev = pf->netdev;
829
830 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name,
831 linfo->link_up ? "UP" : "DOWN", linfo->speed,
832 linfo->full_duplex ? "Full" : "Half");
833 if (linfo->link_up) {
834 netif_carrier_on(netdev);
835 netif_tx_start_all_queues(netdev);
836 } else {
837 netif_tx_stop_all_queues(netdev);
838 netif_carrier_off(netdev);
839 }
840 }
841
otx2_mbox_up_handler_cgx_link_event(struct otx2_nic * pf,struct cgx_link_info_msg * msg,struct msg_rsp * rsp)842 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf,
843 struct cgx_link_info_msg *msg,
844 struct msg_rsp *rsp)
845 {
846 int i;
847
848 /* Copy the link info sent by AF */
849 pf->linfo = msg->link_info;
850
851 /* notify VFs about link event */
852 for (i = 0; i < pci_num_vf(pf->pdev); i++) {
853 struct otx2_vf_config *config = &pf->vf_configs[i];
854 struct delayed_work *dwork = &config->link_event_work;
855
856 if (config->intf_down)
857 continue;
858
859 schedule_delayed_work(dwork, msecs_to_jiffies(100));
860 }
861
862 /* interface has not been fully configured yet */
863 if (pf->flags & OTX2_FLAG_INTF_DOWN)
864 return 0;
865
866 otx2_handle_link_event(pf);
867 return 0;
868 }
869
otx2_process_mbox_msg_up(struct otx2_nic * pf,struct mbox_msghdr * req)870 static int otx2_process_mbox_msg_up(struct otx2_nic *pf,
871 struct mbox_msghdr *req)
872 {
873 /* Check if valid, if not reply with a invalid msg */
874 if (req->sig != OTX2_MBOX_REQ_SIG) {
875 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
876 return -ENODEV;
877 }
878
879 switch (req->id) {
880 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
881 case _id: { \
882 struct _rsp_type *rsp; \
883 int err; \
884 \
885 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \
886 &pf->mbox.mbox_up, 0, \
887 sizeof(struct _rsp_type)); \
888 if (!rsp) \
889 return -ENOMEM; \
890 \
891 rsp->hdr.id = _id; \
892 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \
893 rsp->hdr.pcifunc = 0; \
894 rsp->hdr.rc = 0; \
895 \
896 err = otx2_mbox_up_handler_ ## _fn_name( \
897 pf, (struct _req_type *)req, rsp); \
898 return err; \
899 }
900 MBOX_UP_CGX_MESSAGES
901 #undef M
902 break;
903 default:
904 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
905 return -ENODEV;
906 }
907 return 0;
908 }
909
otx2_pfaf_mbox_up_handler(struct work_struct * work)910 static void otx2_pfaf_mbox_up_handler(struct work_struct *work)
911 {
912 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk);
913 struct otx2_mbox *mbox = &af_mbox->mbox_up;
914 struct otx2_mbox_dev *mdev = &mbox->dev[0];
915 struct otx2_nic *pf = af_mbox->pfvf;
916 int offset, id, devid = 0;
917 struct mbox_hdr *rsp_hdr;
918 struct mbox_msghdr *msg;
919
920 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
921
922 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
923
924 for (id = 0; id < af_mbox->up_num_msgs; id++) {
925 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
926
927 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
928 /* Skip processing VF's messages */
929 if (!devid)
930 otx2_process_mbox_msg_up(pf, msg);
931 offset = mbox->rx_start + msg->next_msgoff;
932 }
933 if (devid) {
934 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up,
935 MBOX_DIR_PFVF_UP, devid - 1,
936 af_mbox->up_num_msgs);
937 return;
938 }
939
940 otx2_mbox_msg_send(mbox, 0);
941 }
942
otx2_pfaf_mbox_intr_handler(int irq,void * pf_irq)943 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq)
944 {
945 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
946 struct mbox *mbox;
947
948 /* Clear the IRQ */
949 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
950
951 mbox = &pf->mbox;
952
953 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0));
954
955 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF);
956
957 return IRQ_HANDLED;
958 }
959
otx2_disable_mbox_intr(struct otx2_nic * pf)960 static void otx2_disable_mbox_intr(struct otx2_nic *pf)
961 {
962 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX);
963
964 /* Disable AF => PF mailbox IRQ */
965 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0));
966 free_irq(vector, pf);
967 }
968
otx2_register_mbox_intr(struct otx2_nic * pf,bool probe_af)969 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af)
970 {
971 struct otx2_hw *hw = &pf->hw;
972 struct msg_req *req;
973 char *irq_name;
974 int err;
975
976 /* Register mailbox interrupt handler */
977 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE];
978 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox");
979 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX),
980 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf);
981 if (err) {
982 dev_err(pf->dev,
983 "RVUPF: IRQ registration failed for PFAF mbox irq\n");
984 return err;
985 }
986
987 /* Enable mailbox interrupt for msgs coming from AF.
988 * First clear to avoid spurious interrupts, if any.
989 */
990 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
991 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0));
992
993 if (!probe_af)
994 return 0;
995
996 /* Check mailbox communication with AF */
997 req = otx2_mbox_alloc_msg_ready(&pf->mbox);
998 if (!req) {
999 otx2_disable_mbox_intr(pf);
1000 return -ENOMEM;
1001 }
1002 err = otx2_sync_mbox_msg(&pf->mbox);
1003 if (err) {
1004 dev_warn(pf->dev,
1005 "AF not responding to mailbox, deferring probe\n");
1006 otx2_disable_mbox_intr(pf);
1007 return -EPROBE_DEFER;
1008 }
1009
1010 return 0;
1011 }
1012
otx2_pfaf_mbox_destroy(struct otx2_nic * pf)1013 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf)
1014 {
1015 struct mbox *mbox = &pf->mbox;
1016
1017 if (pf->mbox_wq) {
1018 destroy_workqueue(pf->mbox_wq);
1019 pf->mbox_wq = NULL;
1020 }
1021
1022 if (mbox->mbox.hwbase)
1023 iounmap((void __iomem *)mbox->mbox.hwbase);
1024
1025 otx2_mbox_destroy(&mbox->mbox);
1026 otx2_mbox_destroy(&mbox->mbox_up);
1027 }
1028
otx2_pfaf_mbox_init(struct otx2_nic * pf)1029 static int otx2_pfaf_mbox_init(struct otx2_nic *pf)
1030 {
1031 struct mbox *mbox = &pf->mbox;
1032 void __iomem *hwbase;
1033 int err;
1034
1035 mbox->pfvf = pf;
1036 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox",
1037 WQ_UNBOUND | WQ_HIGHPRI |
1038 WQ_MEM_RECLAIM, 1);
1039 if (!pf->mbox_wq)
1040 return -ENOMEM;
1041
1042 /* Mailbox is a reserved memory (in RAM) region shared between
1043 * admin function (i.e AF) and this PF, shouldn't be mapped as
1044 * device memory to allow unaligned accesses.
1045 */
1046 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM),
1047 pci_resource_len(pf->pdev, PCI_MBOX_BAR_NUM));
1048 if (!hwbase) {
1049 dev_err(pf->dev, "Unable to map PFAF mailbox region\n");
1050 err = -ENOMEM;
1051 goto exit;
1052 }
1053
1054 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
1055 MBOX_DIR_PFAF, 1);
1056 if (err)
1057 goto exit;
1058
1059 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
1060 MBOX_DIR_PFAF_UP, 1);
1061 if (err)
1062 goto exit;
1063
1064 err = otx2_mbox_bbuf_init(mbox, pf->pdev);
1065 if (err)
1066 goto exit;
1067
1068 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler);
1069 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler);
1070 mutex_init(&mbox->lock);
1071
1072 return 0;
1073 exit:
1074 otx2_pfaf_mbox_destroy(pf);
1075 return err;
1076 }
1077
otx2_cgx_config_linkevents(struct otx2_nic * pf,bool enable)1078 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable)
1079 {
1080 struct msg_req *msg;
1081 int err;
1082
1083 mutex_lock(&pf->mbox.lock);
1084 if (enable)
1085 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox);
1086 else
1087 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox);
1088
1089 if (!msg) {
1090 mutex_unlock(&pf->mbox.lock);
1091 return -ENOMEM;
1092 }
1093
1094 err = otx2_sync_mbox_msg(&pf->mbox);
1095 mutex_unlock(&pf->mbox.lock);
1096 return err;
1097 }
1098
otx2_cgx_config_loopback(struct otx2_nic * pf,bool enable)1099 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable)
1100 {
1101 struct msg_req *msg;
1102 int err;
1103
1104 mutex_lock(&pf->mbox.lock);
1105 if (enable)
1106 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox);
1107 else
1108 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox);
1109
1110 if (!msg) {
1111 mutex_unlock(&pf->mbox.lock);
1112 return -ENOMEM;
1113 }
1114
1115 err = otx2_sync_mbox_msg(&pf->mbox);
1116 mutex_unlock(&pf->mbox.lock);
1117 return err;
1118 }
1119
otx2_set_real_num_queues(struct net_device * netdev,int tx_queues,int rx_queues)1120 int otx2_set_real_num_queues(struct net_device *netdev,
1121 int tx_queues, int rx_queues)
1122 {
1123 int err;
1124
1125 err = netif_set_real_num_tx_queues(netdev, tx_queues);
1126 if (err) {
1127 netdev_err(netdev,
1128 "Failed to set no of Tx queues: %d\n", tx_queues);
1129 return err;
1130 }
1131
1132 err = netif_set_real_num_rx_queues(netdev, rx_queues);
1133 if (err)
1134 netdev_err(netdev,
1135 "Failed to set no of Rx queues: %d\n", rx_queues);
1136 return err;
1137 }
1138 EXPORT_SYMBOL(otx2_set_real_num_queues);
1139
otx2_q_intr_handler(int irq,void * data)1140 static irqreturn_t otx2_q_intr_handler(int irq, void *data)
1141 {
1142 struct otx2_nic *pf = data;
1143 u64 val, *ptr;
1144 u64 qidx = 0;
1145
1146 /* CQ */
1147 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) {
1148 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT);
1149 val = otx2_atomic64_add((qidx << 44), ptr);
1150
1151 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) |
1152 (val & NIX_CQERRINT_BITS));
1153 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42))))
1154 continue;
1155
1156 if (val & BIT_ULL(42)) {
1157 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1158 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1159 } else {
1160 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
1161 netdev_err(pf->netdev, "CQ%lld: Doorbell error",
1162 qidx);
1163 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
1164 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM",
1165 qidx);
1166 }
1167
1168 schedule_work(&pf->reset_task);
1169 }
1170
1171 /* SQ */
1172 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) {
1173 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);
1174 val = otx2_atomic64_add((qidx << 44), ptr);
1175 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) |
1176 (val & NIX_SQINT_BITS));
1177
1178 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42))))
1179 continue;
1180
1181 if (val & BIT_ULL(42)) {
1182 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1183 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1184 } else {
1185 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) {
1186 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx",
1187 qidx,
1188 otx2_read64(pf,
1189 NIX_LF_SQ_OP_ERR_DBG));
1190 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG,
1191 BIT_ULL(44));
1192 }
1193 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
1194 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n",
1195 qidx,
1196 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG));
1197 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG,
1198 BIT_ULL(44));
1199 }
1200 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) {
1201 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx",
1202 qidx,
1203 otx2_read64(pf,
1204 NIX_LF_SEND_ERR_DBG));
1205 otx2_write64(pf, NIX_LF_SEND_ERR_DBG,
1206 BIT_ULL(44));
1207 }
1208 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
1209 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
1210 qidx);
1211 }
1212
1213 schedule_work(&pf->reset_task);
1214 }
1215
1216 return IRQ_HANDLED;
1217 }
1218
otx2_cq_intr_handler(int irq,void * cq_irq)1219 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq)
1220 {
1221 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq;
1222 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev;
1223 int qidx = cq_poll->cint_idx;
1224
1225 /* Disable interrupts.
1226 *
1227 * Completion interrupts behave in a level-triggered interrupt
1228 * fashion, and hence have to be cleared only after it is serviced.
1229 */
1230 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1231
1232 /* Schedule NAPI */
1233 napi_schedule_irqoff(&cq_poll->napi);
1234
1235 return IRQ_HANDLED;
1236 }
1237
otx2_disable_napi(struct otx2_nic * pf)1238 static void otx2_disable_napi(struct otx2_nic *pf)
1239 {
1240 struct otx2_qset *qset = &pf->qset;
1241 struct otx2_cq_poll *cq_poll;
1242 int qidx;
1243
1244 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1245 cq_poll = &qset->napi[qidx];
1246 napi_disable(&cq_poll->napi);
1247 netif_napi_del(&cq_poll->napi);
1248 }
1249 }
1250
otx2_free_cq_res(struct otx2_nic * pf)1251 static void otx2_free_cq_res(struct otx2_nic *pf)
1252 {
1253 struct otx2_qset *qset = &pf->qset;
1254 struct otx2_cq_queue *cq;
1255 int qidx;
1256
1257 /* Disable CQs */
1258 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false);
1259 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1260 cq = &qset->cq[qidx];
1261 qmem_free(pf->dev, cq->cqe);
1262 }
1263 }
1264
otx2_free_sq_res(struct otx2_nic * pf)1265 static void otx2_free_sq_res(struct otx2_nic *pf)
1266 {
1267 struct otx2_qset *qset = &pf->qset;
1268 struct otx2_snd_queue *sq;
1269 int qidx;
1270
1271 /* Disable SQs */
1272 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false);
1273 /* Free SQB pointers */
1274 otx2_sq_free_sqbs(pf);
1275 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) {
1276 sq = &qset->sq[qidx];
1277 qmem_free(pf->dev, sq->sqe);
1278 qmem_free(pf->dev, sq->tso_hdrs);
1279 kfree(sq->sg);
1280 kfree(sq->sqb_ptrs);
1281 }
1282 }
1283
otx2_init_hw_resources(struct otx2_nic * pf)1284 static int otx2_init_hw_resources(struct otx2_nic *pf)
1285 {
1286 struct mbox *mbox = &pf->mbox;
1287 struct otx2_hw *hw = &pf->hw;
1288 struct msg_req *req;
1289 int err = 0, lvl;
1290
1291 /* Set required NPA LF's pool counts
1292 * Auras and Pools are used in a 1:1 mapping,
1293 * so, aura count = pool count.
1294 */
1295 hw->rqpool_cnt = hw->rx_queues;
1296 hw->sqpool_cnt = hw->tx_queues;
1297 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt;
1298
1299 /* Get the size of receive buffers to allocate */
1300 pf->rbsize = RCV_FRAG_LEN(OTX2_HW_TIMESTAMP_LEN + pf->netdev->mtu +
1301 OTX2_ETH_HLEN);
1302
1303 mutex_lock(&mbox->lock);
1304 /* NPA init */
1305 err = otx2_config_npa(pf);
1306 if (err)
1307 goto exit;
1308
1309 /* NIX init */
1310 err = otx2_config_nix(pf);
1311 if (err)
1312 goto err_free_npa_lf;
1313
1314 /* Enable backpressure */
1315 otx2_nix_config_bp(pf, true);
1316
1317 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */
1318 err = otx2_rq_aura_pool_init(pf);
1319 if (err) {
1320 mutex_unlock(&mbox->lock);
1321 goto err_free_nix_lf;
1322 }
1323 /* Init Auras and pools used by NIX SQ, for queueing SQEs */
1324 err = otx2_sq_aura_pool_init(pf);
1325 if (err) {
1326 mutex_unlock(&mbox->lock);
1327 goto err_free_rq_ptrs;
1328 }
1329
1330 err = otx2_txsch_alloc(pf);
1331 if (err) {
1332 mutex_unlock(&mbox->lock);
1333 goto err_free_sq_ptrs;
1334 }
1335
1336 err = otx2_config_nix_queues(pf);
1337 if (err) {
1338 mutex_unlock(&mbox->lock);
1339 goto err_free_txsch;
1340 }
1341 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
1342 err = otx2_txschq_config(pf, lvl);
1343 if (err) {
1344 mutex_unlock(&mbox->lock);
1345 goto err_free_nix_queues;
1346 }
1347 }
1348 mutex_unlock(&mbox->lock);
1349 return err;
1350
1351 err_free_nix_queues:
1352 otx2_free_sq_res(pf);
1353 otx2_free_cq_res(pf);
1354 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1355 err_free_txsch:
1356 if (otx2_txschq_stop(pf))
1357 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__);
1358 err_free_sq_ptrs:
1359 otx2_sq_free_sqbs(pf);
1360 err_free_rq_ptrs:
1361 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1362 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1363 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1364 otx2_aura_pool_free(pf);
1365 err_free_nix_lf:
1366 mutex_lock(&mbox->lock);
1367 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1368 if (req) {
1369 if (otx2_sync_mbox_msg(mbox))
1370 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1371 }
1372 err_free_npa_lf:
1373 /* Reset NPA LF */
1374 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1375 if (req) {
1376 if (otx2_sync_mbox_msg(mbox))
1377 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1378 }
1379 exit:
1380 mutex_unlock(&mbox->lock);
1381 return err;
1382 }
1383
otx2_free_hw_resources(struct otx2_nic * pf)1384 static void otx2_free_hw_resources(struct otx2_nic *pf)
1385 {
1386 struct otx2_qset *qset = &pf->qset;
1387 struct mbox *mbox = &pf->mbox;
1388 struct otx2_cq_queue *cq;
1389 struct msg_req *req;
1390 int qidx, err;
1391
1392 /* Ensure all SQE are processed */
1393 otx2_sqb_flush(pf);
1394
1395 /* Stop transmission */
1396 err = otx2_txschq_stop(pf);
1397 if (err)
1398 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n");
1399
1400 mutex_lock(&mbox->lock);
1401 /* Disable backpressure */
1402 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1403 otx2_nix_config_bp(pf, false);
1404 mutex_unlock(&mbox->lock);
1405
1406 /* Disable RQs */
1407 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1408
1409 /*Dequeue all CQEs */
1410 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1411 cq = &qset->cq[qidx];
1412 if (cq->cq_type == CQ_RX)
1413 otx2_cleanup_rx_cqes(pf, cq);
1414 else
1415 otx2_cleanup_tx_cqes(pf, cq);
1416 }
1417
1418 otx2_free_sq_res(pf);
1419
1420 /* Free RQ buffer pointers*/
1421 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1422
1423 otx2_free_cq_res(pf);
1424
1425 mutex_lock(&mbox->lock);
1426 /* Reset NIX LF */
1427 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1428 if (req) {
1429 if (otx2_sync_mbox_msg(mbox))
1430 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1431 }
1432 mutex_unlock(&mbox->lock);
1433
1434 /* Disable NPA Pool and Aura hw context */
1435 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1436 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1437 otx2_aura_pool_free(pf);
1438
1439 mutex_lock(&mbox->lock);
1440 /* Reset NPA LF */
1441 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1442 if (req) {
1443 if (otx2_sync_mbox_msg(mbox))
1444 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1445 }
1446 mutex_unlock(&mbox->lock);
1447 }
1448
otx2_open(struct net_device * netdev)1449 int otx2_open(struct net_device *netdev)
1450 {
1451 struct otx2_nic *pf = netdev_priv(netdev);
1452 struct otx2_cq_poll *cq_poll = NULL;
1453 struct otx2_qset *qset = &pf->qset;
1454 int err = 0, qidx, vec;
1455 char *irq_name;
1456
1457 netif_carrier_off(netdev);
1458
1459 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tx_queues;
1460 /* RQ and SQs are mapped to different CQs,
1461 * so find out max CQ IRQs (i.e CINTs) needed.
1462 */
1463 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues);
1464 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL);
1465 if (!qset->napi)
1466 return -ENOMEM;
1467
1468 /* CQ size of RQ */
1469 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256);
1470 /* CQ size of SQ */
1471 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K);
1472
1473 err = -ENOMEM;
1474 qset->cq = kcalloc(pf->qset.cq_cnt,
1475 sizeof(struct otx2_cq_queue), GFP_KERNEL);
1476 if (!qset->cq)
1477 goto err_free_mem;
1478
1479 qset->sq = kcalloc(pf->hw.tx_queues,
1480 sizeof(struct otx2_snd_queue), GFP_KERNEL);
1481 if (!qset->sq)
1482 goto err_free_mem;
1483
1484 qset->rq = kcalloc(pf->hw.rx_queues,
1485 sizeof(struct otx2_rcv_queue), GFP_KERNEL);
1486 if (!qset->rq)
1487 goto err_free_mem;
1488
1489 err = otx2_init_hw_resources(pf);
1490 if (err)
1491 goto err_free_mem;
1492
1493 /* Register NAPI handler */
1494 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1495 cq_poll = &qset->napi[qidx];
1496 cq_poll->cint_idx = qidx;
1497 /* RQ0 & SQ0 are mapped to CINT0 and so on..
1498 * 'cq_ids[0]' points to RQ's CQ and
1499 * 'cq_ids[1]' points to SQ's CQ and
1500 */
1501 cq_poll->cq_ids[CQ_RX] =
1502 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ;
1503 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ?
1504 qidx + pf->hw.rx_queues : CINT_INVALID_CQ;
1505 cq_poll->dev = (void *)pf;
1506 netif_napi_add(netdev, &cq_poll->napi,
1507 otx2_napi_handler, NAPI_POLL_WEIGHT);
1508 napi_enable(&cq_poll->napi);
1509 }
1510
1511 /* Set maximum frame size allowed in HW */
1512 err = otx2_hw_set_mtu(pf, netdev->mtu);
1513 if (err)
1514 goto err_disable_napi;
1515
1516 /* Setup segmentation algorithms, if failed, clear offload capability */
1517 otx2_setup_segmentation(pf);
1518
1519 /* Initialize RSS */
1520 err = otx2_rss_init(pf);
1521 if (err)
1522 goto err_disable_napi;
1523
1524 /* Register Queue IRQ handlers */
1525 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START;
1526 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1527
1528 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name);
1529
1530 err = request_irq(pci_irq_vector(pf->pdev, vec),
1531 otx2_q_intr_handler, 0, irq_name, pf);
1532 if (err) {
1533 dev_err(pf->dev,
1534 "RVUPF%d: IRQ registration failed for QERR\n",
1535 rvu_get_pf(pf->pcifunc));
1536 goto err_disable_napi;
1537 }
1538
1539 /* Enable QINT IRQ */
1540 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0));
1541
1542 /* Register CQ IRQ handlers */
1543 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1544 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1545 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1546
1547 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name,
1548 qidx);
1549
1550 err = request_irq(pci_irq_vector(pf->pdev, vec),
1551 otx2_cq_intr_handler, 0, irq_name,
1552 &qset->napi[qidx]);
1553 if (err) {
1554 dev_err(pf->dev,
1555 "RVUPF%d: IRQ registration failed for CQ%d\n",
1556 rvu_get_pf(pf->pcifunc), qidx);
1557 goto err_free_cints;
1558 }
1559 vec++;
1560
1561 otx2_config_irq_coalescing(pf, qidx);
1562
1563 /* Enable CQ IRQ */
1564 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0));
1565 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0));
1566 }
1567
1568 otx2_set_cints_affinity(pf);
1569
1570 /* When reinitializing enable time stamping if it is enabled before */
1571 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) {
1572 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1573 otx2_config_hw_tx_tstamp(pf, true);
1574 }
1575 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) {
1576 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1577 otx2_config_hw_rx_tstamp(pf, true);
1578 }
1579
1580 pf->flags &= ~OTX2_FLAG_INTF_DOWN;
1581 /* 'intf_down' may be checked on any cpu */
1582 smp_wmb();
1583
1584 /* we have already received link status notification */
1585 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1586 otx2_handle_link_event(pf);
1587
1588 /* Restore pause frame settings */
1589 otx2_config_pause_frm(pf);
1590
1591 err = otx2_rxtx_enable(pf, true);
1592 if (err)
1593 goto err_tx_stop_queues;
1594
1595 return 0;
1596
1597 err_tx_stop_queues:
1598 netif_tx_stop_all_queues(netdev);
1599 netif_carrier_off(netdev);
1600 pf->flags |= OTX2_FLAG_INTF_DOWN;
1601 err_free_cints:
1602 otx2_free_cints(pf, qidx);
1603 vec = pci_irq_vector(pf->pdev,
1604 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1605 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1606 synchronize_irq(vec);
1607 free_irq(vec, pf);
1608 err_disable_napi:
1609 otx2_disable_napi(pf);
1610 otx2_free_hw_resources(pf);
1611 err_free_mem:
1612 kfree(qset->sq);
1613 kfree(qset->cq);
1614 kfree(qset->rq);
1615 kfree(qset->napi);
1616 return err;
1617 }
1618 EXPORT_SYMBOL(otx2_open);
1619
otx2_stop(struct net_device * netdev)1620 int otx2_stop(struct net_device *netdev)
1621 {
1622 struct otx2_nic *pf = netdev_priv(netdev);
1623 struct otx2_cq_poll *cq_poll = NULL;
1624 struct otx2_qset *qset = &pf->qset;
1625 struct otx2_rss_info *rss;
1626 int qidx, vec, wrk;
1627
1628 /* If the DOWN flag is set resources are already freed */
1629 if (pf->flags & OTX2_FLAG_INTF_DOWN)
1630 return 0;
1631
1632 netif_carrier_off(netdev);
1633 netif_tx_stop_all_queues(netdev);
1634
1635 pf->flags |= OTX2_FLAG_INTF_DOWN;
1636 /* 'intf_down' may be checked on any cpu */
1637 smp_wmb();
1638
1639 /* First stop packet Rx/Tx */
1640 otx2_rxtx_enable(pf, false);
1641
1642 /* Clear RSS enable flag */
1643 rss = &pf->hw.rss_info;
1644 rss->enable = false;
1645
1646 /* Cleanup Queue IRQ */
1647 vec = pci_irq_vector(pf->pdev,
1648 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1649 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1650 synchronize_irq(vec);
1651 free_irq(vec, pf);
1652
1653 /* Cleanup CQ NAPI and IRQ */
1654 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1655 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1656 /* Disable interrupt */
1657 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1658
1659 synchronize_irq(pci_irq_vector(pf->pdev, vec));
1660
1661 cq_poll = &qset->napi[qidx];
1662 napi_synchronize(&cq_poll->napi);
1663 vec++;
1664 }
1665
1666 netif_tx_disable(netdev);
1667
1668 otx2_free_hw_resources(pf);
1669 otx2_free_cints(pf, pf->hw.cint_cnt);
1670 otx2_disable_napi(pf);
1671
1672 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++)
1673 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx));
1674
1675 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++)
1676 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work);
1677 devm_kfree(pf->dev, pf->refill_wrk);
1678
1679 kfree(qset->sq);
1680 kfree(qset->cq);
1681 kfree(qset->rq);
1682 kfree(qset->napi);
1683 /* Do not clear RQ/SQ ringsize settings */
1684 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0,
1685 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt));
1686 return 0;
1687 }
1688 EXPORT_SYMBOL(otx2_stop);
1689
otx2_xmit(struct sk_buff * skb,struct net_device * netdev)1690 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev)
1691 {
1692 struct otx2_nic *pf = netdev_priv(netdev);
1693 int qidx = skb_get_queue_mapping(skb);
1694 struct otx2_snd_queue *sq;
1695 struct netdev_queue *txq;
1696
1697 /* Check for minimum and maximum packet length */
1698 if (skb->len <= ETH_HLEN ||
1699 (!skb_shinfo(skb)->gso_size && skb->len > pf->max_frs)) {
1700 dev_kfree_skb(skb);
1701 return NETDEV_TX_OK;
1702 }
1703
1704 sq = &pf->qset.sq[qidx];
1705 txq = netdev_get_tx_queue(netdev, qidx);
1706
1707 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
1708 netif_tx_stop_queue(txq);
1709
1710 /* Check again, incase SQBs got freed up */
1711 smp_mb();
1712 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
1713 > sq->sqe_thresh)
1714 netif_tx_wake_queue(txq);
1715
1716 return NETDEV_TX_BUSY;
1717 }
1718
1719 return NETDEV_TX_OK;
1720 }
1721
otx2_set_rx_mode(struct net_device * netdev)1722 static void otx2_set_rx_mode(struct net_device *netdev)
1723 {
1724 struct otx2_nic *pf = netdev_priv(netdev);
1725
1726 queue_work(pf->otx2_wq, &pf->rx_mode_work);
1727 }
1728
otx2_do_set_rx_mode(struct work_struct * work)1729 static void otx2_do_set_rx_mode(struct work_struct *work)
1730 {
1731 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work);
1732 struct net_device *netdev = pf->netdev;
1733 struct nix_rx_mode *req;
1734
1735 if (!(netdev->flags & IFF_UP))
1736 return;
1737
1738 mutex_lock(&pf->mbox.lock);
1739 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox);
1740 if (!req) {
1741 mutex_unlock(&pf->mbox.lock);
1742 return;
1743 }
1744
1745 req->mode = NIX_RX_MODE_UCAST;
1746
1747 /* We don't support MAC address filtering yet */
1748 if (netdev->flags & IFF_PROMISC)
1749 req->mode |= NIX_RX_MODE_PROMISC;
1750 else if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
1751 req->mode |= NIX_RX_MODE_ALLMULTI;
1752
1753 otx2_sync_mbox_msg(&pf->mbox);
1754 mutex_unlock(&pf->mbox.lock);
1755 }
1756
otx2_set_features(struct net_device * netdev,netdev_features_t features)1757 static int otx2_set_features(struct net_device *netdev,
1758 netdev_features_t features)
1759 {
1760 netdev_features_t changed = features ^ netdev->features;
1761 struct otx2_nic *pf = netdev_priv(netdev);
1762
1763 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev))
1764 return otx2_cgx_config_loopback(pf,
1765 features & NETIF_F_LOOPBACK);
1766 return 0;
1767 }
1768
otx2_reset_task(struct work_struct * work)1769 static void otx2_reset_task(struct work_struct *work)
1770 {
1771 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task);
1772
1773 if (!netif_running(pf->netdev))
1774 return;
1775
1776 rtnl_lock();
1777 otx2_stop(pf->netdev);
1778 pf->reset_count++;
1779 otx2_open(pf->netdev);
1780 netif_trans_update(pf->netdev);
1781 rtnl_unlock();
1782 }
1783
otx2_config_hw_rx_tstamp(struct otx2_nic * pfvf,bool enable)1784 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable)
1785 {
1786 struct msg_req *req;
1787 int err;
1788
1789 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable)
1790 return 0;
1791
1792 mutex_lock(&pfvf->mbox.lock);
1793 if (enable)
1794 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox);
1795 else
1796 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox);
1797 if (!req) {
1798 mutex_unlock(&pfvf->mbox.lock);
1799 return -ENOMEM;
1800 }
1801
1802 err = otx2_sync_mbox_msg(&pfvf->mbox);
1803 if (err) {
1804 mutex_unlock(&pfvf->mbox.lock);
1805 return err;
1806 }
1807
1808 mutex_unlock(&pfvf->mbox.lock);
1809 if (enable)
1810 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED;
1811 else
1812 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1813 return 0;
1814 }
1815
otx2_config_hw_tx_tstamp(struct otx2_nic * pfvf,bool enable)1816 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable)
1817 {
1818 struct msg_req *req;
1819 int err;
1820
1821 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable)
1822 return 0;
1823
1824 mutex_lock(&pfvf->mbox.lock);
1825 if (enable)
1826 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox);
1827 else
1828 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox);
1829 if (!req) {
1830 mutex_unlock(&pfvf->mbox.lock);
1831 return -ENOMEM;
1832 }
1833
1834 err = otx2_sync_mbox_msg(&pfvf->mbox);
1835 if (err) {
1836 mutex_unlock(&pfvf->mbox.lock);
1837 return err;
1838 }
1839
1840 mutex_unlock(&pfvf->mbox.lock);
1841 if (enable)
1842 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED;
1843 else
1844 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1845 return 0;
1846 }
1847
otx2_config_hwtstamp(struct net_device * netdev,struct ifreq * ifr)1848 static int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr)
1849 {
1850 struct otx2_nic *pfvf = netdev_priv(netdev);
1851 struct hwtstamp_config config;
1852
1853 if (!pfvf->ptp)
1854 return -ENODEV;
1855
1856 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1857 return -EFAULT;
1858
1859 /* reserved for future extensions */
1860 if (config.flags)
1861 return -EINVAL;
1862
1863 switch (config.tx_type) {
1864 case HWTSTAMP_TX_OFF:
1865 otx2_config_hw_tx_tstamp(pfvf, false);
1866 break;
1867 case HWTSTAMP_TX_ON:
1868 otx2_config_hw_tx_tstamp(pfvf, true);
1869 break;
1870 default:
1871 return -ERANGE;
1872 }
1873
1874 switch (config.rx_filter) {
1875 case HWTSTAMP_FILTER_NONE:
1876 otx2_config_hw_rx_tstamp(pfvf, false);
1877 break;
1878 case HWTSTAMP_FILTER_ALL:
1879 case HWTSTAMP_FILTER_SOME:
1880 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1881 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1882 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1883 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1884 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1885 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1886 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1887 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1888 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1889 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1890 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1891 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1892 otx2_config_hw_rx_tstamp(pfvf, true);
1893 config.rx_filter = HWTSTAMP_FILTER_ALL;
1894 break;
1895 default:
1896 return -ERANGE;
1897 }
1898
1899 memcpy(&pfvf->tstamp, &config, sizeof(config));
1900
1901 return copy_to_user(ifr->ifr_data, &config,
1902 sizeof(config)) ? -EFAULT : 0;
1903 }
1904
otx2_ioctl(struct net_device * netdev,struct ifreq * req,int cmd)1905 static int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
1906 {
1907 struct otx2_nic *pfvf = netdev_priv(netdev);
1908 struct hwtstamp_config *cfg = &pfvf->tstamp;
1909
1910 switch (cmd) {
1911 case SIOCSHWTSTAMP:
1912 return otx2_config_hwtstamp(netdev, req);
1913 case SIOCGHWTSTAMP:
1914 return copy_to_user(req->ifr_data, cfg,
1915 sizeof(*cfg)) ? -EFAULT : 0;
1916 default:
1917 return -EOPNOTSUPP;
1918 }
1919 }
1920
1921 static const struct net_device_ops otx2_netdev_ops = {
1922 .ndo_open = otx2_open,
1923 .ndo_stop = otx2_stop,
1924 .ndo_start_xmit = otx2_xmit,
1925 .ndo_set_mac_address = otx2_set_mac_address,
1926 .ndo_change_mtu = otx2_change_mtu,
1927 .ndo_set_rx_mode = otx2_set_rx_mode,
1928 .ndo_set_features = otx2_set_features,
1929 .ndo_tx_timeout = otx2_tx_timeout,
1930 .ndo_get_stats64 = otx2_get_stats64,
1931 .ndo_do_ioctl = otx2_ioctl,
1932 };
1933
otx2_wq_init(struct otx2_nic * pf)1934 static int otx2_wq_init(struct otx2_nic *pf)
1935 {
1936 pf->otx2_wq = create_singlethread_workqueue("otx2_wq");
1937 if (!pf->otx2_wq)
1938 return -ENOMEM;
1939
1940 INIT_WORK(&pf->rx_mode_work, otx2_do_set_rx_mode);
1941 INIT_WORK(&pf->reset_task, otx2_reset_task);
1942 return 0;
1943 }
1944
otx2_check_pf_usable(struct otx2_nic * nic)1945 static int otx2_check_pf_usable(struct otx2_nic *nic)
1946 {
1947 u64 rev;
1948
1949 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM));
1950 rev = (rev >> 12) & 0xFF;
1951 /* Check if AF has setup revision for RVUM block,
1952 * otherwise this driver probe should be deferred
1953 * until AF driver comes up.
1954 */
1955 if (!rev) {
1956 dev_warn(nic->dev,
1957 "AF is not initialized, deferring probe\n");
1958 return -EPROBE_DEFER;
1959 }
1960 return 0;
1961 }
1962
otx2_realloc_msix_vectors(struct otx2_nic * pf)1963 static int otx2_realloc_msix_vectors(struct otx2_nic *pf)
1964 {
1965 struct otx2_hw *hw = &pf->hw;
1966 int num_vec, err;
1967
1968 /* NPA interrupts are inot registered, so alloc only
1969 * upto NIX vector offset.
1970 */
1971 num_vec = hw->nix_msixoff;
1972 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
1973
1974 otx2_disable_mbox_intr(pf);
1975 pci_free_irq_vectors(hw->pdev);
1976 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
1977 if (err < 0) {
1978 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n",
1979 __func__, num_vec);
1980 return err;
1981 }
1982
1983 return otx2_register_mbox_intr(pf, false);
1984 }
1985
otx2_probe(struct pci_dev * pdev,const struct pci_device_id * id)1986 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1987 {
1988 struct device *dev = &pdev->dev;
1989 struct net_device *netdev;
1990 struct otx2_nic *pf;
1991 struct otx2_hw *hw;
1992 int err, qcount;
1993 int num_vec;
1994
1995 err = pcim_enable_device(pdev);
1996 if (err) {
1997 dev_err(dev, "Failed to enable PCI device\n");
1998 return err;
1999 }
2000
2001 err = pci_request_regions(pdev, DRV_NAME);
2002 if (err) {
2003 dev_err(dev, "PCI request regions failed 0x%x\n", err);
2004 return err;
2005 }
2006
2007 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
2008 if (err) {
2009 dev_err(dev, "DMA mask config failed, abort\n");
2010 goto err_release_regions;
2011 }
2012
2013 pci_set_master(pdev);
2014
2015 /* Set number of queues */
2016 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT);
2017
2018 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount);
2019 if (!netdev) {
2020 err = -ENOMEM;
2021 goto err_release_regions;
2022 }
2023
2024 pci_set_drvdata(pdev, netdev);
2025 SET_NETDEV_DEV(netdev, &pdev->dev);
2026 pf = netdev_priv(netdev);
2027 pf->netdev = netdev;
2028 pf->pdev = pdev;
2029 pf->dev = dev;
2030 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
2031 pf->flags |= OTX2_FLAG_INTF_DOWN;
2032
2033 hw = &pf->hw;
2034 hw->pdev = pdev;
2035 hw->rx_queues = qcount;
2036 hw->tx_queues = qcount;
2037 hw->max_queues = qcount;
2038
2039 num_vec = pci_msix_vec_count(pdev);
2040 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
2041 GFP_KERNEL);
2042 if (!hw->irq_name) {
2043 err = -ENOMEM;
2044 goto err_free_netdev;
2045 }
2046
2047 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
2048 sizeof(cpumask_var_t), GFP_KERNEL);
2049 if (!hw->affinity_mask) {
2050 err = -ENOMEM;
2051 goto err_free_netdev;
2052 }
2053
2054 /* Map CSRs */
2055 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
2056 if (!pf->reg_base) {
2057 dev_err(dev, "Unable to map physical function CSRs, aborting\n");
2058 err = -ENOMEM;
2059 goto err_free_netdev;
2060 }
2061
2062 err = otx2_check_pf_usable(pf);
2063 if (err)
2064 goto err_free_netdev;
2065
2066 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT,
2067 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX);
2068 if (err < 0) {
2069 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
2070 __func__, num_vec);
2071 goto err_free_netdev;
2072 }
2073
2074 /* Init PF <=> AF mailbox stuff */
2075 err = otx2_pfaf_mbox_init(pf);
2076 if (err)
2077 goto err_free_irq_vectors;
2078
2079 /* Register mailbox interrupt */
2080 err = otx2_register_mbox_intr(pf, true);
2081 if (err)
2082 goto err_mbox_destroy;
2083
2084 /* Request AF to attach NPA and NIX LFs to this PF.
2085 * NIX and NPA LFs are needed for this PF to function as a NIC.
2086 */
2087 err = otx2_attach_npa_nix(pf);
2088 if (err)
2089 goto err_disable_mbox_intr;
2090
2091 err = otx2_realloc_msix_vectors(pf);
2092 if (err)
2093 goto err_detach_rsrc;
2094
2095 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues);
2096 if (err)
2097 goto err_detach_rsrc;
2098
2099 otx2_setup_dev_hw_settings(pf);
2100
2101 /* Assign default mac address */
2102 otx2_get_mac_from_af(netdev);
2103
2104 /* Don't check for error. Proceed without ptp */
2105 otx2_ptp_init(pf);
2106
2107 /* NPA's pool is a stack to which SW frees buffer pointers via Aura.
2108 * HW allocates buffer pointer from stack and uses it for DMA'ing
2109 * ingress packet. In some scenarios HW can free back allocated buffer
2110 * pointers to pool. This makes it impossible for SW to maintain a
2111 * parallel list where physical addresses of buffer pointers (IOVAs)
2112 * given to HW can be saved for later reference.
2113 *
2114 * So the only way to convert Rx packet's buffer address is to use
2115 * IOMMU's iova_to_phys() handler which translates the address by
2116 * walking through the translation tables.
2117 */
2118 pf->iommu_domain = iommu_get_domain_for_dev(dev);
2119
2120 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
2121 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
2122 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
2123 NETIF_F_GSO_UDP_L4);
2124 netdev->features |= netdev->hw_features;
2125
2126 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL;
2127
2128 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS;
2129 netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
2130
2131 netdev->netdev_ops = &otx2_netdev_ops;
2132
2133 /* MTU range: 64 - 9190 */
2134 netdev->min_mtu = OTX2_MIN_MTU;
2135 netdev->max_mtu = OTX2_MAX_MTU;
2136
2137 err = register_netdev(netdev);
2138 if (err) {
2139 dev_err(dev, "Failed to register netdevice\n");
2140 goto err_ptp_destroy;
2141 }
2142
2143 err = otx2_wq_init(pf);
2144 if (err)
2145 goto err_unreg_netdev;
2146
2147 otx2_set_ethtool_ops(netdev);
2148
2149 /* Enable link notifications */
2150 otx2_cgx_config_linkevents(pf, true);
2151
2152 /* Enable pause frames by default */
2153 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED;
2154 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED;
2155
2156 return 0;
2157
2158 err_unreg_netdev:
2159 unregister_netdev(netdev);
2160 err_ptp_destroy:
2161 otx2_ptp_destroy(pf);
2162 err_detach_rsrc:
2163 otx2_detach_resources(&pf->mbox);
2164 err_disable_mbox_intr:
2165 otx2_disable_mbox_intr(pf);
2166 err_mbox_destroy:
2167 otx2_pfaf_mbox_destroy(pf);
2168 err_free_irq_vectors:
2169 pci_free_irq_vectors(hw->pdev);
2170 err_free_netdev:
2171 pci_set_drvdata(pdev, NULL);
2172 free_netdev(netdev);
2173 err_release_regions:
2174 pci_release_regions(pdev);
2175 return err;
2176 }
2177
otx2_vf_link_event_task(struct work_struct * work)2178 static void otx2_vf_link_event_task(struct work_struct *work)
2179 {
2180 struct otx2_vf_config *config;
2181 struct cgx_link_info_msg *req;
2182 struct mbox_msghdr *msghdr;
2183 struct otx2_nic *pf;
2184 int vf_idx;
2185
2186 config = container_of(work, struct otx2_vf_config,
2187 link_event_work.work);
2188 vf_idx = config - config->pf->vf_configs;
2189 pf = config->pf;
2190
2191 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx,
2192 sizeof(*req), sizeof(struct msg_rsp));
2193 if (!msghdr) {
2194 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx);
2195 return;
2196 }
2197
2198 req = (struct cgx_link_info_msg *)msghdr;
2199 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
2200 req->hdr.sig = OTX2_MBOX_REQ_SIG;
2201 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info));
2202
2203 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx);
2204 }
2205
otx2_sriov_enable(struct pci_dev * pdev,int numvfs)2206 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs)
2207 {
2208 struct net_device *netdev = pci_get_drvdata(pdev);
2209 struct otx2_nic *pf = netdev_priv(netdev);
2210 int ret, i;
2211
2212 /* Init PF <=> VF mailbox stuff */
2213 ret = otx2_pfvf_mbox_init(pf, numvfs);
2214 if (ret)
2215 return ret;
2216
2217 ret = otx2_register_pfvf_mbox_intr(pf, numvfs);
2218 if (ret)
2219 goto free_mbox;
2220
2221 pf->vf_configs = kcalloc(numvfs, sizeof(struct otx2_vf_config),
2222 GFP_KERNEL);
2223 if (!pf->vf_configs) {
2224 ret = -ENOMEM;
2225 goto free_intr;
2226 }
2227
2228 for (i = 0; i < numvfs; i++) {
2229 pf->vf_configs[i].pf = pf;
2230 pf->vf_configs[i].intf_down = true;
2231 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work,
2232 otx2_vf_link_event_task);
2233 }
2234
2235 ret = otx2_pf_flr_init(pf, numvfs);
2236 if (ret)
2237 goto free_configs;
2238
2239 ret = otx2_register_flr_me_intr(pf, numvfs);
2240 if (ret)
2241 goto free_flr;
2242
2243 ret = pci_enable_sriov(pdev, numvfs);
2244 if (ret)
2245 goto free_flr_intr;
2246
2247 return numvfs;
2248 free_flr_intr:
2249 otx2_disable_flr_me_intr(pf);
2250 free_flr:
2251 otx2_flr_wq_destroy(pf);
2252 free_configs:
2253 kfree(pf->vf_configs);
2254 free_intr:
2255 otx2_disable_pfvf_mbox_intr(pf, numvfs);
2256 free_mbox:
2257 otx2_pfvf_mbox_destroy(pf);
2258 return ret;
2259 }
2260
otx2_sriov_disable(struct pci_dev * pdev)2261 static int otx2_sriov_disable(struct pci_dev *pdev)
2262 {
2263 struct net_device *netdev = pci_get_drvdata(pdev);
2264 struct otx2_nic *pf = netdev_priv(netdev);
2265 int numvfs = pci_num_vf(pdev);
2266 int i;
2267
2268 if (!numvfs)
2269 return 0;
2270
2271 pci_disable_sriov(pdev);
2272
2273 for (i = 0; i < pci_num_vf(pdev); i++)
2274 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work);
2275 kfree(pf->vf_configs);
2276
2277 otx2_disable_flr_me_intr(pf);
2278 otx2_flr_wq_destroy(pf);
2279 otx2_disable_pfvf_mbox_intr(pf, numvfs);
2280 otx2_pfvf_mbox_destroy(pf);
2281
2282 return 0;
2283 }
2284
otx2_sriov_configure(struct pci_dev * pdev,int numvfs)2285 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs)
2286 {
2287 if (numvfs == 0)
2288 return otx2_sriov_disable(pdev);
2289 else
2290 return otx2_sriov_enable(pdev, numvfs);
2291 }
2292
otx2_remove(struct pci_dev * pdev)2293 static void otx2_remove(struct pci_dev *pdev)
2294 {
2295 struct net_device *netdev = pci_get_drvdata(pdev);
2296 struct otx2_nic *pf;
2297
2298 if (!netdev)
2299 return;
2300
2301 pf = netdev_priv(netdev);
2302
2303 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED)
2304 otx2_config_hw_tx_tstamp(pf, false);
2305 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)
2306 otx2_config_hw_rx_tstamp(pf, false);
2307
2308 cancel_work_sync(&pf->reset_task);
2309 /* Disable link notifications */
2310 otx2_cgx_config_linkevents(pf, false);
2311
2312 unregister_netdev(netdev);
2313 otx2_sriov_disable(pf->pdev);
2314 if (pf->otx2_wq)
2315 destroy_workqueue(pf->otx2_wq);
2316
2317 otx2_ptp_destroy(pf);
2318 otx2_detach_resources(&pf->mbox);
2319 otx2_disable_mbox_intr(pf);
2320 otx2_pfaf_mbox_destroy(pf);
2321 pci_free_irq_vectors(pf->pdev);
2322 pci_set_drvdata(pdev, NULL);
2323 free_netdev(netdev);
2324
2325 pci_release_regions(pdev);
2326 }
2327
2328 static struct pci_driver otx2_pf_driver = {
2329 .name = DRV_NAME,
2330 .id_table = otx2_pf_id_table,
2331 .probe = otx2_probe,
2332 .shutdown = otx2_remove,
2333 .remove = otx2_remove,
2334 .sriov_configure = otx2_sriov_configure
2335 };
2336
otx2_rvupf_init_module(void)2337 static int __init otx2_rvupf_init_module(void)
2338 {
2339 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
2340
2341 return pci_register_driver(&otx2_pf_driver);
2342 }
2343
otx2_rvupf_cleanup_module(void)2344 static void __exit otx2_rvupf_cleanup_module(void)
2345 {
2346 pci_unregister_driver(&otx2_pf_driver);
2347 }
2348
2349 module_init(otx2_rvupf_init_module);
2350 module_exit(otx2_rvupf_cleanup_module);
2351