1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "resource.h"
31 #include "include/irq_service_interface.h"
32 #include "link_encoder.h"
33 #include "stream_encoder.h"
34 #include "opp.h"
35 #include "timing_generator.h"
36 #include "transform.h"
37 #include "dccg.h"
38 #include "dchubbub.h"
39 #include "dpp.h"
40 #include "core_types.h"
41 #include "set_mode_types.h"
42 #include "virtual/virtual_stream_encoder.h"
43 #include "dpcd_defs.h"
44
45 #if defined(CONFIG_DRM_AMD_DC_SI)
46 #include "dce60/dce60_resource.h"
47 #endif
48 #include "dce80/dce80_resource.h"
49 #include "dce100/dce100_resource.h"
50 #include "dce110/dce110_resource.h"
51 #include "dce112/dce112_resource.h"
52 #include "dce120/dce120_resource.h"
53 #if defined(CONFIG_DRM_AMD_DC_DCN)
54 #include "dcn10/dcn10_resource.h"
55 #include "dcn20/dcn20_resource.h"
56 #include "dcn21/dcn21_resource.h"
57 #endif
58 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
59 #include "../dcn30/dcn30_resource.h"
60 #endif
61
62 #define DC_LOGGER_INIT(logger)
63
resource_parse_asic_id(struct hw_asic_id asic_id)64 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
65 {
66 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
67 switch (asic_id.chip_family) {
68
69 #if defined(CONFIG_DRM_AMD_DC_SI)
70 case FAMILY_SI:
71 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
72 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
73 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
74 dc_version = DCE_VERSION_6_0;
75 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
76 dc_version = DCE_VERSION_6_4;
77 else
78 dc_version = DCE_VERSION_6_1;
79 break;
80 #endif
81 case FAMILY_CI:
82 dc_version = DCE_VERSION_8_0;
83 break;
84 case FAMILY_KV:
85 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
86 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
87 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
88 dc_version = DCE_VERSION_8_3;
89 else
90 dc_version = DCE_VERSION_8_1;
91 break;
92 case FAMILY_CZ:
93 dc_version = DCE_VERSION_11_0;
94 break;
95
96 case FAMILY_VI:
97 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
98 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
99 dc_version = DCE_VERSION_10_0;
100 break;
101 }
102 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
103 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
104 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
105 dc_version = DCE_VERSION_11_2;
106 }
107 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
108 dc_version = DCE_VERSION_11_22;
109 break;
110 case FAMILY_AI:
111 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
112 dc_version = DCE_VERSION_12_1;
113 else
114 dc_version = DCE_VERSION_12_0;
115 break;
116 #if defined(CONFIG_DRM_AMD_DC_DCN)
117 case FAMILY_RV:
118 dc_version = DCN_VERSION_1_0;
119 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
120 dc_version = DCN_VERSION_1_01;
121 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
122 dc_version = DCN_VERSION_2_1;
123 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
124 dc_version = DCN_VERSION_2_1;
125 break;
126 #endif
127
128 case FAMILY_NV:
129 dc_version = DCN_VERSION_2_0;
130 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
131 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
132 dc_version = DCN_VERSION_3_0;
133 #endif
134 break;
135 default:
136 dc_version = DCE_VERSION_UNKNOWN;
137 break;
138 }
139 return dc_version;
140 }
141
dc_create_resource_pool(struct dc * dc,const struct dc_init_data * init_data,enum dce_version dc_version)142 struct resource_pool *dc_create_resource_pool(struct dc *dc,
143 const struct dc_init_data *init_data,
144 enum dce_version dc_version)
145 {
146 struct resource_pool *res_pool = NULL;
147
148 switch (dc_version) {
149 #if defined(CONFIG_DRM_AMD_DC_SI)
150 case DCE_VERSION_6_0:
151 res_pool = dce60_create_resource_pool(
152 init_data->num_virtual_links, dc);
153 break;
154 case DCE_VERSION_6_1:
155 res_pool = dce61_create_resource_pool(
156 init_data->num_virtual_links, dc);
157 break;
158 case DCE_VERSION_6_4:
159 res_pool = dce64_create_resource_pool(
160 init_data->num_virtual_links, dc);
161 break;
162 #endif
163 case DCE_VERSION_8_0:
164 res_pool = dce80_create_resource_pool(
165 init_data->num_virtual_links, dc);
166 break;
167 case DCE_VERSION_8_1:
168 res_pool = dce81_create_resource_pool(
169 init_data->num_virtual_links, dc);
170 break;
171 case DCE_VERSION_8_3:
172 res_pool = dce83_create_resource_pool(
173 init_data->num_virtual_links, dc);
174 break;
175 case DCE_VERSION_10_0:
176 res_pool = dce100_create_resource_pool(
177 init_data->num_virtual_links, dc);
178 break;
179 case DCE_VERSION_11_0:
180 res_pool = dce110_create_resource_pool(
181 init_data->num_virtual_links, dc,
182 init_data->asic_id);
183 break;
184 case DCE_VERSION_11_2:
185 case DCE_VERSION_11_22:
186 res_pool = dce112_create_resource_pool(
187 init_data->num_virtual_links, dc);
188 break;
189 case DCE_VERSION_12_0:
190 case DCE_VERSION_12_1:
191 res_pool = dce120_create_resource_pool(
192 init_data->num_virtual_links, dc);
193 break;
194
195 #if defined(CONFIG_DRM_AMD_DC_DCN)
196 case DCN_VERSION_1_0:
197 case DCN_VERSION_1_01:
198 res_pool = dcn10_create_resource_pool(init_data, dc);
199 break;
200
201
202 case DCN_VERSION_2_0:
203 res_pool = dcn20_create_resource_pool(init_data, dc);
204 break;
205 case DCN_VERSION_2_1:
206 res_pool = dcn21_create_resource_pool(init_data, dc);
207 break;
208 #endif
209 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
210 case DCN_VERSION_3_0:
211 res_pool = dcn30_create_resource_pool(init_data, dc);
212 break;
213 #endif
214
215 default:
216 break;
217 }
218
219 if (res_pool != NULL) {
220 if (dc->ctx->dc_bios->fw_info_valid) {
221 res_pool->ref_clocks.xtalin_clock_inKhz =
222 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
223 /* initialize with firmware data first, no all
224 * ASIC have DCCG SW component. FPGA or
225 * simulation need initialization of
226 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
227 * with xtalin_clock_inKhz
228 */
229 res_pool->ref_clocks.dccg_ref_clock_inKhz =
230 res_pool->ref_clocks.xtalin_clock_inKhz;
231 res_pool->ref_clocks.dchub_ref_clock_inKhz =
232 res_pool->ref_clocks.xtalin_clock_inKhz;
233 } else
234 ASSERT_CRITICAL(false);
235 }
236
237 return res_pool;
238 }
239
dc_destroy_resource_pool(struct dc * dc)240 void dc_destroy_resource_pool(struct dc *dc)
241 {
242 if (dc) {
243 if (dc->res_pool)
244 dc->res_pool->funcs->destroy(&dc->res_pool);
245
246 kfree(dc->hwseq);
247 }
248 }
249
update_num_audio(const struct resource_straps * straps,unsigned int * num_audio,struct audio_support * aud_support)250 static void update_num_audio(
251 const struct resource_straps *straps,
252 unsigned int *num_audio,
253 struct audio_support *aud_support)
254 {
255 aud_support->dp_audio = true;
256 aud_support->hdmi_audio_native = false;
257 aud_support->hdmi_audio_on_dongle = false;
258
259 if (straps->hdmi_disable == 0) {
260 if (straps->dc_pinstraps_audio & 0x2) {
261 aud_support->hdmi_audio_on_dongle = true;
262 aud_support->hdmi_audio_native = true;
263 }
264 }
265
266 switch (straps->audio_stream_number) {
267 case 0: /* multi streams supported */
268 break;
269 case 1: /* multi streams not supported */
270 *num_audio = 1;
271 break;
272 default:
273 DC_ERR("DC: unexpected audio fuse!\n");
274 }
275 }
276
resource_construct(unsigned int num_virtual_links,struct dc * dc,struct resource_pool * pool,const struct resource_create_funcs * create_funcs)277 bool resource_construct(
278 unsigned int num_virtual_links,
279 struct dc *dc,
280 struct resource_pool *pool,
281 const struct resource_create_funcs *create_funcs)
282 {
283 struct dc_context *ctx = dc->ctx;
284 const struct resource_caps *caps = pool->res_cap;
285 int i;
286 unsigned int num_audio = caps->num_audio;
287 struct resource_straps straps = {0};
288
289 if (create_funcs->read_dce_straps)
290 create_funcs->read_dce_straps(dc->ctx, &straps);
291
292 pool->audio_count = 0;
293 if (create_funcs->create_audio) {
294 /* find the total number of streams available via the
295 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
296 * registers (one for each pin) starting from pin 1
297 * up to the max number of audio pins.
298 * We stop on the first pin where
299 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
300 */
301 update_num_audio(&straps, &num_audio, &pool->audio_support);
302 for (i = 0; i < caps->num_audio; i++) {
303 struct audio *aud = create_funcs->create_audio(ctx, i);
304
305 if (aud == NULL) {
306 DC_ERR("DC: failed to create audio!\n");
307 return false;
308 }
309 if (!aud->funcs->endpoint_valid(aud)) {
310 aud->funcs->destroy(&aud);
311 break;
312 }
313 pool->audios[i] = aud;
314 pool->audio_count++;
315 }
316 }
317
318 pool->stream_enc_count = 0;
319 if (create_funcs->create_stream_encoder) {
320 for (i = 0; i < caps->num_stream_encoder; i++) {
321 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
322 if (pool->stream_enc[i] == NULL)
323 DC_ERR("DC: failed to create stream_encoder!\n");
324 pool->stream_enc_count++;
325 }
326 }
327
328 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
329 for (i = 0; i < caps->num_mpc_3dlut; i++) {
330 pool->mpc_lut[i] = dc_create_3dlut_func();
331 if (pool->mpc_lut[i] == NULL)
332 DC_ERR("DC: failed to create MPC 3dlut!\n");
333 pool->mpc_shaper[i] = dc_create_transfer_func();
334 if (pool->mpc_shaper[i] == NULL)
335 DC_ERR("DC: failed to create MPC shaper!\n");
336 }
337 #endif
338 dc->caps.dynamic_audio = false;
339 if (pool->audio_count < pool->stream_enc_count) {
340 dc->caps.dynamic_audio = true;
341 }
342 for (i = 0; i < num_virtual_links; i++) {
343 pool->stream_enc[pool->stream_enc_count] =
344 virtual_stream_encoder_create(
345 ctx, ctx->dc_bios);
346 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
347 DC_ERR("DC: failed to create stream_encoder!\n");
348 return false;
349 }
350 pool->stream_enc_count++;
351 }
352
353 dc->hwseq = create_funcs->create_hwseq(ctx);
354
355 return true;
356 }
find_matching_clock_source(const struct resource_pool * pool,struct clock_source * clock_source)357 static int find_matching_clock_source(
358 const struct resource_pool *pool,
359 struct clock_source *clock_source)
360 {
361
362 int i;
363
364 for (i = 0; i < pool->clk_src_count; i++) {
365 if (pool->clock_sources[i] == clock_source)
366 return i;
367 }
368 return -1;
369 }
370
resource_unreference_clock_source(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)371 void resource_unreference_clock_source(
372 struct resource_context *res_ctx,
373 const struct resource_pool *pool,
374 struct clock_source *clock_source)
375 {
376 int i = find_matching_clock_source(pool, clock_source);
377
378 if (i > -1)
379 res_ctx->clock_source_ref_count[i]--;
380
381 if (pool->dp_clock_source == clock_source)
382 res_ctx->dp_clock_source_ref_count--;
383 }
384
resource_reference_clock_source(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)385 void resource_reference_clock_source(
386 struct resource_context *res_ctx,
387 const struct resource_pool *pool,
388 struct clock_source *clock_source)
389 {
390 int i = find_matching_clock_source(pool, clock_source);
391
392 if (i > -1)
393 res_ctx->clock_source_ref_count[i]++;
394
395 if (pool->dp_clock_source == clock_source)
396 res_ctx->dp_clock_source_ref_count++;
397 }
398
resource_get_clock_source_reference(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)399 int resource_get_clock_source_reference(
400 struct resource_context *res_ctx,
401 const struct resource_pool *pool,
402 struct clock_source *clock_source)
403 {
404 int i = find_matching_clock_source(pool, clock_source);
405
406 if (i > -1)
407 return res_ctx->clock_source_ref_count[i];
408
409 if (pool->dp_clock_source == clock_source)
410 return res_ctx->dp_clock_source_ref_count;
411
412 return -1;
413 }
414
resource_are_streams_timing_synchronizable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)415 bool resource_are_streams_timing_synchronizable(
416 struct dc_stream_state *stream1,
417 struct dc_stream_state *stream2)
418 {
419 if (stream1->timing.h_total != stream2->timing.h_total)
420 return false;
421
422 if (stream1->timing.v_total != stream2->timing.v_total)
423 return false;
424
425 if (stream1->timing.h_addressable
426 != stream2->timing.h_addressable)
427 return false;
428
429 if (stream1->timing.v_addressable
430 != stream2->timing.v_addressable)
431 return false;
432
433 if (stream1->timing.v_front_porch
434 != stream2->timing.v_front_porch)
435 return false;
436
437 if (stream1->timing.pix_clk_100hz
438 != stream2->timing.pix_clk_100hz)
439 return false;
440
441 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
442 return false;
443
444 if (stream1->phy_pix_clk != stream2->phy_pix_clk
445 && (!dc_is_dp_signal(stream1->signal)
446 || !dc_is_dp_signal(stream2->signal)))
447 return false;
448
449 if (stream1->view_format != stream2->view_format)
450 return false;
451
452 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
453 return false;
454
455 return true;
456 }
is_dp_and_hdmi_sharable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)457 static bool is_dp_and_hdmi_sharable(
458 struct dc_stream_state *stream1,
459 struct dc_stream_state *stream2)
460 {
461 if (stream1->ctx->dc->caps.disable_dp_clk_share)
462 return false;
463
464 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
465 stream2->clamping.c_depth != COLOR_DEPTH_888)
466 return false;
467
468 return true;
469
470 }
471
is_sharable_clk_src(const struct pipe_ctx * pipe_with_clk_src,const struct pipe_ctx * pipe)472 static bool is_sharable_clk_src(
473 const struct pipe_ctx *pipe_with_clk_src,
474 const struct pipe_ctx *pipe)
475 {
476 if (pipe_with_clk_src->clock_source == NULL)
477 return false;
478
479 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
480 return false;
481
482 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
483 (dc_is_dp_signal(pipe->stream->signal) &&
484 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
485 pipe->stream)))
486 return false;
487
488 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
489 && dc_is_dual_link_signal(pipe->stream->signal))
490 return false;
491
492 if (dc_is_hdmi_signal(pipe->stream->signal)
493 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
494 return false;
495
496 if (!resource_are_streams_timing_synchronizable(
497 pipe_with_clk_src->stream, pipe->stream))
498 return false;
499
500 return true;
501 }
502
resource_find_used_clk_src_for_sharing(struct resource_context * res_ctx,struct pipe_ctx * pipe_ctx)503 struct clock_source *resource_find_used_clk_src_for_sharing(
504 struct resource_context *res_ctx,
505 struct pipe_ctx *pipe_ctx)
506 {
507 int i;
508
509 for (i = 0; i < MAX_PIPES; i++) {
510 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
511 return res_ctx->pipe_ctx[i].clock_source;
512 }
513
514 return NULL;
515 }
516
convert_pixel_format_to_dalsurface(enum surface_pixel_format surface_pixel_format)517 static enum pixel_format convert_pixel_format_to_dalsurface(
518 enum surface_pixel_format surface_pixel_format)
519 {
520 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
521
522 switch (surface_pixel_format) {
523 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
524 dal_pixel_format = PIXEL_FORMAT_INDEX8;
525 break;
526 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
527 dal_pixel_format = PIXEL_FORMAT_RGB565;
528 break;
529 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
530 dal_pixel_format = PIXEL_FORMAT_RGB565;
531 break;
532 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
533 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
534 break;
535 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
536 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
537 break;
538 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
539 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
540 break;
541 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
542 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
543 break;
544 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
545 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
546 break;
547 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
548 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
549 dal_pixel_format = PIXEL_FORMAT_FP16;
550 break;
551 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
552 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
553 dal_pixel_format = PIXEL_FORMAT_420BPP8;
554 break;
555 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
556 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
557 dal_pixel_format = PIXEL_FORMAT_420BPP10;
558 break;
559 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
560 default:
561 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
562 break;
563 }
564 return dal_pixel_format;
565 }
566
get_vp_scan_direction(enum dc_rotation_angle rotation,bool horizontal_mirror,bool * orthogonal_rotation,bool * flip_vert_scan_dir,bool * flip_horz_scan_dir)567 static inline void get_vp_scan_direction(
568 enum dc_rotation_angle rotation,
569 bool horizontal_mirror,
570 bool *orthogonal_rotation,
571 bool *flip_vert_scan_dir,
572 bool *flip_horz_scan_dir)
573 {
574 *orthogonal_rotation = false;
575 *flip_vert_scan_dir = false;
576 *flip_horz_scan_dir = false;
577 if (rotation == ROTATION_ANGLE_180) {
578 *flip_vert_scan_dir = true;
579 *flip_horz_scan_dir = true;
580 } else if (rotation == ROTATION_ANGLE_90) {
581 *orthogonal_rotation = true;
582 *flip_horz_scan_dir = true;
583 } else if (rotation == ROTATION_ANGLE_270) {
584 *orthogonal_rotation = true;
585 *flip_vert_scan_dir = true;
586 }
587
588 if (horizontal_mirror)
589 *flip_horz_scan_dir = !*flip_horz_scan_dir;
590 }
591
get_num_mpc_splits(struct pipe_ctx * pipe)592 int get_num_mpc_splits(struct pipe_ctx *pipe)
593 {
594 int mpc_split_count = 0;
595 struct pipe_ctx *other_pipe = pipe->bottom_pipe;
596
597 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
598 mpc_split_count++;
599 other_pipe = other_pipe->bottom_pipe;
600 }
601 other_pipe = pipe->top_pipe;
602 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
603 mpc_split_count++;
604 other_pipe = other_pipe->top_pipe;
605 }
606
607 return mpc_split_count;
608 }
609
get_num_odm_splits(struct pipe_ctx * pipe)610 int get_num_odm_splits(struct pipe_ctx *pipe)
611 {
612 int odm_split_count = 0;
613 struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
614 while (next_pipe) {
615 odm_split_count++;
616 next_pipe = next_pipe->next_odm_pipe;
617 }
618 pipe = pipe->prev_odm_pipe;
619 while (pipe) {
620 odm_split_count++;
621 pipe = pipe->prev_odm_pipe;
622 }
623 return odm_split_count;
624 }
625
calculate_split_count_and_index(struct pipe_ctx * pipe_ctx,int * split_count,int * split_idx)626 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
627 {
628 *split_count = get_num_odm_splits(pipe_ctx);
629 *split_idx = 0;
630 if (*split_count == 0) {
631 /*Check for mpc split*/
632 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
633
634 *split_count = get_num_mpc_splits(pipe_ctx);
635 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
636 (*split_idx)++;
637 split_pipe = split_pipe->top_pipe;
638 }
639 } else {
640 /*Get odm split index*/
641 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
642
643 while (split_pipe) {
644 (*split_idx)++;
645 split_pipe = split_pipe->prev_odm_pipe;
646 }
647 }
648 }
649
calculate_viewport(struct pipe_ctx * pipe_ctx)650 static void calculate_viewport(struct pipe_ctx *pipe_ctx)
651 {
652 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
653 const struct dc_stream_state *stream = pipe_ctx->stream;
654 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
655 struct rect surf_src = plane_state->src_rect;
656 struct rect clip, dest;
657 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
658 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
659 int split_count = 0;
660 int split_idx = 0;
661 bool orthogonal_rotation, flip_y_start, flip_x_start;
662
663 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
664
665 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
666 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
667 split_count = 0;
668 split_idx = 0;
669 }
670
671 /* The actual clip is an intersection between stream
672 * source and surface clip
673 */
674 dest = plane_state->dst_rect;
675 clip.x = stream->src.x > plane_state->clip_rect.x ?
676 stream->src.x : plane_state->clip_rect.x;
677
678 clip.width = stream->src.x + stream->src.width <
679 plane_state->clip_rect.x + plane_state->clip_rect.width ?
680 stream->src.x + stream->src.width - clip.x :
681 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
682
683 clip.y = stream->src.y > plane_state->clip_rect.y ?
684 stream->src.y : plane_state->clip_rect.y;
685
686 clip.height = stream->src.y + stream->src.height <
687 plane_state->clip_rect.y + plane_state->clip_rect.height ?
688 stream->src.y + stream->src.height - clip.y :
689 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
690
691 /*
692 * Need to calculate how scan origin is shifted in vp space
693 * to correctly rotate clip and dst
694 */
695 get_vp_scan_direction(
696 plane_state->rotation,
697 plane_state->horizontal_mirror,
698 &orthogonal_rotation,
699 &flip_y_start,
700 &flip_x_start);
701
702 if (orthogonal_rotation) {
703 swap(clip.x, clip.y);
704 swap(clip.width, clip.height);
705 swap(dest.x, dest.y);
706 swap(dest.width, dest.height);
707 }
708 if (flip_x_start) {
709 clip.x = dest.x + dest.width - clip.x - clip.width;
710 dest.x = 0;
711 }
712 if (flip_y_start) {
713 clip.y = dest.y + dest.height - clip.y - clip.height;
714 dest.y = 0;
715 }
716
717 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
718 * num_pixels = clip.num_pix * scl_ratio
719 */
720 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
721 data->viewport.width = clip.width * surf_src.width / dest.width;
722
723 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
724 data->viewport.height = clip.height * surf_src.height / dest.height;
725
726 /* Handle split */
727 if (split_count) {
728 /* extra pixels in the division remainder need to go to pipes after
729 * the extra pixel index minus one(epimo) defined here as:
730 */
731 int epimo = 0;
732
733 if (orthogonal_rotation) {
734 if (flip_y_start)
735 split_idx = split_count - split_idx;
736
737 epimo = split_count - data->viewport.height % (split_count + 1);
738
739 data->viewport.y += (data->viewport.height / (split_count + 1)) * split_idx;
740 if (split_idx > epimo)
741 data->viewport.y += split_idx - epimo - 1;
742 data->viewport.height = data->viewport.height / (split_count + 1) + (split_idx > epimo ? 1 : 0);
743 } else {
744 if (flip_x_start)
745 split_idx = split_count - split_idx;
746
747 epimo = split_count - data->viewport.width % (split_count + 1);
748
749 data->viewport.x += (data->viewport.width / (split_count + 1)) * split_idx;
750 if (split_idx > epimo)
751 data->viewport.x += split_idx - epimo - 1;
752 data->viewport.width = data->viewport.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
753 }
754 }
755
756 /* Round down, compensate in init */
757 data->viewport_c.x = data->viewport.x / vpc_div;
758 data->viewport_c.y = data->viewport.y / vpc_div;
759 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
760 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
761
762 /* Round up, assume original video size always even dimensions */
763 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
764 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
765
766 data->viewport_unadjusted = data->viewport;
767 data->viewport_c_unadjusted = data->viewport_c;
768 }
769
calculate_recout(struct pipe_ctx * pipe_ctx)770 static void calculate_recout(struct pipe_ctx *pipe_ctx)
771 {
772 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
773 const struct dc_stream_state *stream = pipe_ctx->stream;
774 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
775 struct rect surf_clip = plane_state->clip_rect;
776 bool pri_split_tb = pipe_ctx->bottom_pipe &&
777 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state &&
778 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
779 bool sec_split_tb = pipe_ctx->top_pipe &&
780 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state &&
781 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
782 int split_count = 0;
783 int split_idx = 0;
784
785 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
786
787 /*
788 * Only the leftmost ODM pipe should be offset by a nonzero distance
789 */
790 if (!pipe_ctx->prev_odm_pipe) {
791 data->recout.x = stream->dst.x;
792 if (stream->src.x < surf_clip.x)
793 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
794 / stream->src.width;
795
796 } else
797 data->recout.x = 0;
798
799 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
800 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
801 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
802
803 data->recout.y = stream->dst.y;
804 if (stream->src.y < surf_clip.y)
805 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
806 / stream->src.height;
807
808 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
809 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
810 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
811
812 /* Handle h & v split, handle rotation using viewport */
813 if (sec_split_tb) {
814 data->recout.y += data->recout.height / 2;
815 /* Floor primary pipe, ceil 2ndary pipe */
816 data->recout.height = (data->recout.height + 1) / 2;
817 } else if (pri_split_tb)
818 data->recout.height /= 2;
819 else if (split_count) {
820 /* extra pixels in the division remainder need to go to pipes after
821 * the extra pixel index minus one(epimo) defined here as:
822 */
823 int epimo = split_count - data->recout.width % (split_count + 1);
824
825 /*no recout offset due to odm */
826 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
827 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
828 if (split_idx > epimo)
829 data->recout.x += split_idx - epimo - 1;
830 }
831 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
832 }
833 }
834
calculate_scaling_ratios(struct pipe_ctx * pipe_ctx)835 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
836 {
837 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
838 const struct dc_stream_state *stream = pipe_ctx->stream;
839 struct rect surf_src = plane_state->src_rect;
840 const int in_w = stream->src.width;
841 const int in_h = stream->src.height;
842 const int out_w = stream->dst.width;
843 const int out_h = stream->dst.height;
844
845 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
846 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
847 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
848 swap(surf_src.height, surf_src.width);
849
850 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
851 surf_src.width,
852 plane_state->dst_rect.width);
853 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
854 surf_src.height,
855 plane_state->dst_rect.height);
856
857 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
858 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
859 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
860 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
861
862 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
863 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
864 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
865 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
866
867 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
868 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
869
870 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
871 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
872 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
873 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
874 }
875 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
876 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
877 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
878 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
879 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
880 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
881 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
882 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
883 }
884
adjust_vp_and_init_for_seamless_clip(bool flip_scan_dir,int recout_skip,int src_size,int taps,struct fixed31_32 ratio,struct fixed31_32 * init,int * vp_offset,int * vp_size)885 static inline void adjust_vp_and_init_for_seamless_clip(
886 bool flip_scan_dir,
887 int recout_skip,
888 int src_size,
889 int taps,
890 struct fixed31_32 ratio,
891 struct fixed31_32 *init,
892 int *vp_offset,
893 int *vp_size)
894 {
895 if (!flip_scan_dir) {
896 /* Adjust for viewport end clip-off */
897 if ((*vp_offset + *vp_size) < src_size) {
898 int vp_clip = src_size - *vp_size - *vp_offset;
899 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
900
901 int_part = int_part > 0 ? int_part : 0;
902 *vp_size += int_part < vp_clip ? int_part : vp_clip;
903 }
904
905 /* Adjust for non-0 viewport offset */
906 if (*vp_offset) {
907 int int_part;
908
909 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
910 int_part = dc_fixpt_floor(*init) - *vp_offset;
911 if (int_part < taps) {
912 int int_adj = *vp_offset >= (taps - int_part) ?
913 (taps - int_part) : *vp_offset;
914 *vp_offset -= int_adj;
915 *vp_size += int_adj;
916 int_part += int_adj;
917 } else if (int_part > taps) {
918 *vp_offset += int_part - taps;
919 *vp_size -= int_part - taps;
920 int_part = taps;
921 }
922 init->value &= 0xffffffff;
923 *init = dc_fixpt_add_int(*init, int_part);
924 }
925 } else {
926 /* Adjust for non-0 viewport offset */
927 if (*vp_offset) {
928 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
929
930 int_part = int_part > 0 ? int_part : 0;
931 *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
932 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
933 }
934
935 /* Adjust for viewport end clip-off */
936 if ((*vp_offset + *vp_size) < src_size) {
937 int int_part;
938 int end_offset = src_size - *vp_offset - *vp_size;
939
940 /*
941 * this is init if vp had no offset, keep in mind this is from the
942 * right side of vp due to scan direction
943 */
944 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
945 /*
946 * this is the difference between first pixel of viewport available to read
947 * and init position, takning into account scan direction
948 */
949 int_part = dc_fixpt_floor(*init) - end_offset;
950 if (int_part < taps) {
951 int int_adj = end_offset >= (taps - int_part) ?
952 (taps - int_part) : end_offset;
953 *vp_size += int_adj;
954 int_part += int_adj;
955 } else if (int_part > taps) {
956 *vp_size += int_part - taps;
957 int_part = taps;
958 }
959 init->value &= 0xffffffff;
960 *init = dc_fixpt_add_int(*init, int_part);
961 }
962 }
963 }
964
calculate_inits_and_adj_vp(struct pipe_ctx * pipe_ctx)965 static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
966 {
967 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
968 const struct dc_stream_state *stream = pipe_ctx->stream;
969 struct pipe_ctx *odm_pipe = pipe_ctx;
970 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
971 struct rect src = pipe_ctx->plane_state->src_rect;
972 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
973 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
974 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
975 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
976 int odm_idx = 0;
977
978 /*
979 * Need to calculate the scan direction for viewport to make adjustments
980 */
981 get_vp_scan_direction(
982 plane_state->rotation,
983 plane_state->horizontal_mirror,
984 &orthogonal_rotation,
985 &flip_vert_scan_dir,
986 &flip_horz_scan_dir);
987
988 /* Calculate src rect rotation adjusted to recout space */
989 surf_size_h = src.x + src.width;
990 surf_size_v = src.y + src.height;
991 if (flip_horz_scan_dir)
992 src.x = 0;
993 if (flip_vert_scan_dir)
994 src.y = 0;
995 if (orthogonal_rotation) {
996 swap(src.x, src.y);
997 swap(src.width, src.height);
998 }
999
1000 /*modified recout_skip_h calculation due to odm having no recout offset*/
1001 while (odm_pipe->prev_odm_pipe) {
1002 odm_idx++;
1003 odm_pipe = odm_pipe->prev_odm_pipe;
1004 }
1005 /*odm_pipe is the leftmost pipe in the ODM group*/
1006 recout_skip_h = odm_idx * data->recout.width;
1007
1008 /* Recout matching initial vp offset = recout_offset - (stream dst offset +
1009 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
1010 * - (surf surf_src offset * 1/ full scl ratio))
1011 */
1012 recout_skip_h += odm_pipe->plane_res.scl_data.recout.x
1013 - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
1014 * stream->dst.width / stream->src.width -
1015 src.x * plane_state->dst_rect.width / src.width
1016 * stream->dst.width / stream->src.width);
1017
1018
1019 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
1020 * stream->dst.height / stream->src.height -
1021 src.y * plane_state->dst_rect.height / src.height
1022 * stream->dst.height / stream->src.height);
1023 if (orthogonal_rotation)
1024 swap(recout_skip_h, recout_skip_v);
1025 /*
1026 * Init calculated according to formula:
1027 * init = (scaling_ratio + number_of_taps + 1) / 2
1028 * init_bot = init + scaling_ratio
1029 * init_c = init + truncated_vp_c_offset(from calculate viewport)
1030 */
1031 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
1032 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
1033
1034 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
1035 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
1036
1037 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
1038 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
1039
1040 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
1041 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
1042
1043 /*
1044 * Taps, inits and scaling ratios are in recout space need to rotate
1045 * to viewport rotation before adjustment
1046 */
1047 adjust_vp_and_init_for_seamless_clip(
1048 flip_horz_scan_dir,
1049 recout_skip_h,
1050 surf_size_h,
1051 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
1052 orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
1053 orthogonal_rotation ? &data->inits.v : &data->inits.h,
1054 &data->viewport.x,
1055 &data->viewport.width);
1056 adjust_vp_and_init_for_seamless_clip(
1057 flip_horz_scan_dir,
1058 recout_skip_h,
1059 surf_size_h / vpc_div,
1060 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
1061 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
1062 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
1063 &data->viewport_c.x,
1064 &data->viewport_c.width);
1065 adjust_vp_and_init_for_seamless_clip(
1066 flip_vert_scan_dir,
1067 recout_skip_v,
1068 surf_size_v,
1069 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
1070 orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
1071 orthogonal_rotation ? &data->inits.h : &data->inits.v,
1072 &data->viewport.y,
1073 &data->viewport.height);
1074 adjust_vp_and_init_for_seamless_clip(
1075 flip_vert_scan_dir,
1076 recout_skip_v,
1077 surf_size_v / vpc_div,
1078 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
1079 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
1080 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
1081 &data->viewport_c.y,
1082 &data->viewport_c.height);
1083
1084 /* Interlaced inits based on final vert inits */
1085 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
1086 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1087
1088 }
1089
1090 /*
1091 * When handling 270 rotation in mixed SLS mode, we have
1092 * stream->timing.h_border_left that is non zero. If we are doing
1093 * pipe-splitting, this h_border_left value gets added to recout.x and when it
1094 * calls calculate_inits_and_adj_vp() and
1095 * adjust_vp_and_init_for_seamless_clip(), it can cause viewport.height for a
1096 * pipe to be incorrect.
1097 *
1098 * To fix this, instead of using stream->timing.h_border_left, we can use
1099 * stream->dst.x to represent the border instead. So we will set h_border_left
1100 * to 0 and shift the appropriate amount in stream->dst.x. We will then
1101 * perform all calculations in resource_build_scaling_params() based on this
1102 * and then restore the h_border_left and stream->dst.x to their original
1103 * values.
1104 *
1105 * shift_border_left_to_dst() will shift the amount of h_border_left to
1106 * stream->dst.x and set h_border_left to 0. restore_border_left_from_dst()
1107 * will restore h_border_left and stream->dst.x back to their original values
1108 * We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the
1109 * original h_border_left value in its calculation.
1110 */
shift_border_left_to_dst(struct pipe_ctx * pipe_ctx)1111 int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
1112 {
1113 int store_h_border_left = pipe_ctx->stream->timing.h_border_left;
1114
1115 if (store_h_border_left) {
1116 pipe_ctx->stream->timing.h_border_left = 0;
1117 pipe_ctx->stream->dst.x += store_h_border_left;
1118 }
1119 return store_h_border_left;
1120 }
1121
restore_border_left_from_dst(struct pipe_ctx * pipe_ctx,int store_h_border_left)1122 void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx,
1123 int store_h_border_left)
1124 {
1125 pipe_ctx->stream->dst.x -= store_h_border_left;
1126 pipe_ctx->stream->timing.h_border_left = store_h_border_left;
1127 }
1128
resource_build_scaling_params(struct pipe_ctx * pipe_ctx)1129 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
1130 {
1131 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1132 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1133 bool res = false;
1134 int store_h_border_left = shift_border_left_to_dst(pipe_ctx);
1135 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1136 /* Important: scaling ratio calculation requires pixel format,
1137 * lb depth calculation requires recout and taps require scaling ratios.
1138 * Inits require viewport, taps, ratios and recout of split pipe
1139 */
1140 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
1141 pipe_ctx->plane_state->format);
1142
1143 calculate_scaling_ratios(pipe_ctx);
1144
1145 calculate_viewport(pipe_ctx);
1146
1147 if (pipe_ctx->plane_res.scl_data.viewport.height < 12 ||
1148 pipe_ctx->plane_res.scl_data.viewport.width < 12) {
1149 if (store_h_border_left) {
1150 restore_border_left_from_dst(pipe_ctx,
1151 store_h_border_left);
1152 }
1153 return false;
1154 }
1155
1156 calculate_recout(pipe_ctx);
1157
1158 /**
1159 * Setting line buffer pixel depth to 24bpp yields banding
1160 * on certain displays, such as the Sharp 4k
1161 */
1162 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1163 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1164
1165 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
1166 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
1167
1168 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
1169 store_h_border_left + timing->h_border_right;
1170 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
1171 timing->v_border_top + timing->v_border_bottom;
1172 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
1173 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1174
1175 /* Taps calculations */
1176 if (pipe_ctx->plane_res.xfm != NULL)
1177 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1178 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1179
1180 if (pipe_ctx->plane_res.dpp != NULL)
1181 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1182 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1183
1184
1185 if (!res) {
1186 /* Try 24 bpp linebuffer */
1187 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
1188
1189 if (pipe_ctx->plane_res.xfm != NULL)
1190 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1191 pipe_ctx->plane_res.xfm,
1192 &pipe_ctx->plane_res.scl_data,
1193 &plane_state->scaling_quality);
1194
1195 if (pipe_ctx->plane_res.dpp != NULL)
1196 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1197 pipe_ctx->plane_res.dpp,
1198 &pipe_ctx->plane_res.scl_data,
1199 &plane_state->scaling_quality);
1200 }
1201
1202 if (res)
1203 /* May need to re-check lb size after this in some obscure scenario */
1204 calculate_inits_and_adj_vp(pipe_ctx);
1205
1206 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
1207 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
1208 __func__,
1209 pipe_ctx->pipe_idx,
1210 pipe_ctx->plane_res.scl_data.viewport.height,
1211 pipe_ctx->plane_res.scl_data.viewport.width,
1212 pipe_ctx->plane_res.scl_data.viewport.x,
1213 pipe_ctx->plane_res.scl_data.viewport.y,
1214 pipe_ctx->plane_res.scl_data.recout.height,
1215 pipe_ctx->plane_res.scl_data.recout.width,
1216 pipe_ctx->plane_res.scl_data.recout.x,
1217 pipe_ctx->plane_res.scl_data.recout.y,
1218 pipe_ctx->plane_res.scl_data.h_active,
1219 pipe_ctx->plane_res.scl_data.v_active,
1220 plane_state->src_rect.height,
1221 plane_state->src_rect.width,
1222 plane_state->src_rect.x,
1223 plane_state->src_rect.y,
1224 plane_state->dst_rect.height,
1225 plane_state->dst_rect.width,
1226 plane_state->dst_rect.x,
1227 plane_state->dst_rect.y,
1228 plane_state->clip_rect.height,
1229 plane_state->clip_rect.width,
1230 plane_state->clip_rect.x,
1231 plane_state->clip_rect.y);
1232
1233 if (store_h_border_left)
1234 restore_border_left_from_dst(pipe_ctx, store_h_border_left);
1235
1236 return res;
1237 }
1238
1239
resource_build_scaling_params_for_context(const struct dc * dc,struct dc_state * context)1240 enum dc_status resource_build_scaling_params_for_context(
1241 const struct dc *dc,
1242 struct dc_state *context)
1243 {
1244 int i;
1245
1246 for (i = 0; i < MAX_PIPES; i++) {
1247 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1248 context->res_ctx.pipe_ctx[i].stream != NULL)
1249 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
1250 return DC_FAIL_SCALING;
1251 }
1252
1253 return DC_OK;
1254 }
1255
find_idle_secondary_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)1256 struct pipe_ctx *find_idle_secondary_pipe(
1257 struct resource_context *res_ctx,
1258 const struct resource_pool *pool,
1259 const struct pipe_ctx *primary_pipe)
1260 {
1261 int i;
1262 struct pipe_ctx *secondary_pipe = NULL;
1263
1264 /*
1265 * We add a preferred pipe mapping to avoid the chance that
1266 * MPCCs already in use will need to be reassigned to other trees.
1267 * For example, if we went with the strict, assign backwards logic:
1268 *
1269 * (State 1)
1270 * Display A on, no surface, top pipe = 0
1271 * Display B on, no surface, top pipe = 1
1272 *
1273 * (State 2)
1274 * Display A on, no surface, top pipe = 0
1275 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1276 *
1277 * (State 3)
1278 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1279 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1280 *
1281 * The state 2->3 transition requires remapping MPCC 5 from display B
1282 * to display A.
1283 *
1284 * However, with the preferred pipe logic, state 2 would look like:
1285 *
1286 * (State 2)
1287 * Display A on, no surface, top pipe = 0
1288 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1289 *
1290 * This would then cause 2->3 to not require remapping any MPCCs.
1291 */
1292 if (primary_pipe) {
1293 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1294 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1295 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1296 secondary_pipe->pipe_idx = preferred_pipe_idx;
1297 }
1298 }
1299
1300 /*
1301 * search backwards for the second pipe to keep pipe
1302 * assignment more consistent
1303 */
1304 if (!secondary_pipe)
1305 for (i = pool->pipe_count - 1; i >= 0; i--) {
1306 if (res_ctx->pipe_ctx[i].stream == NULL) {
1307 secondary_pipe = &res_ctx->pipe_ctx[i];
1308 secondary_pipe->pipe_idx = i;
1309 break;
1310 }
1311 }
1312
1313 return secondary_pipe;
1314 }
1315
resource_get_head_pipe_for_stream(struct resource_context * res_ctx,struct dc_stream_state * stream)1316 struct pipe_ctx *resource_get_head_pipe_for_stream(
1317 struct resource_context *res_ctx,
1318 struct dc_stream_state *stream)
1319 {
1320 int i;
1321
1322 for (i = 0; i < MAX_PIPES; i++) {
1323 if (res_ctx->pipe_ctx[i].stream == stream
1324 && !res_ctx->pipe_ctx[i].top_pipe
1325 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
1326 return &res_ctx->pipe_ctx[i];
1327 }
1328 return NULL;
1329 }
1330
resource_get_tail_pipe(struct resource_context * res_ctx,struct pipe_ctx * head_pipe)1331 static struct pipe_ctx *resource_get_tail_pipe(
1332 struct resource_context *res_ctx,
1333 struct pipe_ctx *head_pipe)
1334 {
1335 struct pipe_ctx *tail_pipe;
1336
1337 tail_pipe = head_pipe->bottom_pipe;
1338
1339 while (tail_pipe) {
1340 head_pipe = tail_pipe;
1341 tail_pipe = tail_pipe->bottom_pipe;
1342 }
1343
1344 return head_pipe;
1345 }
1346
1347 /*
1348 * A free_pipe for a stream is defined here as a pipe
1349 * that has no surface attached yet
1350 */
acquire_free_pipe_for_head(struct dc_state * context,const struct resource_pool * pool,struct pipe_ctx * head_pipe)1351 static struct pipe_ctx *acquire_free_pipe_for_head(
1352 struct dc_state *context,
1353 const struct resource_pool *pool,
1354 struct pipe_ctx *head_pipe)
1355 {
1356 int i;
1357 struct resource_context *res_ctx = &context->res_ctx;
1358
1359 if (!head_pipe->plane_state)
1360 return head_pipe;
1361
1362 /* Re-use pipe already acquired for this stream if available*/
1363 for (i = pool->pipe_count - 1; i >= 0; i--) {
1364 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
1365 !res_ctx->pipe_ctx[i].plane_state) {
1366 return &res_ctx->pipe_ctx[i];
1367 }
1368 }
1369
1370 /*
1371 * At this point we have no re-useable pipe for this stream and we need
1372 * to acquire an idle one to satisfy the request
1373 */
1374
1375 if (!pool->funcs->acquire_idle_pipe_for_layer)
1376 return NULL;
1377
1378 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
1379 }
1380
1381 #if defined(CONFIG_DRM_AMD_DC_DCN)
acquire_first_split_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1382 static int acquire_first_split_pipe(
1383 struct resource_context *res_ctx,
1384 const struct resource_pool *pool,
1385 struct dc_stream_state *stream)
1386 {
1387 int i;
1388
1389 for (i = 0; i < pool->pipe_count; i++) {
1390 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1391
1392 if (split_pipe->top_pipe &&
1393 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1394 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1395 if (split_pipe->bottom_pipe)
1396 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1397
1398 if (split_pipe->top_pipe->plane_state)
1399 resource_build_scaling_params(split_pipe->top_pipe);
1400
1401 memset(split_pipe, 0, sizeof(*split_pipe));
1402 split_pipe->stream_res.tg = pool->timing_generators[i];
1403 split_pipe->plane_res.hubp = pool->hubps[i];
1404 split_pipe->plane_res.ipp = pool->ipps[i];
1405 split_pipe->plane_res.dpp = pool->dpps[i];
1406 split_pipe->stream_res.opp = pool->opps[i];
1407 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1408 split_pipe->pipe_idx = i;
1409
1410 split_pipe->stream = stream;
1411 return i;
1412 }
1413 }
1414 return -1;
1415 }
1416 #endif
1417
dc_add_plane_to_context(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * plane_state,struct dc_state * context)1418 bool dc_add_plane_to_context(
1419 const struct dc *dc,
1420 struct dc_stream_state *stream,
1421 struct dc_plane_state *plane_state,
1422 struct dc_state *context)
1423 {
1424 int i;
1425 struct resource_pool *pool = dc->res_pool;
1426 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
1427 struct dc_stream_status *stream_status = NULL;
1428
1429 for (i = 0; i < context->stream_count; i++)
1430 if (context->streams[i] == stream) {
1431 stream_status = &context->stream_status[i];
1432 break;
1433 }
1434 if (stream_status == NULL) {
1435 dm_error("Existing stream not found; failed to attach surface!\n");
1436 return false;
1437 }
1438
1439
1440 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1441 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1442 plane_state, MAX_SURFACE_NUM);
1443 return false;
1444 }
1445
1446 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1447
1448 if (!head_pipe) {
1449 dm_error("Head pipe not found for stream_state %p !\n", stream);
1450 return false;
1451 }
1452
1453 /* retain new surface, but only once per stream */
1454 dc_plane_state_retain(plane_state);
1455
1456 while (head_pipe) {
1457 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
1458
1459 #if defined(CONFIG_DRM_AMD_DC_DCN)
1460 if (!free_pipe) {
1461 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1462 if (pipe_idx >= 0)
1463 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1464 }
1465 #endif
1466 if (!free_pipe) {
1467 dc_plane_state_release(plane_state);
1468 return false;
1469 }
1470
1471 free_pipe->plane_state = plane_state;
1472
1473 if (head_pipe != free_pipe) {
1474 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1475 ASSERT(tail_pipe);
1476 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1477 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1478 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1479 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1480 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1481 free_pipe->clock_source = tail_pipe->clock_source;
1482 free_pipe->top_pipe = tail_pipe;
1483 tail_pipe->bottom_pipe = free_pipe;
1484 }
1485 head_pipe = head_pipe->next_odm_pipe;
1486 }
1487 /* assign new surfaces*/
1488 stream_status->plane_states[stream_status->plane_count] = plane_state;
1489
1490 stream_status->plane_count++;
1491
1492 return true;
1493 }
1494
dc_remove_plane_from_context(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * plane_state,struct dc_state * context)1495 bool dc_remove_plane_from_context(
1496 const struct dc *dc,
1497 struct dc_stream_state *stream,
1498 struct dc_plane_state *plane_state,
1499 struct dc_state *context)
1500 {
1501 int i;
1502 struct dc_stream_status *stream_status = NULL;
1503 struct resource_pool *pool = dc->res_pool;
1504
1505 for (i = 0; i < context->stream_count; i++)
1506 if (context->streams[i] == stream) {
1507 stream_status = &context->stream_status[i];
1508 break;
1509 }
1510
1511 if (stream_status == NULL) {
1512 dm_error("Existing stream not found; failed to remove plane.\n");
1513 return false;
1514 }
1515
1516 /* release pipe for plane*/
1517 for (i = pool->pipe_count - 1; i >= 0; i--) {
1518 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1519
1520 if (pipe_ctx->plane_state == plane_state) {
1521 if (pipe_ctx->top_pipe)
1522 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1523
1524 /* Second condition is to avoid setting NULL to top pipe
1525 * of tail pipe making it look like head pipe in subsequent
1526 * deletes
1527 */
1528 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1529 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1530
1531 /*
1532 * For head pipe detach surfaces from pipe for tail
1533 * pipe just zero it out
1534 */
1535 if (!pipe_ctx->top_pipe)
1536 pipe_ctx->plane_state = NULL;
1537 else
1538 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1539 }
1540 }
1541
1542
1543 for (i = 0; i < stream_status->plane_count; i++) {
1544 if (stream_status->plane_states[i] == plane_state) {
1545
1546 dc_plane_state_release(stream_status->plane_states[i]);
1547 break;
1548 }
1549 }
1550
1551 if (i == stream_status->plane_count) {
1552 dm_error("Existing plane_state not found; failed to detach it!\n");
1553 return false;
1554 }
1555
1556 stream_status->plane_count--;
1557
1558 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1559 for (; i < stream_status->plane_count; i++)
1560 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1561
1562 stream_status->plane_states[stream_status->plane_count] = NULL;
1563
1564 return true;
1565 }
1566
dc_rem_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_state * context)1567 bool dc_rem_all_planes_for_stream(
1568 const struct dc *dc,
1569 struct dc_stream_state *stream,
1570 struct dc_state *context)
1571 {
1572 int i, old_plane_count;
1573 struct dc_stream_status *stream_status = NULL;
1574 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1575
1576 for (i = 0; i < context->stream_count; i++)
1577 if (context->streams[i] == stream) {
1578 stream_status = &context->stream_status[i];
1579 break;
1580 }
1581
1582 if (stream_status == NULL) {
1583 dm_error("Existing stream %p not found!\n", stream);
1584 return false;
1585 }
1586
1587 old_plane_count = stream_status->plane_count;
1588
1589 for (i = 0; i < old_plane_count; i++)
1590 del_planes[i] = stream_status->plane_states[i];
1591
1592 for (i = 0; i < old_plane_count; i++)
1593 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1594 return false;
1595
1596 return true;
1597 }
1598
add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count,struct dc_state * context)1599 static bool add_all_planes_for_stream(
1600 const struct dc *dc,
1601 struct dc_stream_state *stream,
1602 const struct dc_validation_set set[],
1603 int set_count,
1604 struct dc_state *context)
1605 {
1606 int i, j;
1607
1608 for (i = 0; i < set_count; i++)
1609 if (set[i].stream == stream)
1610 break;
1611
1612 if (i == set_count) {
1613 dm_error("Stream %p not found in set!\n", stream);
1614 return false;
1615 }
1616
1617 for (j = 0; j < set[i].plane_count; j++)
1618 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1619 return false;
1620
1621 return true;
1622 }
1623
dc_add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * const * plane_states,int plane_count,struct dc_state * context)1624 bool dc_add_all_planes_for_stream(
1625 const struct dc *dc,
1626 struct dc_stream_state *stream,
1627 struct dc_plane_state * const *plane_states,
1628 int plane_count,
1629 struct dc_state *context)
1630 {
1631 struct dc_validation_set set;
1632 int i;
1633
1634 set.stream = stream;
1635 set.plane_count = plane_count;
1636
1637 for (i = 0; i < plane_count; i++)
1638 set.plane_states[i] = plane_states[i];
1639
1640 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1641 }
1642
is_timing_changed(struct dc_stream_state * cur_stream,struct dc_stream_state * new_stream)1643 static bool is_timing_changed(struct dc_stream_state *cur_stream,
1644 struct dc_stream_state *new_stream)
1645 {
1646 if (cur_stream == NULL)
1647 return true;
1648
1649 /* If sink pointer changed, it means this is a hotplug, we should do
1650 * full hw setting.
1651 */
1652 if (cur_stream->sink != new_stream->sink)
1653 return true;
1654
1655 /* If output color space is changed, need to reprogram info frames */
1656 if (cur_stream->output_color_space != new_stream->output_color_space)
1657 return true;
1658
1659 return memcmp(
1660 &cur_stream->timing,
1661 &new_stream->timing,
1662 sizeof(struct dc_crtc_timing)) != 0;
1663 }
1664
are_stream_backends_same(struct dc_stream_state * stream_a,struct dc_stream_state * stream_b)1665 static bool are_stream_backends_same(
1666 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
1667 {
1668 if (stream_a == stream_b)
1669 return true;
1670
1671 if (stream_a == NULL || stream_b == NULL)
1672 return false;
1673
1674 if (is_timing_changed(stream_a, stream_b))
1675 return false;
1676
1677 if (stream_a->dpms_off != stream_b->dpms_off)
1678 return false;
1679
1680 return true;
1681 }
1682
1683 /**
1684 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1685 *
1686 * Checks if there a difference between the two states
1687 * that would require a mode change.
1688 *
1689 * Does not compare cursor position or attributes.
1690 */
dc_is_stream_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream)1691 bool dc_is_stream_unchanged(
1692 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1693 {
1694
1695 if (!are_stream_backends_same(old_stream, stream))
1696 return false;
1697
1698 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1699 return false;
1700
1701 // Only Have Audio left to check whether it is same or not. This is a corner case for Tiled sinks
1702 if (old_stream->audio_info.mode_count != stream->audio_info.mode_count)
1703 return false;
1704
1705 return true;
1706 }
1707
1708 /**
1709 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1710 */
dc_is_stream_scaling_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream)1711 bool dc_is_stream_scaling_unchanged(
1712 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1713 {
1714 if (old_stream == stream)
1715 return true;
1716
1717 if (old_stream == NULL || stream == NULL)
1718 return false;
1719
1720 if (memcmp(&old_stream->src,
1721 &stream->src,
1722 sizeof(struct rect)) != 0)
1723 return false;
1724
1725 if (memcmp(&old_stream->dst,
1726 &stream->dst,
1727 sizeof(struct rect)) != 0)
1728 return false;
1729
1730 return true;
1731 }
1732
update_stream_engine_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct stream_encoder * stream_enc,bool acquired)1733 static void update_stream_engine_usage(
1734 struct resource_context *res_ctx,
1735 const struct resource_pool *pool,
1736 struct stream_encoder *stream_enc,
1737 bool acquired)
1738 {
1739 int i;
1740
1741 for (i = 0; i < pool->stream_enc_count; i++) {
1742 if (pool->stream_enc[i] == stream_enc)
1743 res_ctx->is_stream_enc_acquired[i] = acquired;
1744 }
1745 }
1746
1747 /* TODO: release audio object */
update_audio_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct audio * audio,bool acquired)1748 void update_audio_usage(
1749 struct resource_context *res_ctx,
1750 const struct resource_pool *pool,
1751 struct audio *audio,
1752 bool acquired)
1753 {
1754 int i;
1755 for (i = 0; i < pool->audio_count; i++) {
1756 if (pool->audios[i] == audio)
1757 res_ctx->is_audio_acquired[i] = acquired;
1758 }
1759 }
1760
acquire_first_free_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1761 static int acquire_first_free_pipe(
1762 struct resource_context *res_ctx,
1763 const struct resource_pool *pool,
1764 struct dc_stream_state *stream)
1765 {
1766 int i;
1767
1768 for (i = 0; i < pool->pipe_count; i++) {
1769 if (!res_ctx->pipe_ctx[i].stream) {
1770 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1771
1772 pipe_ctx->stream_res.tg = pool->timing_generators[i];
1773 pipe_ctx->plane_res.mi = pool->mis[i];
1774 pipe_ctx->plane_res.hubp = pool->hubps[i];
1775 pipe_ctx->plane_res.ipp = pool->ipps[i];
1776 pipe_ctx->plane_res.xfm = pool->transforms[i];
1777 pipe_ctx->plane_res.dpp = pool->dpps[i];
1778 pipe_ctx->stream_res.opp = pool->opps[i];
1779 if (pool->dpps[i])
1780 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
1781 pipe_ctx->pipe_idx = i;
1782
1783
1784 pipe_ctx->stream = stream;
1785 return i;
1786 }
1787 }
1788 return -1;
1789 }
1790
find_first_free_audio(struct resource_context * res_ctx,const struct resource_pool * pool,enum engine_id id,enum dce_version dc_version)1791 static struct audio *find_first_free_audio(
1792 struct resource_context *res_ctx,
1793 const struct resource_pool *pool,
1794 enum engine_id id,
1795 enum dce_version dc_version)
1796 {
1797 int i, available_audio_count;
1798
1799 available_audio_count = pool->audio_count;
1800
1801 for (i = 0; i < available_audio_count; i++) {
1802 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
1803 /*we have enough audio endpoint, find the matching inst*/
1804 if (id != i)
1805 continue;
1806 return pool->audios[i];
1807 }
1808 }
1809
1810 /* use engine id to find free audio */
1811 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
1812 return pool->audios[id];
1813 }
1814 /*not found the matching one, first come first serve*/
1815 for (i = 0; i < available_audio_count; i++) {
1816 if (res_ctx->is_audio_acquired[i] == false) {
1817 return pool->audios[i];
1818 }
1819 }
1820 return 0;
1821 }
1822
1823 /**
1824 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1825 */
dc_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * stream)1826 enum dc_status dc_add_stream_to_ctx(
1827 struct dc *dc,
1828 struct dc_state *new_ctx,
1829 struct dc_stream_state *stream)
1830 {
1831 enum dc_status res;
1832 DC_LOGGER_INIT(dc->ctx->logger);
1833
1834 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
1835 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1836 return DC_ERROR_UNEXPECTED;
1837 }
1838
1839 new_ctx->streams[new_ctx->stream_count] = stream;
1840 dc_stream_retain(stream);
1841 new_ctx->stream_count++;
1842
1843 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1844 if (res != DC_OK)
1845 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1846
1847 return res;
1848 }
1849
1850 /**
1851 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1852 */
dc_remove_stream_from_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * stream)1853 enum dc_status dc_remove_stream_from_ctx(
1854 struct dc *dc,
1855 struct dc_state *new_ctx,
1856 struct dc_stream_state *stream)
1857 {
1858 int i;
1859 struct dc_context *dc_ctx = dc->ctx;
1860 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1861 struct pipe_ctx *odm_pipe;
1862
1863 if (!del_pipe) {
1864 DC_ERROR("Pipe not found for stream %p !\n", stream);
1865 return DC_ERROR_UNEXPECTED;
1866 }
1867
1868 odm_pipe = del_pipe->next_odm_pipe;
1869
1870 /* Release primary pipe */
1871 ASSERT(del_pipe->stream_res.stream_enc);
1872 update_stream_engine_usage(
1873 &new_ctx->res_ctx,
1874 dc->res_pool,
1875 del_pipe->stream_res.stream_enc,
1876 false);
1877
1878 if (del_pipe->stream_res.audio)
1879 update_audio_usage(
1880 &new_ctx->res_ctx,
1881 dc->res_pool,
1882 del_pipe->stream_res.audio,
1883 false);
1884
1885 resource_unreference_clock_source(&new_ctx->res_ctx,
1886 dc->res_pool,
1887 del_pipe->clock_source);
1888
1889 if (dc->res_pool->funcs->remove_stream_from_ctx)
1890 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1891
1892 while (odm_pipe) {
1893 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1894
1895 memset(odm_pipe, 0, sizeof(*odm_pipe));
1896 odm_pipe = next_odm_pipe;
1897 }
1898 memset(del_pipe, 0, sizeof(*del_pipe));
1899
1900 for (i = 0; i < new_ctx->stream_count; i++)
1901 if (new_ctx->streams[i] == stream)
1902 break;
1903
1904 if (new_ctx->streams[i] != stream) {
1905 DC_ERROR("Context doesn't have stream %p !\n", stream);
1906 return DC_ERROR_UNEXPECTED;
1907 }
1908
1909 dc_stream_release(new_ctx->streams[i]);
1910 new_ctx->stream_count--;
1911
1912 /* Trim back arrays */
1913 for (; i < new_ctx->stream_count; i++) {
1914 new_ctx->streams[i] = new_ctx->streams[i + 1];
1915 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1916 }
1917
1918 new_ctx->streams[new_ctx->stream_count] = NULL;
1919 memset(
1920 &new_ctx->stream_status[new_ctx->stream_count],
1921 0,
1922 sizeof(new_ctx->stream_status[0]));
1923
1924 return DC_OK;
1925 }
1926
find_pll_sharable_stream(struct dc_stream_state * stream_needs_pll,struct dc_state * context)1927 static struct dc_stream_state *find_pll_sharable_stream(
1928 struct dc_stream_state *stream_needs_pll,
1929 struct dc_state *context)
1930 {
1931 int i;
1932
1933 for (i = 0; i < context->stream_count; i++) {
1934 struct dc_stream_state *stream_has_pll = context->streams[i];
1935
1936 /* We are looking for non dp, non virtual stream */
1937 if (resource_are_streams_timing_synchronizable(
1938 stream_needs_pll, stream_has_pll)
1939 && !dc_is_dp_signal(stream_has_pll->signal)
1940 && stream_has_pll->link->connector_signal
1941 != SIGNAL_TYPE_VIRTUAL)
1942 return stream_has_pll;
1943
1944 }
1945
1946 return NULL;
1947 }
1948
get_norm_pix_clk(const struct dc_crtc_timing * timing)1949 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1950 {
1951 uint32_t pix_clk = timing->pix_clk_100hz;
1952 uint32_t normalized_pix_clk = pix_clk;
1953
1954 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1955 pix_clk /= 2;
1956 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1957 switch (timing->display_color_depth) {
1958 case COLOR_DEPTH_666:
1959 case COLOR_DEPTH_888:
1960 normalized_pix_clk = pix_clk;
1961 break;
1962 case COLOR_DEPTH_101010:
1963 normalized_pix_clk = (pix_clk * 30) / 24;
1964 break;
1965 case COLOR_DEPTH_121212:
1966 normalized_pix_clk = (pix_clk * 36) / 24;
1967 break;
1968 case COLOR_DEPTH_161616:
1969 normalized_pix_clk = (pix_clk * 48) / 24;
1970 break;
1971 default:
1972 ASSERT(0);
1973 break;
1974 }
1975 }
1976 return normalized_pix_clk;
1977 }
1978
calculate_phy_pix_clks(struct dc_stream_state * stream)1979 static void calculate_phy_pix_clks(struct dc_stream_state *stream)
1980 {
1981 /* update actual pixel clock on all streams */
1982 if (dc_is_hdmi_signal(stream->signal))
1983 stream->phy_pix_clk = get_norm_pix_clk(
1984 &stream->timing) / 10;
1985 else
1986 stream->phy_pix_clk =
1987 stream->timing.pix_clk_100hz / 10;
1988
1989 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1990 stream->phy_pix_clk *= 2;
1991 }
1992
acquire_resource_from_hw_enabled_state(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1993 static int acquire_resource_from_hw_enabled_state(
1994 struct resource_context *res_ctx,
1995 const struct resource_pool *pool,
1996 struct dc_stream_state *stream)
1997 {
1998 struct dc_link *link = stream->link;
1999 unsigned int i, inst, tg_inst = 0;
2000
2001 /* Check for enabled DIG to identify enabled display */
2002 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
2003 return -1;
2004
2005 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2006
2007 if (inst == ENGINE_ID_UNKNOWN)
2008 return -1;
2009
2010 for (i = 0; i < pool->stream_enc_count; i++) {
2011 if (pool->stream_enc[i]->id == inst) {
2012 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
2013 pool->stream_enc[i]);
2014 break;
2015 }
2016 }
2017
2018 // tg_inst not found
2019 if (i == pool->stream_enc_count)
2020 return -1;
2021
2022 if (tg_inst >= pool->timing_generator_count)
2023 return -1;
2024
2025 if (!res_ctx->pipe_ctx[tg_inst].stream) {
2026 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
2027
2028 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2029 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
2030 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
2031 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
2032 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
2033 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
2034 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
2035
2036 if (pool->dpps[tg_inst]) {
2037 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
2038
2039 // Read DPP->MPCC->OPP Pipe from HW State
2040 if (pool->mpc->funcs->read_mpcc_state) {
2041 struct mpcc_state s = {0};
2042
2043 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
2044
2045 if (s.dpp_id < MAX_MPCC)
2046 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
2047
2048 if (s.bot_mpcc_id < MAX_MPCC)
2049 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
2050 &pool->mpc->mpcc_array[s.bot_mpcc_id];
2051
2052 if (s.opp_id < MAX_OPP)
2053 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
2054 }
2055 }
2056 pipe_ctx->pipe_idx = tg_inst;
2057
2058 pipe_ctx->stream = stream;
2059 return tg_inst;
2060 }
2061
2062 return -1;
2063 }
2064
resource_map_pool_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)2065 enum dc_status resource_map_pool_resources(
2066 const struct dc *dc,
2067 struct dc_state *context,
2068 struct dc_stream_state *stream)
2069 {
2070 const struct resource_pool *pool = dc->res_pool;
2071 int i;
2072 struct dc_context *dc_ctx = dc->ctx;
2073 struct pipe_ctx *pipe_ctx = NULL;
2074 int pipe_idx = -1;
2075 struct dc_bios *dcb = dc->ctx->dc_bios;
2076
2077 calculate_phy_pix_clks(stream);
2078
2079 /* TODO: Check Linux */
2080 if (dc->config.allow_seamless_boot_optimization &&
2081 !dcb->funcs->is_accelerated_mode(dcb)) {
2082 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
2083 stream->apply_seamless_boot_optimization = true;
2084 }
2085
2086 if (stream->apply_seamless_boot_optimization)
2087 pipe_idx = acquire_resource_from_hw_enabled_state(
2088 &context->res_ctx,
2089 pool,
2090 stream);
2091
2092 if (pipe_idx < 0)
2093 /* acquire new resources */
2094 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
2095
2096 #ifdef CONFIG_DRM_AMD_DC_DCN
2097 if (pipe_idx < 0)
2098 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
2099 #endif
2100
2101 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
2102 return DC_NO_CONTROLLER_RESOURCE;
2103
2104 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2105
2106 pipe_ctx->stream_res.stream_enc =
2107 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
2108 &context->res_ctx, pool, stream);
2109
2110 if (!pipe_ctx->stream_res.stream_enc)
2111 return DC_NO_STREAM_ENC_RESOURCE;
2112
2113 update_stream_engine_usage(
2114 &context->res_ctx, pool,
2115 pipe_ctx->stream_res.stream_enc,
2116 true);
2117
2118 /* TODO: Add check if ASIC support and EDID audio */
2119 if (!stream->converter_disable_audio &&
2120 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
2121 stream->audio_info.mode_count && stream->audio_info.flags.all) {
2122 pipe_ctx->stream_res.audio = find_first_free_audio(
2123 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
2124
2125 /*
2126 * Audio assigned in order first come first get.
2127 * There are asics which has number of audio
2128 * resources less then number of pipes
2129 */
2130 if (pipe_ctx->stream_res.audio)
2131 update_audio_usage(&context->res_ctx, pool,
2132 pipe_ctx->stream_res.audio, true);
2133 }
2134
2135 /* Add ABM to the resource if on EDP */
2136 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
2137 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2138 if (pool->abm)
2139 pipe_ctx->stream_res.abm = pool->abm;
2140 else
2141 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
2142 #else
2143 pipe_ctx->stream_res.abm = pool->abm;
2144 #endif
2145 }
2146
2147 for (i = 0; i < context->stream_count; i++)
2148 if (context->streams[i] == stream) {
2149 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
2150 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
2151 context->stream_status[i].audio_inst =
2152 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2153
2154 return DC_OK;
2155 }
2156
2157 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2158 return DC_ERROR_UNEXPECTED;
2159 }
2160
2161 /**
2162 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2163 * Is a shallow copy. Increments refcounts on existing streams and planes.
2164 * @dc: copy out of dc->current_state
2165 * @dst_ctx: copy into this
2166 */
dc_resource_state_copy_construct_current(const struct dc * dc,struct dc_state * dst_ctx)2167 void dc_resource_state_copy_construct_current(
2168 const struct dc *dc,
2169 struct dc_state *dst_ctx)
2170 {
2171 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
2172 }
2173
2174
dc_resource_state_construct(const struct dc * dc,struct dc_state * dst_ctx)2175 void dc_resource_state_construct(
2176 const struct dc *dc,
2177 struct dc_state *dst_ctx)
2178 {
2179 dst_ctx->clk_mgr = dc->clk_mgr;
2180 }
2181
2182
dc_resource_is_dsc_encoding_supported(const struct dc * dc)2183 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2184 {
2185 return dc->res_pool->res_cap->num_dsc > 0;
2186 }
2187
2188
2189 /**
2190 * dc_validate_global_state() - Determine if HW can support a given state
2191 * Checks HW resource availability and bandwidth requirement.
2192 * @dc: dc struct for this driver
2193 * @new_ctx: state to be validated
2194 * @fast_validate: set to true if only yes/no to support matters
2195 *
2196 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2197 */
dc_validate_global_state(struct dc * dc,struct dc_state * new_ctx,bool fast_validate)2198 enum dc_status dc_validate_global_state(
2199 struct dc *dc,
2200 struct dc_state *new_ctx,
2201 bool fast_validate)
2202 {
2203 enum dc_status result = DC_ERROR_UNEXPECTED;
2204 int i, j;
2205
2206 if (!new_ctx)
2207 return DC_ERROR_UNEXPECTED;
2208
2209 if (dc->res_pool->funcs->validate_global) {
2210 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2211 if (result != DC_OK)
2212 return result;
2213 }
2214
2215 for (i = 0; i < new_ctx->stream_count; i++) {
2216 struct dc_stream_state *stream = new_ctx->streams[i];
2217
2218 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2219 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2220
2221 if (pipe_ctx->stream != stream)
2222 continue;
2223
2224 if (dc->res_pool->funcs->patch_unknown_plane_state &&
2225 pipe_ctx->plane_state &&
2226 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2227 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
2228 if (result != DC_OK)
2229 return result;
2230 }
2231
2232 /* Switch to dp clock source only if there is
2233 * no non dp stream that shares the same timing
2234 * with the dp stream.
2235 */
2236 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2237 !find_pll_sharable_stream(stream, new_ctx)) {
2238
2239 resource_unreference_clock_source(
2240 &new_ctx->res_ctx,
2241 dc->res_pool,
2242 pipe_ctx->clock_source);
2243
2244 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2245 resource_reference_clock_source(
2246 &new_ctx->res_ctx,
2247 dc->res_pool,
2248 pipe_ctx->clock_source);
2249 }
2250 }
2251 }
2252
2253 result = resource_build_scaling_params_for_context(dc, new_ctx);
2254
2255 if (result == DC_OK)
2256 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
2257 result = DC_FAIL_BANDWIDTH_VALIDATE;
2258
2259 return result;
2260 }
2261
patch_gamut_packet_checksum(struct dc_info_packet * gamut_packet)2262 static void patch_gamut_packet_checksum(
2263 struct dc_info_packet *gamut_packet)
2264 {
2265 /* For gamut we recalc checksum */
2266 if (gamut_packet->valid) {
2267 uint8_t chk_sum = 0;
2268 uint8_t *ptr;
2269 uint8_t i;
2270
2271 /*start of the Gamut data. */
2272 ptr = &gamut_packet->sb[3];
2273
2274 for (i = 0; i <= gamut_packet->sb[1]; i++)
2275 chk_sum += ptr[i];
2276
2277 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
2278 }
2279 }
2280
set_avi_info_frame(struct dc_info_packet * info_packet,struct pipe_ctx * pipe_ctx)2281 static void set_avi_info_frame(
2282 struct dc_info_packet *info_packet,
2283 struct pipe_ctx *pipe_ctx)
2284 {
2285 struct dc_stream_state *stream = pipe_ctx->stream;
2286 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
2287 uint32_t pixel_encoding = 0;
2288 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2289 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2290 bool itc = false;
2291 uint8_t itc_value = 0;
2292 uint8_t cn0_cn1 = 0;
2293 unsigned int cn0_cn1_value = 0;
2294 uint8_t *check_sum = NULL;
2295 uint8_t byte_index = 0;
2296 union hdmi_info_packet hdmi_info;
2297 union display_content_support support = {0};
2298 unsigned int vic = pipe_ctx->stream->timing.vic;
2299 enum dc_timing_3d_format format;
2300
2301 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2302
2303 color_space = pipe_ctx->stream->output_color_space;
2304 if (color_space == COLOR_SPACE_UNKNOWN)
2305 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
2306 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
2307
2308 /* Initialize header */
2309 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
2310 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2311 * not be used in HDMI 2.0 (Section 10.1) */
2312 hdmi_info.bits.header.version = 2;
2313 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
2314
2315 /*
2316 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2317 * according to HDMI 2.0 spec (Section 10.1)
2318 */
2319
2320 switch (stream->timing.pixel_encoding) {
2321 case PIXEL_ENCODING_YCBCR422:
2322 pixel_encoding = 1;
2323 break;
2324
2325 case PIXEL_ENCODING_YCBCR444:
2326 pixel_encoding = 2;
2327 break;
2328 case PIXEL_ENCODING_YCBCR420:
2329 pixel_encoding = 3;
2330 break;
2331
2332 case PIXEL_ENCODING_RGB:
2333 default:
2334 pixel_encoding = 0;
2335 }
2336
2337 /* Y0_Y1_Y2 : The pixel encoding */
2338 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
2339 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
2340
2341 /* A0 = 1 Active Format Information valid */
2342 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
2343
2344 /* B0, B1 = 3; Bar info data is valid */
2345 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
2346
2347 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
2348
2349 /* S0, S1 : Underscan / Overscan */
2350 /* TODO: un-hardcode scan type */
2351 scan_type = SCANNING_TYPE_UNDERSCAN;
2352 hdmi_info.bits.S0_S1 = scan_type;
2353
2354 /* C0, C1 : Colorimetry */
2355 if (color_space == COLOR_SPACE_YCBCR709 ||
2356 color_space == COLOR_SPACE_YCBCR709_LIMITED)
2357 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
2358 else if (color_space == COLOR_SPACE_YCBCR601 ||
2359 color_space == COLOR_SPACE_YCBCR601_LIMITED)
2360 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
2361 else {
2362 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
2363 }
2364 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
2365 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2366 color_space == COLOR_SPACE_2020_YCBCR) {
2367 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2368 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
2369 } else if (color_space == COLOR_SPACE_ADOBERGB) {
2370 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2371 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
2372 }
2373
2374 /* TODO: un-hardcode aspect ratio */
2375 aspect = stream->timing.aspect_ratio;
2376
2377 switch (aspect) {
2378 case ASPECT_RATIO_4_3:
2379 case ASPECT_RATIO_16_9:
2380 hdmi_info.bits.M0_M1 = aspect;
2381 break;
2382
2383 case ASPECT_RATIO_NO_DATA:
2384 case ASPECT_RATIO_64_27:
2385 case ASPECT_RATIO_256_135:
2386 default:
2387 hdmi_info.bits.M0_M1 = 0;
2388 }
2389
2390 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
2391 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
2392
2393 /* TODO: un-hardcode cn0_cn1 and itc */
2394
2395 cn0_cn1 = 0;
2396 cn0_cn1_value = 0;
2397
2398 itc = true;
2399 itc_value = 1;
2400
2401 support = stream->content_support;
2402
2403 if (itc) {
2404 if (!support.bits.valid_content_type) {
2405 cn0_cn1_value = 0;
2406 } else {
2407 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2408 if (support.bits.graphics_content == 1) {
2409 cn0_cn1_value = 0;
2410 }
2411 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2412 if (support.bits.photo_content == 1) {
2413 cn0_cn1_value = 1;
2414 } else {
2415 cn0_cn1_value = 0;
2416 itc_value = 0;
2417 }
2418 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2419 if (support.bits.cinema_content == 1) {
2420 cn0_cn1_value = 2;
2421 } else {
2422 cn0_cn1_value = 0;
2423 itc_value = 0;
2424 }
2425 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2426 if (support.bits.game_content == 1) {
2427 cn0_cn1_value = 3;
2428 } else {
2429 cn0_cn1_value = 0;
2430 itc_value = 0;
2431 }
2432 }
2433 }
2434 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2435 hdmi_info.bits.ITC = itc_value;
2436 }
2437
2438 /* TODO : We should handle YCC quantization */
2439 /* but we do not have matrix calculation */
2440 if (stream->qs_bit == 1 &&
2441 stream->qy_bit == 1) {
2442 if (color_space == COLOR_SPACE_SRGB ||
2443 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
2444 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2445 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2446 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2447 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
2448 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2449 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2450 } else {
2451 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2452 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2453 }
2454 } else {
2455 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2456 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2457 }
2458
2459 ///VIC
2460 format = stream->timing.timing_3d_format;
2461 /*todo, add 3DStereo support*/
2462 if (format != TIMING_3D_FORMAT_NONE) {
2463 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
2464 switch (pipe_ctx->stream->timing.hdmi_vic) {
2465 case 1:
2466 vic = 95;
2467 break;
2468 case 2:
2469 vic = 94;
2470 break;
2471 case 3:
2472 vic = 93;
2473 break;
2474 case 4:
2475 vic = 98;
2476 break;
2477 default:
2478 break;
2479 }
2480 }
2481 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
2482 hdmi_info.bits.VIC0_VIC7 = vic;
2483 if (vic >= 128)
2484 hdmi_info.bits.header.version = 3;
2485 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2486 * the Source shall use 20 AVI InfoFrame Version 4
2487 */
2488 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2489 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2490 hdmi_info.bits.header.version = 4;
2491 hdmi_info.bits.header.length = 14;
2492 }
2493
2494 /* pixel repetition
2495 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2496 * repetition start from 1 */
2497 hdmi_info.bits.PR0_PR3 = 0;
2498
2499 /* Bar Info
2500 * barTop: Line Number of End of Top Bar.
2501 * barBottom: Line Number of Start of Bottom Bar.
2502 * barLeft: Pixel Number of End of Left Bar.
2503 * barRight: Pixel Number of Start of Right Bar. */
2504 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2505 hdmi_info.bits.bar_bottom = (stream->timing.v_total
2506 - stream->timing.v_border_bottom + 1);
2507 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2508 hdmi_info.bits.bar_right = (stream->timing.h_total
2509 - stream->timing.h_border_right + 1);
2510
2511 /* Additional Colorimetry Extension
2512 * Used in conduction with C0-C1 and EC0-EC2
2513 * 0 = DCI-P3 RGB (D65)
2514 * 1 = DCI-P3 RGB (theater)
2515 */
2516 hdmi_info.bits.ACE0_ACE3 = 0;
2517
2518 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
2519 check_sum = &hdmi_info.packet_raw_data.sb[0];
2520
2521 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
2522
2523 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
2524 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
2525
2526 /* one byte complement */
2527 *check_sum = (uint8_t) (0x100 - *check_sum);
2528
2529 /* Store in hw_path_mode */
2530 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2531 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2532 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
2533
2534 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2535 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
2536
2537 info_packet->valid = true;
2538 }
2539
set_vendor_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)2540 static void set_vendor_info_packet(
2541 struct dc_info_packet *info_packet,
2542 struct dc_stream_state *stream)
2543 {
2544 /* SPD info packet for FreeSync */
2545
2546 /* Check if Freesync is supported. Return if false. If true,
2547 * set the corresponding bit in the info packet
2548 */
2549 if (!stream->vsp_infopacket.valid)
2550 return;
2551
2552 *info_packet = stream->vsp_infopacket;
2553 }
2554
set_spd_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)2555 static void set_spd_info_packet(
2556 struct dc_info_packet *info_packet,
2557 struct dc_stream_state *stream)
2558 {
2559 /* SPD info packet for FreeSync */
2560
2561 /* Check if Freesync is supported. Return if false. If true,
2562 * set the corresponding bit in the info packet
2563 */
2564 if (!stream->vrr_infopacket.valid)
2565 return;
2566
2567 *info_packet = stream->vrr_infopacket;
2568 }
2569
set_hdr_static_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)2570 static void set_hdr_static_info_packet(
2571 struct dc_info_packet *info_packet,
2572 struct dc_stream_state *stream)
2573 {
2574 /* HDR Static Metadata info packet for HDR10 */
2575
2576 if (!stream->hdr_static_metadata.valid ||
2577 stream->use_dynamic_meta)
2578 return;
2579
2580 *info_packet = stream->hdr_static_metadata;
2581 }
2582
set_vsc_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)2583 static void set_vsc_info_packet(
2584 struct dc_info_packet *info_packet,
2585 struct dc_stream_state *stream)
2586 {
2587 if (!stream->vsc_infopacket.valid)
2588 return;
2589
2590 *info_packet = stream->vsc_infopacket;
2591 }
2592
dc_resource_state_destruct(struct dc_state * context)2593 void dc_resource_state_destruct(struct dc_state *context)
2594 {
2595 int i, j;
2596
2597 for (i = 0; i < context->stream_count; i++) {
2598 for (j = 0; j < context->stream_status[i].plane_count; j++)
2599 dc_plane_state_release(
2600 context->stream_status[i].plane_states[j]);
2601
2602 context->stream_status[i].plane_count = 0;
2603 dc_stream_release(context->streams[i]);
2604 context->streams[i] = NULL;
2605 }
2606 }
2607
dc_resource_state_copy_construct(const struct dc_state * src_ctx,struct dc_state * dst_ctx)2608 void dc_resource_state_copy_construct(
2609 const struct dc_state *src_ctx,
2610 struct dc_state *dst_ctx)
2611 {
2612 int i, j;
2613 struct kref refcount = dst_ctx->refcount;
2614
2615 *dst_ctx = *src_ctx;
2616
2617 for (i = 0; i < MAX_PIPES; i++) {
2618 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2619
2620 if (cur_pipe->top_pipe)
2621 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2622
2623 if (cur_pipe->bottom_pipe)
2624 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2625
2626 if (cur_pipe->next_odm_pipe)
2627 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2628
2629 if (cur_pipe->prev_odm_pipe)
2630 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
2631 }
2632
2633 for (i = 0; i < dst_ctx->stream_count; i++) {
2634 dc_stream_retain(dst_ctx->streams[i]);
2635 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2636 dc_plane_state_retain(
2637 dst_ctx->stream_status[i].plane_states[j]);
2638 }
2639
2640 /* context refcount should not be overridden */
2641 dst_ctx->refcount = refcount;
2642
2643 }
2644
dc_resource_find_first_free_pll(struct resource_context * res_ctx,const struct resource_pool * pool)2645 struct clock_source *dc_resource_find_first_free_pll(
2646 struct resource_context *res_ctx,
2647 const struct resource_pool *pool)
2648 {
2649 int i;
2650
2651 for (i = 0; i < pool->clk_src_count; ++i) {
2652 if (res_ctx->clock_source_ref_count[i] == 0)
2653 return pool->clock_sources[i];
2654 }
2655
2656 return NULL;
2657 }
2658
resource_build_info_frame(struct pipe_ctx * pipe_ctx)2659 void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2660 {
2661 enum signal_type signal = SIGNAL_TYPE_NONE;
2662 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
2663
2664 /* default all packets to invalid */
2665 info->avi.valid = false;
2666 info->gamut.valid = false;
2667 info->vendor.valid = false;
2668 info->spd.valid = false;
2669 info->hdrsmd.valid = false;
2670 info->vsc.valid = false;
2671
2672 signal = pipe_ctx->stream->signal;
2673
2674 /* HDMi and DP have different info packets*/
2675 if (dc_is_hdmi_signal(signal)) {
2676 set_avi_info_frame(&info->avi, pipe_ctx);
2677
2678 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2679
2680 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2681
2682 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2683
2684 } else if (dc_is_dp_signal(signal)) {
2685 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2686
2687 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2688
2689 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2690 }
2691
2692 patch_gamut_packet_checksum(&info->gamut);
2693 }
2694
resource_map_clock_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)2695 enum dc_status resource_map_clock_resources(
2696 const struct dc *dc,
2697 struct dc_state *context,
2698 struct dc_stream_state *stream)
2699 {
2700 /* acquire new resources */
2701 const struct resource_pool *pool = dc->res_pool;
2702 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2703 &context->res_ctx, stream);
2704
2705 if (!pipe_ctx)
2706 return DC_ERROR_UNEXPECTED;
2707
2708 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2709 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2710 pipe_ctx->clock_source = pool->dp_clock_source;
2711 else {
2712 pipe_ctx->clock_source = NULL;
2713
2714 if (!dc->config.disable_disp_pll_sharing)
2715 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
2716 &context->res_ctx,
2717 pipe_ctx);
2718
2719 if (pipe_ctx->clock_source == NULL)
2720 pipe_ctx->clock_source =
2721 dc_resource_find_first_free_pll(
2722 &context->res_ctx,
2723 pool);
2724 }
2725
2726 if (pipe_ctx->clock_source == NULL)
2727 return DC_NO_CLOCK_SOURCE_RESOURCE;
2728
2729 resource_reference_clock_source(
2730 &context->res_ctx, pool,
2731 pipe_ctx->clock_source);
2732
2733 return DC_OK;
2734 }
2735
2736 /*
2737 * Note: We need to disable output if clock sources change,
2738 * since bios does optimization and doesn't apply if changing
2739 * PHY when not already disabled.
2740 */
pipe_need_reprogram(struct pipe_ctx * pipe_ctx_old,struct pipe_ctx * pipe_ctx)2741 bool pipe_need_reprogram(
2742 struct pipe_ctx *pipe_ctx_old,
2743 struct pipe_ctx *pipe_ctx)
2744 {
2745 if (!pipe_ctx_old->stream)
2746 return false;
2747
2748 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2749 return true;
2750
2751 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2752 return true;
2753
2754 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
2755 return true;
2756
2757 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2758 && pipe_ctx_old->stream != pipe_ctx->stream)
2759 return true;
2760
2761 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
2762 return true;
2763
2764 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2765 return true;
2766
2767 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2768 return true;
2769
2770 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2771 false == pipe_ctx_old->stream->dpms_off)
2772 return true;
2773
2774 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
2775 return true;
2776
2777 return false;
2778 }
2779
resource_build_bit_depth_reduction_params(struct dc_stream_state * stream,struct bit_depth_reduction_params * fmt_bit_depth)2780 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
2781 struct bit_depth_reduction_params *fmt_bit_depth)
2782 {
2783 enum dc_dither_option option = stream->dither_option;
2784 enum dc_pixel_encoding pixel_encoding =
2785 stream->timing.pixel_encoding;
2786
2787 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2788
2789 if (option == DITHER_OPTION_DEFAULT) {
2790 switch (stream->timing.display_color_depth) {
2791 case COLOR_DEPTH_666:
2792 option = DITHER_OPTION_SPATIAL6;
2793 break;
2794 case COLOR_DEPTH_888:
2795 option = DITHER_OPTION_SPATIAL8;
2796 break;
2797 case COLOR_DEPTH_101010:
2798 option = DITHER_OPTION_SPATIAL10;
2799 break;
2800 default:
2801 option = DITHER_OPTION_DISABLE;
2802 }
2803 }
2804
2805 if (option == DITHER_OPTION_DISABLE)
2806 return;
2807
2808 if (option == DITHER_OPTION_TRUN6) {
2809 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2810 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2811 } else if (option == DITHER_OPTION_TRUN8 ||
2812 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2813 option == DITHER_OPTION_TRUN8_FM6) {
2814 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2815 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2816 } else if (option == DITHER_OPTION_TRUN10 ||
2817 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2818 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2819 option == DITHER_OPTION_TRUN10_FM8 ||
2820 option == DITHER_OPTION_TRUN10_FM6 ||
2821 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2822 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2823 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2824 }
2825
2826 /* special case - Formatter can only reduce by 4 bits at most.
2827 * When reducing from 12 to 6 bits,
2828 * HW recommends we use trunc with round mode
2829 * (if we did nothing, trunc to 10 bits would be used)
2830 * note that any 12->10 bit reduction is ignored prior to DCE8,
2831 * as the input was 10 bits.
2832 */
2833 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2834 option == DITHER_OPTION_SPATIAL6 ||
2835 option == DITHER_OPTION_FM6) {
2836 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2837 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2838 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2839 }
2840
2841 /* spatial dither
2842 * note that spatial modes 1-3 are never used
2843 */
2844 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2845 option == DITHER_OPTION_SPATIAL6 ||
2846 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
2847 option == DITHER_OPTION_TRUN8_SPATIAL6) {
2848 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2849 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2850 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2851 fmt_bit_depth->flags.RGB_RANDOM =
2852 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2853 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
2854 option == DITHER_OPTION_SPATIAL8 ||
2855 option == DITHER_OPTION_SPATIAL8_FM6 ||
2856 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
2857 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2858 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2859 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2860 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2861 fmt_bit_depth->flags.RGB_RANDOM =
2862 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2863 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2864 option == DITHER_OPTION_SPATIAL10 ||
2865 option == DITHER_OPTION_SPATIAL10_FM8 ||
2866 option == DITHER_OPTION_SPATIAL10_FM6) {
2867 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2868 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2869 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2870 fmt_bit_depth->flags.RGB_RANDOM =
2871 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2872 }
2873
2874 if (option == DITHER_OPTION_SPATIAL6 ||
2875 option == DITHER_OPTION_SPATIAL8 ||
2876 option == DITHER_OPTION_SPATIAL10) {
2877 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2878 } else {
2879 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2880 }
2881
2882 //////////////////////
2883 //// temporal dither
2884 //////////////////////
2885 if (option == DITHER_OPTION_FM6 ||
2886 option == DITHER_OPTION_SPATIAL8_FM6 ||
2887 option == DITHER_OPTION_SPATIAL10_FM6 ||
2888 option == DITHER_OPTION_TRUN10_FM6 ||
2889 option == DITHER_OPTION_TRUN8_FM6 ||
2890 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2891 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2892 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2893 } else if (option == DITHER_OPTION_FM8 ||
2894 option == DITHER_OPTION_SPATIAL10_FM8 ||
2895 option == DITHER_OPTION_TRUN10_FM8) {
2896 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2897 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2898 } else if (option == DITHER_OPTION_FM10) {
2899 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2900 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2901 }
2902
2903 fmt_bit_depth->pixel_encoding = pixel_encoding;
2904 }
2905
dc_validate_stream(struct dc * dc,struct dc_stream_state * stream)2906 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
2907 {
2908 struct dc_link *link = stream->link;
2909 struct timing_generator *tg = dc->res_pool->timing_generators[0];
2910 enum dc_status res = DC_OK;
2911
2912 calculate_phy_pix_clks(stream);
2913
2914 if (!tg->funcs->validate_timing(tg, &stream->timing))
2915 res = DC_FAIL_CONTROLLER_VALIDATE;
2916
2917 if (res == DC_OK) {
2918 if (!link->link_enc->funcs->validate_output_with_stream(
2919 link->link_enc, stream))
2920 res = DC_FAIL_ENC_VALIDATE;
2921 }
2922
2923 /* TODO: validate audio ASIC caps, encoder */
2924
2925 if (res == DC_OK)
2926 res = dc_link_validate_mode_timing(stream,
2927 link,
2928 &stream->timing);
2929
2930 return res;
2931 }
2932
dc_validate_plane(struct dc * dc,const struct dc_plane_state * plane_state)2933 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
2934 {
2935 enum dc_status res = DC_OK;
2936
2937 /* TODO For now validates pixel format only */
2938 if (dc->res_pool->funcs->validate_plane)
2939 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
2940
2941 return res;
2942 }
2943
resource_pixel_format_to_bpp(enum surface_pixel_format format)2944 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2945 {
2946 switch (format) {
2947 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2948 return 8;
2949 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2950 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2951 return 12;
2952 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2953 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2954 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2955 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2956 return 16;
2957 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2958 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2959 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2960 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2961 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2962 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2963 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
2964 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
2965 #endif
2966 return 32;
2967 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2968 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2969 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2970 return 64;
2971 default:
2972 ASSERT_CRITICAL(false);
2973 return -1;
2974 }
2975 }
get_max_audio_sample_rate(struct audio_mode * modes)2976 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
2977 {
2978 if (modes) {
2979 if (modes->sample_rates.rate.RATE_192)
2980 return 192000;
2981 if (modes->sample_rates.rate.RATE_176_4)
2982 return 176400;
2983 if (modes->sample_rates.rate.RATE_96)
2984 return 96000;
2985 if (modes->sample_rates.rate.RATE_88_2)
2986 return 88200;
2987 if (modes->sample_rates.rate.RATE_48)
2988 return 48000;
2989 if (modes->sample_rates.rate.RATE_44_1)
2990 return 44100;
2991 if (modes->sample_rates.rate.RATE_32)
2992 return 32000;
2993 }
2994 /*original logic when no audio info*/
2995 return 441000;
2996 }
2997
get_audio_check(struct audio_info * aud_modes,struct audio_check * audio_chk)2998 void get_audio_check(struct audio_info *aud_modes,
2999 struct audio_check *audio_chk)
3000 {
3001 unsigned int i;
3002 unsigned int max_sample_rate = 0;
3003
3004 if (aud_modes) {
3005 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
3006
3007 audio_chk->max_audiosample_rate = 0;
3008 for (i = 0; i < aud_modes->mode_count; i++) {
3009 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
3010 if (audio_chk->max_audiosample_rate < max_sample_rate)
3011 audio_chk->max_audiosample_rate = max_sample_rate;
3012 /*dts takes the same as type 2: AP = 0.25*/
3013 }
3014 /*check which one take more bandwidth*/
3015 if (audio_chk->max_audiosample_rate > 192000)
3016 audio_chk->audio_packet_type = 0x9;/*AP =1*/
3017 audio_chk->acat = 0;/*not support*/
3018 }
3019 }
3020
3021