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Searched defs:pll_settings (Results 1 – 3 of 3) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/
Dclock_source.h106 struct pll_settings { struct
107 uint32_t actual_pix_clk_100hz;
108 uint32_t adjusted_pix_clk_100hz;
109 uint32_t calculated_pix_clk_100hz;
110 uint32_t vco_freq;
111 uint32_t reference_freq;
112 uint32_t reference_divider;
113 uint32_t feedback_divider;
114 uint32_t fract_feedback_divider;
115 uint32_t pix_clk_post_divider;
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Dcore_types.h317 struct pll_settings pll_settings; member
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.c196 struct pll_settings *pll_settings, in calc_fb_divider_checking_tolerance()
252 struct pll_settings *pll_settings, in calc_pll_dividers_in_range()
294 struct pll_settings *pll_settings) in calculate_pixel_clock_pll_dividers()
398 struct pll_settings *pll_settings) in pll_adjust_pix_clk()
476 struct pll_settings *pll_settings, in dce110_get_pix_clk_dividers_helper()
538 struct pll_settings *pll_settings, in dce112_get_pix_clk_dividers_helper()
568 struct pll_settings *pll_settings) in dce110_get_pix_clk_dividers()
601 struct pll_settings *pll_settings) in dce112_get_pix_clk_dividers()
647 const struct pll_settings *pll_settings, in calculate_ss()
713 enum signal_type signal, struct pll_settings *pll_settings) in enable_spread_spectrum()
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