/third_party/ffmpeg/libavutil/mips/ |
D | mmiutils.h | 101 #define MMI_LQ(reg1, reg2, addr, bias) \ argument 105 #define MMI_SQ(reg1, reg2, addr, bias) \ argument 192 #define MMI_LQ(reg1, reg2, addr, bias) \ argument 195 #define MMI_SQ(reg1, reg2, addr, bias) \ argument
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/third_party/openssl/crypto/aria/ |
D | aria.c | 474 register uint32_t reg0, reg1, reg2, reg3; in aria_encrypt() local 541 register uint32_t reg0, reg1, reg2, reg3; in aria_set_encrypt_key() local 676 register uint32_t reg0, reg1, reg2, reg3; in aria_set_decrypt_key() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64PBQPRegAlloc.cpp | 149 bool haveSameParity(unsigned reg1, unsigned reg2) { in haveSameParity()
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/third_party/mesa3d/src/util/ |
D | register_allocate.c | 134 struct ra_reg *reg1 = ®s->regs[r1]; in ra_add_conflict_list() local 180 unsigned int base_reg, unsigned int reg0, unsigned int reg1) in ra_add_transitive_reg_pair_conflict()
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/third_party/ffmpeg/libavcodec/mips/ |
D | vp9_idct_msa.c | 67 #define VP9_DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \ argument 968 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vp9_idct16_1d_columns_addblk_msa() local 1071 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vp9_idct16_1d_columns_msa() local 1634 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in vp9_idct8x32_column_even_process_store() local 1718 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in vp9_idct8x32_column_odd_process_store() local
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D | h264pred_msa.c | 217 v4i32 reg0, reg1, reg2, reg3; in intra_predict_plane_16x16_msa() local
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/third_party/pcre2/pcre2/src/sljit/ |
D | sljitNativeARM_T2_32.c | 70 #define IS_2_LO_REGS(reg1, reg2) \ argument 72 #define IS_3_LO_REGS(reg1, reg2, reg3) \ argument
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/third_party/mesa3d/src/intel/compiler/ |
D | brw_fs_bank_conflicts.cpp | 416 for (unsigned reg1 = reg + 1; reg1 <= max_reg; reg1++) { in require_contiguous() local
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/third_party/mesa3d/src/freedreno/decode/ |
D | crashdec.c | 595 uint32_t reg1 : 18; in dump_mem_pool_chunk() member
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/third_party/mesa3d/src/panfrost/bifrost/ |
D | bifrost.h | 221 unsigned reg1 : 6; member
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/third_party/pixman/pixman/ |
D | pixman-region.c | 749 region_type_t * reg1, /* First region in operation */ in pixman_op()
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
D | IceAssemblerX8664.cpp | 2168 void AssemblerX8664::arith_int(Type Ty, GPRRegister reg0, GPRRegister reg1) { in arith_int() 2230 void AssemblerX8664::cmp(Type Ty, GPRRegister reg0, GPRRegister reg1) { in cmp() 2247 void AssemblerX8664::test(Type Ty, GPRRegister reg1, GPRRegister reg2) { in test() 3130 void AssemblerX8664::xchg(Type Ty, GPRRegister reg0, GPRRegister reg1) { in xchg()
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D | IceAssemblerX8632.cpp | 2050 void AssemblerX8632::arith_int(Type Ty, GPRRegister reg0, GPRRegister reg1) { in arith_int() 2108 void AssemblerX8632::cmp(Type Ty, GPRRegister reg0, GPRRegister reg1) { in cmp() 2125 void AssemblerX8632::test(Type Ty, GPRRegister reg1, GPRRegister reg2) { in test() 2972 void AssemblerX8632::xchg(Type Ty, GPRRegister reg0, GPRRegister reg1) { in xchg()
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/third_party/ltp/tools/sparse/sparse-src/ |
D | example.c | 925 struct hardreg *reg1, *reg2; in generate_commutative_binop() local
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D | compile-i386.c | 1233 struct storage *reg1, *reg2; in emit_compare() local
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