1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RPC-IF core driver
4 *
5 * Copyright (C) 2018-2019 Renesas Solutions Corp.
6 * Copyright (C) 2019 Macronix International Co., Ltd.
7 * Copyright (C) 2019-2020 Cogent Embedded, Inc.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/of.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18
19 #include <memory/renesas-rpc-if.h>
20
21 #define RPCIF_CMNCR 0x0000 /* R/W */
22 #define RPCIF_CMNCR_MD BIT(31)
23 #define RPCIF_CMNCR_SFDE BIT(24) /* undocumented but must be set */
24 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
25 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
26 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
27 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
28 #define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \
29 RPCIF_CMNCR_MOIIO1(3) | \
30 RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
31 #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
32 #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
33 #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
34 #define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
35 RPCIF_CMNCR_IO3FV(3))
36 #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
37
38 #define RPCIF_SSLDR 0x0004 /* R/W */
39 #define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
40 #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
41 #define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
42
43 #define RPCIF_DRCR 0x000C /* R/W */
44 #define RPCIF_DRCR_SSLN BIT(24)
45 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
46 #define RPCIF_DRCR_RCF BIT(9)
47 #define RPCIF_DRCR_RBE BIT(8)
48 #define RPCIF_DRCR_SSLE BIT(0)
49
50 #define RPCIF_DRCMR 0x0010 /* R/W */
51 #define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
52 #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
53
54 #define RPCIF_DREAR 0x0014 /* R/W */
55 #define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
56 #define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
57
58 #define RPCIF_DROPR 0x0018 /* R/W */
59
60 #define RPCIF_DRENR 0x001C /* R/W */
61 #define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
62 #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
63 #define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
64 #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
65 #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
66 #define RPCIF_DRENR_DME BIT(15)
67 #define RPCIF_DRENR_CDE BIT(14)
68 #define RPCIF_DRENR_OCDE BIT(12)
69 #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
70 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
71
72 #define RPCIF_SMCR 0x0020 /* R/W */
73 #define RPCIF_SMCR_SSLKP BIT(8)
74 #define RPCIF_SMCR_SPIRE BIT(2)
75 #define RPCIF_SMCR_SPIWE BIT(1)
76 #define RPCIF_SMCR_SPIE BIT(0)
77
78 #define RPCIF_SMCMR 0x0024 /* R/W */
79 #define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
80 #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
81
82 #define RPCIF_SMADR 0x0028 /* R/W */
83
84 #define RPCIF_SMOPR 0x002C /* R/W */
85 #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
86 #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
87 #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
88 #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
89
90 #define RPCIF_SMENR 0x0030 /* R/W */
91 #define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
92 #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
93 #define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
94 #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
95 #define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
96 #define RPCIF_SMENR_DME BIT(15)
97 #define RPCIF_SMENR_CDE BIT(14)
98 #define RPCIF_SMENR_OCDE BIT(12)
99 #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
100 #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
101 #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
102
103 #define RPCIF_SMRDR0 0x0038 /* R */
104 #define RPCIF_SMRDR1 0x003C /* R */
105 #define RPCIF_SMWDR0 0x0040 /* W */
106 #define RPCIF_SMWDR1 0x0044 /* W */
107
108 #define RPCIF_CMNSR 0x0048 /* R */
109 #define RPCIF_CMNSR_SSLF BIT(1)
110 #define RPCIF_CMNSR_TEND BIT(0)
111
112 #define RPCIF_DRDMCR 0x0058 /* R/W */
113 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
114
115 #define RPCIF_DRDRENR 0x005C /* R/W */
116 #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
117 #define RPCIF_DRDRENR_ADDRE BIT(8)
118 #define RPCIF_DRDRENR_OPDRE BIT(4)
119 #define RPCIF_DRDRENR_DRDRE BIT(0)
120
121 #define RPCIF_SMDMCR 0x0060 /* R/W */
122 #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
123
124 #define RPCIF_SMDRENR 0x0064 /* R/W */
125 #define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
126 #define RPCIF_SMDRENR_ADDRE BIT(8)
127 #define RPCIF_SMDRENR_OPDRE BIT(4)
128 #define RPCIF_SMDRENR_SPIDRE BIT(0)
129
130 #define RPCIF_PHYCNT 0x007C /* R/W */
131 #define RPCIF_PHYCNT_CAL BIT(31)
132 #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
133 #define RPCIF_PHYCNT_EXDS BIT(21)
134 #define RPCIF_PHYCNT_OCT BIT(20)
135 #define RPCIF_PHYCNT_DDRCAL BIT(19)
136 #define RPCIF_PHYCNT_HS BIT(18)
137 #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
138 #define RPCIF_PHYCNT_WBUF2 BIT(4)
139 #define RPCIF_PHYCNT_WBUF BIT(2)
140 #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
141
142 #define RPCIF_PHYOFFSET1 0x0080 /* R/W */
143 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
144
145 #define RPCIF_PHYOFFSET2 0x0084 /* R/W */
146 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
147
148 #define RPCIF_PHYINT 0x0088 /* R/W */
149 #define RPCIF_PHYINT_WPVAL BIT(1)
150
151 #define RPCIF_DIRMAP_SIZE 0x4000000
152
153 static const struct regmap_range rpcif_volatile_ranges[] = {
154 regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
155 regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
156 regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
157 };
158
159 static const struct regmap_access_table rpcif_volatile_table = {
160 .yes_ranges = rpcif_volatile_ranges,
161 .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
162 };
163
164
165 /*
166 * Custom accessor functions to ensure SMRDR0 and SMWDR0 are always accessed
167 * with proper width. Requires SMENR_SPIDE to be correctly set before!
168 */
rpcif_reg_read(void * context,unsigned int reg,unsigned int * val)169 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
170 {
171 struct rpcif *rpc = context;
172
173 if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
174 u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
175
176 if (spide == 0x8) {
177 *val = readb(rpc->base + reg);
178 return 0;
179 } else if (spide == 0xC) {
180 *val = readw(rpc->base + reg);
181 return 0;
182 } else if (spide != 0xF) {
183 return -EILSEQ;
184 }
185 }
186
187 *val = readl(rpc->base + reg);
188 return 0;
189
190 }
191
rpcif_reg_write(void * context,unsigned int reg,unsigned int val)192 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
193 {
194 struct rpcif *rpc = context;
195
196 if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
197 u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
198
199 if (spide == 0x8) {
200 writeb(val, rpc->base + reg);
201 return 0;
202 } else if (spide == 0xC) {
203 writew(val, rpc->base + reg);
204 return 0;
205 } else if (spide != 0xF) {
206 return -EILSEQ;
207 }
208 }
209
210 writel(val, rpc->base + reg);
211 return 0;
212 }
213
214 static const struct regmap_config rpcif_regmap_config = {
215 .reg_bits = 32,
216 .val_bits = 32,
217 .reg_stride = 4,
218 .reg_read = rpcif_reg_read,
219 .reg_write = rpcif_reg_write,
220 .fast_io = true,
221 .max_register = RPCIF_PHYINT,
222 .volatile_table = &rpcif_volatile_table,
223 };
224
rpcif_sw_init(struct rpcif * rpc,struct device * dev)225 int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
226 {
227 struct platform_device *pdev = to_platform_device(dev);
228 struct resource *res;
229
230 rpc->dev = dev;
231
232 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
233 rpc->base = devm_ioremap_resource(&pdev->dev, res);
234 if (IS_ERR(rpc->base))
235 return PTR_ERR(rpc->base);
236
237 rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config);
238 if (IS_ERR(rpc->regmap)) {
239 dev_err(&pdev->dev,
240 "failed to init regmap for rpcif, error %ld\n",
241 PTR_ERR(rpc->regmap));
242 return PTR_ERR(rpc->regmap);
243 }
244
245 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
246 rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
247 if (IS_ERR(rpc->dirmap))
248 return PTR_ERR(rpc->dirmap);
249 rpc->size = resource_size(res);
250
251 rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
252
253 return PTR_ERR_OR_ZERO(rpc->rstc);
254 }
255 EXPORT_SYMBOL(rpcif_sw_init);
256
rpcif_enable_rpm(struct rpcif * rpc)257 void rpcif_enable_rpm(struct rpcif *rpc)
258 {
259 pm_runtime_enable(rpc->dev);
260 }
261 EXPORT_SYMBOL(rpcif_enable_rpm);
262
rpcif_disable_rpm(struct rpcif * rpc)263 void rpcif_disable_rpm(struct rpcif *rpc)
264 {
265 pm_runtime_disable(rpc->dev);
266 }
267 EXPORT_SYMBOL(rpcif_disable_rpm);
268
rpcif_hw_init(struct rpcif * rpc,bool hyperflash)269 void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
270 {
271 u32 dummy;
272
273 pm_runtime_get_sync(rpc->dev);
274
275 /*
276 * NOTE: The 0x260 are undocumented bits, but they must be set.
277 * RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
278 * 0x0 : the delay is biggest,
279 * 0x1 : the delay is 2nd biggest,
280 * On H3 ES1.x, the value should be 0, while on others,
281 * the value should be 7.
282 */
283 regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
284 RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
285
286 /*
287 * NOTE: The 0x1511144 are undocumented bits, but they must be set
288 * for RPCIF_PHYOFFSET1.
289 * The 0x31 are undocumented bits, but they must be set
290 * for RPCIF_PHYOFFSET2.
291 */
292 regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 |
293 RPCIF_PHYOFFSET1_DDRTMG(3));
294 regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 |
295 RPCIF_PHYOFFSET2_OCTTMG(4));
296
297 if (hyperflash)
298 regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
299 RPCIF_PHYINT_WPVAL, 0);
300
301 regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
302 RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
303 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
304 /* Set RCF after BSZ update */
305 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
306 /* Dummy read according to spec */
307 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
308 regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
309 RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
310
311 pm_runtime_put(rpc->dev);
312
313 rpc->bus_size = hyperflash ? 2 : 1;
314 }
315 EXPORT_SYMBOL(rpcif_hw_init);
316
wait_msg_xfer_end(struct rpcif * rpc)317 static int wait_msg_xfer_end(struct rpcif *rpc)
318 {
319 u32 sts;
320
321 return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
322 sts & RPCIF_CMNSR_TEND, 0,
323 USEC_PER_SEC);
324 }
325
rpcif_bits_set(struct rpcif * rpc,u32 nbytes)326 static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
327 {
328 if (rpc->bus_size == 2)
329 nbytes /= 2;
330 nbytes = clamp(nbytes, 1U, 4U);
331 return GENMASK(3, 4 - nbytes);
332 }
333
rpcif_bit_size(u8 buswidth)334 static u8 rpcif_bit_size(u8 buswidth)
335 {
336 return buswidth > 4 ? 2 : ilog2(buswidth);
337 }
338
rpcif_prepare(struct rpcif * rpc,const struct rpcif_op * op,u64 * offs,size_t * len)339 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
340 size_t *len)
341 {
342 rpc->smcr = 0;
343 rpc->smadr = 0;
344 rpc->enable = 0;
345 rpc->command = 0;
346 rpc->option = 0;
347 rpc->dummy = 0;
348 rpc->ddr = 0;
349 rpc->xferlen = 0;
350
351 if (op->cmd.buswidth) {
352 rpc->enable = RPCIF_SMENR_CDE |
353 RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
354 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
355 if (op->cmd.ddr)
356 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
357 }
358 if (op->ocmd.buswidth) {
359 rpc->enable |= RPCIF_SMENR_OCDE |
360 RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
361 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
362 }
363
364 if (op->addr.buswidth) {
365 rpc->enable |=
366 RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
367 if (op->addr.nbytes == 4)
368 rpc->enable |= RPCIF_SMENR_ADE(0xF);
369 else
370 rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
371 2, 3 - op->addr.nbytes));
372 if (op->addr.ddr)
373 rpc->ddr |= RPCIF_SMDRENR_ADDRE;
374
375 if (offs && len)
376 rpc->smadr = *offs;
377 else
378 rpc->smadr = op->addr.val;
379 }
380
381 if (op->dummy.buswidth) {
382 rpc->enable |= RPCIF_SMENR_DME;
383 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
384 op->dummy.buswidth);
385 }
386
387 if (op->option.buswidth) {
388 rpc->enable |= RPCIF_SMENR_OPDE(
389 rpcif_bits_set(rpc, op->option.nbytes)) |
390 RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
391 if (op->option.ddr)
392 rpc->ddr |= RPCIF_SMDRENR_OPDRE;
393 rpc->option = op->option.val;
394 }
395
396 rpc->dir = op->data.dir;
397 if (op->data.buswidth) {
398 u32 nbytes;
399
400 rpc->buffer = op->data.buf.in;
401 switch (op->data.dir) {
402 case RPCIF_DATA_IN:
403 rpc->smcr = RPCIF_SMCR_SPIRE;
404 break;
405 case RPCIF_DATA_OUT:
406 rpc->smcr = RPCIF_SMCR_SPIWE;
407 break;
408 default:
409 break;
410 }
411 if (op->data.ddr)
412 rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
413
414 if (offs && len)
415 nbytes = *len;
416 else
417 nbytes = op->data.nbytes;
418 rpc->xferlen = nbytes;
419
420 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
421 }
422 }
423 EXPORT_SYMBOL(rpcif_prepare);
424
rpcif_manual_xfer(struct rpcif * rpc)425 int rpcif_manual_xfer(struct rpcif *rpc)
426 {
427 u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
428 int ret = 0;
429
430 pm_runtime_get_sync(rpc->dev);
431
432 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
433 RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
434 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
435 RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
436 regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
437 regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
438 regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
439 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
440 regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
441 smenr = rpc->enable;
442
443 switch (rpc->dir) {
444 case RPCIF_DATA_OUT:
445 while (pos < rpc->xferlen) {
446 u32 bytes_left = rpc->xferlen - pos;
447 u32 nbytes, data[2];
448
449 smcr = rpc->smcr | RPCIF_SMCR_SPIE;
450
451 /* nbytes may only be 1, 2, 4, or 8 */
452 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
453 if (bytes_left > nbytes)
454 smcr |= RPCIF_SMCR_SSLKP;
455
456 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
457 regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
458
459 memcpy(data, rpc->buffer + pos, nbytes);
460 if (nbytes == 8) {
461 regmap_write(rpc->regmap, RPCIF_SMWDR1,
462 data[0]);
463 regmap_write(rpc->regmap, RPCIF_SMWDR0,
464 data[1]);
465 } else {
466 regmap_write(rpc->regmap, RPCIF_SMWDR0,
467 data[0]);
468 }
469
470 regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
471 ret = wait_msg_xfer_end(rpc);
472 if (ret)
473 goto err_out;
474
475 pos += nbytes;
476 smenr = rpc->enable &
477 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
478 }
479 break;
480 case RPCIF_DATA_IN:
481 /*
482 * RPC-IF spoils the data for the commands without an address
483 * phase (like RDID) in the manual mode, so we'll have to work
484 * around this issue by using the external address space read
485 * mode instead.
486 */
487 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
488 u32 dummy;
489
490 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
491 RPCIF_CMNCR_MD, 0);
492 regmap_write(rpc->regmap, RPCIF_DRCR,
493 RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
494 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
495 regmap_write(rpc->regmap, RPCIF_DREAR,
496 RPCIF_DREAR_EAC(1));
497 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
498 regmap_write(rpc->regmap, RPCIF_DRENR,
499 smenr & ~RPCIF_SMENR_SPIDE(0xF));
500 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
501 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
502 memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
503 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
504 /* Dummy read according to spec */
505 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
506 break;
507 }
508 while (pos < rpc->xferlen) {
509 u32 bytes_left = rpc->xferlen - pos;
510 u32 nbytes, data[2];
511
512 /* nbytes may only be 1, 2, 4, or 8 */
513 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
514
515 regmap_write(rpc->regmap, RPCIF_SMADR,
516 rpc->smadr + pos);
517 smenr &= ~RPCIF_SMENR_SPIDE(0xF);
518 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
519 regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
520 regmap_write(rpc->regmap, RPCIF_SMCR,
521 rpc->smcr | RPCIF_SMCR_SPIE);
522 ret = wait_msg_xfer_end(rpc);
523 if (ret)
524 goto err_out;
525
526 if (nbytes == 8) {
527 regmap_read(rpc->regmap, RPCIF_SMRDR1,
528 &data[0]);
529 regmap_read(rpc->regmap, RPCIF_SMRDR0,
530 &data[1]);
531 } else {
532 regmap_read(rpc->regmap, RPCIF_SMRDR0,
533 &data[0]);
534 }
535 memcpy(rpc->buffer + pos, data, nbytes);
536
537 pos += nbytes;
538 }
539 break;
540 default:
541 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
542 regmap_write(rpc->regmap, RPCIF_SMCR,
543 rpc->smcr | RPCIF_SMCR_SPIE);
544 ret = wait_msg_xfer_end(rpc);
545 if (ret)
546 goto err_out;
547 }
548
549 exit:
550 pm_runtime_put(rpc->dev);
551 return ret;
552
553 err_out:
554 if (reset_control_reset(rpc->rstc))
555 dev_err(rpc->dev, "Failed to reset HW\n");
556 rpcif_hw_init(rpc, rpc->bus_size == 2);
557 goto exit;
558 }
559 EXPORT_SYMBOL(rpcif_manual_xfer);
560
rpcif_dirmap_read(struct rpcif * rpc,u64 offs,size_t len,void * buf)561 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
562 {
563 loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
564 size_t size = RPCIF_DIRMAP_SIZE - from;
565
566 if (len > size)
567 len = size;
568
569 pm_runtime_get_sync(rpc->dev);
570
571 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
572 regmap_write(rpc->regmap, RPCIF_DRCR, 0);
573 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
574 regmap_write(rpc->regmap, RPCIF_DREAR,
575 RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
576 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
577 regmap_write(rpc->regmap, RPCIF_DRENR,
578 rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
579 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
580 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
581
582 memcpy_fromio(buf, rpc->dirmap + from, len);
583
584 pm_runtime_put(rpc->dev);
585
586 return len;
587 }
588 EXPORT_SYMBOL(rpcif_dirmap_read);
589
rpcif_probe(struct platform_device * pdev)590 static int rpcif_probe(struct platform_device *pdev)
591 {
592 struct platform_device *vdev;
593 struct device_node *flash;
594 const char *name;
595
596 flash = of_get_next_child(pdev->dev.of_node, NULL);
597 if (!flash) {
598 dev_warn(&pdev->dev, "no flash node found\n");
599 return -ENODEV;
600 }
601
602 if (of_device_is_compatible(flash, "jedec,spi-nor")) {
603 name = "rpc-if-spi";
604 } else if (of_device_is_compatible(flash, "cfi-flash")) {
605 name = "rpc-if-hyperflash";
606 } else {
607 of_node_put(flash);
608 dev_warn(&pdev->dev, "unknown flash type\n");
609 return -ENODEV;
610 }
611 of_node_put(flash);
612
613 vdev = platform_device_alloc(name, pdev->id);
614 if (!vdev)
615 return -ENOMEM;
616 vdev->dev.parent = &pdev->dev;
617 platform_set_drvdata(pdev, vdev);
618 return platform_device_add(vdev);
619 }
620
rpcif_remove(struct platform_device * pdev)621 static int rpcif_remove(struct platform_device *pdev)
622 {
623 struct platform_device *vdev = platform_get_drvdata(pdev);
624
625 platform_device_unregister(vdev);
626
627 return 0;
628 }
629
630 static const struct of_device_id rpcif_of_match[] = {
631 { .compatible = "renesas,rcar-gen3-rpc-if", },
632 {},
633 };
634 MODULE_DEVICE_TABLE(of, rpcif_of_match);
635
636 static struct platform_driver rpcif_driver = {
637 .probe = rpcif_probe,
638 .remove = rpcif_remove,
639 .driver = {
640 .name = "rpc-if",
641 .of_match_table = rpcif_of_match,
642 },
643 };
644 module_platform_driver(rpcif_driver);
645
646 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
647 MODULE_LICENSE("GPL v2");
648