1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SVM_H
3 #define __SVM_H
4
5 #include <uapi/asm/svm.h>
6 #include <uapi/asm/kvm.h>
7
8 /*
9 * 32-bit intercept words in the VMCB Control Area, starting
10 * at Byte offset 000h.
11 */
12
13 enum intercept_words {
14 INTERCEPT_CR = 0,
15 INTERCEPT_DR,
16 INTERCEPT_EXCEPTION,
17 INTERCEPT_WORD3,
18 INTERCEPT_WORD4,
19 INTERCEPT_WORD5,
20 MAX_INTERCEPT,
21 };
22
23 enum {
24 /* Byte offset 000h (word 0) */
25 INTERCEPT_CR0_READ = 0,
26 INTERCEPT_CR3_READ = 3,
27 INTERCEPT_CR4_READ = 4,
28 INTERCEPT_CR8_READ = 8,
29 INTERCEPT_CR0_WRITE = 16,
30 INTERCEPT_CR3_WRITE = 16 + 3,
31 INTERCEPT_CR4_WRITE = 16 + 4,
32 INTERCEPT_CR8_WRITE = 16 + 8,
33 /* Byte offset 004h (word 1) */
34 INTERCEPT_DR0_READ = 32,
35 INTERCEPT_DR1_READ,
36 INTERCEPT_DR2_READ,
37 INTERCEPT_DR3_READ,
38 INTERCEPT_DR4_READ,
39 INTERCEPT_DR5_READ,
40 INTERCEPT_DR6_READ,
41 INTERCEPT_DR7_READ,
42 INTERCEPT_DR0_WRITE = 48,
43 INTERCEPT_DR1_WRITE,
44 INTERCEPT_DR2_WRITE,
45 INTERCEPT_DR3_WRITE,
46 INTERCEPT_DR4_WRITE,
47 INTERCEPT_DR5_WRITE,
48 INTERCEPT_DR6_WRITE,
49 INTERCEPT_DR7_WRITE,
50 /* Byte offset 008h (word 2) */
51 INTERCEPT_EXCEPTION_OFFSET = 64,
52 /* Byte offset 00Ch (word 3) */
53 INTERCEPT_INTR = 96,
54 INTERCEPT_NMI,
55 INTERCEPT_SMI,
56 INTERCEPT_INIT,
57 INTERCEPT_VINTR,
58 INTERCEPT_SELECTIVE_CR0,
59 INTERCEPT_STORE_IDTR,
60 INTERCEPT_STORE_GDTR,
61 INTERCEPT_STORE_LDTR,
62 INTERCEPT_STORE_TR,
63 INTERCEPT_LOAD_IDTR,
64 INTERCEPT_LOAD_GDTR,
65 INTERCEPT_LOAD_LDTR,
66 INTERCEPT_LOAD_TR,
67 INTERCEPT_RDTSC,
68 INTERCEPT_RDPMC,
69 INTERCEPT_PUSHF,
70 INTERCEPT_POPF,
71 INTERCEPT_CPUID,
72 INTERCEPT_RSM,
73 INTERCEPT_IRET,
74 INTERCEPT_INTn,
75 INTERCEPT_INVD,
76 INTERCEPT_PAUSE,
77 INTERCEPT_HLT,
78 INTERCEPT_INVLPG,
79 INTERCEPT_INVLPGA,
80 INTERCEPT_IOIO_PROT,
81 INTERCEPT_MSR_PROT,
82 INTERCEPT_TASK_SWITCH,
83 INTERCEPT_FERR_FREEZE,
84 INTERCEPT_SHUTDOWN,
85 /* Byte offset 010h (word 4) */
86 INTERCEPT_VMRUN = 128,
87 INTERCEPT_VMMCALL,
88 INTERCEPT_VMLOAD,
89 INTERCEPT_VMSAVE,
90 INTERCEPT_STGI,
91 INTERCEPT_CLGI,
92 INTERCEPT_SKINIT,
93 INTERCEPT_RDTSCP,
94 INTERCEPT_ICEBP,
95 INTERCEPT_WBINVD,
96 INTERCEPT_MONITOR,
97 INTERCEPT_MWAIT,
98 INTERCEPT_MWAIT_COND,
99 INTERCEPT_XSETBV,
100 INTERCEPT_RDPRU,
101 /* Byte offset 014h (word 5) */
102 INTERCEPT_INVLPGB = 160,
103 INTERCEPT_INVLPGB_ILLEGAL,
104 INTERCEPT_INVPCID,
105 INTERCEPT_MCOMMIT,
106 INTERCEPT_TLBSYNC,
107 };
108
109
110 struct __attribute__ ((__packed__)) vmcb_control_area {
111 u32 intercepts[MAX_INTERCEPT];
112 u32 reserved_1[15 - MAX_INTERCEPT];
113 u16 pause_filter_thresh;
114 u16 pause_filter_count;
115 u64 iopm_base_pa;
116 u64 msrpm_base_pa;
117 u64 tsc_offset;
118 u32 asid;
119 u8 tlb_ctl;
120 u8 reserved_2[3];
121 u32 int_ctl;
122 u32 int_vector;
123 u32 int_state;
124 u8 reserved_3[4];
125 u32 exit_code;
126 u32 exit_code_hi;
127 u64 exit_info_1;
128 u64 exit_info_2;
129 u32 exit_int_info;
130 u32 exit_int_info_err;
131 u64 nested_ctl;
132 u64 avic_vapic_bar;
133 u8 reserved_4[8];
134 u32 event_inj;
135 u32 event_inj_err;
136 u64 nested_cr3;
137 u64 virt_ext;
138 u32 clean;
139 u32 reserved_5;
140 u64 next_rip;
141 u8 insn_len;
142 u8 insn_bytes[15];
143 u64 avic_backing_page; /* Offset 0xe0 */
144 u8 reserved_6[8]; /* Offset 0xe8 */
145 u64 avic_logical_id; /* Offset 0xf0 */
146 u64 avic_physical_id; /* Offset 0xf8 */
147 };
148
149
150 #define TLB_CONTROL_DO_NOTHING 0
151 #define TLB_CONTROL_FLUSH_ALL_ASID 1
152 #define TLB_CONTROL_FLUSH_ASID 3
153 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
154
155 #define V_TPR_MASK 0x0f
156
157 #define V_IRQ_SHIFT 8
158 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
159
160 #define V_GIF_SHIFT 9
161 #define V_GIF_MASK (1 << V_GIF_SHIFT)
162
163 #define V_INTR_PRIO_SHIFT 16
164 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
165
166 #define V_IGN_TPR_SHIFT 20
167 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
168
169 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
170
171 #define V_INTR_MASKING_SHIFT 24
172 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
173
174 #define V_GIF_ENABLE_SHIFT 25
175 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
176
177 #define AVIC_ENABLE_SHIFT 31
178 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
179
180 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
181 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
182
183 #define SVM_INTERRUPT_SHADOW_MASK 1
184
185 #define SVM_IOIO_STR_SHIFT 2
186 #define SVM_IOIO_REP_SHIFT 3
187 #define SVM_IOIO_SIZE_SHIFT 4
188 #define SVM_IOIO_ASIZE_SHIFT 7
189
190 #define SVM_IOIO_TYPE_MASK 1
191 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
192 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
193 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
194 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
195
196 #define SVM_VM_CR_VALID_MASK 0x001fULL
197 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
198 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
199
200 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
201 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
202
203 struct vmcb_seg {
204 u16 selector;
205 u16 attrib;
206 u32 limit;
207 u64 base;
208 } __packed;
209
210 struct vmcb_save_area {
211 struct vmcb_seg es;
212 struct vmcb_seg cs;
213 struct vmcb_seg ss;
214 struct vmcb_seg ds;
215 struct vmcb_seg fs;
216 struct vmcb_seg gs;
217 struct vmcb_seg gdtr;
218 struct vmcb_seg ldtr;
219 struct vmcb_seg idtr;
220 struct vmcb_seg tr;
221 u8 reserved_1[43];
222 u8 cpl;
223 u8 reserved_2[4];
224 u64 efer;
225 u8 reserved_3[112];
226 u64 cr4;
227 u64 cr3;
228 u64 cr0;
229 u64 dr7;
230 u64 dr6;
231 u64 rflags;
232 u64 rip;
233 u8 reserved_4[88];
234 u64 rsp;
235 u8 reserved_5[24];
236 u64 rax;
237 u64 star;
238 u64 lstar;
239 u64 cstar;
240 u64 sfmask;
241 u64 kernel_gs_base;
242 u64 sysenter_cs;
243 u64 sysenter_esp;
244 u64 sysenter_eip;
245 u64 cr2;
246 u8 reserved_6[32];
247 u64 g_pat;
248 u64 dbgctl;
249 u64 br_from;
250 u64 br_to;
251 u64 last_excp_from;
252 u64 last_excp_to;
253
254 /*
255 * The following part of the save area is valid only for
256 * SEV-ES guests when referenced through the GHCB.
257 */
258 u8 reserved_7[104];
259 u64 reserved_8; /* rax already available at 0x01f8 */
260 u64 rcx;
261 u64 rdx;
262 u64 rbx;
263 u64 reserved_9; /* rsp already available at 0x01d8 */
264 u64 rbp;
265 u64 rsi;
266 u64 rdi;
267 u64 r8;
268 u64 r9;
269 u64 r10;
270 u64 r11;
271 u64 r12;
272 u64 r13;
273 u64 r14;
274 u64 r15;
275 u8 reserved_10[16];
276 u64 sw_exit_code;
277 u64 sw_exit_info_1;
278 u64 sw_exit_info_2;
279 u64 sw_scratch;
280 u8 reserved_11[56];
281 u64 xcr0;
282 u8 valid_bitmap[16];
283 u64 x87_state_gpa;
284 } __packed;
285
286 struct ghcb {
287 struct vmcb_save_area save;
288 u8 reserved_save[2048 - sizeof(struct vmcb_save_area)];
289
290 u8 shared_buffer[2032];
291
292 u8 reserved_1[10];
293 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
294 u32 ghcb_usage;
295 } __packed;
296
297
298 #define EXPECTED_VMCB_SAVE_AREA_SIZE 1032
299 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 256
300 #define EXPECTED_GHCB_SIZE PAGE_SIZE
301
__unused_size_checks(void)302 static inline void __unused_size_checks(void)
303 {
304 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
305 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
306 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
307 }
308
309 struct vmcb {
310 struct vmcb_control_area control;
311 u8 reserved_control[1024 - sizeof(struct vmcb_control_area)];
312 struct vmcb_save_area save;
313 } __packed;
314
315 #define SVM_CPUID_FUNC 0x8000000a
316
317 #define SVM_VM_CR_SVM_DISABLE 4
318
319 #define SVM_SELECTOR_S_SHIFT 4
320 #define SVM_SELECTOR_DPL_SHIFT 5
321 #define SVM_SELECTOR_P_SHIFT 7
322 #define SVM_SELECTOR_AVL_SHIFT 8
323 #define SVM_SELECTOR_L_SHIFT 9
324 #define SVM_SELECTOR_DB_SHIFT 10
325 #define SVM_SELECTOR_G_SHIFT 11
326
327 #define SVM_SELECTOR_TYPE_MASK (0xf)
328 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
329 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
330 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
331 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
332 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
333 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
334 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
335
336 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
337 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
338 #define SVM_SELECTOR_CODE_MASK (1 << 3)
339
340 #define SVM_EVTINJ_VEC_MASK 0xff
341
342 #define SVM_EVTINJ_TYPE_SHIFT 8
343 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
344
345 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
346 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
347 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
348 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
349
350 #define SVM_EVTINJ_VALID (1 << 31)
351 #define SVM_EVTINJ_VALID_ERR (1 << 11)
352
353 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
354 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
355
356 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
357 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
358 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
359 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
360
361 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
362 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
363
364 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
365 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
366 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
367
368 #define SVM_EXITINFO_REG_MASK 0x0F
369
370 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
371
372 /* GHCB Accessor functions */
373
374 #define GHCB_BITMAP_IDX(field) \
375 (offsetof(struct vmcb_save_area, field) / sizeof(u64))
376
377 #define DEFINE_GHCB_ACCESSORS(field) \
378 static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
379 { \
380 return test_bit(GHCB_BITMAP_IDX(field), \
381 (unsigned long *)&ghcb->save.valid_bitmap); \
382 } \
383 \
384 static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
385 { \
386 __set_bit(GHCB_BITMAP_IDX(field), \
387 (unsigned long *)&ghcb->save.valid_bitmap); \
388 ghcb->save.field = value; \
389 }
390
391 DEFINE_GHCB_ACCESSORS(cpl)
392 DEFINE_GHCB_ACCESSORS(rip)
393 DEFINE_GHCB_ACCESSORS(rsp)
394 DEFINE_GHCB_ACCESSORS(rax)
395 DEFINE_GHCB_ACCESSORS(rcx)
396 DEFINE_GHCB_ACCESSORS(rdx)
397 DEFINE_GHCB_ACCESSORS(rbx)
398 DEFINE_GHCB_ACCESSORS(rbp)
399 DEFINE_GHCB_ACCESSORS(rsi)
400 DEFINE_GHCB_ACCESSORS(rdi)
401 DEFINE_GHCB_ACCESSORS(r8)
402 DEFINE_GHCB_ACCESSORS(r9)
403 DEFINE_GHCB_ACCESSORS(r10)
404 DEFINE_GHCB_ACCESSORS(r11)
405 DEFINE_GHCB_ACCESSORS(r12)
406 DEFINE_GHCB_ACCESSORS(r13)
407 DEFINE_GHCB_ACCESSORS(r14)
408 DEFINE_GHCB_ACCESSORS(r15)
409 DEFINE_GHCB_ACCESSORS(sw_exit_code)
410 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
411 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
412 DEFINE_GHCB_ACCESSORS(sw_scratch)
413 DEFINE_GHCB_ACCESSORS(xcr0)
414
415 #endif
416