1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/delay.h>
36 #include "cxgb4.h"
37 #include "t4_regs.h"
38 #include "t4_values.h"
39 #include "t4fw_api.h"
40 #include "t4fw_version.h"
41
42 /**
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
51 *
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
56 */
t4_wait_op_done_val(struct adapter * adapter,int reg,u32 mask,int polarity,int attempts,int delay,u32 * valp)57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
59 {
60 while (1) {
61 u32 val = t4_read_reg(adapter, reg);
62
63 if (!!(val & mask) == polarity) {
64 if (valp)
65 *valp = val;
66 return 0;
67 }
68 if (--attempts == 0)
69 return -EAGAIN;
70 if (delay)
71 udelay(delay);
72 }
73 }
74
t4_wait_op_done(struct adapter * adapter,int reg,u32 mask,int polarity,int attempts,int delay)75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
77 {
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
79 delay, NULL);
80 }
81
82 /**
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
88 *
89 * Sets a register field specified by the supplied mask to the
90 * given value.
91 */
t4_set_reg_field(struct adapter * adapter,unsigned int addr,u32 mask,u32 val)92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
93 u32 val)
94 {
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
96
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
99 }
100
101 /**
102 * t4_read_indirect - read indirectly addressed registers
103 * @adap: the adapter
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
109 *
110 * Reads registers that are accessed indirectly through an address/data
111 * register pair.
112 */
t4_read_indirect(struct adapter * adap,unsigned int addr_reg,unsigned int data_reg,u32 * vals,unsigned int nregs,unsigned int start_idx)113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
116 {
117 while (nregs--) {
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
120 start_idx++;
121 }
122 }
123
124 /**
125 * t4_write_indirect - write indirectly addressed registers
126 * @adap: the adapter
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
132 *
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
135 */
t4_write_indirect(struct adapter * adap,unsigned int addr_reg,unsigned int data_reg,const u32 * vals,unsigned int nregs,unsigned int start_idx)136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
139 {
140 while (nregs--) {
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
143 }
144 }
145
146 /*
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
151 */
t4_hw_pci_read_cfg4(struct adapter * adap,int reg,u32 * val)152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
153 {
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
155
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
157 req |= ENABLE_F;
158 else
159 req |= T6_ENABLE_F;
160
161 if (is_t4(adap->params.chip))
162 req |= LOCALCFG_F;
163
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
166
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
171 */
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
173 }
174
175 /*
176 * t4_report_fw_error - report firmware error
177 * @adap: the adapter
178 *
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
182 */
t4_report_fw_error(struct adapter * adap)183 static void t4_report_fw_error(struct adapter *adap)
184 {
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
194 };
195 u32 pcie_fw;
196
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F) {
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
201 adap->flags &= ~CXGB4_FW_OK;
202 }
203 }
204
205 /*
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
207 */
get_mbox_rpl(struct adapter * adap,__be64 * rpl,int nflit,u32 mbox_addr)208 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 u32 mbox_addr)
210 {
211 for ( ; nflit; nflit--, mbox_addr += 8)
212 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
213 }
214
215 /*
216 * Handle a FW assertion reported in a mailbox.
217 */
fw_asrt(struct adapter * adap,u32 mbox_addr)218 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
219 {
220 struct fw_debug_cmd asrt;
221
222 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
223 dev_alert(adap->pdev_dev,
224 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
225 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
226 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
227 }
228
229 /**
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
236 */
t4_record_mbox(struct adapter * adapter,const __be64 * cmd,unsigned int size,int access,int execute)237 static void t4_record_mbox(struct adapter *adapter,
238 const __be64 *cmd, unsigned int size,
239 int access, int execute)
240 {
241 struct mbox_cmd_log *log = adapter->mbox_log;
242 struct mbox_cmd *entry;
243 int i;
244
245 entry = mbox_cmd_log_entry(log, log->cursor++);
246 if (log->cursor == log->size)
247 log->cursor = 0;
248
249 for (i = 0; i < size / 8; i++)
250 entry->cmd[i] = be64_to_cpu(cmd[i]);
251 while (i < MBOX_LEN / 8)
252 entry->cmd[i++] = 0;
253 entry->timestamp = jiffies;
254 entry->seqno = log->seqno++;
255 entry->access = access;
256 entry->execute = execute;
257 }
258
259 /**
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
261 * @adap: the adapter
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
268 *
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
275 * otherwise we spin.
276 *
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
281 */
t4_wr_mbox_meat_timeout(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl,bool sleep_ok,int timeout)282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
283 int size, void *rpl, bool sleep_ok, int timeout)
284 {
285 static const int delay[] = {
286 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
287 };
288
289 struct mbox_list entry;
290 u16 access = 0;
291 u16 execute = 0;
292 u32 v;
293 u64 res;
294 int i, ms, delay_idx, ret;
295 const __be64 *p = cmd;
296 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
297 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
298 __be64 cmd_rpl[MBOX_LEN / 8];
299 u32 pcie_fw;
300
301 if ((size & 15) || size > MBOX_LEN)
302 return -EINVAL;
303
304 /*
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
307 */
308 if (adap->pdev->error_state != pci_channel_io_normal)
309 return -EIO;
310
311 /* If we have a negative timeout, that implies that we can't sleep. */
312 if (timeout < 0) {
313 sleep_ok = false;
314 timeout = -timeout;
315 }
316
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
320 * EBUSY] ...
321 */
322 spin_lock_bh(&adap->mbox_lock);
323 list_add_tail(&entry.list, &adap->mlist.list);
324 spin_unlock_bh(&adap->mbox_lock);
325
326 delay_idx = 0;
327 ms = delay[0];
328
329 for (i = 0; ; i += ms) {
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rarely
333 * contend on access to the mailbox ...
334 */
335 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
336 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
337 spin_lock_bh(&adap->mbox_lock);
338 list_del(&entry.list);
339 spin_unlock_bh(&adap->mbox_lock);
340 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
341 t4_record_mbox(adap, cmd, size, access, ret);
342 return ret;
343 }
344
345 /* If we're at the head, break out and start the mailbox
346 * protocol.
347 */
348 if (list_first_entry(&adap->mlist.list, struct mbox_list,
349 list) == &entry)
350 break;
351
352 /* Delay for a bit before checking again ... */
353 if (sleep_ok) {
354 ms = delay[delay_idx]; /* last element may repeat */
355 if (delay_idx < ARRAY_SIZE(delay) - 1)
356 delay_idx++;
357 msleep(ms);
358 } else {
359 mdelay(ms);
360 }
361 }
362
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
365 */
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
367 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
368 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
369 if (v != MBOX_OWNER_DRV) {
370 spin_lock_bh(&adap->mbox_lock);
371 list_del(&entry.list);
372 spin_unlock_bh(&adap->mbox_lock);
373 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
374 t4_record_mbox(adap, cmd, size, access, ret);
375 return ret;
376 }
377
378 /* Copy in the new mailbox command and send it on its way ... */
379 t4_record_mbox(adap, cmd, size, access, 0);
380 for (i = 0; i < size; i += 8)
381 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
382
383 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
384 t4_read_reg(adap, ctl_reg); /* flush write */
385
386 delay_idx = 0;
387 ms = delay[0];
388
389 for (i = 0;
390 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
391 i < timeout;
392 i += ms) {
393 if (sleep_ok) {
394 ms = delay[delay_idx]; /* last element may repeat */
395 if (delay_idx < ARRAY_SIZE(delay) - 1)
396 delay_idx++;
397 msleep(ms);
398 } else
399 mdelay(ms);
400
401 v = t4_read_reg(adap, ctl_reg);
402 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
403 if (!(v & MBMSGVALID_F)) {
404 t4_write_reg(adap, ctl_reg, 0);
405 continue;
406 }
407
408 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
409 res = be64_to_cpu(cmd_rpl[0]);
410
411 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
412 fw_asrt(adap, data_reg);
413 res = FW_CMD_RETVAL_V(EIO);
414 } else if (rpl) {
415 memcpy(rpl, cmd_rpl, size);
416 }
417
418 t4_write_reg(adap, ctl_reg, 0);
419
420 execute = i + ms;
421 t4_record_mbox(adap, cmd_rpl,
422 MBOX_LEN, access, execute);
423 spin_lock_bh(&adap->mbox_lock);
424 list_del(&entry.list);
425 spin_unlock_bh(&adap->mbox_lock);
426 return -FW_CMD_RETVAL_G((int)res);
427 }
428 }
429
430 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
431 t4_record_mbox(adap, cmd, size, access, ret);
432 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
433 *(const u8 *)cmd, mbox);
434 t4_report_fw_error(adap);
435 spin_lock_bh(&adap->mbox_lock);
436 list_del(&entry.list);
437 spin_unlock_bh(&adap->mbox_lock);
438 t4_fatal_err(adap);
439 return ret;
440 }
441
t4_wr_mbox_meat(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl,bool sleep_ok)442 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
443 void *rpl, bool sleep_ok)
444 {
445 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
446 FW_CMD_MAX_TIMEOUT);
447 }
448
t4_edc_err_read(struct adapter * adap,int idx)449 static int t4_edc_err_read(struct adapter *adap, int idx)
450 {
451 u32 edc_ecc_err_addr_reg;
452 u32 rdata_reg;
453
454 if (is_t4(adap->params.chip)) {
455 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
456 return 0;
457 }
458 if (idx != 0 && idx != 1) {
459 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
460 return 0;
461 }
462
463 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
464 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
465
466 CH_WARN(adap,
467 "edc%d err addr 0x%x: 0x%x.\n",
468 idx, edc_ecc_err_addr_reg,
469 t4_read_reg(adap, edc_ecc_err_addr_reg));
470 CH_WARN(adap,
471 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
472 rdata_reg,
473 (unsigned long long)t4_read_reg64(adap, rdata_reg),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
480 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
481 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
482
483 return 0;
484 }
485
486 /**
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
488 * @adap: the adapter
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
494 *
495 * Get the configured memory window's relative offset, base, and size.
496 */
t4_memory_rw_init(struct adapter * adap,int win,int mtype,u32 * mem_off,u32 * mem_base,u32 * mem_aperture)497 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
498 u32 *mem_base, u32 *mem_aperture)
499 {
500 u32 edc_size, mc_size, mem_reg;
501
502 /* Offset into the region of memory which is being accessed
503 * MEM_EDC0 = 0
504 * MEM_EDC1 = 1
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
507 * MEM_HMA = 4
508 */
509 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
510 if (mtype == MEM_HMA) {
511 *mem_off = 2 * (edc_size * 1024 * 1024);
512 } else if (mtype != MEM_MC1) {
513 *mem_off = (mtype * (edc_size * 1024 * 1024));
514 } else {
515 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
516 MA_EXT_MEMORY0_BAR_A));
517 *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
518 }
519
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
527 */
528 mem_reg = t4_read_reg(adap,
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
530 win));
531 /* a dead adapter will return 0xffffffff for PIO reads */
532 if (mem_reg == 0xffffffff)
533 return -ENXIO;
534
535 *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
536 *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
537 if (is_t4(adap->params.chip))
538 *mem_base -= adap->t4_bar0;
539
540 return 0;
541 }
542
543 /**
544 * t4_memory_update_win - Move memory window to specified address.
545 * @adap: the adapter
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
548 *
549 * Move memory window to specified address.
550 */
t4_memory_update_win(struct adapter * adap,int win,u32 addr)551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
552 {
553 t4_write_reg(adap,
554 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
555 addr);
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
558 */
559 t4_read_reg(adap,
560 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
561 }
562
563 /**
564 * t4_memory_rw_residual - Read/Write residual data.
565 * @adap: the adapter
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
570 *
571 * Read/Write residual data less than 32-bits.
572 */
t4_memory_rw_residual(struct adapter * adap,u32 off,u32 addr,u8 * buf,int dir)573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
574 int dir)
575 {
576 union {
577 u32 word;
578 char byte[4];
579 } last;
580 unsigned char *bp;
581 int i;
582
583 if (dir == T4_MEMORY_READ) {
584 last.word = le32_to_cpu((__force __le32)
585 t4_read_reg(adap, addr));
586 for (bp = (unsigned char *)buf, i = off; i < 4; i++)
587 bp[i] = last.byte[i];
588 } else {
589 last.word = *buf;
590 for (i = off; i < 4; i++)
591 last.byte[i] = 0;
592 t4_write_reg(adap, addr,
593 (__force u32)cpu_to_le32(last.word));
594 }
595 }
596
597 /**
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
599 * @adap: the adapter
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
606 *
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boundaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
613 */
t4_memory_rw(struct adapter * adap,int win,int mtype,u32 addr,u32 len,void * hbuf,int dir)614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
615 u32 len, void *hbuf, int dir)
616 {
617 u32 pos, offset, resid, memoffset;
618 u32 win_pf, mem_aperture, mem_base;
619 u32 *buf;
620 int ret;
621
622 /* Argument sanity checks ...
623 */
624 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
625 return -EINVAL;
626 buf = (u32 *)hbuf;
627
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
632 */
633 resid = len & 0x3;
634 len -= resid;
635
636 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
637 &mem_aperture);
638 if (ret)
639 return ret;
640
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
642 addr = addr + memoffset;
643
644 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
645
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
647 * that Window.
648 */
649 pos = addr & ~(mem_aperture - 1);
650 offset = addr - pos;
651
652 /* Set up initial PCI-E Memory Window to cover the start of our
653 * transfer.
654 */
655 t4_memory_update_win(adap, win, pos | win_pf);
656
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
659 *
660 * A note on Endianness issues:
661 *
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
666 *
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
669 *
670 * Then a read of the adapter memory via the PCI-E Memory Window
671 * will yield:
672 *
673 * x = readl(i)
674 * 31 0
675 * [ b3 | b2 | b1 | b0 ]
676 *
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
679 *
680 * ( ..., b0, b1, b2, b3, ... )
681 *
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
684 *
685 * ( ..., b3, b2, b1, b0, ... )
686 *
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
689 * swizzels.
690 */
691 while (len > 0) {
692 if (dir == T4_MEMORY_READ)
693 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
694 mem_base + offset));
695 else
696 t4_write_reg(adap, mem_base + offset,
697 (__force u32)cpu_to_le32(*buf++));
698 offset += sizeof(__be32);
699 len -= sizeof(__be32);
700
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
705 * transfer below ...
706 */
707 if (offset == mem_aperture) {
708 pos += mem_aperture;
709 offset = 0;
710 t4_memory_update_win(adap, win, pos | win_pf);
711 }
712 }
713
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
718 */
719 if (resid)
720 t4_memory_rw_residual(adap, resid, mem_base + offset,
721 (u8 *)buf, dir);
722
723 return 0;
724 }
725
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
730 */
t4_read_pcie_cfg4(struct adapter * adap,int reg)731 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
732 {
733 u32 val, ldst_addrspace;
734
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
737 */
738 struct fw_ldst_cmd ldst_cmd;
739 int ret;
740
741 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
742 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
743 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
744 FW_CMD_REQUEST_F |
745 FW_CMD_READ_F |
746 ldst_addrspace);
747 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
748 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
749 ldst_cmd.u.pcie.ctrl_to_fn =
750 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
751 ldst_cmd.u.pcie.r = reg;
752
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
755 */
756 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
757 &ldst_cmd);
758 if (ret == 0)
759 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
760 else
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
763 */
764 t4_hw_pci_read_cfg4(adap, reg, &val);
765 return val;
766 }
767
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
770 * right now
771 */
t4_get_window(struct adapter * adap,u32 pci_base,u64 pci_mask,u32 memwin_base)772 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
773 u32 memwin_base)
774 {
775 u32 ret;
776
777 if (is_t4(adap->params.chip)) {
778 u32 bar0;
779
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
788 */
789 bar0 = t4_read_pcie_cfg4(adap, pci_base);
790 bar0 &= pci_mask;
791 adap->t4_bar0 = bar0;
792
793 ret = bar0 + memwin_base;
794 } else {
795 /* For T5, only relative offset inside the PCIe BAR is passed */
796 ret = memwin_base;
797 }
798 return ret;
799 }
800
801 /* Get the default utility window (win0) used by everyone */
t4_get_util_window(struct adapter * adap)802 u32 t4_get_util_window(struct adapter *adap)
803 {
804 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
805 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
806 }
807
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
811 */
t4_setup_memwin(struct adapter * adap,u32 memwin_base,u32 window)812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
813 {
814 t4_write_reg(adap,
815 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
816 memwin_base | BIR_V(0) |
817 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
818 t4_read_reg(adap,
819 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
820 }
821
822 /**
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
825 *
826 * Returns the size of the chip's BAR0 register space.
827 */
t4_get_regs_len(struct adapter * adapter)828 unsigned int t4_get_regs_len(struct adapter *adapter)
829 {
830 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
831
832 switch (chip_version) {
833 case CHELSIO_T4:
834 return T4_REGMAP_SIZE;
835
836 case CHELSIO_T5:
837 case CHELSIO_T6:
838 return T5_REGMAP_SIZE;
839 }
840
841 dev_err(adapter->pdev_dev,
842 "Unsupported chip version %d\n", chip_version);
843 return 0;
844 }
845
846 /**
847 * t4_get_regs - read chip registers into provided buffer
848 * @adap: the adapter
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
851 *
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
855 */
t4_get_regs(struct adapter * adap,void * buf,size_t buf_size)856 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
857 {
858 static const unsigned int t4_reg_ranges[] = {
859 0x1008, 0x1108,
860 0x1180, 0x1184,
861 0x1190, 0x1194,
862 0x11a0, 0x11a4,
863 0x11b0, 0x11b4,
864 0x11fc, 0x123c,
865 0x1300, 0x173c,
866 0x1800, 0x18fc,
867 0x3000, 0x30d8,
868 0x30e0, 0x30e4,
869 0x30ec, 0x5910,
870 0x5920, 0x5924,
871 0x5960, 0x5960,
872 0x5968, 0x5968,
873 0x5970, 0x5970,
874 0x5978, 0x5978,
875 0x5980, 0x5980,
876 0x5988, 0x5988,
877 0x5990, 0x5990,
878 0x5998, 0x5998,
879 0x59a0, 0x59d4,
880 0x5a00, 0x5ae0,
881 0x5ae8, 0x5ae8,
882 0x5af0, 0x5af0,
883 0x5af8, 0x5af8,
884 0x6000, 0x6098,
885 0x6100, 0x6150,
886 0x6200, 0x6208,
887 0x6240, 0x6248,
888 0x6280, 0x62b0,
889 0x62c0, 0x6338,
890 0x6370, 0x638c,
891 0x6400, 0x643c,
892 0x6500, 0x6524,
893 0x6a00, 0x6a04,
894 0x6a14, 0x6a38,
895 0x6a60, 0x6a70,
896 0x6a78, 0x6a78,
897 0x6b00, 0x6b0c,
898 0x6b1c, 0x6b84,
899 0x6bf0, 0x6bf8,
900 0x6c00, 0x6c0c,
901 0x6c1c, 0x6c84,
902 0x6cf0, 0x6cf8,
903 0x6d00, 0x6d0c,
904 0x6d1c, 0x6d84,
905 0x6df0, 0x6df8,
906 0x6e00, 0x6e0c,
907 0x6e1c, 0x6e84,
908 0x6ef0, 0x6ef8,
909 0x6f00, 0x6f0c,
910 0x6f1c, 0x6f84,
911 0x6ff0, 0x6ff8,
912 0x7000, 0x700c,
913 0x701c, 0x7084,
914 0x70f0, 0x70f8,
915 0x7100, 0x710c,
916 0x711c, 0x7184,
917 0x71f0, 0x71f8,
918 0x7200, 0x720c,
919 0x721c, 0x7284,
920 0x72f0, 0x72f8,
921 0x7300, 0x730c,
922 0x731c, 0x7384,
923 0x73f0, 0x73f8,
924 0x7400, 0x7450,
925 0x7500, 0x7530,
926 0x7600, 0x760c,
927 0x7614, 0x761c,
928 0x7680, 0x76cc,
929 0x7700, 0x7798,
930 0x77c0, 0x77fc,
931 0x7900, 0x79fc,
932 0x7b00, 0x7b58,
933 0x7b60, 0x7b84,
934 0x7b8c, 0x7c38,
935 0x7d00, 0x7d38,
936 0x7d40, 0x7d80,
937 0x7d8c, 0x7ddc,
938 0x7de4, 0x7e04,
939 0x7e10, 0x7e1c,
940 0x7e24, 0x7e38,
941 0x7e40, 0x7e44,
942 0x7e4c, 0x7e78,
943 0x7e80, 0x7ea4,
944 0x7eac, 0x7edc,
945 0x7ee8, 0x7efc,
946 0x8dc0, 0x8e04,
947 0x8e10, 0x8e1c,
948 0x8e30, 0x8e78,
949 0x8ea0, 0x8eb8,
950 0x8ec0, 0x8f6c,
951 0x8fc0, 0x9008,
952 0x9010, 0x9058,
953 0x9060, 0x9060,
954 0x9068, 0x9074,
955 0x90fc, 0x90fc,
956 0x9400, 0x9408,
957 0x9410, 0x9458,
958 0x9600, 0x9600,
959 0x9608, 0x9638,
960 0x9640, 0x96bc,
961 0x9800, 0x9808,
962 0x9820, 0x983c,
963 0x9850, 0x9864,
964 0x9c00, 0x9c6c,
965 0x9c80, 0x9cec,
966 0x9d00, 0x9d6c,
967 0x9d80, 0x9dec,
968 0x9e00, 0x9e6c,
969 0x9e80, 0x9eec,
970 0x9f00, 0x9f6c,
971 0x9f80, 0x9fec,
972 0xd004, 0xd004,
973 0xd010, 0xd03c,
974 0xdfc0, 0xdfe0,
975 0xe000, 0xea7c,
976 0xf000, 0x11110,
977 0x11118, 0x11190,
978 0x19040, 0x1906c,
979 0x19078, 0x19080,
980 0x1908c, 0x190e4,
981 0x190f0, 0x190f8,
982 0x19100, 0x19110,
983 0x19120, 0x19124,
984 0x19150, 0x19194,
985 0x1919c, 0x191b0,
986 0x191d0, 0x191e8,
987 0x19238, 0x1924c,
988 0x193f8, 0x1943c,
989 0x1944c, 0x19474,
990 0x19490, 0x194e0,
991 0x194f0, 0x194f8,
992 0x19800, 0x19c08,
993 0x19c10, 0x19c90,
994 0x19ca0, 0x19ce4,
995 0x19cf0, 0x19d40,
996 0x19d50, 0x19d94,
997 0x19da0, 0x19de8,
998 0x19df0, 0x19e40,
999 0x19e50, 0x19e90,
1000 0x19ea0, 0x19f4c,
1001 0x1a000, 0x1a004,
1002 0x1a010, 0x1a06c,
1003 0x1a0b0, 0x1a0e4,
1004 0x1a0ec, 0x1a0f4,
1005 0x1a100, 0x1a108,
1006 0x1a114, 0x1a120,
1007 0x1a128, 0x1a130,
1008 0x1a138, 0x1a138,
1009 0x1a190, 0x1a1c4,
1010 0x1a1fc, 0x1a1fc,
1011 0x1e040, 0x1e04c,
1012 0x1e284, 0x1e28c,
1013 0x1e2c0, 0x1e2c0,
1014 0x1e2e0, 0x1e2e0,
1015 0x1e300, 0x1e384,
1016 0x1e3c0, 0x1e3c8,
1017 0x1e440, 0x1e44c,
1018 0x1e684, 0x1e68c,
1019 0x1e6c0, 0x1e6c0,
1020 0x1e6e0, 0x1e6e0,
1021 0x1e700, 0x1e784,
1022 0x1e7c0, 0x1e7c8,
1023 0x1e840, 0x1e84c,
1024 0x1ea84, 0x1ea8c,
1025 0x1eac0, 0x1eac0,
1026 0x1eae0, 0x1eae0,
1027 0x1eb00, 0x1eb84,
1028 0x1ebc0, 0x1ebc8,
1029 0x1ec40, 0x1ec4c,
1030 0x1ee84, 0x1ee8c,
1031 0x1eec0, 0x1eec0,
1032 0x1eee0, 0x1eee0,
1033 0x1ef00, 0x1ef84,
1034 0x1efc0, 0x1efc8,
1035 0x1f040, 0x1f04c,
1036 0x1f284, 0x1f28c,
1037 0x1f2c0, 0x1f2c0,
1038 0x1f2e0, 0x1f2e0,
1039 0x1f300, 0x1f384,
1040 0x1f3c0, 0x1f3c8,
1041 0x1f440, 0x1f44c,
1042 0x1f684, 0x1f68c,
1043 0x1f6c0, 0x1f6c0,
1044 0x1f6e0, 0x1f6e0,
1045 0x1f700, 0x1f784,
1046 0x1f7c0, 0x1f7c8,
1047 0x1f840, 0x1f84c,
1048 0x1fa84, 0x1fa8c,
1049 0x1fac0, 0x1fac0,
1050 0x1fae0, 0x1fae0,
1051 0x1fb00, 0x1fb84,
1052 0x1fbc0, 0x1fbc8,
1053 0x1fc40, 0x1fc4c,
1054 0x1fe84, 0x1fe8c,
1055 0x1fec0, 0x1fec0,
1056 0x1fee0, 0x1fee0,
1057 0x1ff00, 0x1ff84,
1058 0x1ffc0, 0x1ffc8,
1059 0x20000, 0x2002c,
1060 0x20100, 0x2013c,
1061 0x20190, 0x201a0,
1062 0x201a8, 0x201b8,
1063 0x201c4, 0x201c8,
1064 0x20200, 0x20318,
1065 0x20400, 0x204b4,
1066 0x204c0, 0x20528,
1067 0x20540, 0x20614,
1068 0x21000, 0x21040,
1069 0x2104c, 0x21060,
1070 0x210c0, 0x210ec,
1071 0x21200, 0x21268,
1072 0x21270, 0x21284,
1073 0x212fc, 0x21388,
1074 0x21400, 0x21404,
1075 0x21500, 0x21500,
1076 0x21510, 0x21518,
1077 0x2152c, 0x21530,
1078 0x2153c, 0x2153c,
1079 0x21550, 0x21554,
1080 0x21600, 0x21600,
1081 0x21608, 0x2161c,
1082 0x21624, 0x21628,
1083 0x21630, 0x21634,
1084 0x2163c, 0x2163c,
1085 0x21700, 0x2171c,
1086 0x21780, 0x2178c,
1087 0x21800, 0x21818,
1088 0x21820, 0x21828,
1089 0x21830, 0x21848,
1090 0x21850, 0x21854,
1091 0x21860, 0x21868,
1092 0x21870, 0x21870,
1093 0x21878, 0x21898,
1094 0x218a0, 0x218a8,
1095 0x218b0, 0x218c8,
1096 0x218d0, 0x218d4,
1097 0x218e0, 0x218e8,
1098 0x218f0, 0x218f0,
1099 0x218f8, 0x21a18,
1100 0x21a20, 0x21a28,
1101 0x21a30, 0x21a48,
1102 0x21a50, 0x21a54,
1103 0x21a60, 0x21a68,
1104 0x21a70, 0x21a70,
1105 0x21a78, 0x21a98,
1106 0x21aa0, 0x21aa8,
1107 0x21ab0, 0x21ac8,
1108 0x21ad0, 0x21ad4,
1109 0x21ae0, 0x21ae8,
1110 0x21af0, 0x21af0,
1111 0x21af8, 0x21c18,
1112 0x21c20, 0x21c20,
1113 0x21c28, 0x21c30,
1114 0x21c38, 0x21c38,
1115 0x21c80, 0x21c98,
1116 0x21ca0, 0x21ca8,
1117 0x21cb0, 0x21cc8,
1118 0x21cd0, 0x21cd4,
1119 0x21ce0, 0x21ce8,
1120 0x21cf0, 0x21cf0,
1121 0x21cf8, 0x21d7c,
1122 0x21e00, 0x21e04,
1123 0x22000, 0x2202c,
1124 0x22100, 0x2213c,
1125 0x22190, 0x221a0,
1126 0x221a8, 0x221b8,
1127 0x221c4, 0x221c8,
1128 0x22200, 0x22318,
1129 0x22400, 0x224b4,
1130 0x224c0, 0x22528,
1131 0x22540, 0x22614,
1132 0x23000, 0x23040,
1133 0x2304c, 0x23060,
1134 0x230c0, 0x230ec,
1135 0x23200, 0x23268,
1136 0x23270, 0x23284,
1137 0x232fc, 0x23388,
1138 0x23400, 0x23404,
1139 0x23500, 0x23500,
1140 0x23510, 0x23518,
1141 0x2352c, 0x23530,
1142 0x2353c, 0x2353c,
1143 0x23550, 0x23554,
1144 0x23600, 0x23600,
1145 0x23608, 0x2361c,
1146 0x23624, 0x23628,
1147 0x23630, 0x23634,
1148 0x2363c, 0x2363c,
1149 0x23700, 0x2371c,
1150 0x23780, 0x2378c,
1151 0x23800, 0x23818,
1152 0x23820, 0x23828,
1153 0x23830, 0x23848,
1154 0x23850, 0x23854,
1155 0x23860, 0x23868,
1156 0x23870, 0x23870,
1157 0x23878, 0x23898,
1158 0x238a0, 0x238a8,
1159 0x238b0, 0x238c8,
1160 0x238d0, 0x238d4,
1161 0x238e0, 0x238e8,
1162 0x238f0, 0x238f0,
1163 0x238f8, 0x23a18,
1164 0x23a20, 0x23a28,
1165 0x23a30, 0x23a48,
1166 0x23a50, 0x23a54,
1167 0x23a60, 0x23a68,
1168 0x23a70, 0x23a70,
1169 0x23a78, 0x23a98,
1170 0x23aa0, 0x23aa8,
1171 0x23ab0, 0x23ac8,
1172 0x23ad0, 0x23ad4,
1173 0x23ae0, 0x23ae8,
1174 0x23af0, 0x23af0,
1175 0x23af8, 0x23c18,
1176 0x23c20, 0x23c20,
1177 0x23c28, 0x23c30,
1178 0x23c38, 0x23c38,
1179 0x23c80, 0x23c98,
1180 0x23ca0, 0x23ca8,
1181 0x23cb0, 0x23cc8,
1182 0x23cd0, 0x23cd4,
1183 0x23ce0, 0x23ce8,
1184 0x23cf0, 0x23cf0,
1185 0x23cf8, 0x23d7c,
1186 0x23e00, 0x23e04,
1187 0x24000, 0x2402c,
1188 0x24100, 0x2413c,
1189 0x24190, 0x241a0,
1190 0x241a8, 0x241b8,
1191 0x241c4, 0x241c8,
1192 0x24200, 0x24318,
1193 0x24400, 0x244b4,
1194 0x244c0, 0x24528,
1195 0x24540, 0x24614,
1196 0x25000, 0x25040,
1197 0x2504c, 0x25060,
1198 0x250c0, 0x250ec,
1199 0x25200, 0x25268,
1200 0x25270, 0x25284,
1201 0x252fc, 0x25388,
1202 0x25400, 0x25404,
1203 0x25500, 0x25500,
1204 0x25510, 0x25518,
1205 0x2552c, 0x25530,
1206 0x2553c, 0x2553c,
1207 0x25550, 0x25554,
1208 0x25600, 0x25600,
1209 0x25608, 0x2561c,
1210 0x25624, 0x25628,
1211 0x25630, 0x25634,
1212 0x2563c, 0x2563c,
1213 0x25700, 0x2571c,
1214 0x25780, 0x2578c,
1215 0x25800, 0x25818,
1216 0x25820, 0x25828,
1217 0x25830, 0x25848,
1218 0x25850, 0x25854,
1219 0x25860, 0x25868,
1220 0x25870, 0x25870,
1221 0x25878, 0x25898,
1222 0x258a0, 0x258a8,
1223 0x258b0, 0x258c8,
1224 0x258d0, 0x258d4,
1225 0x258e0, 0x258e8,
1226 0x258f0, 0x258f0,
1227 0x258f8, 0x25a18,
1228 0x25a20, 0x25a28,
1229 0x25a30, 0x25a48,
1230 0x25a50, 0x25a54,
1231 0x25a60, 0x25a68,
1232 0x25a70, 0x25a70,
1233 0x25a78, 0x25a98,
1234 0x25aa0, 0x25aa8,
1235 0x25ab0, 0x25ac8,
1236 0x25ad0, 0x25ad4,
1237 0x25ae0, 0x25ae8,
1238 0x25af0, 0x25af0,
1239 0x25af8, 0x25c18,
1240 0x25c20, 0x25c20,
1241 0x25c28, 0x25c30,
1242 0x25c38, 0x25c38,
1243 0x25c80, 0x25c98,
1244 0x25ca0, 0x25ca8,
1245 0x25cb0, 0x25cc8,
1246 0x25cd0, 0x25cd4,
1247 0x25ce0, 0x25ce8,
1248 0x25cf0, 0x25cf0,
1249 0x25cf8, 0x25d7c,
1250 0x25e00, 0x25e04,
1251 0x26000, 0x2602c,
1252 0x26100, 0x2613c,
1253 0x26190, 0x261a0,
1254 0x261a8, 0x261b8,
1255 0x261c4, 0x261c8,
1256 0x26200, 0x26318,
1257 0x26400, 0x264b4,
1258 0x264c0, 0x26528,
1259 0x26540, 0x26614,
1260 0x27000, 0x27040,
1261 0x2704c, 0x27060,
1262 0x270c0, 0x270ec,
1263 0x27200, 0x27268,
1264 0x27270, 0x27284,
1265 0x272fc, 0x27388,
1266 0x27400, 0x27404,
1267 0x27500, 0x27500,
1268 0x27510, 0x27518,
1269 0x2752c, 0x27530,
1270 0x2753c, 0x2753c,
1271 0x27550, 0x27554,
1272 0x27600, 0x27600,
1273 0x27608, 0x2761c,
1274 0x27624, 0x27628,
1275 0x27630, 0x27634,
1276 0x2763c, 0x2763c,
1277 0x27700, 0x2771c,
1278 0x27780, 0x2778c,
1279 0x27800, 0x27818,
1280 0x27820, 0x27828,
1281 0x27830, 0x27848,
1282 0x27850, 0x27854,
1283 0x27860, 0x27868,
1284 0x27870, 0x27870,
1285 0x27878, 0x27898,
1286 0x278a0, 0x278a8,
1287 0x278b0, 0x278c8,
1288 0x278d0, 0x278d4,
1289 0x278e0, 0x278e8,
1290 0x278f0, 0x278f0,
1291 0x278f8, 0x27a18,
1292 0x27a20, 0x27a28,
1293 0x27a30, 0x27a48,
1294 0x27a50, 0x27a54,
1295 0x27a60, 0x27a68,
1296 0x27a70, 0x27a70,
1297 0x27a78, 0x27a98,
1298 0x27aa0, 0x27aa8,
1299 0x27ab0, 0x27ac8,
1300 0x27ad0, 0x27ad4,
1301 0x27ae0, 0x27ae8,
1302 0x27af0, 0x27af0,
1303 0x27af8, 0x27c18,
1304 0x27c20, 0x27c20,
1305 0x27c28, 0x27c30,
1306 0x27c38, 0x27c38,
1307 0x27c80, 0x27c98,
1308 0x27ca0, 0x27ca8,
1309 0x27cb0, 0x27cc8,
1310 0x27cd0, 0x27cd4,
1311 0x27ce0, 0x27ce8,
1312 0x27cf0, 0x27cf0,
1313 0x27cf8, 0x27d7c,
1314 0x27e00, 0x27e04,
1315 };
1316
1317 static const unsigned int t5_reg_ranges[] = {
1318 0x1008, 0x10c0,
1319 0x10cc, 0x10f8,
1320 0x1100, 0x1100,
1321 0x110c, 0x1148,
1322 0x1180, 0x1184,
1323 0x1190, 0x1194,
1324 0x11a0, 0x11a4,
1325 0x11b0, 0x11b4,
1326 0x11fc, 0x123c,
1327 0x1280, 0x173c,
1328 0x1800, 0x18fc,
1329 0x3000, 0x3028,
1330 0x3060, 0x30b0,
1331 0x30b8, 0x30d8,
1332 0x30e0, 0x30fc,
1333 0x3140, 0x357c,
1334 0x35a8, 0x35cc,
1335 0x35ec, 0x35ec,
1336 0x3600, 0x5624,
1337 0x56cc, 0x56ec,
1338 0x56f4, 0x5720,
1339 0x5728, 0x575c,
1340 0x580c, 0x5814,
1341 0x5890, 0x589c,
1342 0x58a4, 0x58ac,
1343 0x58b8, 0x58bc,
1344 0x5940, 0x59c8,
1345 0x59d0, 0x59dc,
1346 0x59fc, 0x5a18,
1347 0x5a60, 0x5a70,
1348 0x5a80, 0x5a9c,
1349 0x5b94, 0x5bfc,
1350 0x6000, 0x6020,
1351 0x6028, 0x6040,
1352 0x6058, 0x609c,
1353 0x60a8, 0x614c,
1354 0x7700, 0x7798,
1355 0x77c0, 0x78fc,
1356 0x7b00, 0x7b58,
1357 0x7b60, 0x7b84,
1358 0x7b8c, 0x7c54,
1359 0x7d00, 0x7d38,
1360 0x7d40, 0x7d80,
1361 0x7d8c, 0x7ddc,
1362 0x7de4, 0x7e04,
1363 0x7e10, 0x7e1c,
1364 0x7e24, 0x7e38,
1365 0x7e40, 0x7e44,
1366 0x7e4c, 0x7e78,
1367 0x7e80, 0x7edc,
1368 0x7ee8, 0x7efc,
1369 0x8dc0, 0x8de0,
1370 0x8df8, 0x8e04,
1371 0x8e10, 0x8e84,
1372 0x8ea0, 0x8f84,
1373 0x8fc0, 0x9058,
1374 0x9060, 0x9060,
1375 0x9068, 0x90f8,
1376 0x9400, 0x9408,
1377 0x9410, 0x9470,
1378 0x9600, 0x9600,
1379 0x9608, 0x9638,
1380 0x9640, 0x96f4,
1381 0x9800, 0x9808,
1382 0x9810, 0x9864,
1383 0x9c00, 0x9c6c,
1384 0x9c80, 0x9cec,
1385 0x9d00, 0x9d6c,
1386 0x9d80, 0x9dec,
1387 0x9e00, 0x9e6c,
1388 0x9e80, 0x9eec,
1389 0x9f00, 0x9f6c,
1390 0x9f80, 0xa020,
1391 0xd000, 0xd004,
1392 0xd010, 0xd03c,
1393 0xdfc0, 0xdfe0,
1394 0xe000, 0x1106c,
1395 0x11074, 0x11088,
1396 0x1109c, 0x1117c,
1397 0x11190, 0x11204,
1398 0x19040, 0x1906c,
1399 0x19078, 0x19080,
1400 0x1908c, 0x190e8,
1401 0x190f0, 0x190f8,
1402 0x19100, 0x19110,
1403 0x19120, 0x19124,
1404 0x19150, 0x19194,
1405 0x1919c, 0x191b0,
1406 0x191d0, 0x191e8,
1407 0x19238, 0x19290,
1408 0x193f8, 0x19428,
1409 0x19430, 0x19444,
1410 0x1944c, 0x1946c,
1411 0x19474, 0x19474,
1412 0x19490, 0x194cc,
1413 0x194f0, 0x194f8,
1414 0x19c00, 0x19c08,
1415 0x19c10, 0x19c60,
1416 0x19c94, 0x19ce4,
1417 0x19cf0, 0x19d40,
1418 0x19d50, 0x19d94,
1419 0x19da0, 0x19de8,
1420 0x19df0, 0x19e10,
1421 0x19e50, 0x19e90,
1422 0x19ea0, 0x19f24,
1423 0x19f34, 0x19f34,
1424 0x19f40, 0x19f50,
1425 0x19f90, 0x19fb4,
1426 0x19fc4, 0x19fe4,
1427 0x1a000, 0x1a004,
1428 0x1a010, 0x1a06c,
1429 0x1a0b0, 0x1a0e4,
1430 0x1a0ec, 0x1a0f8,
1431 0x1a100, 0x1a108,
1432 0x1a114, 0x1a130,
1433 0x1a138, 0x1a1c4,
1434 0x1a1fc, 0x1a1fc,
1435 0x1e008, 0x1e00c,
1436 0x1e040, 0x1e044,
1437 0x1e04c, 0x1e04c,
1438 0x1e284, 0x1e290,
1439 0x1e2c0, 0x1e2c0,
1440 0x1e2e0, 0x1e2e0,
1441 0x1e300, 0x1e384,
1442 0x1e3c0, 0x1e3c8,
1443 0x1e408, 0x1e40c,
1444 0x1e440, 0x1e444,
1445 0x1e44c, 0x1e44c,
1446 0x1e684, 0x1e690,
1447 0x1e6c0, 0x1e6c0,
1448 0x1e6e0, 0x1e6e0,
1449 0x1e700, 0x1e784,
1450 0x1e7c0, 0x1e7c8,
1451 0x1e808, 0x1e80c,
1452 0x1e840, 0x1e844,
1453 0x1e84c, 0x1e84c,
1454 0x1ea84, 0x1ea90,
1455 0x1eac0, 0x1eac0,
1456 0x1eae0, 0x1eae0,
1457 0x1eb00, 0x1eb84,
1458 0x1ebc0, 0x1ebc8,
1459 0x1ec08, 0x1ec0c,
1460 0x1ec40, 0x1ec44,
1461 0x1ec4c, 0x1ec4c,
1462 0x1ee84, 0x1ee90,
1463 0x1eec0, 0x1eec0,
1464 0x1eee0, 0x1eee0,
1465 0x1ef00, 0x1ef84,
1466 0x1efc0, 0x1efc8,
1467 0x1f008, 0x1f00c,
1468 0x1f040, 0x1f044,
1469 0x1f04c, 0x1f04c,
1470 0x1f284, 0x1f290,
1471 0x1f2c0, 0x1f2c0,
1472 0x1f2e0, 0x1f2e0,
1473 0x1f300, 0x1f384,
1474 0x1f3c0, 0x1f3c8,
1475 0x1f408, 0x1f40c,
1476 0x1f440, 0x1f444,
1477 0x1f44c, 0x1f44c,
1478 0x1f684, 0x1f690,
1479 0x1f6c0, 0x1f6c0,
1480 0x1f6e0, 0x1f6e0,
1481 0x1f700, 0x1f784,
1482 0x1f7c0, 0x1f7c8,
1483 0x1f808, 0x1f80c,
1484 0x1f840, 0x1f844,
1485 0x1f84c, 0x1f84c,
1486 0x1fa84, 0x1fa90,
1487 0x1fac0, 0x1fac0,
1488 0x1fae0, 0x1fae0,
1489 0x1fb00, 0x1fb84,
1490 0x1fbc0, 0x1fbc8,
1491 0x1fc08, 0x1fc0c,
1492 0x1fc40, 0x1fc44,
1493 0x1fc4c, 0x1fc4c,
1494 0x1fe84, 0x1fe90,
1495 0x1fec0, 0x1fec0,
1496 0x1fee0, 0x1fee0,
1497 0x1ff00, 0x1ff84,
1498 0x1ffc0, 0x1ffc8,
1499 0x30000, 0x30030,
1500 0x30100, 0x30144,
1501 0x30190, 0x301a0,
1502 0x301a8, 0x301b8,
1503 0x301c4, 0x301c8,
1504 0x301d0, 0x301d0,
1505 0x30200, 0x30318,
1506 0x30400, 0x304b4,
1507 0x304c0, 0x3052c,
1508 0x30540, 0x3061c,
1509 0x30800, 0x30828,
1510 0x30834, 0x30834,
1511 0x308c0, 0x30908,
1512 0x30910, 0x309ac,
1513 0x30a00, 0x30a14,
1514 0x30a1c, 0x30a2c,
1515 0x30a44, 0x30a50,
1516 0x30a74, 0x30a74,
1517 0x30a7c, 0x30afc,
1518 0x30b08, 0x30c24,
1519 0x30d00, 0x30d00,
1520 0x30d08, 0x30d14,
1521 0x30d1c, 0x30d20,
1522 0x30d3c, 0x30d3c,
1523 0x30d48, 0x30d50,
1524 0x31200, 0x3120c,
1525 0x31220, 0x31220,
1526 0x31240, 0x31240,
1527 0x31600, 0x3160c,
1528 0x31a00, 0x31a1c,
1529 0x31e00, 0x31e20,
1530 0x31e38, 0x31e3c,
1531 0x31e80, 0x31e80,
1532 0x31e88, 0x31ea8,
1533 0x31eb0, 0x31eb4,
1534 0x31ec8, 0x31ed4,
1535 0x31fb8, 0x32004,
1536 0x32200, 0x32200,
1537 0x32208, 0x32240,
1538 0x32248, 0x32280,
1539 0x32288, 0x322c0,
1540 0x322c8, 0x322fc,
1541 0x32600, 0x32630,
1542 0x32a00, 0x32abc,
1543 0x32b00, 0x32b10,
1544 0x32b20, 0x32b30,
1545 0x32b40, 0x32b50,
1546 0x32b60, 0x32b70,
1547 0x33000, 0x33028,
1548 0x33030, 0x33048,
1549 0x33060, 0x33068,
1550 0x33070, 0x3309c,
1551 0x330f0, 0x33128,
1552 0x33130, 0x33148,
1553 0x33160, 0x33168,
1554 0x33170, 0x3319c,
1555 0x331f0, 0x33238,
1556 0x33240, 0x33240,
1557 0x33248, 0x33250,
1558 0x3325c, 0x33264,
1559 0x33270, 0x332b8,
1560 0x332c0, 0x332e4,
1561 0x332f8, 0x33338,
1562 0x33340, 0x33340,
1563 0x33348, 0x33350,
1564 0x3335c, 0x33364,
1565 0x33370, 0x333b8,
1566 0x333c0, 0x333e4,
1567 0x333f8, 0x33428,
1568 0x33430, 0x33448,
1569 0x33460, 0x33468,
1570 0x33470, 0x3349c,
1571 0x334f0, 0x33528,
1572 0x33530, 0x33548,
1573 0x33560, 0x33568,
1574 0x33570, 0x3359c,
1575 0x335f0, 0x33638,
1576 0x33640, 0x33640,
1577 0x33648, 0x33650,
1578 0x3365c, 0x33664,
1579 0x33670, 0x336b8,
1580 0x336c0, 0x336e4,
1581 0x336f8, 0x33738,
1582 0x33740, 0x33740,
1583 0x33748, 0x33750,
1584 0x3375c, 0x33764,
1585 0x33770, 0x337b8,
1586 0x337c0, 0x337e4,
1587 0x337f8, 0x337fc,
1588 0x33814, 0x33814,
1589 0x3382c, 0x3382c,
1590 0x33880, 0x3388c,
1591 0x338e8, 0x338ec,
1592 0x33900, 0x33928,
1593 0x33930, 0x33948,
1594 0x33960, 0x33968,
1595 0x33970, 0x3399c,
1596 0x339f0, 0x33a38,
1597 0x33a40, 0x33a40,
1598 0x33a48, 0x33a50,
1599 0x33a5c, 0x33a64,
1600 0x33a70, 0x33ab8,
1601 0x33ac0, 0x33ae4,
1602 0x33af8, 0x33b10,
1603 0x33b28, 0x33b28,
1604 0x33b3c, 0x33b50,
1605 0x33bf0, 0x33c10,
1606 0x33c28, 0x33c28,
1607 0x33c3c, 0x33c50,
1608 0x33cf0, 0x33cfc,
1609 0x34000, 0x34030,
1610 0x34100, 0x34144,
1611 0x34190, 0x341a0,
1612 0x341a8, 0x341b8,
1613 0x341c4, 0x341c8,
1614 0x341d0, 0x341d0,
1615 0x34200, 0x34318,
1616 0x34400, 0x344b4,
1617 0x344c0, 0x3452c,
1618 0x34540, 0x3461c,
1619 0x34800, 0x34828,
1620 0x34834, 0x34834,
1621 0x348c0, 0x34908,
1622 0x34910, 0x349ac,
1623 0x34a00, 0x34a14,
1624 0x34a1c, 0x34a2c,
1625 0x34a44, 0x34a50,
1626 0x34a74, 0x34a74,
1627 0x34a7c, 0x34afc,
1628 0x34b08, 0x34c24,
1629 0x34d00, 0x34d00,
1630 0x34d08, 0x34d14,
1631 0x34d1c, 0x34d20,
1632 0x34d3c, 0x34d3c,
1633 0x34d48, 0x34d50,
1634 0x35200, 0x3520c,
1635 0x35220, 0x35220,
1636 0x35240, 0x35240,
1637 0x35600, 0x3560c,
1638 0x35a00, 0x35a1c,
1639 0x35e00, 0x35e20,
1640 0x35e38, 0x35e3c,
1641 0x35e80, 0x35e80,
1642 0x35e88, 0x35ea8,
1643 0x35eb0, 0x35eb4,
1644 0x35ec8, 0x35ed4,
1645 0x35fb8, 0x36004,
1646 0x36200, 0x36200,
1647 0x36208, 0x36240,
1648 0x36248, 0x36280,
1649 0x36288, 0x362c0,
1650 0x362c8, 0x362fc,
1651 0x36600, 0x36630,
1652 0x36a00, 0x36abc,
1653 0x36b00, 0x36b10,
1654 0x36b20, 0x36b30,
1655 0x36b40, 0x36b50,
1656 0x36b60, 0x36b70,
1657 0x37000, 0x37028,
1658 0x37030, 0x37048,
1659 0x37060, 0x37068,
1660 0x37070, 0x3709c,
1661 0x370f0, 0x37128,
1662 0x37130, 0x37148,
1663 0x37160, 0x37168,
1664 0x37170, 0x3719c,
1665 0x371f0, 0x37238,
1666 0x37240, 0x37240,
1667 0x37248, 0x37250,
1668 0x3725c, 0x37264,
1669 0x37270, 0x372b8,
1670 0x372c0, 0x372e4,
1671 0x372f8, 0x37338,
1672 0x37340, 0x37340,
1673 0x37348, 0x37350,
1674 0x3735c, 0x37364,
1675 0x37370, 0x373b8,
1676 0x373c0, 0x373e4,
1677 0x373f8, 0x37428,
1678 0x37430, 0x37448,
1679 0x37460, 0x37468,
1680 0x37470, 0x3749c,
1681 0x374f0, 0x37528,
1682 0x37530, 0x37548,
1683 0x37560, 0x37568,
1684 0x37570, 0x3759c,
1685 0x375f0, 0x37638,
1686 0x37640, 0x37640,
1687 0x37648, 0x37650,
1688 0x3765c, 0x37664,
1689 0x37670, 0x376b8,
1690 0x376c0, 0x376e4,
1691 0x376f8, 0x37738,
1692 0x37740, 0x37740,
1693 0x37748, 0x37750,
1694 0x3775c, 0x37764,
1695 0x37770, 0x377b8,
1696 0x377c0, 0x377e4,
1697 0x377f8, 0x377fc,
1698 0x37814, 0x37814,
1699 0x3782c, 0x3782c,
1700 0x37880, 0x3788c,
1701 0x378e8, 0x378ec,
1702 0x37900, 0x37928,
1703 0x37930, 0x37948,
1704 0x37960, 0x37968,
1705 0x37970, 0x3799c,
1706 0x379f0, 0x37a38,
1707 0x37a40, 0x37a40,
1708 0x37a48, 0x37a50,
1709 0x37a5c, 0x37a64,
1710 0x37a70, 0x37ab8,
1711 0x37ac0, 0x37ae4,
1712 0x37af8, 0x37b10,
1713 0x37b28, 0x37b28,
1714 0x37b3c, 0x37b50,
1715 0x37bf0, 0x37c10,
1716 0x37c28, 0x37c28,
1717 0x37c3c, 0x37c50,
1718 0x37cf0, 0x37cfc,
1719 0x38000, 0x38030,
1720 0x38100, 0x38144,
1721 0x38190, 0x381a0,
1722 0x381a8, 0x381b8,
1723 0x381c4, 0x381c8,
1724 0x381d0, 0x381d0,
1725 0x38200, 0x38318,
1726 0x38400, 0x384b4,
1727 0x384c0, 0x3852c,
1728 0x38540, 0x3861c,
1729 0x38800, 0x38828,
1730 0x38834, 0x38834,
1731 0x388c0, 0x38908,
1732 0x38910, 0x389ac,
1733 0x38a00, 0x38a14,
1734 0x38a1c, 0x38a2c,
1735 0x38a44, 0x38a50,
1736 0x38a74, 0x38a74,
1737 0x38a7c, 0x38afc,
1738 0x38b08, 0x38c24,
1739 0x38d00, 0x38d00,
1740 0x38d08, 0x38d14,
1741 0x38d1c, 0x38d20,
1742 0x38d3c, 0x38d3c,
1743 0x38d48, 0x38d50,
1744 0x39200, 0x3920c,
1745 0x39220, 0x39220,
1746 0x39240, 0x39240,
1747 0x39600, 0x3960c,
1748 0x39a00, 0x39a1c,
1749 0x39e00, 0x39e20,
1750 0x39e38, 0x39e3c,
1751 0x39e80, 0x39e80,
1752 0x39e88, 0x39ea8,
1753 0x39eb0, 0x39eb4,
1754 0x39ec8, 0x39ed4,
1755 0x39fb8, 0x3a004,
1756 0x3a200, 0x3a200,
1757 0x3a208, 0x3a240,
1758 0x3a248, 0x3a280,
1759 0x3a288, 0x3a2c0,
1760 0x3a2c8, 0x3a2fc,
1761 0x3a600, 0x3a630,
1762 0x3aa00, 0x3aabc,
1763 0x3ab00, 0x3ab10,
1764 0x3ab20, 0x3ab30,
1765 0x3ab40, 0x3ab50,
1766 0x3ab60, 0x3ab70,
1767 0x3b000, 0x3b028,
1768 0x3b030, 0x3b048,
1769 0x3b060, 0x3b068,
1770 0x3b070, 0x3b09c,
1771 0x3b0f0, 0x3b128,
1772 0x3b130, 0x3b148,
1773 0x3b160, 0x3b168,
1774 0x3b170, 0x3b19c,
1775 0x3b1f0, 0x3b238,
1776 0x3b240, 0x3b240,
1777 0x3b248, 0x3b250,
1778 0x3b25c, 0x3b264,
1779 0x3b270, 0x3b2b8,
1780 0x3b2c0, 0x3b2e4,
1781 0x3b2f8, 0x3b338,
1782 0x3b340, 0x3b340,
1783 0x3b348, 0x3b350,
1784 0x3b35c, 0x3b364,
1785 0x3b370, 0x3b3b8,
1786 0x3b3c0, 0x3b3e4,
1787 0x3b3f8, 0x3b428,
1788 0x3b430, 0x3b448,
1789 0x3b460, 0x3b468,
1790 0x3b470, 0x3b49c,
1791 0x3b4f0, 0x3b528,
1792 0x3b530, 0x3b548,
1793 0x3b560, 0x3b568,
1794 0x3b570, 0x3b59c,
1795 0x3b5f0, 0x3b638,
1796 0x3b640, 0x3b640,
1797 0x3b648, 0x3b650,
1798 0x3b65c, 0x3b664,
1799 0x3b670, 0x3b6b8,
1800 0x3b6c0, 0x3b6e4,
1801 0x3b6f8, 0x3b738,
1802 0x3b740, 0x3b740,
1803 0x3b748, 0x3b750,
1804 0x3b75c, 0x3b764,
1805 0x3b770, 0x3b7b8,
1806 0x3b7c0, 0x3b7e4,
1807 0x3b7f8, 0x3b7fc,
1808 0x3b814, 0x3b814,
1809 0x3b82c, 0x3b82c,
1810 0x3b880, 0x3b88c,
1811 0x3b8e8, 0x3b8ec,
1812 0x3b900, 0x3b928,
1813 0x3b930, 0x3b948,
1814 0x3b960, 0x3b968,
1815 0x3b970, 0x3b99c,
1816 0x3b9f0, 0x3ba38,
1817 0x3ba40, 0x3ba40,
1818 0x3ba48, 0x3ba50,
1819 0x3ba5c, 0x3ba64,
1820 0x3ba70, 0x3bab8,
1821 0x3bac0, 0x3bae4,
1822 0x3baf8, 0x3bb10,
1823 0x3bb28, 0x3bb28,
1824 0x3bb3c, 0x3bb50,
1825 0x3bbf0, 0x3bc10,
1826 0x3bc28, 0x3bc28,
1827 0x3bc3c, 0x3bc50,
1828 0x3bcf0, 0x3bcfc,
1829 0x3c000, 0x3c030,
1830 0x3c100, 0x3c144,
1831 0x3c190, 0x3c1a0,
1832 0x3c1a8, 0x3c1b8,
1833 0x3c1c4, 0x3c1c8,
1834 0x3c1d0, 0x3c1d0,
1835 0x3c200, 0x3c318,
1836 0x3c400, 0x3c4b4,
1837 0x3c4c0, 0x3c52c,
1838 0x3c540, 0x3c61c,
1839 0x3c800, 0x3c828,
1840 0x3c834, 0x3c834,
1841 0x3c8c0, 0x3c908,
1842 0x3c910, 0x3c9ac,
1843 0x3ca00, 0x3ca14,
1844 0x3ca1c, 0x3ca2c,
1845 0x3ca44, 0x3ca50,
1846 0x3ca74, 0x3ca74,
1847 0x3ca7c, 0x3cafc,
1848 0x3cb08, 0x3cc24,
1849 0x3cd00, 0x3cd00,
1850 0x3cd08, 0x3cd14,
1851 0x3cd1c, 0x3cd20,
1852 0x3cd3c, 0x3cd3c,
1853 0x3cd48, 0x3cd50,
1854 0x3d200, 0x3d20c,
1855 0x3d220, 0x3d220,
1856 0x3d240, 0x3d240,
1857 0x3d600, 0x3d60c,
1858 0x3da00, 0x3da1c,
1859 0x3de00, 0x3de20,
1860 0x3de38, 0x3de3c,
1861 0x3de80, 0x3de80,
1862 0x3de88, 0x3dea8,
1863 0x3deb0, 0x3deb4,
1864 0x3dec8, 0x3ded4,
1865 0x3dfb8, 0x3e004,
1866 0x3e200, 0x3e200,
1867 0x3e208, 0x3e240,
1868 0x3e248, 0x3e280,
1869 0x3e288, 0x3e2c0,
1870 0x3e2c8, 0x3e2fc,
1871 0x3e600, 0x3e630,
1872 0x3ea00, 0x3eabc,
1873 0x3eb00, 0x3eb10,
1874 0x3eb20, 0x3eb30,
1875 0x3eb40, 0x3eb50,
1876 0x3eb60, 0x3eb70,
1877 0x3f000, 0x3f028,
1878 0x3f030, 0x3f048,
1879 0x3f060, 0x3f068,
1880 0x3f070, 0x3f09c,
1881 0x3f0f0, 0x3f128,
1882 0x3f130, 0x3f148,
1883 0x3f160, 0x3f168,
1884 0x3f170, 0x3f19c,
1885 0x3f1f0, 0x3f238,
1886 0x3f240, 0x3f240,
1887 0x3f248, 0x3f250,
1888 0x3f25c, 0x3f264,
1889 0x3f270, 0x3f2b8,
1890 0x3f2c0, 0x3f2e4,
1891 0x3f2f8, 0x3f338,
1892 0x3f340, 0x3f340,
1893 0x3f348, 0x3f350,
1894 0x3f35c, 0x3f364,
1895 0x3f370, 0x3f3b8,
1896 0x3f3c0, 0x3f3e4,
1897 0x3f3f8, 0x3f428,
1898 0x3f430, 0x3f448,
1899 0x3f460, 0x3f468,
1900 0x3f470, 0x3f49c,
1901 0x3f4f0, 0x3f528,
1902 0x3f530, 0x3f548,
1903 0x3f560, 0x3f568,
1904 0x3f570, 0x3f59c,
1905 0x3f5f0, 0x3f638,
1906 0x3f640, 0x3f640,
1907 0x3f648, 0x3f650,
1908 0x3f65c, 0x3f664,
1909 0x3f670, 0x3f6b8,
1910 0x3f6c0, 0x3f6e4,
1911 0x3f6f8, 0x3f738,
1912 0x3f740, 0x3f740,
1913 0x3f748, 0x3f750,
1914 0x3f75c, 0x3f764,
1915 0x3f770, 0x3f7b8,
1916 0x3f7c0, 0x3f7e4,
1917 0x3f7f8, 0x3f7fc,
1918 0x3f814, 0x3f814,
1919 0x3f82c, 0x3f82c,
1920 0x3f880, 0x3f88c,
1921 0x3f8e8, 0x3f8ec,
1922 0x3f900, 0x3f928,
1923 0x3f930, 0x3f948,
1924 0x3f960, 0x3f968,
1925 0x3f970, 0x3f99c,
1926 0x3f9f0, 0x3fa38,
1927 0x3fa40, 0x3fa40,
1928 0x3fa48, 0x3fa50,
1929 0x3fa5c, 0x3fa64,
1930 0x3fa70, 0x3fab8,
1931 0x3fac0, 0x3fae4,
1932 0x3faf8, 0x3fb10,
1933 0x3fb28, 0x3fb28,
1934 0x3fb3c, 0x3fb50,
1935 0x3fbf0, 0x3fc10,
1936 0x3fc28, 0x3fc28,
1937 0x3fc3c, 0x3fc50,
1938 0x3fcf0, 0x3fcfc,
1939 0x40000, 0x4000c,
1940 0x40040, 0x40050,
1941 0x40060, 0x40068,
1942 0x4007c, 0x4008c,
1943 0x40094, 0x400b0,
1944 0x400c0, 0x40144,
1945 0x40180, 0x4018c,
1946 0x40200, 0x40254,
1947 0x40260, 0x40264,
1948 0x40270, 0x40288,
1949 0x40290, 0x40298,
1950 0x402ac, 0x402c8,
1951 0x402d0, 0x402e0,
1952 0x402f0, 0x402f0,
1953 0x40300, 0x4033c,
1954 0x403f8, 0x403fc,
1955 0x41304, 0x413c4,
1956 0x41400, 0x4140c,
1957 0x41414, 0x4141c,
1958 0x41480, 0x414d0,
1959 0x44000, 0x44054,
1960 0x4405c, 0x44078,
1961 0x440c0, 0x44174,
1962 0x44180, 0x441ac,
1963 0x441b4, 0x441b8,
1964 0x441c0, 0x44254,
1965 0x4425c, 0x44278,
1966 0x442c0, 0x44374,
1967 0x44380, 0x443ac,
1968 0x443b4, 0x443b8,
1969 0x443c0, 0x44454,
1970 0x4445c, 0x44478,
1971 0x444c0, 0x44574,
1972 0x44580, 0x445ac,
1973 0x445b4, 0x445b8,
1974 0x445c0, 0x44654,
1975 0x4465c, 0x44678,
1976 0x446c0, 0x44774,
1977 0x44780, 0x447ac,
1978 0x447b4, 0x447b8,
1979 0x447c0, 0x44854,
1980 0x4485c, 0x44878,
1981 0x448c0, 0x44974,
1982 0x44980, 0x449ac,
1983 0x449b4, 0x449b8,
1984 0x449c0, 0x449fc,
1985 0x45000, 0x45004,
1986 0x45010, 0x45030,
1987 0x45040, 0x45060,
1988 0x45068, 0x45068,
1989 0x45080, 0x45084,
1990 0x450a0, 0x450b0,
1991 0x45200, 0x45204,
1992 0x45210, 0x45230,
1993 0x45240, 0x45260,
1994 0x45268, 0x45268,
1995 0x45280, 0x45284,
1996 0x452a0, 0x452b0,
1997 0x460c0, 0x460e4,
1998 0x47000, 0x4703c,
1999 0x47044, 0x4708c,
2000 0x47200, 0x47250,
2001 0x47400, 0x47408,
2002 0x47414, 0x47420,
2003 0x47600, 0x47618,
2004 0x47800, 0x47814,
2005 0x48000, 0x4800c,
2006 0x48040, 0x48050,
2007 0x48060, 0x48068,
2008 0x4807c, 0x4808c,
2009 0x48094, 0x480b0,
2010 0x480c0, 0x48144,
2011 0x48180, 0x4818c,
2012 0x48200, 0x48254,
2013 0x48260, 0x48264,
2014 0x48270, 0x48288,
2015 0x48290, 0x48298,
2016 0x482ac, 0x482c8,
2017 0x482d0, 0x482e0,
2018 0x482f0, 0x482f0,
2019 0x48300, 0x4833c,
2020 0x483f8, 0x483fc,
2021 0x49304, 0x493c4,
2022 0x49400, 0x4940c,
2023 0x49414, 0x4941c,
2024 0x49480, 0x494d0,
2025 0x4c000, 0x4c054,
2026 0x4c05c, 0x4c078,
2027 0x4c0c0, 0x4c174,
2028 0x4c180, 0x4c1ac,
2029 0x4c1b4, 0x4c1b8,
2030 0x4c1c0, 0x4c254,
2031 0x4c25c, 0x4c278,
2032 0x4c2c0, 0x4c374,
2033 0x4c380, 0x4c3ac,
2034 0x4c3b4, 0x4c3b8,
2035 0x4c3c0, 0x4c454,
2036 0x4c45c, 0x4c478,
2037 0x4c4c0, 0x4c574,
2038 0x4c580, 0x4c5ac,
2039 0x4c5b4, 0x4c5b8,
2040 0x4c5c0, 0x4c654,
2041 0x4c65c, 0x4c678,
2042 0x4c6c0, 0x4c774,
2043 0x4c780, 0x4c7ac,
2044 0x4c7b4, 0x4c7b8,
2045 0x4c7c0, 0x4c854,
2046 0x4c85c, 0x4c878,
2047 0x4c8c0, 0x4c974,
2048 0x4c980, 0x4c9ac,
2049 0x4c9b4, 0x4c9b8,
2050 0x4c9c0, 0x4c9fc,
2051 0x4d000, 0x4d004,
2052 0x4d010, 0x4d030,
2053 0x4d040, 0x4d060,
2054 0x4d068, 0x4d068,
2055 0x4d080, 0x4d084,
2056 0x4d0a0, 0x4d0b0,
2057 0x4d200, 0x4d204,
2058 0x4d210, 0x4d230,
2059 0x4d240, 0x4d260,
2060 0x4d268, 0x4d268,
2061 0x4d280, 0x4d284,
2062 0x4d2a0, 0x4d2b0,
2063 0x4e0c0, 0x4e0e4,
2064 0x4f000, 0x4f03c,
2065 0x4f044, 0x4f08c,
2066 0x4f200, 0x4f250,
2067 0x4f400, 0x4f408,
2068 0x4f414, 0x4f420,
2069 0x4f600, 0x4f618,
2070 0x4f800, 0x4f814,
2071 0x50000, 0x50084,
2072 0x50090, 0x500cc,
2073 0x50400, 0x50400,
2074 0x50800, 0x50884,
2075 0x50890, 0x508cc,
2076 0x50c00, 0x50c00,
2077 0x51000, 0x5101c,
2078 0x51300, 0x51308,
2079 };
2080
2081 static const unsigned int t6_reg_ranges[] = {
2082 0x1008, 0x101c,
2083 0x1024, 0x10a8,
2084 0x10b4, 0x10f8,
2085 0x1100, 0x1114,
2086 0x111c, 0x112c,
2087 0x1138, 0x113c,
2088 0x1144, 0x114c,
2089 0x1180, 0x1184,
2090 0x1190, 0x1194,
2091 0x11a0, 0x11a4,
2092 0x11b0, 0x11b4,
2093 0x11fc, 0x123c,
2094 0x1254, 0x1274,
2095 0x1280, 0x133c,
2096 0x1800, 0x18fc,
2097 0x3000, 0x302c,
2098 0x3060, 0x30b0,
2099 0x30b8, 0x30d8,
2100 0x30e0, 0x30fc,
2101 0x3140, 0x357c,
2102 0x35a8, 0x35cc,
2103 0x35ec, 0x35ec,
2104 0x3600, 0x5624,
2105 0x56cc, 0x56ec,
2106 0x56f4, 0x5720,
2107 0x5728, 0x575c,
2108 0x580c, 0x5814,
2109 0x5890, 0x589c,
2110 0x58a4, 0x58ac,
2111 0x58b8, 0x58bc,
2112 0x5940, 0x595c,
2113 0x5980, 0x598c,
2114 0x59b0, 0x59c8,
2115 0x59d0, 0x59dc,
2116 0x59fc, 0x5a18,
2117 0x5a60, 0x5a6c,
2118 0x5a80, 0x5a8c,
2119 0x5a94, 0x5a9c,
2120 0x5b94, 0x5bfc,
2121 0x5c10, 0x5e48,
2122 0x5e50, 0x5e94,
2123 0x5ea0, 0x5eb0,
2124 0x5ec0, 0x5ec0,
2125 0x5ec8, 0x5ed0,
2126 0x5ee0, 0x5ee0,
2127 0x5ef0, 0x5ef0,
2128 0x5f00, 0x5f00,
2129 0x6000, 0x6020,
2130 0x6028, 0x6040,
2131 0x6058, 0x609c,
2132 0x60a8, 0x619c,
2133 0x7700, 0x7798,
2134 0x77c0, 0x7880,
2135 0x78cc, 0x78fc,
2136 0x7b00, 0x7b58,
2137 0x7b60, 0x7b84,
2138 0x7b8c, 0x7c54,
2139 0x7d00, 0x7d38,
2140 0x7d40, 0x7d84,
2141 0x7d8c, 0x7ddc,
2142 0x7de4, 0x7e04,
2143 0x7e10, 0x7e1c,
2144 0x7e24, 0x7e38,
2145 0x7e40, 0x7e44,
2146 0x7e4c, 0x7e78,
2147 0x7e80, 0x7edc,
2148 0x7ee8, 0x7efc,
2149 0x8dc0, 0x8de4,
2150 0x8df8, 0x8e04,
2151 0x8e10, 0x8e84,
2152 0x8ea0, 0x8f88,
2153 0x8fb8, 0x9058,
2154 0x9060, 0x9060,
2155 0x9068, 0x90f8,
2156 0x9100, 0x9124,
2157 0x9400, 0x9470,
2158 0x9600, 0x9600,
2159 0x9608, 0x9638,
2160 0x9640, 0x9704,
2161 0x9710, 0x971c,
2162 0x9800, 0x9808,
2163 0x9810, 0x9864,
2164 0x9c00, 0x9c6c,
2165 0x9c80, 0x9cec,
2166 0x9d00, 0x9d6c,
2167 0x9d80, 0x9dec,
2168 0x9e00, 0x9e6c,
2169 0x9e80, 0x9eec,
2170 0x9f00, 0x9f6c,
2171 0x9f80, 0xa020,
2172 0xd000, 0xd03c,
2173 0xd100, 0xd118,
2174 0xd200, 0xd214,
2175 0xd220, 0xd234,
2176 0xd240, 0xd254,
2177 0xd260, 0xd274,
2178 0xd280, 0xd294,
2179 0xd2a0, 0xd2b4,
2180 0xd2c0, 0xd2d4,
2181 0xd2e0, 0xd2f4,
2182 0xd300, 0xd31c,
2183 0xdfc0, 0xdfe0,
2184 0xe000, 0xf008,
2185 0xf010, 0xf018,
2186 0xf020, 0xf028,
2187 0x11000, 0x11014,
2188 0x11048, 0x1106c,
2189 0x11074, 0x11088,
2190 0x11098, 0x11120,
2191 0x1112c, 0x1117c,
2192 0x11190, 0x112e0,
2193 0x11300, 0x1130c,
2194 0x12000, 0x1206c,
2195 0x19040, 0x1906c,
2196 0x19078, 0x19080,
2197 0x1908c, 0x190e8,
2198 0x190f0, 0x190f8,
2199 0x19100, 0x19110,
2200 0x19120, 0x19124,
2201 0x19150, 0x19194,
2202 0x1919c, 0x191b0,
2203 0x191d0, 0x191e8,
2204 0x19238, 0x19290,
2205 0x192a4, 0x192b0,
2206 0x192bc, 0x192bc,
2207 0x19348, 0x1934c,
2208 0x193f8, 0x19418,
2209 0x19420, 0x19428,
2210 0x19430, 0x19444,
2211 0x1944c, 0x1946c,
2212 0x19474, 0x19474,
2213 0x19490, 0x194cc,
2214 0x194f0, 0x194f8,
2215 0x19c00, 0x19c48,
2216 0x19c50, 0x19c80,
2217 0x19c94, 0x19c98,
2218 0x19ca0, 0x19cbc,
2219 0x19ce4, 0x19ce4,
2220 0x19cf0, 0x19cf8,
2221 0x19d00, 0x19d28,
2222 0x19d50, 0x19d78,
2223 0x19d94, 0x19d98,
2224 0x19da0, 0x19dc8,
2225 0x19df0, 0x19e10,
2226 0x19e50, 0x19e6c,
2227 0x19ea0, 0x19ebc,
2228 0x19ec4, 0x19ef4,
2229 0x19f04, 0x19f2c,
2230 0x19f34, 0x19f34,
2231 0x19f40, 0x19f50,
2232 0x19f90, 0x19fac,
2233 0x19fc4, 0x19fc8,
2234 0x19fd0, 0x19fe4,
2235 0x1a000, 0x1a004,
2236 0x1a010, 0x1a06c,
2237 0x1a0b0, 0x1a0e4,
2238 0x1a0ec, 0x1a0f8,
2239 0x1a100, 0x1a108,
2240 0x1a114, 0x1a130,
2241 0x1a138, 0x1a1c4,
2242 0x1a1fc, 0x1a1fc,
2243 0x1e008, 0x1e00c,
2244 0x1e040, 0x1e044,
2245 0x1e04c, 0x1e04c,
2246 0x1e284, 0x1e290,
2247 0x1e2c0, 0x1e2c0,
2248 0x1e2e0, 0x1e2e0,
2249 0x1e300, 0x1e384,
2250 0x1e3c0, 0x1e3c8,
2251 0x1e408, 0x1e40c,
2252 0x1e440, 0x1e444,
2253 0x1e44c, 0x1e44c,
2254 0x1e684, 0x1e690,
2255 0x1e6c0, 0x1e6c0,
2256 0x1e6e0, 0x1e6e0,
2257 0x1e700, 0x1e784,
2258 0x1e7c0, 0x1e7c8,
2259 0x1e808, 0x1e80c,
2260 0x1e840, 0x1e844,
2261 0x1e84c, 0x1e84c,
2262 0x1ea84, 0x1ea90,
2263 0x1eac0, 0x1eac0,
2264 0x1eae0, 0x1eae0,
2265 0x1eb00, 0x1eb84,
2266 0x1ebc0, 0x1ebc8,
2267 0x1ec08, 0x1ec0c,
2268 0x1ec40, 0x1ec44,
2269 0x1ec4c, 0x1ec4c,
2270 0x1ee84, 0x1ee90,
2271 0x1eec0, 0x1eec0,
2272 0x1eee0, 0x1eee0,
2273 0x1ef00, 0x1ef84,
2274 0x1efc0, 0x1efc8,
2275 0x1f008, 0x1f00c,
2276 0x1f040, 0x1f044,
2277 0x1f04c, 0x1f04c,
2278 0x1f284, 0x1f290,
2279 0x1f2c0, 0x1f2c0,
2280 0x1f2e0, 0x1f2e0,
2281 0x1f300, 0x1f384,
2282 0x1f3c0, 0x1f3c8,
2283 0x1f408, 0x1f40c,
2284 0x1f440, 0x1f444,
2285 0x1f44c, 0x1f44c,
2286 0x1f684, 0x1f690,
2287 0x1f6c0, 0x1f6c0,
2288 0x1f6e0, 0x1f6e0,
2289 0x1f700, 0x1f784,
2290 0x1f7c0, 0x1f7c8,
2291 0x1f808, 0x1f80c,
2292 0x1f840, 0x1f844,
2293 0x1f84c, 0x1f84c,
2294 0x1fa84, 0x1fa90,
2295 0x1fac0, 0x1fac0,
2296 0x1fae0, 0x1fae0,
2297 0x1fb00, 0x1fb84,
2298 0x1fbc0, 0x1fbc8,
2299 0x1fc08, 0x1fc0c,
2300 0x1fc40, 0x1fc44,
2301 0x1fc4c, 0x1fc4c,
2302 0x1fe84, 0x1fe90,
2303 0x1fec0, 0x1fec0,
2304 0x1fee0, 0x1fee0,
2305 0x1ff00, 0x1ff84,
2306 0x1ffc0, 0x1ffc8,
2307 0x30000, 0x30030,
2308 0x30100, 0x30168,
2309 0x30190, 0x301a0,
2310 0x301a8, 0x301b8,
2311 0x301c4, 0x301c8,
2312 0x301d0, 0x301d0,
2313 0x30200, 0x30320,
2314 0x30400, 0x304b4,
2315 0x304c0, 0x3052c,
2316 0x30540, 0x3061c,
2317 0x30800, 0x308a0,
2318 0x308c0, 0x30908,
2319 0x30910, 0x309b8,
2320 0x30a00, 0x30a04,
2321 0x30a0c, 0x30a14,
2322 0x30a1c, 0x30a2c,
2323 0x30a44, 0x30a50,
2324 0x30a74, 0x30a74,
2325 0x30a7c, 0x30afc,
2326 0x30b08, 0x30c24,
2327 0x30d00, 0x30d14,
2328 0x30d1c, 0x30d3c,
2329 0x30d44, 0x30d4c,
2330 0x30d54, 0x30d74,
2331 0x30d7c, 0x30d7c,
2332 0x30de0, 0x30de0,
2333 0x30e00, 0x30ed4,
2334 0x30f00, 0x30fa4,
2335 0x30fc0, 0x30fc4,
2336 0x31000, 0x31004,
2337 0x31080, 0x310fc,
2338 0x31208, 0x31220,
2339 0x3123c, 0x31254,
2340 0x31300, 0x31300,
2341 0x31308, 0x3131c,
2342 0x31338, 0x3133c,
2343 0x31380, 0x31380,
2344 0x31388, 0x313a8,
2345 0x313b4, 0x313b4,
2346 0x31400, 0x31420,
2347 0x31438, 0x3143c,
2348 0x31480, 0x31480,
2349 0x314a8, 0x314a8,
2350 0x314b0, 0x314b4,
2351 0x314c8, 0x314d4,
2352 0x31a40, 0x31a4c,
2353 0x31af0, 0x31b20,
2354 0x31b38, 0x31b3c,
2355 0x31b80, 0x31b80,
2356 0x31ba8, 0x31ba8,
2357 0x31bb0, 0x31bb4,
2358 0x31bc8, 0x31bd4,
2359 0x32140, 0x3218c,
2360 0x321f0, 0x321f4,
2361 0x32200, 0x32200,
2362 0x32218, 0x32218,
2363 0x32400, 0x32400,
2364 0x32408, 0x3241c,
2365 0x32618, 0x32620,
2366 0x32664, 0x32664,
2367 0x326a8, 0x326a8,
2368 0x326ec, 0x326ec,
2369 0x32a00, 0x32abc,
2370 0x32b00, 0x32b18,
2371 0x32b20, 0x32b38,
2372 0x32b40, 0x32b58,
2373 0x32b60, 0x32b78,
2374 0x32c00, 0x32c00,
2375 0x32c08, 0x32c3c,
2376 0x33000, 0x3302c,
2377 0x33034, 0x33050,
2378 0x33058, 0x33058,
2379 0x33060, 0x3308c,
2380 0x3309c, 0x330ac,
2381 0x330c0, 0x330c0,
2382 0x330c8, 0x330d0,
2383 0x330d8, 0x330e0,
2384 0x330ec, 0x3312c,
2385 0x33134, 0x33150,
2386 0x33158, 0x33158,
2387 0x33160, 0x3318c,
2388 0x3319c, 0x331ac,
2389 0x331c0, 0x331c0,
2390 0x331c8, 0x331d0,
2391 0x331d8, 0x331e0,
2392 0x331ec, 0x33290,
2393 0x33298, 0x332c4,
2394 0x332e4, 0x33390,
2395 0x33398, 0x333c4,
2396 0x333e4, 0x3342c,
2397 0x33434, 0x33450,
2398 0x33458, 0x33458,
2399 0x33460, 0x3348c,
2400 0x3349c, 0x334ac,
2401 0x334c0, 0x334c0,
2402 0x334c8, 0x334d0,
2403 0x334d8, 0x334e0,
2404 0x334ec, 0x3352c,
2405 0x33534, 0x33550,
2406 0x33558, 0x33558,
2407 0x33560, 0x3358c,
2408 0x3359c, 0x335ac,
2409 0x335c0, 0x335c0,
2410 0x335c8, 0x335d0,
2411 0x335d8, 0x335e0,
2412 0x335ec, 0x33690,
2413 0x33698, 0x336c4,
2414 0x336e4, 0x33790,
2415 0x33798, 0x337c4,
2416 0x337e4, 0x337fc,
2417 0x33814, 0x33814,
2418 0x33854, 0x33868,
2419 0x33880, 0x3388c,
2420 0x338c0, 0x338d0,
2421 0x338e8, 0x338ec,
2422 0x33900, 0x3392c,
2423 0x33934, 0x33950,
2424 0x33958, 0x33958,
2425 0x33960, 0x3398c,
2426 0x3399c, 0x339ac,
2427 0x339c0, 0x339c0,
2428 0x339c8, 0x339d0,
2429 0x339d8, 0x339e0,
2430 0x339ec, 0x33a90,
2431 0x33a98, 0x33ac4,
2432 0x33ae4, 0x33b10,
2433 0x33b24, 0x33b28,
2434 0x33b38, 0x33b50,
2435 0x33bf0, 0x33c10,
2436 0x33c24, 0x33c28,
2437 0x33c38, 0x33c50,
2438 0x33cf0, 0x33cfc,
2439 0x34000, 0x34030,
2440 0x34100, 0x34168,
2441 0x34190, 0x341a0,
2442 0x341a8, 0x341b8,
2443 0x341c4, 0x341c8,
2444 0x341d0, 0x341d0,
2445 0x34200, 0x34320,
2446 0x34400, 0x344b4,
2447 0x344c0, 0x3452c,
2448 0x34540, 0x3461c,
2449 0x34800, 0x348a0,
2450 0x348c0, 0x34908,
2451 0x34910, 0x349b8,
2452 0x34a00, 0x34a04,
2453 0x34a0c, 0x34a14,
2454 0x34a1c, 0x34a2c,
2455 0x34a44, 0x34a50,
2456 0x34a74, 0x34a74,
2457 0x34a7c, 0x34afc,
2458 0x34b08, 0x34c24,
2459 0x34d00, 0x34d14,
2460 0x34d1c, 0x34d3c,
2461 0x34d44, 0x34d4c,
2462 0x34d54, 0x34d74,
2463 0x34d7c, 0x34d7c,
2464 0x34de0, 0x34de0,
2465 0x34e00, 0x34ed4,
2466 0x34f00, 0x34fa4,
2467 0x34fc0, 0x34fc4,
2468 0x35000, 0x35004,
2469 0x35080, 0x350fc,
2470 0x35208, 0x35220,
2471 0x3523c, 0x35254,
2472 0x35300, 0x35300,
2473 0x35308, 0x3531c,
2474 0x35338, 0x3533c,
2475 0x35380, 0x35380,
2476 0x35388, 0x353a8,
2477 0x353b4, 0x353b4,
2478 0x35400, 0x35420,
2479 0x35438, 0x3543c,
2480 0x35480, 0x35480,
2481 0x354a8, 0x354a8,
2482 0x354b0, 0x354b4,
2483 0x354c8, 0x354d4,
2484 0x35a40, 0x35a4c,
2485 0x35af0, 0x35b20,
2486 0x35b38, 0x35b3c,
2487 0x35b80, 0x35b80,
2488 0x35ba8, 0x35ba8,
2489 0x35bb0, 0x35bb4,
2490 0x35bc8, 0x35bd4,
2491 0x36140, 0x3618c,
2492 0x361f0, 0x361f4,
2493 0x36200, 0x36200,
2494 0x36218, 0x36218,
2495 0x36400, 0x36400,
2496 0x36408, 0x3641c,
2497 0x36618, 0x36620,
2498 0x36664, 0x36664,
2499 0x366a8, 0x366a8,
2500 0x366ec, 0x366ec,
2501 0x36a00, 0x36abc,
2502 0x36b00, 0x36b18,
2503 0x36b20, 0x36b38,
2504 0x36b40, 0x36b58,
2505 0x36b60, 0x36b78,
2506 0x36c00, 0x36c00,
2507 0x36c08, 0x36c3c,
2508 0x37000, 0x3702c,
2509 0x37034, 0x37050,
2510 0x37058, 0x37058,
2511 0x37060, 0x3708c,
2512 0x3709c, 0x370ac,
2513 0x370c0, 0x370c0,
2514 0x370c8, 0x370d0,
2515 0x370d8, 0x370e0,
2516 0x370ec, 0x3712c,
2517 0x37134, 0x37150,
2518 0x37158, 0x37158,
2519 0x37160, 0x3718c,
2520 0x3719c, 0x371ac,
2521 0x371c0, 0x371c0,
2522 0x371c8, 0x371d0,
2523 0x371d8, 0x371e0,
2524 0x371ec, 0x37290,
2525 0x37298, 0x372c4,
2526 0x372e4, 0x37390,
2527 0x37398, 0x373c4,
2528 0x373e4, 0x3742c,
2529 0x37434, 0x37450,
2530 0x37458, 0x37458,
2531 0x37460, 0x3748c,
2532 0x3749c, 0x374ac,
2533 0x374c0, 0x374c0,
2534 0x374c8, 0x374d0,
2535 0x374d8, 0x374e0,
2536 0x374ec, 0x3752c,
2537 0x37534, 0x37550,
2538 0x37558, 0x37558,
2539 0x37560, 0x3758c,
2540 0x3759c, 0x375ac,
2541 0x375c0, 0x375c0,
2542 0x375c8, 0x375d0,
2543 0x375d8, 0x375e0,
2544 0x375ec, 0x37690,
2545 0x37698, 0x376c4,
2546 0x376e4, 0x37790,
2547 0x37798, 0x377c4,
2548 0x377e4, 0x377fc,
2549 0x37814, 0x37814,
2550 0x37854, 0x37868,
2551 0x37880, 0x3788c,
2552 0x378c0, 0x378d0,
2553 0x378e8, 0x378ec,
2554 0x37900, 0x3792c,
2555 0x37934, 0x37950,
2556 0x37958, 0x37958,
2557 0x37960, 0x3798c,
2558 0x3799c, 0x379ac,
2559 0x379c0, 0x379c0,
2560 0x379c8, 0x379d0,
2561 0x379d8, 0x379e0,
2562 0x379ec, 0x37a90,
2563 0x37a98, 0x37ac4,
2564 0x37ae4, 0x37b10,
2565 0x37b24, 0x37b28,
2566 0x37b38, 0x37b50,
2567 0x37bf0, 0x37c10,
2568 0x37c24, 0x37c28,
2569 0x37c38, 0x37c50,
2570 0x37cf0, 0x37cfc,
2571 0x40040, 0x40040,
2572 0x40080, 0x40084,
2573 0x40100, 0x40100,
2574 0x40140, 0x401bc,
2575 0x40200, 0x40214,
2576 0x40228, 0x40228,
2577 0x40240, 0x40258,
2578 0x40280, 0x40280,
2579 0x40304, 0x40304,
2580 0x40330, 0x4033c,
2581 0x41304, 0x413c8,
2582 0x413d0, 0x413dc,
2583 0x413f0, 0x413f0,
2584 0x41400, 0x4140c,
2585 0x41414, 0x4141c,
2586 0x41480, 0x414d0,
2587 0x44000, 0x4407c,
2588 0x440c0, 0x441ac,
2589 0x441b4, 0x4427c,
2590 0x442c0, 0x443ac,
2591 0x443b4, 0x4447c,
2592 0x444c0, 0x445ac,
2593 0x445b4, 0x4467c,
2594 0x446c0, 0x447ac,
2595 0x447b4, 0x4487c,
2596 0x448c0, 0x449ac,
2597 0x449b4, 0x44a7c,
2598 0x44ac0, 0x44bac,
2599 0x44bb4, 0x44c7c,
2600 0x44cc0, 0x44dac,
2601 0x44db4, 0x44e7c,
2602 0x44ec0, 0x44fac,
2603 0x44fb4, 0x4507c,
2604 0x450c0, 0x451ac,
2605 0x451b4, 0x451fc,
2606 0x45800, 0x45804,
2607 0x45810, 0x45830,
2608 0x45840, 0x45860,
2609 0x45868, 0x45868,
2610 0x45880, 0x45884,
2611 0x458a0, 0x458b0,
2612 0x45a00, 0x45a04,
2613 0x45a10, 0x45a30,
2614 0x45a40, 0x45a60,
2615 0x45a68, 0x45a68,
2616 0x45a80, 0x45a84,
2617 0x45aa0, 0x45ab0,
2618 0x460c0, 0x460e4,
2619 0x47000, 0x4703c,
2620 0x47044, 0x4708c,
2621 0x47200, 0x47250,
2622 0x47400, 0x47408,
2623 0x47414, 0x47420,
2624 0x47600, 0x47618,
2625 0x47800, 0x47814,
2626 0x47820, 0x4782c,
2627 0x50000, 0x50084,
2628 0x50090, 0x500cc,
2629 0x50300, 0x50384,
2630 0x50400, 0x50400,
2631 0x50800, 0x50884,
2632 0x50890, 0x508cc,
2633 0x50b00, 0x50b84,
2634 0x50c00, 0x50c00,
2635 0x51000, 0x51020,
2636 0x51028, 0x510b0,
2637 0x51300, 0x51324,
2638 };
2639
2640 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2641 const unsigned int *reg_ranges;
2642 int reg_ranges_size, range;
2643 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2644
2645 /* Select the right set of register ranges to dump depending on the
2646 * adapter chip type.
2647 */
2648 switch (chip_version) {
2649 case CHELSIO_T4:
2650 reg_ranges = t4_reg_ranges;
2651 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2652 break;
2653
2654 case CHELSIO_T5:
2655 reg_ranges = t5_reg_ranges;
2656 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2657 break;
2658
2659 case CHELSIO_T6:
2660 reg_ranges = t6_reg_ranges;
2661 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2662 break;
2663
2664 default:
2665 dev_err(adap->pdev_dev,
2666 "Unsupported chip version %d\n", chip_version);
2667 return;
2668 }
2669
2670 /* Clear the register buffer and insert the appropriate register
2671 * values selected by the above register ranges.
2672 */
2673 memset(buf, 0, buf_size);
2674 for (range = 0; range < reg_ranges_size; range += 2) {
2675 unsigned int reg = reg_ranges[range];
2676 unsigned int last_reg = reg_ranges[range + 1];
2677 u32 *bufp = (u32 *)((char *)buf + reg);
2678
2679 /* Iterate across the register range filling in the register
2680 * buffer but don't write past the end of the register buffer.
2681 */
2682 while (reg <= last_reg && bufp < buf_end) {
2683 *bufp++ = t4_read_reg(adap, reg);
2684 reg += sizeof(u32);
2685 }
2686 }
2687 }
2688
2689 #define EEPROM_STAT_ADDR 0x7bfc
2690 #define VPD_BASE 0x400
2691 #define VPD_BASE_OLD 0
2692 #define VPD_LEN 1024
2693 #define CHELSIO_VPD_UNIQUE_ID 0x82
2694
2695 /**
2696 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2697 * @phys_addr: the physical EEPROM address
2698 * @fn: the PCI function number
2699 * @sz: size of function-specific area
2700 *
2701 * Translate a physical EEPROM address to virtual. The first 1K is
2702 * accessed through virtual addresses starting at 31K, the rest is
2703 * accessed through virtual addresses starting at 0.
2704 *
2705 * The mapping is as follows:
2706 * [0..1K) -> [31K..32K)
2707 * [1K..1K+A) -> [31K-A..31K)
2708 * [1K+A..ES) -> [0..ES-A-1K)
2709 *
2710 * where A = @fn * @sz, and ES = EEPROM size.
2711 */
t4_eeprom_ptov(unsigned int phys_addr,unsigned int fn,unsigned int sz)2712 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2713 {
2714 fn *= sz;
2715 if (phys_addr < 1024)
2716 return phys_addr + (31 << 10);
2717 if (phys_addr < 1024 + fn)
2718 return 31744 - fn + phys_addr - 1024;
2719 if (phys_addr < EEPROMSIZE)
2720 return phys_addr - 1024 - fn;
2721 return -EINVAL;
2722 }
2723
2724 /**
2725 * t4_seeprom_wp - enable/disable EEPROM write protection
2726 * @adapter: the adapter
2727 * @enable: whether to enable or disable write protection
2728 *
2729 * Enables or disables write protection on the serial EEPROM.
2730 */
t4_seeprom_wp(struct adapter * adapter,bool enable)2731 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2732 {
2733 unsigned int v = enable ? 0xc : 0;
2734 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2735 return ret < 0 ? ret : 0;
2736 }
2737
2738 /**
2739 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2740 * @adapter: adapter to read
2741 * @p: where to store the parameters
2742 *
2743 * Reads card parameters stored in VPD EEPROM.
2744 */
t4_get_raw_vpd_params(struct adapter * adapter,struct vpd_params * p)2745 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2746 {
2747 int i, ret = 0, addr;
2748 int ec, sn, pn, na;
2749 u8 *vpd, csum;
2750 unsigned int vpdr_len, kw_offset, id_len;
2751
2752 vpd = vmalloc(VPD_LEN);
2753 if (!vpd)
2754 return -ENOMEM;
2755
2756 /* Card information normally starts at VPD_BASE but early cards had
2757 * it at 0.
2758 */
2759 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2760 if (ret < 0)
2761 goto out;
2762
2763 /* The VPD shall have a unique identifier specified by the PCI SIG.
2764 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2765 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2766 * is expected to automatically put this entry at the
2767 * beginning of the VPD.
2768 */
2769 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2770
2771 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2772 if (ret < 0)
2773 goto out;
2774
2775 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2776 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2777 ret = -EINVAL;
2778 goto out;
2779 }
2780
2781 id_len = pci_vpd_lrdt_size(vpd);
2782 if (id_len > ID_LEN)
2783 id_len = ID_LEN;
2784
2785 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2786 if (i < 0) {
2787 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2788 ret = -EINVAL;
2789 goto out;
2790 }
2791
2792 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2793 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2794 if (vpdr_len + kw_offset > VPD_LEN) {
2795 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2796 ret = -EINVAL;
2797 goto out;
2798 }
2799
2800 #define FIND_VPD_KW(var, name) do { \
2801 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2802 if (var < 0) { \
2803 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2804 ret = -EINVAL; \
2805 goto out; \
2806 } \
2807 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2808 } while (0)
2809
2810 FIND_VPD_KW(i, "RV");
2811 for (csum = 0; i >= 0; i--)
2812 csum += vpd[i];
2813
2814 if (csum) {
2815 dev_err(adapter->pdev_dev,
2816 "corrupted VPD EEPROM, actual csum %u\n", csum);
2817 ret = -EINVAL;
2818 goto out;
2819 }
2820
2821 FIND_VPD_KW(ec, "EC");
2822 FIND_VPD_KW(sn, "SN");
2823 FIND_VPD_KW(pn, "PN");
2824 FIND_VPD_KW(na, "NA");
2825 #undef FIND_VPD_KW
2826
2827 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2828 strim(p->id);
2829 memcpy(p->ec, vpd + ec, EC_LEN);
2830 strim(p->ec);
2831 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2832 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2833 strim(p->sn);
2834 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2835 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2836 strim(p->pn);
2837 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2838 strim((char *)p->na);
2839
2840 out:
2841 vfree(vpd);
2842 return ret < 0 ? ret : 0;
2843 }
2844
2845 /**
2846 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2847 * @adapter: adapter to read
2848 * @p: where to store the parameters
2849 *
2850 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2851 * Clock. This can only be called after a connection to the firmware
2852 * is established.
2853 */
t4_get_vpd_params(struct adapter * adapter,struct vpd_params * p)2854 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2855 {
2856 u32 cclk_param, cclk_val;
2857 int ret;
2858
2859 /* Grab the raw VPD parameters.
2860 */
2861 ret = t4_get_raw_vpd_params(adapter, p);
2862 if (ret)
2863 return ret;
2864
2865 /* Ask firmware for the Core Clock since it knows how to translate the
2866 * Reference Clock ('V2') VPD field into a Core Clock value ...
2867 */
2868 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2869 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2870 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2871 1, &cclk_param, &cclk_val);
2872
2873 if (ret)
2874 return ret;
2875 p->cclk = cclk_val;
2876
2877 return 0;
2878 }
2879
2880 /**
2881 * t4_get_pfres - retrieve VF resource limits
2882 * @adapter: the adapter
2883 *
2884 * Retrieves configured resource limits and capabilities for a physical
2885 * function. The results are stored in @adapter->pfres.
2886 */
t4_get_pfres(struct adapter * adapter)2887 int t4_get_pfres(struct adapter *adapter)
2888 {
2889 struct pf_resources *pfres = &adapter->params.pfres;
2890 struct fw_pfvf_cmd cmd, rpl;
2891 int v;
2892 u32 word;
2893
2894 /* Execute PFVF Read command to get VF resource limits; bail out early
2895 * with error on command failure.
2896 */
2897 memset(&cmd, 0, sizeof(cmd));
2898 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
2899 FW_CMD_REQUEST_F |
2900 FW_CMD_READ_F |
2901 FW_PFVF_CMD_PFN_V(adapter->pf) |
2902 FW_PFVF_CMD_VFN_V(0));
2903 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2904 v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2905 if (v != FW_SUCCESS)
2906 return v;
2907
2908 /* Extract PF resource limits and return success.
2909 */
2910 word = be32_to_cpu(rpl.niqflint_niq);
2911 pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
2912 pfres->niq = FW_PFVF_CMD_NIQ_G(word);
2913
2914 word = be32_to_cpu(rpl.type_to_neq);
2915 pfres->neq = FW_PFVF_CMD_NEQ_G(word);
2916 pfres->pmask = FW_PFVF_CMD_PMASK_G(word);
2917
2918 word = be32_to_cpu(rpl.tc_to_nexactf);
2919 pfres->tc = FW_PFVF_CMD_TC_G(word);
2920 pfres->nvi = FW_PFVF_CMD_NVI_G(word);
2921 pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
2922
2923 word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2924 pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
2925 pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
2926 pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
2927
2928 return 0;
2929 }
2930
2931 /* serial flash and firmware constants */
2932 enum {
2933 SF_ATTEMPTS = 10, /* max retries for SF operations */
2934
2935 /* flash command opcodes */
2936 SF_PROG_PAGE = 2, /* program page */
2937 SF_WR_DISABLE = 4, /* disable writes */
2938 SF_RD_STATUS = 5, /* read status register */
2939 SF_WR_ENABLE = 6, /* enable writes */
2940 SF_RD_DATA_FAST = 0xb, /* read flash */
2941 SF_RD_ID = 0x9f, /* read ID */
2942 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2943 };
2944
2945 /**
2946 * sf1_read - read data from the serial flash
2947 * @adapter: the adapter
2948 * @byte_cnt: number of bytes to read
2949 * @cont: whether another operation will be chained
2950 * @lock: whether to lock SF for PL access only
2951 * @valp: where to store the read data
2952 *
2953 * Reads up to 4 bytes of data from the serial flash. The location of
2954 * the read needs to be specified prior to calling this by issuing the
2955 * appropriate commands to the serial flash.
2956 */
sf1_read(struct adapter * adapter,unsigned int byte_cnt,int cont,int lock,u32 * valp)2957 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2958 int lock, u32 *valp)
2959 {
2960 int ret;
2961
2962 if (!byte_cnt || byte_cnt > 4)
2963 return -EINVAL;
2964 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2965 return -EBUSY;
2966 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2967 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2968 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2969 if (!ret)
2970 *valp = t4_read_reg(adapter, SF_DATA_A);
2971 return ret;
2972 }
2973
2974 /**
2975 * sf1_write - write data to the serial flash
2976 * @adapter: the adapter
2977 * @byte_cnt: number of bytes to write
2978 * @cont: whether another operation will be chained
2979 * @lock: whether to lock SF for PL access only
2980 * @val: value to write
2981 *
2982 * Writes up to 4 bytes of data to the serial flash. The location of
2983 * the write needs to be specified prior to calling this by issuing the
2984 * appropriate commands to the serial flash.
2985 */
sf1_write(struct adapter * adapter,unsigned int byte_cnt,int cont,int lock,u32 val)2986 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2987 int lock, u32 val)
2988 {
2989 if (!byte_cnt || byte_cnt > 4)
2990 return -EINVAL;
2991 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2992 return -EBUSY;
2993 t4_write_reg(adapter, SF_DATA_A, val);
2994 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2995 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2996 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2997 }
2998
2999 /**
3000 * flash_wait_op - wait for a flash operation to complete
3001 * @adapter: the adapter
3002 * @attempts: max number of polls of the status register
3003 * @delay: delay between polls in ms
3004 *
3005 * Wait for a flash operation to complete by polling the status register.
3006 */
flash_wait_op(struct adapter * adapter,int attempts,int delay)3007 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3008 {
3009 int ret;
3010 u32 status;
3011
3012 while (1) {
3013 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3014 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3015 return ret;
3016 if (!(status & 1))
3017 return 0;
3018 if (--attempts == 0)
3019 return -EAGAIN;
3020 if (delay)
3021 msleep(delay);
3022 }
3023 }
3024
3025 /**
3026 * t4_read_flash - read words from serial flash
3027 * @adapter: the adapter
3028 * @addr: the start address for the read
3029 * @nwords: how many 32-bit words to read
3030 * @data: where to store the read data
3031 * @byte_oriented: whether to store data as bytes or as words
3032 *
3033 * Read the specified number of 32-bit words from the serial flash.
3034 * If @byte_oriented is set the read data is stored as a byte array
3035 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3036 * natural endianness.
3037 */
t4_read_flash(struct adapter * adapter,unsigned int addr,unsigned int nwords,u32 * data,int byte_oriented)3038 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3039 unsigned int nwords, u32 *data, int byte_oriented)
3040 {
3041 int ret;
3042
3043 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3044 return -EINVAL;
3045
3046 addr = swab32(addr) | SF_RD_DATA_FAST;
3047
3048 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3049 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3050 return ret;
3051
3052 for ( ; nwords; nwords--, data++) {
3053 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3054 if (nwords == 1)
3055 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3056 if (ret)
3057 return ret;
3058 if (byte_oriented)
3059 *data = (__force __u32)(cpu_to_be32(*data));
3060 }
3061 return 0;
3062 }
3063
3064 /**
3065 * t4_write_flash - write up to a page of data to the serial flash
3066 * @adapter: the adapter
3067 * @addr: the start address to write
3068 * @n: length of data to write in bytes
3069 * @data: the data to write
3070 * @byte_oriented: whether to store data as bytes or as words
3071 *
3072 * Writes up to a page of data (256 bytes) to the serial flash starting
3073 * at the given address. All the data must be written to the same page.
3074 * If @byte_oriented is set the write data is stored as byte stream
3075 * (i.e. matches what on disk), otherwise in big-endian.
3076 */
t4_write_flash(struct adapter * adapter,unsigned int addr,unsigned int n,const u8 * data,bool byte_oriented)3077 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3078 unsigned int n, const u8 *data, bool byte_oriented)
3079 {
3080 unsigned int i, c, left, val, offset = addr & 0xff;
3081 u32 buf[64];
3082 int ret;
3083
3084 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3085 return -EINVAL;
3086
3087 val = swab32(addr) | SF_PROG_PAGE;
3088
3089 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3090 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3091 goto unlock;
3092
3093 for (left = n; left; left -= c, data += c) {
3094 c = min(left, 4U);
3095 for (val = 0, i = 0; i < c; ++i) {
3096 if (byte_oriented)
3097 val = (val << 8) + data[i];
3098 else
3099 val = (val << 8) + data[c - i - 1];
3100 }
3101
3102 ret = sf1_write(adapter, c, c != left, 1, val);
3103 if (ret)
3104 goto unlock;
3105 }
3106 ret = flash_wait_op(adapter, 8, 1);
3107 if (ret)
3108 goto unlock;
3109
3110 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3111
3112 /* Read the page to verify the write succeeded */
3113 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3114 byte_oriented);
3115 if (ret)
3116 return ret;
3117
3118 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3119 dev_err(adapter->pdev_dev,
3120 "failed to correctly write the flash page at %#x\n",
3121 addr);
3122 return -EIO;
3123 }
3124 return 0;
3125
3126 unlock:
3127 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3128 return ret;
3129 }
3130
3131 /**
3132 * t4_get_fw_version - read the firmware version
3133 * @adapter: the adapter
3134 * @vers: where to place the version
3135 *
3136 * Reads the FW version from flash.
3137 */
t4_get_fw_version(struct adapter * adapter,u32 * vers)3138 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3139 {
3140 return t4_read_flash(adapter, FLASH_FW_START +
3141 offsetof(struct fw_hdr, fw_ver), 1,
3142 vers, 0);
3143 }
3144
3145 /**
3146 * t4_get_bs_version - read the firmware bootstrap version
3147 * @adapter: the adapter
3148 * @vers: where to place the version
3149 *
3150 * Reads the FW Bootstrap version from flash.
3151 */
t4_get_bs_version(struct adapter * adapter,u32 * vers)3152 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3153 {
3154 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3155 offsetof(struct fw_hdr, fw_ver), 1,
3156 vers, 0);
3157 }
3158
3159 /**
3160 * t4_get_tp_version - read the TP microcode version
3161 * @adapter: the adapter
3162 * @vers: where to place the version
3163 *
3164 * Reads the TP microcode version from flash.
3165 */
t4_get_tp_version(struct adapter * adapter,u32 * vers)3166 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3167 {
3168 return t4_read_flash(adapter, FLASH_FW_START +
3169 offsetof(struct fw_hdr, tp_microcode_ver),
3170 1, vers, 0);
3171 }
3172
3173 /**
3174 * t4_get_exprom_version - return the Expansion ROM version (if any)
3175 * @adap: the adapter
3176 * @vers: where to place the version
3177 *
3178 * Reads the Expansion ROM header from FLASH and returns the version
3179 * number (if present) through the @vers return value pointer. We return
3180 * this in the Firmware Version Format since it's convenient. Return
3181 * 0 on success, -ENOENT if no Expansion ROM is present.
3182 */
t4_get_exprom_version(struct adapter * adap,u32 * vers)3183 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3184 {
3185 struct exprom_header {
3186 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3187 unsigned char hdr_ver[4]; /* Expansion ROM version */
3188 } *hdr;
3189 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3190 sizeof(u32))];
3191 int ret;
3192
3193 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3194 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3195 0);
3196 if (ret)
3197 return ret;
3198
3199 hdr = (struct exprom_header *)exprom_header_buf;
3200 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3201 return -ENOENT;
3202
3203 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3204 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3205 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3206 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3207 return 0;
3208 }
3209
3210 /**
3211 * t4_get_vpd_version - return the VPD version
3212 * @adapter: the adapter
3213 * @vers: where to place the version
3214 *
3215 * Reads the VPD via the Firmware interface (thus this can only be called
3216 * once we're ready to issue Firmware commands). The format of the
3217 * VPD version is adapter specific. Returns 0 on success, an error on
3218 * failure.
3219 *
3220 * Note that early versions of the Firmware didn't include the ability
3221 * to retrieve the VPD version, so we zero-out the return-value parameter
3222 * in that case to avoid leaving it with garbage in it.
3223 *
3224 * Also note that the Firmware will return its cached copy of the VPD
3225 * Revision ID, not the actual Revision ID as written in the Serial
3226 * EEPROM. This is only an issue if a new VPD has been written and the
3227 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3228 * to defer calling this routine till after a FW_RESET_CMD has been issued
3229 * if the Host Driver will be performing a full adapter initialization.
3230 */
t4_get_vpd_version(struct adapter * adapter,u32 * vers)3231 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3232 {
3233 u32 vpdrev_param;
3234 int ret;
3235
3236 vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3237 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3238 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3239 1, &vpdrev_param, vers);
3240 if (ret)
3241 *vers = 0;
3242 return ret;
3243 }
3244
3245 /**
3246 * t4_get_scfg_version - return the Serial Configuration version
3247 * @adapter: the adapter
3248 * @vers: where to place the version
3249 *
3250 * Reads the Serial Configuration Version via the Firmware interface
3251 * (thus this can only be called once we're ready to issue Firmware
3252 * commands). The format of the Serial Configuration version is
3253 * adapter specific. Returns 0 on success, an error on failure.
3254 *
3255 * Note that early versions of the Firmware didn't include the ability
3256 * to retrieve the Serial Configuration version, so we zero-out the
3257 * return-value parameter in that case to avoid leaving it with
3258 * garbage in it.
3259 *
3260 * Also note that the Firmware will return its cached copy of the Serial
3261 * Initialization Revision ID, not the actual Revision ID as written in
3262 * the Serial EEPROM. This is only an issue if a new VPD has been written
3263 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3264 * it's best to defer calling this routine till after a FW_RESET_CMD has
3265 * been issued if the Host Driver will be performing a full adapter
3266 * initialization.
3267 */
t4_get_scfg_version(struct adapter * adapter,u32 * vers)3268 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3269 {
3270 u32 scfgrev_param;
3271 int ret;
3272
3273 scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3274 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3275 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3276 1, &scfgrev_param, vers);
3277 if (ret)
3278 *vers = 0;
3279 return ret;
3280 }
3281
3282 /**
3283 * t4_get_version_info - extract various chip/firmware version information
3284 * @adapter: the adapter
3285 *
3286 * Reads various chip/firmware version numbers and stores them into the
3287 * adapter Adapter Parameters structure. If any of the efforts fails
3288 * the first failure will be returned, but all of the version numbers
3289 * will be read.
3290 */
t4_get_version_info(struct adapter * adapter)3291 int t4_get_version_info(struct adapter *adapter)
3292 {
3293 int ret = 0;
3294
3295 #define FIRST_RET(__getvinfo) \
3296 do { \
3297 int __ret = __getvinfo; \
3298 if (__ret && !ret) \
3299 ret = __ret; \
3300 } while (0)
3301
3302 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3303 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3304 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3305 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3306 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3307 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3308
3309 #undef FIRST_RET
3310 return ret;
3311 }
3312
3313 /**
3314 * t4_dump_version_info - dump all of the adapter configuration IDs
3315 * @adapter: the adapter
3316 *
3317 * Dumps all of the various bits of adapter configuration version/revision
3318 * IDs information. This is typically called at some point after
3319 * t4_get_version_info() has been called.
3320 */
t4_dump_version_info(struct adapter * adapter)3321 void t4_dump_version_info(struct adapter *adapter)
3322 {
3323 /* Device information */
3324 dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3325 adapter->params.vpd.id,
3326 CHELSIO_CHIP_RELEASE(adapter->params.chip));
3327 dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3328 adapter->params.vpd.sn, adapter->params.vpd.pn);
3329
3330 /* Firmware Version */
3331 if (!adapter->params.fw_vers)
3332 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3333 else
3334 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3335 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3336 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3337 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3338 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3339
3340 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3341 * Firmware, so dev_info() is more appropriate here.)
3342 */
3343 if (!adapter->params.bs_vers)
3344 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3345 else
3346 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3347 FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3348 FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3349 FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3350 FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3351
3352 /* TP Microcode Version */
3353 if (!adapter->params.tp_vers)
3354 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3355 else
3356 dev_info(adapter->pdev_dev,
3357 "TP Microcode version: %u.%u.%u.%u\n",
3358 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3359 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3360 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3361 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3362
3363 /* Expansion ROM version */
3364 if (!adapter->params.er_vers)
3365 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3366 else
3367 dev_info(adapter->pdev_dev,
3368 "Expansion ROM version: %u.%u.%u.%u\n",
3369 FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3370 FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3371 FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3372 FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3373
3374 /* Serial Configuration version */
3375 dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3376 adapter->params.scfg_vers);
3377
3378 /* VPD Version */
3379 dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3380 adapter->params.vpd_vers);
3381 }
3382
3383 /**
3384 * t4_check_fw_version - check if the FW is supported with this driver
3385 * @adap: the adapter
3386 *
3387 * Checks if an adapter's FW is compatible with the driver. Returns 0
3388 * if there's exact match, a negative error if the version could not be
3389 * read or there's a major version mismatch
3390 */
t4_check_fw_version(struct adapter * adap)3391 int t4_check_fw_version(struct adapter *adap)
3392 {
3393 int i, ret, major, minor, micro;
3394 int exp_major, exp_minor, exp_micro;
3395 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3396
3397 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3398 /* Try multiple times before returning error */
3399 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3400 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3401
3402 if (ret)
3403 return ret;
3404
3405 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3406 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3407 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3408
3409 switch (chip_version) {
3410 case CHELSIO_T4:
3411 exp_major = T4FW_MIN_VERSION_MAJOR;
3412 exp_minor = T4FW_MIN_VERSION_MINOR;
3413 exp_micro = T4FW_MIN_VERSION_MICRO;
3414 break;
3415 case CHELSIO_T5:
3416 exp_major = T5FW_MIN_VERSION_MAJOR;
3417 exp_minor = T5FW_MIN_VERSION_MINOR;
3418 exp_micro = T5FW_MIN_VERSION_MICRO;
3419 break;
3420 case CHELSIO_T6:
3421 exp_major = T6FW_MIN_VERSION_MAJOR;
3422 exp_minor = T6FW_MIN_VERSION_MINOR;
3423 exp_micro = T6FW_MIN_VERSION_MICRO;
3424 break;
3425 default:
3426 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3427 adap->chip);
3428 return -EINVAL;
3429 }
3430
3431 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3432 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3433 dev_err(adap->pdev_dev,
3434 "Card has firmware version %u.%u.%u, minimum "
3435 "supported firmware is %u.%u.%u.\n", major, minor,
3436 micro, exp_major, exp_minor, exp_micro);
3437 return -EFAULT;
3438 }
3439 return 0;
3440 }
3441
3442 /* Is the given firmware API compatible with the one the driver was compiled
3443 * with?
3444 */
fw_compatible(const struct fw_hdr * hdr1,const struct fw_hdr * hdr2)3445 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3446 {
3447
3448 /* short circuit if it's the exact same firmware version */
3449 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3450 return 1;
3451
3452 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3453 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3454 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3455 return 1;
3456 #undef SAME_INTF
3457
3458 return 0;
3459 }
3460
3461 /* The firmware in the filesystem is usable, but should it be installed?
3462 * This routine explains itself in detail if it indicates the filesystem
3463 * firmware should be installed.
3464 */
should_install_fs_fw(struct adapter * adap,int card_fw_usable,int k,int c)3465 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3466 int k, int c)
3467 {
3468 const char *reason;
3469
3470 if (!card_fw_usable) {
3471 reason = "incompatible or unusable";
3472 goto install;
3473 }
3474
3475 if (k > c) {
3476 reason = "older than the version supported with this driver";
3477 goto install;
3478 }
3479
3480 return 0;
3481
3482 install:
3483 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3484 "installing firmware %u.%u.%u.%u on card.\n",
3485 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3486 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3487 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3488 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3489
3490 return 1;
3491 }
3492
t4_prep_fw(struct adapter * adap,struct fw_info * fw_info,const u8 * fw_data,unsigned int fw_size,struct fw_hdr * card_fw,enum dev_state state,int * reset)3493 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3494 const u8 *fw_data, unsigned int fw_size,
3495 struct fw_hdr *card_fw, enum dev_state state,
3496 int *reset)
3497 {
3498 int ret, card_fw_usable, fs_fw_usable;
3499 const struct fw_hdr *fs_fw;
3500 const struct fw_hdr *drv_fw;
3501
3502 drv_fw = &fw_info->fw_hdr;
3503
3504 /* Read the header of the firmware on the card */
3505 ret = t4_read_flash(adap, FLASH_FW_START,
3506 sizeof(*card_fw) / sizeof(uint32_t),
3507 (uint32_t *)card_fw, 1);
3508 if (ret == 0) {
3509 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3510 } else {
3511 dev_err(adap->pdev_dev,
3512 "Unable to read card's firmware header: %d\n", ret);
3513 card_fw_usable = 0;
3514 }
3515
3516 if (fw_data != NULL) {
3517 fs_fw = (const void *)fw_data;
3518 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3519 } else {
3520 fs_fw = NULL;
3521 fs_fw_usable = 0;
3522 }
3523
3524 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3525 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3526 /* Common case: the firmware on the card is an exact match and
3527 * the filesystem one is an exact match too, or the filesystem
3528 * one is absent/incompatible.
3529 */
3530 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3531 should_install_fs_fw(adap, card_fw_usable,
3532 be32_to_cpu(fs_fw->fw_ver),
3533 be32_to_cpu(card_fw->fw_ver))) {
3534 ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3535 fw_size, 0);
3536 if (ret != 0) {
3537 dev_err(adap->pdev_dev,
3538 "failed to install firmware: %d\n", ret);
3539 goto bye;
3540 }
3541
3542 /* Installed successfully, update the cached header too. */
3543 *card_fw = *fs_fw;
3544 card_fw_usable = 1;
3545 *reset = 0; /* already reset as part of load_fw */
3546 }
3547
3548 if (!card_fw_usable) {
3549 uint32_t d, c, k;
3550
3551 d = be32_to_cpu(drv_fw->fw_ver);
3552 c = be32_to_cpu(card_fw->fw_ver);
3553 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3554
3555 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3556 "chip state %d, "
3557 "driver compiled with %d.%d.%d.%d, "
3558 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3559 state,
3560 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3561 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3562 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3563 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3564 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3565 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3566 ret = -EINVAL;
3567 goto bye;
3568 }
3569
3570 /* We're using whatever's on the card and it's known to be good. */
3571 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3572 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3573
3574 bye:
3575 return ret;
3576 }
3577
3578 /**
3579 * t4_flash_erase_sectors - erase a range of flash sectors
3580 * @adapter: the adapter
3581 * @start: the first sector to erase
3582 * @end: the last sector to erase
3583 *
3584 * Erases the sectors in the given inclusive range.
3585 */
t4_flash_erase_sectors(struct adapter * adapter,int start,int end)3586 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3587 {
3588 int ret = 0;
3589
3590 if (end >= adapter->params.sf_nsec)
3591 return -EINVAL;
3592
3593 while (start <= end) {
3594 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3595 (ret = sf1_write(adapter, 4, 0, 1,
3596 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3597 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3598 dev_err(adapter->pdev_dev,
3599 "erase of flash sector %d failed, error %d\n",
3600 start, ret);
3601 break;
3602 }
3603 start++;
3604 }
3605 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3606 return ret;
3607 }
3608
3609 /**
3610 * t4_flash_cfg_addr - return the address of the flash configuration file
3611 * @adapter: the adapter
3612 *
3613 * Return the address within the flash where the Firmware Configuration
3614 * File is stored.
3615 */
t4_flash_cfg_addr(struct adapter * adapter)3616 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3617 {
3618 if (adapter->params.sf_size == 0x100000)
3619 return FLASH_FPGA_CFG_START;
3620 else
3621 return FLASH_CFG_START;
3622 }
3623
3624 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3625 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3626 * and emit an error message for mismatched firmware to save our caller the
3627 * effort ...
3628 */
t4_fw_matches_chip(const struct adapter * adap,const struct fw_hdr * hdr)3629 static bool t4_fw_matches_chip(const struct adapter *adap,
3630 const struct fw_hdr *hdr)
3631 {
3632 /* The expression below will return FALSE for any unsupported adapter
3633 * which will keep us "honest" in the future ...
3634 */
3635 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3636 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3637 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3638 return true;
3639
3640 dev_err(adap->pdev_dev,
3641 "FW image (%d) is not suitable for this adapter (%d)\n",
3642 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3643 return false;
3644 }
3645
3646 /**
3647 * t4_load_fw - download firmware
3648 * @adap: the adapter
3649 * @fw_data: the firmware image to write
3650 * @size: image size
3651 *
3652 * Write the supplied firmware image to the card's serial flash.
3653 */
t4_load_fw(struct adapter * adap,const u8 * fw_data,unsigned int size)3654 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3655 {
3656 u32 csum;
3657 int ret, addr;
3658 unsigned int i;
3659 u8 first_page[SF_PAGE_SIZE];
3660 const __be32 *p = (const __be32 *)fw_data;
3661 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3662 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3663 unsigned int fw_start_sec = FLASH_FW_START_SEC;
3664 unsigned int fw_size = FLASH_FW_MAX_SIZE;
3665 unsigned int fw_start = FLASH_FW_START;
3666
3667 if (!size) {
3668 dev_err(adap->pdev_dev, "FW image has no data\n");
3669 return -EINVAL;
3670 }
3671 if (size & 511) {
3672 dev_err(adap->pdev_dev,
3673 "FW image size not multiple of 512 bytes\n");
3674 return -EINVAL;
3675 }
3676 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3677 dev_err(adap->pdev_dev,
3678 "FW image size differs from size in FW header\n");
3679 return -EINVAL;
3680 }
3681 if (size > fw_size) {
3682 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3683 fw_size);
3684 return -EFBIG;
3685 }
3686 if (!t4_fw_matches_chip(adap, hdr))
3687 return -EINVAL;
3688
3689 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3690 csum += be32_to_cpu(p[i]);
3691
3692 if (csum != 0xffffffff) {
3693 dev_err(adap->pdev_dev,
3694 "corrupted firmware image, checksum %#x\n", csum);
3695 return -EINVAL;
3696 }
3697
3698 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3699 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3700 if (ret)
3701 goto out;
3702
3703 /*
3704 * We write the correct version at the end so the driver can see a bad
3705 * version if the FW write fails. Start by writing a copy of the
3706 * first page with a bad version.
3707 */
3708 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3709 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3710 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, true);
3711 if (ret)
3712 goto out;
3713
3714 addr = fw_start;
3715 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3716 addr += SF_PAGE_SIZE;
3717 fw_data += SF_PAGE_SIZE;
3718 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, true);
3719 if (ret)
3720 goto out;
3721 }
3722
3723 ret = t4_write_flash(adap, fw_start + offsetof(struct fw_hdr, fw_ver),
3724 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver,
3725 true);
3726 out:
3727 if (ret)
3728 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3729 ret);
3730 else
3731 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3732 return ret;
3733 }
3734
3735 /**
3736 * t4_phy_fw_ver - return current PHY firmware version
3737 * @adap: the adapter
3738 * @phy_fw_ver: return value buffer for PHY firmware version
3739 *
3740 * Returns the current version of external PHY firmware on the
3741 * adapter.
3742 */
t4_phy_fw_ver(struct adapter * adap,int * phy_fw_ver)3743 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3744 {
3745 u32 param, val;
3746 int ret;
3747
3748 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3749 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3750 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3751 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3752 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3753 ¶m, &val);
3754 if (ret)
3755 return ret;
3756 *phy_fw_ver = val;
3757 return 0;
3758 }
3759
3760 /**
3761 * t4_load_phy_fw - download port PHY firmware
3762 * @adap: the adapter
3763 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3764 * @phy_fw_version: function to check PHY firmware versions
3765 * @phy_fw_data: the PHY firmware image to write
3766 * @phy_fw_size: image size
3767 *
3768 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3769 * @phy_fw_version is supplied, then it will be used to determine if
3770 * it's necessary to perform the transfer by comparing the version
3771 * of any existing adapter PHY firmware with that of the passed in
3772 * PHY firmware image.
3773 *
3774 * A negative error number will be returned if an error occurs. If
3775 * version number support is available and there's no need to upgrade
3776 * the firmware, 0 will be returned. If firmware is successfully
3777 * transferred to the adapter, 1 will be returned.
3778 *
3779 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3780 * a result, a RESET of the adapter would cause that RAM to lose its
3781 * contents. Thus, loading PHY firmware on such adapters must happen
3782 * after any FW_RESET_CMDs ...
3783 */
t4_load_phy_fw(struct adapter * adap,int win,int (* phy_fw_version)(const u8 *,size_t),const u8 * phy_fw_data,size_t phy_fw_size)3784 int t4_load_phy_fw(struct adapter *adap, int win,
3785 int (*phy_fw_version)(const u8 *, size_t),
3786 const u8 *phy_fw_data, size_t phy_fw_size)
3787 {
3788 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3789 unsigned long mtype = 0, maddr = 0;
3790 u32 param, val;
3791 int ret;
3792
3793 /* If we have version number support, then check to see if the adapter
3794 * already has up-to-date PHY firmware loaded.
3795 */
3796 if (phy_fw_version) {
3797 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3798 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3799 if (ret < 0)
3800 return ret;
3801
3802 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3803 CH_WARN(adap, "PHY Firmware already up-to-date, "
3804 "version %#x\n", cur_phy_fw_ver);
3805 return 0;
3806 }
3807 }
3808
3809 /* Ask the firmware where it wants us to copy the PHY firmware image.
3810 * The size of the file requires a special version of the READ command
3811 * which will pass the file size via the values field in PARAMS_CMD and
3812 * retrieve the return value from firmware and place it in the same
3813 * buffer values
3814 */
3815 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3816 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3817 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3818 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3819 val = phy_fw_size;
3820 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3821 ¶m, &val, 1, true);
3822 if (ret < 0)
3823 return ret;
3824 mtype = val >> 8;
3825 maddr = (val & 0xff) << 16;
3826
3827 /* Copy the supplied PHY Firmware image to the adapter memory location
3828 * allocated by the adapter firmware.
3829 */
3830 spin_lock_bh(&adap->win0_lock);
3831 ret = t4_memory_rw(adap, win, mtype, maddr,
3832 phy_fw_size, (__be32 *)phy_fw_data,
3833 T4_MEMORY_WRITE);
3834 spin_unlock_bh(&adap->win0_lock);
3835 if (ret)
3836 return ret;
3837
3838 /* Tell the firmware that the PHY firmware image has been written to
3839 * RAM and it can now start copying it over to the PHYs. The chip
3840 * firmware will RESET the affected PHYs as part of this operation
3841 * leaving them running the new PHY firmware image.
3842 */
3843 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3844 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3845 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3846 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3847 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3848 ¶m, &val, 30000);
3849
3850 /* If we have version number support, then check to see that the new
3851 * firmware got loaded properly.
3852 */
3853 if (phy_fw_version) {
3854 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3855 if (ret < 0)
3856 return ret;
3857
3858 if (cur_phy_fw_ver != new_phy_fw_vers) {
3859 CH_WARN(adap, "PHY Firmware did not update: "
3860 "version on adapter %#x, "
3861 "version flashed %#x\n",
3862 cur_phy_fw_ver, new_phy_fw_vers);
3863 return -ENXIO;
3864 }
3865 }
3866
3867 return 1;
3868 }
3869
3870 /**
3871 * t4_fwcache - firmware cache operation
3872 * @adap: the adapter
3873 * @op : the operation (flush or flush and invalidate)
3874 */
t4_fwcache(struct adapter * adap,enum fw_params_param_dev_fwcache op)3875 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3876 {
3877 struct fw_params_cmd c;
3878
3879 memset(&c, 0, sizeof(c));
3880 c.op_to_vfn =
3881 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3882 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3883 FW_PARAMS_CMD_PFN_V(adap->pf) |
3884 FW_PARAMS_CMD_VFN_V(0));
3885 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3886 c.param[0].mnem =
3887 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3888 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3889 c.param[0].val = cpu_to_be32(op);
3890
3891 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3892 }
3893
t4_cim_read_pif_la(struct adapter * adap,u32 * pif_req,u32 * pif_rsp,unsigned int * pif_req_wrptr,unsigned int * pif_rsp_wrptr)3894 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3895 unsigned int *pif_req_wrptr,
3896 unsigned int *pif_rsp_wrptr)
3897 {
3898 int i, j;
3899 u32 cfg, val, req, rsp;
3900
3901 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3902 if (cfg & LADBGEN_F)
3903 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3904
3905 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3906 req = POLADBGWRPTR_G(val);
3907 rsp = PILADBGWRPTR_G(val);
3908 if (pif_req_wrptr)
3909 *pif_req_wrptr = req;
3910 if (pif_rsp_wrptr)
3911 *pif_rsp_wrptr = rsp;
3912
3913 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3914 for (j = 0; j < 6; j++) {
3915 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3916 PILADBGRDPTR_V(rsp));
3917 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3918 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3919 req++;
3920 rsp++;
3921 }
3922 req = (req + 2) & POLADBGRDPTR_M;
3923 rsp = (rsp + 2) & PILADBGRDPTR_M;
3924 }
3925 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3926 }
3927
t4_cim_read_ma_la(struct adapter * adap,u32 * ma_req,u32 * ma_rsp)3928 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3929 {
3930 u32 cfg;
3931 int i, j, idx;
3932
3933 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3934 if (cfg & LADBGEN_F)
3935 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3936
3937 for (i = 0; i < CIM_MALA_SIZE; i++) {
3938 for (j = 0; j < 5; j++) {
3939 idx = 8 * i + j;
3940 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3941 PILADBGRDPTR_V(idx));
3942 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3943 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3944 }
3945 }
3946 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3947 }
3948
t4_ulprx_read_la(struct adapter * adap,u32 * la_buf)3949 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3950 {
3951 unsigned int i, j;
3952
3953 for (i = 0; i < 8; i++) {
3954 u32 *p = la_buf + i;
3955
3956 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3957 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3958 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3959 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3960 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3961 }
3962 }
3963
3964 /* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3965 * Capabilities which we control with separate controls -- see, for instance,
3966 * Pause Frames and Forward Error Correction. In order to determine what the
3967 * full set of Advertised Port Capabilities are, the base Advertised Port
3968 * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3969 * Port Capabilities associated with those other controls. See
3970 * t4_link_acaps() for how this is done.
3971 */
3972 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3973 FW_PORT_CAP32_ANEG)
3974
3975 /**
3976 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3977 * @caps16: a 16-bit Port Capabilities value
3978 *
3979 * Returns the equivalent 32-bit Port Capabilities value.
3980 */
fwcaps16_to_caps32(fw_port_cap16_t caps16)3981 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3982 {
3983 fw_port_cap32_t caps32 = 0;
3984
3985 #define CAP16_TO_CAP32(__cap) \
3986 do { \
3987 if (caps16 & FW_PORT_CAP_##__cap) \
3988 caps32 |= FW_PORT_CAP32_##__cap; \
3989 } while (0)
3990
3991 CAP16_TO_CAP32(SPEED_100M);
3992 CAP16_TO_CAP32(SPEED_1G);
3993 CAP16_TO_CAP32(SPEED_25G);
3994 CAP16_TO_CAP32(SPEED_10G);
3995 CAP16_TO_CAP32(SPEED_40G);
3996 CAP16_TO_CAP32(SPEED_100G);
3997 CAP16_TO_CAP32(FC_RX);
3998 CAP16_TO_CAP32(FC_TX);
3999 CAP16_TO_CAP32(ANEG);
4000 CAP16_TO_CAP32(FORCE_PAUSE);
4001 CAP16_TO_CAP32(MDIAUTO);
4002 CAP16_TO_CAP32(MDISTRAIGHT);
4003 CAP16_TO_CAP32(FEC_RS);
4004 CAP16_TO_CAP32(FEC_BASER_RS);
4005 CAP16_TO_CAP32(802_3_PAUSE);
4006 CAP16_TO_CAP32(802_3_ASM_DIR);
4007
4008 #undef CAP16_TO_CAP32
4009
4010 return caps32;
4011 }
4012
4013 /**
4014 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4015 * @caps32: a 32-bit Port Capabilities value
4016 *
4017 * Returns the equivalent 16-bit Port Capabilities value. Note that
4018 * not all 32-bit Port Capabilities can be represented in the 16-bit
4019 * Port Capabilities and some fields/values may not make it.
4020 */
fwcaps32_to_caps16(fw_port_cap32_t caps32)4021 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
4022 {
4023 fw_port_cap16_t caps16 = 0;
4024
4025 #define CAP32_TO_CAP16(__cap) \
4026 do { \
4027 if (caps32 & FW_PORT_CAP32_##__cap) \
4028 caps16 |= FW_PORT_CAP_##__cap; \
4029 } while (0)
4030
4031 CAP32_TO_CAP16(SPEED_100M);
4032 CAP32_TO_CAP16(SPEED_1G);
4033 CAP32_TO_CAP16(SPEED_10G);
4034 CAP32_TO_CAP16(SPEED_25G);
4035 CAP32_TO_CAP16(SPEED_40G);
4036 CAP32_TO_CAP16(SPEED_100G);
4037 CAP32_TO_CAP16(FC_RX);
4038 CAP32_TO_CAP16(FC_TX);
4039 CAP32_TO_CAP16(802_3_PAUSE);
4040 CAP32_TO_CAP16(802_3_ASM_DIR);
4041 CAP32_TO_CAP16(ANEG);
4042 CAP32_TO_CAP16(FORCE_PAUSE);
4043 CAP32_TO_CAP16(MDIAUTO);
4044 CAP32_TO_CAP16(MDISTRAIGHT);
4045 CAP32_TO_CAP16(FEC_RS);
4046 CAP32_TO_CAP16(FEC_BASER_RS);
4047
4048 #undef CAP32_TO_CAP16
4049
4050 return caps16;
4051 }
4052
4053 /* Translate Firmware Port Capabilities Pause specification to Common Code */
fwcap_to_cc_pause(fw_port_cap32_t fw_pause)4054 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4055 {
4056 enum cc_pause cc_pause = 0;
4057
4058 if (fw_pause & FW_PORT_CAP32_FC_RX)
4059 cc_pause |= PAUSE_RX;
4060 if (fw_pause & FW_PORT_CAP32_FC_TX)
4061 cc_pause |= PAUSE_TX;
4062
4063 return cc_pause;
4064 }
4065
4066 /* Translate Common Code Pause specification into Firmware Port Capabilities */
cc_to_fwcap_pause(enum cc_pause cc_pause)4067 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4068 {
4069 /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4070 * commands, etc.
4071 */
4072 fw_port_cap32_t fw_pause = 0;
4073
4074 if (cc_pause & PAUSE_RX)
4075 fw_pause |= FW_PORT_CAP32_FC_RX;
4076 if (cc_pause & PAUSE_TX)
4077 fw_pause |= FW_PORT_CAP32_FC_TX;
4078 if (!(cc_pause & PAUSE_AUTONEG))
4079 fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4080
4081 /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4082 * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4083 * Note that these bits are ignored in L1 Configure commands.
4084 */
4085 if (cc_pause & PAUSE_RX) {
4086 if (cc_pause & PAUSE_TX)
4087 fw_pause |= FW_PORT_CAP32_802_3_PAUSE;
4088 else
4089 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR |
4090 FW_PORT_CAP32_802_3_PAUSE;
4091 } else if (cc_pause & PAUSE_TX) {
4092 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR;
4093 }
4094
4095 return fw_pause;
4096 }
4097
4098 /* Translate Firmware Forward Error Correction specification to Common Code */
fwcap_to_cc_fec(fw_port_cap32_t fw_fec)4099 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4100 {
4101 enum cc_fec cc_fec = 0;
4102
4103 if (fw_fec & FW_PORT_CAP32_FEC_RS)
4104 cc_fec |= FEC_RS;
4105 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4106 cc_fec |= FEC_BASER_RS;
4107
4108 return cc_fec;
4109 }
4110
4111 /* Translate Common Code Forward Error Correction specification to Firmware */
cc_to_fwcap_fec(enum cc_fec cc_fec)4112 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4113 {
4114 fw_port_cap32_t fw_fec = 0;
4115
4116 if (cc_fec & FEC_RS)
4117 fw_fec |= FW_PORT_CAP32_FEC_RS;
4118 if (cc_fec & FEC_BASER_RS)
4119 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4120
4121 return fw_fec;
4122 }
4123
4124 /**
4125 * t4_link_acaps - compute Link Advertised Port Capabilities
4126 * @adapter: the adapter
4127 * @port: the Port ID
4128 * @lc: the Port's Link Configuration
4129 *
4130 * Synthesize the Advertised Port Capabilities we'll be using based on
4131 * the base Advertised Port Capabilities (which have been filtered by
4132 * ADVERT_MASK) plus the individual controls for things like Pause
4133 * Frames, Forward Error Correction, MDI, etc.
4134 */
t4_link_acaps(struct adapter * adapter,unsigned int port,struct link_config * lc)4135 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
4136 struct link_config *lc)
4137 {
4138 fw_port_cap32_t fw_fc, fw_fec, acaps;
4139 unsigned int fw_mdi;
4140 char cc_fec;
4141
4142 fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4143
4144 /* Convert driver coding of Pause Frame Flow Control settings into the
4145 * Firmware's API.
4146 */
4147 fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4148
4149 /* Convert Common Code Forward Error Control settings into the
4150 * Firmware's API. If the current Requested FEC has "Automatic"
4151 * (IEEE 802.3) specified, then we use whatever the Firmware
4152 * sent us as part of its IEEE 802.3-based interpretation of
4153 * the Transceiver Module EPROM FEC parameters. Otherwise we
4154 * use whatever is in the current Requested FEC settings.
4155 */
4156 if (lc->requested_fec & FEC_AUTO)
4157 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4158 else
4159 cc_fec = lc->requested_fec;
4160 fw_fec = cc_to_fwcap_fec(cc_fec);
4161
4162 /* Figure out what our Requested Port Capabilities are going to be.
4163 * Note parallel structure in t4_handle_get_port_info() and
4164 * init_link_config().
4165 */
4166 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4167 acaps = lc->acaps | fw_fc | fw_fec;
4168 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4169 lc->fec = cc_fec;
4170 } else if (lc->autoneg == AUTONEG_DISABLE) {
4171 acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4172 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4173 lc->fec = cc_fec;
4174 } else {
4175 acaps = lc->acaps | fw_fc | fw_fec | fw_mdi;
4176 }
4177
4178 /* Some Requested Port Capabilities are trivially wrong if they exceed
4179 * the Physical Port Capabilities. We can check that here and provide
4180 * moderately useful feedback in the system log.
4181 *
4182 * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4183 * we need to exclude this from this check in order to maintain
4184 * compatibility ...
4185 */
4186 if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4187 dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4188 acaps, lc->pcaps);
4189 return -EINVAL;
4190 }
4191
4192 return acaps;
4193 }
4194
4195 /**
4196 * t4_link_l1cfg_core - apply link configuration to MAC/PHY
4197 * @adapter: the adapter
4198 * @mbox: the Firmware Mailbox to use
4199 * @port: the Port ID
4200 * @lc: the Port's Link Configuration
4201 * @sleep_ok: if true we may sleep while awaiting command completion
4202 * @timeout: time to wait for command to finish before timing out
4203 * (negative implies @sleep_ok=false)
4204 *
4205 * Set up a port's MAC and PHY according to a desired link configuration.
4206 * - If the PHY can auto-negotiate first decide what to advertise, then
4207 * enable/disable auto-negotiation as desired, and reset.
4208 * - If the PHY does not auto-negotiate just reset it.
4209 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4210 * otherwise do it later based on the outcome of auto-negotiation.
4211 */
t4_link_l1cfg_core(struct adapter * adapter,unsigned int mbox,unsigned int port,struct link_config * lc,u8 sleep_ok,int timeout)4212 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4213 unsigned int port, struct link_config *lc,
4214 u8 sleep_ok, int timeout)
4215 {
4216 unsigned int fw_caps = adapter->params.fw_caps_support;
4217 struct fw_port_cmd cmd;
4218 fw_port_cap32_t rcap;
4219 int ret;
4220
4221 if (!(lc->pcaps & FW_PORT_CAP32_ANEG) &&
4222 lc->autoneg == AUTONEG_ENABLE) {
4223 return -EINVAL;
4224 }
4225
4226 /* Compute our Requested Port Capabilities and send that on to the
4227 * Firmware.
4228 */
4229 rcap = t4_link_acaps(adapter, port, lc);
4230 memset(&cmd, 0, sizeof(cmd));
4231 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4232 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4233 FW_PORT_CMD_PORTID_V(port));
4234 cmd.action_to_len16 =
4235 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4236 ? FW_PORT_ACTION_L1_CFG
4237 : FW_PORT_ACTION_L1_CFG32) |
4238 FW_LEN16(cmd));
4239 if (fw_caps == FW_CAPS16)
4240 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4241 else
4242 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4243
4244 ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4245 sleep_ok, timeout);
4246
4247 /* Unfortunately, even if the Requested Port Capabilities "fit" within
4248 * the Physical Port Capabilities, some combinations of features may
4249 * still not be legal. For example, 40Gb/s and Reed-Solomon Forward
4250 * Error Correction. So if the Firmware rejects the L1 Configure
4251 * request, flag that here.
4252 */
4253 if (ret) {
4254 dev_err(adapter->pdev_dev,
4255 "Requested Port Capabilities %#x rejected, error %d\n",
4256 rcap, -ret);
4257 return ret;
4258 }
4259 return 0;
4260 }
4261
4262 /**
4263 * t4_restart_aneg - restart autonegotiation
4264 * @adap: the adapter
4265 * @mbox: mbox to use for the FW command
4266 * @port: the port id
4267 *
4268 * Restarts autonegotiation for the selected port.
4269 */
t4_restart_aneg(struct adapter * adap,unsigned int mbox,unsigned int port)4270 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4271 {
4272 unsigned int fw_caps = adap->params.fw_caps_support;
4273 struct fw_port_cmd c;
4274
4275 memset(&c, 0, sizeof(c));
4276 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4277 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4278 FW_PORT_CMD_PORTID_V(port));
4279 c.action_to_len16 =
4280 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4281 ? FW_PORT_ACTION_L1_CFG
4282 : FW_PORT_ACTION_L1_CFG32) |
4283 FW_LEN16(c));
4284 if (fw_caps == FW_CAPS16)
4285 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4286 else
4287 c.u.l1cfg32.rcap32 = cpu_to_be32(FW_PORT_CAP32_ANEG);
4288 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4289 }
4290
4291 typedef void (*int_handler_t)(struct adapter *adap);
4292
4293 struct intr_info {
4294 unsigned int mask; /* bits to check in interrupt status */
4295 const char *msg; /* message to print or NULL */
4296 short stat_idx; /* stat counter to increment or -1 */
4297 unsigned short fatal; /* whether the condition reported is fatal */
4298 int_handler_t int_handler; /* platform-specific int handler */
4299 };
4300
4301 /**
4302 * t4_handle_intr_status - table driven interrupt handler
4303 * @adapter: the adapter that generated the interrupt
4304 * @reg: the interrupt status register to process
4305 * @acts: table of interrupt actions
4306 *
4307 * A table driven interrupt handler that applies a set of masks to an
4308 * interrupt status word and performs the corresponding actions if the
4309 * interrupts described by the mask have occurred. The actions include
4310 * optionally emitting a warning or alert message. The table is terminated
4311 * by an entry specifying mask 0. Returns the number of fatal interrupt
4312 * conditions.
4313 */
t4_handle_intr_status(struct adapter * adapter,unsigned int reg,const struct intr_info * acts)4314 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4315 const struct intr_info *acts)
4316 {
4317 int fatal = 0;
4318 unsigned int mask = 0;
4319 unsigned int status = t4_read_reg(adapter, reg);
4320
4321 for ( ; acts->mask; ++acts) {
4322 if (!(status & acts->mask))
4323 continue;
4324 if (acts->fatal) {
4325 fatal++;
4326 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4327 status & acts->mask);
4328 } else if (acts->msg && printk_ratelimit())
4329 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4330 status & acts->mask);
4331 if (acts->int_handler)
4332 acts->int_handler(adapter);
4333 mask |= acts->mask;
4334 }
4335 status &= mask;
4336 if (status) /* clear processed interrupts */
4337 t4_write_reg(adapter, reg, status);
4338 return fatal;
4339 }
4340
4341 /*
4342 * Interrupt handler for the PCIE module.
4343 */
pcie_intr_handler(struct adapter * adapter)4344 static void pcie_intr_handler(struct adapter *adapter)
4345 {
4346 static const struct intr_info sysbus_intr_info[] = {
4347 { RNPP_F, "RXNP array parity error", -1, 1 },
4348 { RPCP_F, "RXPC array parity error", -1, 1 },
4349 { RCIP_F, "RXCIF array parity error", -1, 1 },
4350 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4351 { RFTP_F, "RXFT array parity error", -1, 1 },
4352 { 0 }
4353 };
4354 static const struct intr_info pcie_port_intr_info[] = {
4355 { TPCP_F, "TXPC array parity error", -1, 1 },
4356 { TNPP_F, "TXNP array parity error", -1, 1 },
4357 { TFTP_F, "TXFT array parity error", -1, 1 },
4358 { TCAP_F, "TXCA array parity error", -1, 1 },
4359 { TCIP_F, "TXCIF array parity error", -1, 1 },
4360 { RCAP_F, "RXCA array parity error", -1, 1 },
4361 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4362 { RDPE_F, "Rx data parity error", -1, 1 },
4363 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4364 { 0 }
4365 };
4366 static const struct intr_info pcie_intr_info[] = {
4367 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4368 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4369 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4370 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4371 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4372 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4373 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4374 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4375 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4376 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4377 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4378 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4379 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4380 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4381 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4382 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4383 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4384 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4385 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4386 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4387 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4388 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4389 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4390 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4391 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4392 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4393 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4394 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4395 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4396 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4397 -1, 0 },
4398 { 0 }
4399 };
4400
4401 static struct intr_info t5_pcie_intr_info[] = {
4402 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4403 -1, 1 },
4404 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4405 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4406 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4407 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4408 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4409 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4410 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4411 -1, 1 },
4412 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4413 -1, 1 },
4414 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4415 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4416 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4417 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4418 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4419 -1, 1 },
4420 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4421 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4422 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4423 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4424 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4425 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4426 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4427 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4428 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4429 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4430 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4431 -1, 1 },
4432 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4433 -1, 1 },
4434 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4435 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4436 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4437 { READRSPERR_F, "Outbound read error", -1, 0 },
4438 { 0 }
4439 };
4440
4441 int fat;
4442
4443 if (is_t4(adapter->params.chip))
4444 fat = t4_handle_intr_status(adapter,
4445 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4446 sysbus_intr_info) +
4447 t4_handle_intr_status(adapter,
4448 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4449 pcie_port_intr_info) +
4450 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4451 pcie_intr_info);
4452 else
4453 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4454 t5_pcie_intr_info);
4455
4456 if (fat)
4457 t4_fatal_err(adapter);
4458 }
4459
4460 /*
4461 * TP interrupt handler.
4462 */
tp_intr_handler(struct adapter * adapter)4463 static void tp_intr_handler(struct adapter *adapter)
4464 {
4465 static const struct intr_info tp_intr_info[] = {
4466 { 0x3fffffff, "TP parity error", -1, 1 },
4467 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4468 { 0 }
4469 };
4470
4471 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4472 t4_fatal_err(adapter);
4473 }
4474
4475 /*
4476 * SGE interrupt handler.
4477 */
sge_intr_handler(struct adapter * adapter)4478 static void sge_intr_handler(struct adapter *adapter)
4479 {
4480 u32 v = 0, perr;
4481 u32 err;
4482
4483 static const struct intr_info sge_intr_info[] = {
4484 { ERR_CPL_EXCEED_IQE_SIZE_F,
4485 "SGE received CPL exceeding IQE size", -1, 1 },
4486 { ERR_INVALID_CIDX_INC_F,
4487 "SGE GTS CIDX increment too large", -1, 0 },
4488 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4489 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4490 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4491 "SGE IQID > 1023 received CPL for FL", -1, 0 },
4492 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4493 0 },
4494 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4495 0 },
4496 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4497 0 },
4498 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4499 0 },
4500 { ERR_ING_CTXT_PRIO_F,
4501 "SGE too many priority ingress contexts", -1, 0 },
4502 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4503 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4504 { 0 }
4505 };
4506
4507 static struct intr_info t4t5_sge_intr_info[] = {
4508 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4509 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4510 { ERR_EGR_CTXT_PRIO_F,
4511 "SGE too many priority egress contexts", -1, 0 },
4512 { 0 }
4513 };
4514
4515 perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
4516 if (perr) {
4517 v |= perr;
4518 dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n",
4519 perr);
4520 }
4521
4522 perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);
4523 if (perr) {
4524 v |= perr;
4525 dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n",
4526 perr);
4527 }
4528
4529 if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
4530 perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
4531 /* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
4532 perr &= ~ERR_T_RXCRC_F;
4533 if (perr) {
4534 v |= perr;
4535 dev_alert(adapter->pdev_dev,
4536 "SGE Cause5 Parity Error %#x\n", perr);
4537 }
4538 }
4539
4540 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4541 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4542 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4543 t4t5_sge_intr_info);
4544
4545 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4546 if (err & ERROR_QID_VALID_F) {
4547 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4548 ERROR_QID_G(err));
4549 if (err & UNCAPTURED_ERROR_F)
4550 dev_err(adapter->pdev_dev,
4551 "SGE UNCAPTURED_ERROR set (clearing)\n");
4552 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4553 UNCAPTURED_ERROR_F);
4554 }
4555
4556 if (v != 0)
4557 t4_fatal_err(adapter);
4558 }
4559
4560 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4561 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4562 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4563 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4564
4565 /*
4566 * CIM interrupt handler.
4567 */
cim_intr_handler(struct adapter * adapter)4568 static void cim_intr_handler(struct adapter *adapter)
4569 {
4570 static const struct intr_info cim_intr_info[] = {
4571 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4572 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4573 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4574 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4575 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4576 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4577 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4578 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4579 { 0 }
4580 };
4581 static const struct intr_info cim_upintr_info[] = {
4582 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4583 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4584 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4585 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4586 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4587 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4588 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4589 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4590 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4591 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4592 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4593 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4594 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4595 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4596 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4597 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4598 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4599 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4600 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4601 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4602 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4603 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4604 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4605 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4606 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4607 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4608 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4609 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4610 { 0 }
4611 };
4612
4613 u32 val, fw_err;
4614 int fat;
4615
4616 fw_err = t4_read_reg(adapter, PCIE_FW_A);
4617 if (fw_err & PCIE_FW_ERR_F)
4618 t4_report_fw_error(adapter);
4619
4620 /* When the Firmware detects an internal error which normally
4621 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4622 * in order to make sure the Host sees the Firmware Crash. So
4623 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4624 * ignore the Timer0 interrupt.
4625 */
4626
4627 val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4628 if (val & TIMER0INT_F)
4629 if (!(fw_err & PCIE_FW_ERR_F) ||
4630 (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4631 t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4632 TIMER0INT_F);
4633
4634 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4635 cim_intr_info) +
4636 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4637 cim_upintr_info);
4638 if (fat)
4639 t4_fatal_err(adapter);
4640 }
4641
4642 /*
4643 * ULP RX interrupt handler.
4644 */
ulprx_intr_handler(struct adapter * adapter)4645 static void ulprx_intr_handler(struct adapter *adapter)
4646 {
4647 static const struct intr_info ulprx_intr_info[] = {
4648 { 0x1800000, "ULPRX context error", -1, 1 },
4649 { 0x7fffff, "ULPRX parity error", -1, 1 },
4650 { 0 }
4651 };
4652
4653 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4654 t4_fatal_err(adapter);
4655 }
4656
4657 /*
4658 * ULP TX interrupt handler.
4659 */
ulptx_intr_handler(struct adapter * adapter)4660 static void ulptx_intr_handler(struct adapter *adapter)
4661 {
4662 static const struct intr_info ulptx_intr_info[] = {
4663 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4664 0 },
4665 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4666 0 },
4667 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4668 0 },
4669 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4670 0 },
4671 { 0xfffffff, "ULPTX parity error", -1, 1 },
4672 { 0 }
4673 };
4674
4675 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4676 t4_fatal_err(adapter);
4677 }
4678
4679 /*
4680 * PM TX interrupt handler.
4681 */
pmtx_intr_handler(struct adapter * adapter)4682 static void pmtx_intr_handler(struct adapter *adapter)
4683 {
4684 static const struct intr_info pmtx_intr_info[] = {
4685 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4686 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4687 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4688 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4689 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4690 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4691 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4692 -1, 1 },
4693 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4694 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4695 { 0 }
4696 };
4697
4698 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4699 t4_fatal_err(adapter);
4700 }
4701
4702 /*
4703 * PM RX interrupt handler.
4704 */
pmrx_intr_handler(struct adapter * adapter)4705 static void pmrx_intr_handler(struct adapter *adapter)
4706 {
4707 static const struct intr_info pmrx_intr_info[] = {
4708 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4709 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4710 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4711 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4712 -1, 1 },
4713 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4714 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4715 { 0 }
4716 };
4717
4718 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4719 t4_fatal_err(adapter);
4720 }
4721
4722 /*
4723 * CPL switch interrupt handler.
4724 */
cplsw_intr_handler(struct adapter * adapter)4725 static void cplsw_intr_handler(struct adapter *adapter)
4726 {
4727 static const struct intr_info cplsw_intr_info[] = {
4728 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4729 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4730 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4731 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4732 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4733 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4734 { 0 }
4735 };
4736
4737 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4738 t4_fatal_err(adapter);
4739 }
4740
4741 /*
4742 * LE interrupt handler.
4743 */
le_intr_handler(struct adapter * adap)4744 static void le_intr_handler(struct adapter *adap)
4745 {
4746 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4747 static const struct intr_info le_intr_info[] = {
4748 { LIPMISS_F, "LE LIP miss", -1, 0 },
4749 { LIP0_F, "LE 0 LIP error", -1, 0 },
4750 { PARITYERR_F, "LE parity error", -1, 1 },
4751 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4752 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4753 { 0 }
4754 };
4755
4756 static struct intr_info t6_le_intr_info[] = {
4757 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4758 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4759 { CMDTIDERR_F, "LE cmd tid error", -1, 1 },
4760 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4761 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4762 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4763 { HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 },
4764 { 0 }
4765 };
4766
4767 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4768 (chip <= CHELSIO_T5) ?
4769 le_intr_info : t6_le_intr_info))
4770 t4_fatal_err(adap);
4771 }
4772
4773 /*
4774 * MPS interrupt handler.
4775 */
mps_intr_handler(struct adapter * adapter)4776 static void mps_intr_handler(struct adapter *adapter)
4777 {
4778 static const struct intr_info mps_rx_intr_info[] = {
4779 { 0xffffff, "MPS Rx parity error", -1, 1 },
4780 { 0 }
4781 };
4782 static const struct intr_info mps_tx_intr_info[] = {
4783 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4784 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4785 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4786 -1, 1 },
4787 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4788 -1, 1 },
4789 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4790 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4791 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4792 { 0 }
4793 };
4794 static const struct intr_info t6_mps_tx_intr_info[] = {
4795 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4796 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4797 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4798 -1, 1 },
4799 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4800 -1, 1 },
4801 /* MPS Tx Bubble is normal for T6 */
4802 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4803 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4804 { 0 }
4805 };
4806 static const struct intr_info mps_trc_intr_info[] = {
4807 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4808 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4809 -1, 1 },
4810 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4811 { 0 }
4812 };
4813 static const struct intr_info mps_stat_sram_intr_info[] = {
4814 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4815 { 0 }
4816 };
4817 static const struct intr_info mps_stat_tx_intr_info[] = {
4818 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4819 { 0 }
4820 };
4821 static const struct intr_info mps_stat_rx_intr_info[] = {
4822 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4823 { 0 }
4824 };
4825 static const struct intr_info mps_cls_intr_info[] = {
4826 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4827 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4828 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4829 { 0 }
4830 };
4831
4832 int fat;
4833
4834 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4835 mps_rx_intr_info) +
4836 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4837 is_t6(adapter->params.chip)
4838 ? t6_mps_tx_intr_info
4839 : mps_tx_intr_info) +
4840 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4841 mps_trc_intr_info) +
4842 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4843 mps_stat_sram_intr_info) +
4844 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4845 mps_stat_tx_intr_info) +
4846 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4847 mps_stat_rx_intr_info) +
4848 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4849 mps_cls_intr_info);
4850
4851 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4852 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4853 if (fat)
4854 t4_fatal_err(adapter);
4855 }
4856
4857 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4858 ECC_UE_INT_CAUSE_F)
4859
4860 /*
4861 * EDC/MC interrupt handler.
4862 */
mem_intr_handler(struct adapter * adapter,int idx)4863 static void mem_intr_handler(struct adapter *adapter, int idx)
4864 {
4865 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4866
4867 unsigned int addr, cnt_addr, v;
4868
4869 if (idx <= MEM_EDC1) {
4870 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4871 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4872 } else if (idx == MEM_MC) {
4873 if (is_t4(adapter->params.chip)) {
4874 addr = MC_INT_CAUSE_A;
4875 cnt_addr = MC_ECC_STATUS_A;
4876 } else {
4877 addr = MC_P_INT_CAUSE_A;
4878 cnt_addr = MC_P_ECC_STATUS_A;
4879 }
4880 } else {
4881 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4882 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4883 }
4884
4885 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4886 if (v & PERR_INT_CAUSE_F)
4887 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4888 name[idx]);
4889 if (v & ECC_CE_INT_CAUSE_F) {
4890 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4891
4892 t4_edc_err_read(adapter, idx);
4893
4894 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4895 if (printk_ratelimit())
4896 dev_warn(adapter->pdev_dev,
4897 "%u %s correctable ECC data error%s\n",
4898 cnt, name[idx], cnt > 1 ? "s" : "");
4899 }
4900 if (v & ECC_UE_INT_CAUSE_F)
4901 dev_alert(adapter->pdev_dev,
4902 "%s uncorrectable ECC data error\n", name[idx]);
4903
4904 t4_write_reg(adapter, addr, v);
4905 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4906 t4_fatal_err(adapter);
4907 }
4908
4909 /*
4910 * MA interrupt handler.
4911 */
ma_intr_handler(struct adapter * adap)4912 static void ma_intr_handler(struct adapter *adap)
4913 {
4914 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4915
4916 if (status & MEM_PERR_INT_CAUSE_F) {
4917 dev_alert(adap->pdev_dev,
4918 "MA parity error, parity status %#x\n",
4919 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4920 if (is_t5(adap->params.chip))
4921 dev_alert(adap->pdev_dev,
4922 "MA parity error, parity status %#x\n",
4923 t4_read_reg(adap,
4924 MA_PARITY_ERROR_STATUS2_A));
4925 }
4926 if (status & MEM_WRAP_INT_CAUSE_F) {
4927 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4928 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4929 "client %u to address %#x\n",
4930 MEM_WRAP_CLIENT_NUM_G(v),
4931 MEM_WRAP_ADDRESS_G(v) << 4);
4932 }
4933 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4934 t4_fatal_err(adap);
4935 }
4936
4937 /*
4938 * SMB interrupt handler.
4939 */
smb_intr_handler(struct adapter * adap)4940 static void smb_intr_handler(struct adapter *adap)
4941 {
4942 static const struct intr_info smb_intr_info[] = {
4943 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4944 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4945 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4946 { 0 }
4947 };
4948
4949 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4950 t4_fatal_err(adap);
4951 }
4952
4953 /*
4954 * NC-SI interrupt handler.
4955 */
ncsi_intr_handler(struct adapter * adap)4956 static void ncsi_intr_handler(struct adapter *adap)
4957 {
4958 static const struct intr_info ncsi_intr_info[] = {
4959 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4960 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4961 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4962 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4963 { 0 }
4964 };
4965
4966 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4967 t4_fatal_err(adap);
4968 }
4969
4970 /*
4971 * XGMAC interrupt handler.
4972 */
xgmac_intr_handler(struct adapter * adap,int port)4973 static void xgmac_intr_handler(struct adapter *adap, int port)
4974 {
4975 u32 v, int_cause_reg;
4976
4977 if (is_t4(adap->params.chip))
4978 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4979 else
4980 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4981
4982 v = t4_read_reg(adap, int_cause_reg);
4983
4984 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4985 if (!v)
4986 return;
4987
4988 if (v & TXFIFO_PRTY_ERR_F)
4989 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4990 port);
4991 if (v & RXFIFO_PRTY_ERR_F)
4992 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4993 port);
4994 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4995 t4_fatal_err(adap);
4996 }
4997
4998 /*
4999 * PL interrupt handler.
5000 */
pl_intr_handler(struct adapter * adap)5001 static void pl_intr_handler(struct adapter *adap)
5002 {
5003 static const struct intr_info pl_intr_info[] = {
5004 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
5005 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
5006 { 0 }
5007 };
5008
5009 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
5010 t4_fatal_err(adap);
5011 }
5012
5013 #define PF_INTR_MASK (PFSW_F)
5014 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
5015 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
5016 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
5017
5018 /**
5019 * t4_slow_intr_handler - control path interrupt handler
5020 * @adapter: the adapter
5021 *
5022 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5023 * The designation 'slow' is because it involves register reads, while
5024 * data interrupts typically don't involve any MMIOs.
5025 */
t4_slow_intr_handler(struct adapter * adapter)5026 int t4_slow_intr_handler(struct adapter *adapter)
5027 {
5028 /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5029 * set when the corresponding PL_INT_ENABLE bit isn't set. It's
5030 * easiest just to mask that case here.
5031 */
5032 u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
5033 u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
5034 u32 cause = raw_cause & enable;
5035
5036 if (!(cause & GLBL_INTR_MASK))
5037 return 0;
5038 if (cause & CIM_F)
5039 cim_intr_handler(adapter);
5040 if (cause & MPS_F)
5041 mps_intr_handler(adapter);
5042 if (cause & NCSI_F)
5043 ncsi_intr_handler(adapter);
5044 if (cause & PL_F)
5045 pl_intr_handler(adapter);
5046 if (cause & SMB_F)
5047 smb_intr_handler(adapter);
5048 if (cause & XGMAC0_F)
5049 xgmac_intr_handler(adapter, 0);
5050 if (cause & XGMAC1_F)
5051 xgmac_intr_handler(adapter, 1);
5052 if (cause & XGMAC_KR0_F)
5053 xgmac_intr_handler(adapter, 2);
5054 if (cause & XGMAC_KR1_F)
5055 xgmac_intr_handler(adapter, 3);
5056 if (cause & PCIE_F)
5057 pcie_intr_handler(adapter);
5058 if (cause & MC_F)
5059 mem_intr_handler(adapter, MEM_MC);
5060 if (is_t5(adapter->params.chip) && (cause & MC1_F))
5061 mem_intr_handler(adapter, MEM_MC1);
5062 if (cause & EDC0_F)
5063 mem_intr_handler(adapter, MEM_EDC0);
5064 if (cause & EDC1_F)
5065 mem_intr_handler(adapter, MEM_EDC1);
5066 if (cause & LE_F)
5067 le_intr_handler(adapter);
5068 if (cause & TP_F)
5069 tp_intr_handler(adapter);
5070 if (cause & MA_F)
5071 ma_intr_handler(adapter);
5072 if (cause & PM_TX_F)
5073 pmtx_intr_handler(adapter);
5074 if (cause & PM_RX_F)
5075 pmrx_intr_handler(adapter);
5076 if (cause & ULP_RX_F)
5077 ulprx_intr_handler(adapter);
5078 if (cause & CPL_SWITCH_F)
5079 cplsw_intr_handler(adapter);
5080 if (cause & SGE_F)
5081 sge_intr_handler(adapter);
5082 if (cause & ULP_TX_F)
5083 ulptx_intr_handler(adapter);
5084
5085 /* Clear the interrupts just processed for which we are the master. */
5086 t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
5087 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
5088 return 1;
5089 }
5090
5091 /**
5092 * t4_intr_enable - enable interrupts
5093 * @adapter: the adapter whose interrupts should be enabled
5094 *
5095 * Enable PF-specific interrupts for the calling function and the top-level
5096 * interrupt concentrator for global interrupts. Interrupts are already
5097 * enabled at each module, here we just enable the roots of the interrupt
5098 * hierarchies.
5099 *
5100 * Note: this function should be called only when the driver manages
5101 * non PF-specific interrupts from the various HW modules. Only one PCI
5102 * function at a time should be doing this.
5103 */
t4_intr_enable(struct adapter * adapter)5104 void t4_intr_enable(struct adapter *adapter)
5105 {
5106 u32 val = 0;
5107 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5108 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5109 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5110
5111 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
5112 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
5113 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
5114 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
5115 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
5116 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
5117 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
5118 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
5119 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
5120 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
5121 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
5122 }
5123
5124 /**
5125 * t4_intr_disable - disable interrupts
5126 * @adapter: the adapter whose interrupts should be disabled
5127 *
5128 * Disable interrupts. We only disable the top-level interrupt
5129 * concentrators. The caller must be a PCI function managing global
5130 * interrupts.
5131 */
t4_intr_disable(struct adapter * adapter)5132 void t4_intr_disable(struct adapter *adapter)
5133 {
5134 u32 whoami, pf;
5135
5136 if (pci_channel_offline(adapter->pdev))
5137 return;
5138
5139 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5140 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5141 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5142
5143 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
5144 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
5145 }
5146
t4_chip_rss_size(struct adapter * adap)5147 unsigned int t4_chip_rss_size(struct adapter *adap)
5148 {
5149 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5150 return RSS_NENTRIES;
5151 else
5152 return T6_RSS_NENTRIES;
5153 }
5154
5155 /**
5156 * t4_config_rss_range - configure a portion of the RSS mapping table
5157 * @adapter: the adapter
5158 * @mbox: mbox to use for the FW command
5159 * @viid: virtual interface whose RSS subtable is to be written
5160 * @start: start entry in the table to write
5161 * @n: how many table entries to write
5162 * @rspq: values for the response queue lookup table
5163 * @nrspq: number of values in @rspq
5164 *
5165 * Programs the selected part of the VI's RSS mapping table with the
5166 * provided values. If @nrspq < @n the supplied values are used repeatedly
5167 * until the full table range is populated.
5168 *
5169 * The caller must ensure the values in @rspq are in the range allowed for
5170 * @viid.
5171 */
t4_config_rss_range(struct adapter * adapter,int mbox,unsigned int viid,int start,int n,const u16 * rspq,unsigned int nrspq)5172 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5173 int start, int n, const u16 *rspq, unsigned int nrspq)
5174 {
5175 int ret;
5176 const u16 *rsp = rspq;
5177 const u16 *rsp_end = rspq + nrspq;
5178 struct fw_rss_ind_tbl_cmd cmd;
5179
5180 memset(&cmd, 0, sizeof(cmd));
5181 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5182 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5183 FW_RSS_IND_TBL_CMD_VIID_V(viid));
5184 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5185
5186 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5187 while (n > 0) {
5188 int nq = min(n, 32);
5189 __be32 *qp = &cmd.iq0_to_iq2;
5190
5191 cmd.niqid = cpu_to_be16(nq);
5192 cmd.startidx = cpu_to_be16(start);
5193
5194 start += nq;
5195 n -= nq;
5196
5197 while (nq > 0) {
5198 unsigned int v;
5199
5200 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5201 if (++rsp >= rsp_end)
5202 rsp = rspq;
5203 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5204 if (++rsp >= rsp_end)
5205 rsp = rspq;
5206 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5207 if (++rsp >= rsp_end)
5208 rsp = rspq;
5209
5210 *qp++ = cpu_to_be32(v);
5211 nq -= 3;
5212 }
5213
5214 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5215 if (ret)
5216 return ret;
5217 }
5218 return 0;
5219 }
5220
5221 /**
5222 * t4_config_glbl_rss - configure the global RSS mode
5223 * @adapter: the adapter
5224 * @mbox: mbox to use for the FW command
5225 * @mode: global RSS mode
5226 * @flags: mode-specific flags
5227 *
5228 * Sets the global RSS mode.
5229 */
t4_config_glbl_rss(struct adapter * adapter,int mbox,unsigned int mode,unsigned int flags)5230 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5231 unsigned int flags)
5232 {
5233 struct fw_rss_glb_config_cmd c;
5234
5235 memset(&c, 0, sizeof(c));
5236 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5237 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5238 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5239 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5240 c.u.manual.mode_pkd =
5241 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5242 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5243 c.u.basicvirtual.mode_pkd =
5244 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5245 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5246 } else
5247 return -EINVAL;
5248 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5249 }
5250
5251 /**
5252 * t4_config_vi_rss - configure per VI RSS settings
5253 * @adapter: the adapter
5254 * @mbox: mbox to use for the FW command
5255 * @viid: the VI id
5256 * @flags: RSS flags
5257 * @defq: id of the default RSS queue for the VI.
5258 *
5259 * Configures VI-specific RSS properties.
5260 */
t4_config_vi_rss(struct adapter * adapter,int mbox,unsigned int viid,unsigned int flags,unsigned int defq)5261 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5262 unsigned int flags, unsigned int defq)
5263 {
5264 struct fw_rss_vi_config_cmd c;
5265
5266 memset(&c, 0, sizeof(c));
5267 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5268 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5269 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5270 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5271 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5272 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5273 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5274 }
5275
5276 /* Read an RSS table row */
rd_rss_row(struct adapter * adap,int row,u32 * val)5277 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5278 {
5279 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5280 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5281 5, 0, val);
5282 }
5283
5284 /**
5285 * t4_read_rss - read the contents of the RSS mapping table
5286 * @adapter: the adapter
5287 * @map: holds the contents of the RSS mapping table
5288 *
5289 * Reads the contents of the RSS hash->queue mapping table.
5290 */
t4_read_rss(struct adapter * adapter,u16 * map)5291 int t4_read_rss(struct adapter *adapter, u16 *map)
5292 {
5293 int i, ret, nentries;
5294 u32 val;
5295
5296 nentries = t4_chip_rss_size(adapter);
5297 for (i = 0; i < nentries / 2; ++i) {
5298 ret = rd_rss_row(adapter, i, &val);
5299 if (ret)
5300 return ret;
5301 *map++ = LKPTBLQUEUE0_G(val);
5302 *map++ = LKPTBLQUEUE1_G(val);
5303 }
5304 return 0;
5305 }
5306
t4_use_ldst(struct adapter * adap)5307 static unsigned int t4_use_ldst(struct adapter *adap)
5308 {
5309 return (adap->flags & CXGB4_FW_OK) && !adap->use_bd;
5310 }
5311
5312 /**
5313 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5314 * @adap: the adapter
5315 * @cmd: TP fw ldst address space type
5316 * @vals: where the indirect register values are stored/written
5317 * @nregs: how many indirect registers to read/write
5318 * @start_index: index of first indirect register to read/write
5319 * @rw: Read (1) or Write (0)
5320 * @sleep_ok: if true we may sleep while awaiting command completion
5321 *
5322 * Access TP indirect registers through LDST
5323 */
t4_tp_fw_ldst_rw(struct adapter * adap,int cmd,u32 * vals,unsigned int nregs,unsigned int start_index,unsigned int rw,bool sleep_ok)5324 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5325 unsigned int nregs, unsigned int start_index,
5326 unsigned int rw, bool sleep_ok)
5327 {
5328 int ret = 0;
5329 unsigned int i;
5330 struct fw_ldst_cmd c;
5331
5332 for (i = 0; i < nregs; i++) {
5333 memset(&c, 0, sizeof(c));
5334 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5335 FW_CMD_REQUEST_F |
5336 (rw ? FW_CMD_READ_F :
5337 FW_CMD_WRITE_F) |
5338 FW_LDST_CMD_ADDRSPACE_V(cmd));
5339 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5340
5341 c.u.addrval.addr = cpu_to_be32(start_index + i);
5342 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5343 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5344 sleep_ok);
5345 if (ret)
5346 return ret;
5347
5348 if (rw)
5349 vals[i] = be32_to_cpu(c.u.addrval.val);
5350 }
5351 return 0;
5352 }
5353
5354 /**
5355 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5356 * @adap: the adapter
5357 * @reg_addr: Address Register
5358 * @reg_data: Data register
5359 * @buff: where the indirect register values are stored/written
5360 * @nregs: how many indirect registers to read/write
5361 * @start_index: index of first indirect register to read/write
5362 * @rw: READ(1) or WRITE(0)
5363 * @sleep_ok: if true we may sleep while awaiting command completion
5364 *
5365 * Read/Write TP indirect registers through LDST if possible.
5366 * Else, use backdoor access
5367 **/
t4_tp_indirect_rw(struct adapter * adap,u32 reg_addr,u32 reg_data,u32 * buff,u32 nregs,u32 start_index,int rw,bool sleep_ok)5368 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5369 u32 *buff, u32 nregs, u32 start_index, int rw,
5370 bool sleep_ok)
5371 {
5372 int rc = -EINVAL;
5373 int cmd;
5374
5375 switch (reg_addr) {
5376 case TP_PIO_ADDR_A:
5377 cmd = FW_LDST_ADDRSPC_TP_PIO;
5378 break;
5379 case TP_TM_PIO_ADDR_A:
5380 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5381 break;
5382 case TP_MIB_INDEX_A:
5383 cmd = FW_LDST_ADDRSPC_TP_MIB;
5384 break;
5385 default:
5386 goto indirect_access;
5387 }
5388
5389 if (t4_use_ldst(adap))
5390 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5391 sleep_ok);
5392
5393 indirect_access:
5394
5395 if (rc) {
5396 if (rw)
5397 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5398 start_index);
5399 else
5400 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5401 start_index);
5402 }
5403 }
5404
5405 /**
5406 * t4_tp_pio_read - Read TP PIO registers
5407 * @adap: the adapter
5408 * @buff: where the indirect register values are written
5409 * @nregs: how many indirect registers to read
5410 * @start_index: index of first indirect register to read
5411 * @sleep_ok: if true we may sleep while awaiting command completion
5412 *
5413 * Read TP PIO Registers
5414 **/
t4_tp_pio_read(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)5415 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5416 u32 start_index, bool sleep_ok)
5417 {
5418 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5419 start_index, 1, sleep_ok);
5420 }
5421
5422 /**
5423 * t4_tp_pio_write - Write TP PIO registers
5424 * @adap: the adapter
5425 * @buff: where the indirect register values are stored
5426 * @nregs: how many indirect registers to write
5427 * @start_index: index of first indirect register to write
5428 * @sleep_ok: if true we may sleep while awaiting command completion
5429 *
5430 * Write TP PIO Registers
5431 **/
t4_tp_pio_write(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)5432 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5433 u32 start_index, bool sleep_ok)
5434 {
5435 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5436 start_index, 0, sleep_ok);
5437 }
5438
5439 /**
5440 * t4_tp_tm_pio_read - Read TP TM PIO registers
5441 * @adap: the adapter
5442 * @buff: where the indirect register values are written
5443 * @nregs: how many indirect registers to read
5444 * @start_index: index of first indirect register to read
5445 * @sleep_ok: if true we may sleep while awaiting command completion
5446 *
5447 * Read TP TM PIO Registers
5448 **/
t4_tp_tm_pio_read(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)5449 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5450 u32 start_index, bool sleep_ok)
5451 {
5452 t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5453 nregs, start_index, 1, sleep_ok);
5454 }
5455
5456 /**
5457 * t4_tp_mib_read - Read TP MIB registers
5458 * @adap: the adapter
5459 * @buff: where the indirect register values are written
5460 * @nregs: how many indirect registers to read
5461 * @start_index: index of first indirect register to read
5462 * @sleep_ok: if true we may sleep while awaiting command completion
5463 *
5464 * Read TP MIB Registers
5465 **/
t4_tp_mib_read(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)5466 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5467 bool sleep_ok)
5468 {
5469 t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5470 start_index, 1, sleep_ok);
5471 }
5472
5473 /**
5474 * t4_read_rss_key - read the global RSS key
5475 * @adap: the adapter
5476 * @key: 10-entry array holding the 320-bit RSS key
5477 * @sleep_ok: if true we may sleep while awaiting command completion
5478 *
5479 * Reads the global 320-bit RSS key.
5480 */
t4_read_rss_key(struct adapter * adap,u32 * key,bool sleep_ok)5481 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5482 {
5483 t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5484 }
5485
5486 /**
5487 * t4_write_rss_key - program one of the RSS keys
5488 * @adap: the adapter
5489 * @key: 10-entry array holding the 320-bit RSS key
5490 * @idx: which RSS key to write
5491 * @sleep_ok: if true we may sleep while awaiting command completion
5492 *
5493 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5494 * 0..15 the corresponding entry in the RSS key table is written,
5495 * otherwise the global RSS key is written.
5496 */
t4_write_rss_key(struct adapter * adap,const u32 * key,int idx,bool sleep_ok)5497 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5498 bool sleep_ok)
5499 {
5500 u8 rss_key_addr_cnt = 16;
5501 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5502
5503 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5504 * allows access to key addresses 16-63 by using KeyWrAddrX
5505 * as index[5:4](upper 2) into key table
5506 */
5507 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5508 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5509 rss_key_addr_cnt = 32;
5510
5511 t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5512
5513 if (idx >= 0 && idx < rss_key_addr_cnt) {
5514 if (rss_key_addr_cnt > 16)
5515 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5516 KEYWRADDRX_V(idx >> 4) |
5517 T6_VFWRADDR_V(idx) | KEYWREN_F);
5518 else
5519 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5520 KEYWRADDR_V(idx) | KEYWREN_F);
5521 }
5522 }
5523
5524 /**
5525 * t4_read_rss_pf_config - read PF RSS Configuration Table
5526 * @adapter: the adapter
5527 * @index: the entry in the PF RSS table to read
5528 * @valp: where to store the returned value
5529 * @sleep_ok: if true we may sleep while awaiting command completion
5530 *
5531 * Reads the PF RSS Configuration Table at the specified index and returns
5532 * the value found there.
5533 */
t4_read_rss_pf_config(struct adapter * adapter,unsigned int index,u32 * valp,bool sleep_ok)5534 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5535 u32 *valp, bool sleep_ok)
5536 {
5537 t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5538 }
5539
5540 /**
5541 * t4_read_rss_vf_config - read VF RSS Configuration Table
5542 * @adapter: the adapter
5543 * @index: the entry in the VF RSS table to read
5544 * @vfl: where to store the returned VFL
5545 * @vfh: where to store the returned VFH
5546 * @sleep_ok: if true we may sleep while awaiting command completion
5547 *
5548 * Reads the VF RSS Configuration Table at the specified index and returns
5549 * the (VFL, VFH) values found there.
5550 */
t4_read_rss_vf_config(struct adapter * adapter,unsigned int index,u32 * vfl,u32 * vfh,bool sleep_ok)5551 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5552 u32 *vfl, u32 *vfh, bool sleep_ok)
5553 {
5554 u32 vrt, mask, data;
5555
5556 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5557 mask = VFWRADDR_V(VFWRADDR_M);
5558 data = VFWRADDR_V(index);
5559 } else {
5560 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
5561 data = T6_VFWRADDR_V(index);
5562 }
5563
5564 /* Request that the index'th VF Table values be read into VFL/VFH.
5565 */
5566 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5567 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5568 vrt |= data | VFRDEN_F;
5569 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5570
5571 /* Grab the VFL/VFH values ...
5572 */
5573 t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5574 t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5575 }
5576
5577 /**
5578 * t4_read_rss_pf_map - read PF RSS Map
5579 * @adapter: the adapter
5580 * @sleep_ok: if true we may sleep while awaiting command completion
5581 *
5582 * Reads the PF RSS Map register and returns its value.
5583 */
t4_read_rss_pf_map(struct adapter * adapter,bool sleep_ok)5584 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5585 {
5586 u32 pfmap;
5587
5588 t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5589 return pfmap;
5590 }
5591
5592 /**
5593 * t4_read_rss_pf_mask - read PF RSS Mask
5594 * @adapter: the adapter
5595 * @sleep_ok: if true we may sleep while awaiting command completion
5596 *
5597 * Reads the PF RSS Mask register and returns its value.
5598 */
t4_read_rss_pf_mask(struct adapter * adapter,bool sleep_ok)5599 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5600 {
5601 u32 pfmask;
5602
5603 t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5604 return pfmask;
5605 }
5606
5607 /**
5608 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5609 * @adap: the adapter
5610 * @v4: holds the TCP/IP counter values
5611 * @v6: holds the TCP/IPv6 counter values
5612 * @sleep_ok: if true we may sleep while awaiting command completion
5613 *
5614 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5615 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5616 */
t4_tp_get_tcp_stats(struct adapter * adap,struct tp_tcp_stats * v4,struct tp_tcp_stats * v6,bool sleep_ok)5617 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5618 struct tp_tcp_stats *v6, bool sleep_ok)
5619 {
5620 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5621
5622 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5623 #define STAT(x) val[STAT_IDX(x)]
5624 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5625
5626 if (v4) {
5627 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5628 TP_MIB_TCP_OUT_RST_A, sleep_ok);
5629 v4->tcp_out_rsts = STAT(OUT_RST);
5630 v4->tcp_in_segs = STAT64(IN_SEG);
5631 v4->tcp_out_segs = STAT64(OUT_SEG);
5632 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5633 }
5634 if (v6) {
5635 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5636 TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5637 v6->tcp_out_rsts = STAT(OUT_RST);
5638 v6->tcp_in_segs = STAT64(IN_SEG);
5639 v6->tcp_out_segs = STAT64(OUT_SEG);
5640 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5641 }
5642 #undef STAT64
5643 #undef STAT
5644 #undef STAT_IDX
5645 }
5646
5647 /**
5648 * t4_tp_get_err_stats - read TP's error MIB counters
5649 * @adap: the adapter
5650 * @st: holds the counter values
5651 * @sleep_ok: if true we may sleep while awaiting command completion
5652 *
5653 * Returns the values of TP's error counters.
5654 */
t4_tp_get_err_stats(struct adapter * adap,struct tp_err_stats * st,bool sleep_ok)5655 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5656 bool sleep_ok)
5657 {
5658 int nchan = adap->params.arch.nchan;
5659
5660 t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5661 sleep_ok);
5662 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5663 sleep_ok);
5664 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5665 sleep_ok);
5666 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5667 TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5668 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5669 TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5670 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5671 sleep_ok);
5672 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5673 TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5674 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5675 TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5676 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5677 sleep_ok);
5678 }
5679
5680 /**
5681 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5682 * @adap: the adapter
5683 * @st: holds the counter values
5684 * @sleep_ok: if true we may sleep while awaiting command completion
5685 *
5686 * Returns the values of TP's CPL counters.
5687 */
t4_tp_get_cpl_stats(struct adapter * adap,struct tp_cpl_stats * st,bool sleep_ok)5688 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5689 bool sleep_ok)
5690 {
5691 int nchan = adap->params.arch.nchan;
5692
5693 t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5694
5695 t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5696 }
5697
5698 /**
5699 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5700 * @adap: the adapter
5701 * @st: holds the counter values
5702 * @sleep_ok: if true we may sleep while awaiting command completion
5703 *
5704 * Returns the values of TP's RDMA counters.
5705 */
t4_tp_get_rdma_stats(struct adapter * adap,struct tp_rdma_stats * st,bool sleep_ok)5706 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5707 bool sleep_ok)
5708 {
5709 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5710 sleep_ok);
5711 }
5712
5713 /**
5714 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5715 * @adap: the adapter
5716 * @idx: the port index
5717 * @st: holds the counter values
5718 * @sleep_ok: if true we may sleep while awaiting command completion
5719 *
5720 * Returns the values of TP's FCoE counters for the selected port.
5721 */
t4_get_fcoe_stats(struct adapter * adap,unsigned int idx,struct tp_fcoe_stats * st,bool sleep_ok)5722 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5723 struct tp_fcoe_stats *st, bool sleep_ok)
5724 {
5725 u32 val[2];
5726
5727 t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5728 sleep_ok);
5729
5730 t4_tp_mib_read(adap, &st->frames_drop, 1,
5731 TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5732
5733 t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5734 sleep_ok);
5735
5736 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5737 }
5738
5739 /**
5740 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5741 * @adap: the adapter
5742 * @st: holds the counter values
5743 * @sleep_ok: if true we may sleep while awaiting command completion
5744 *
5745 * Returns the values of TP's counters for non-TCP directly-placed packets.
5746 */
t4_get_usm_stats(struct adapter * adap,struct tp_usm_stats * st,bool sleep_ok)5747 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5748 bool sleep_ok)
5749 {
5750 u32 val[4];
5751
5752 t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5753 st->frames = val[0];
5754 st->drops = val[1];
5755 st->octets = ((u64)val[2] << 32) | val[3];
5756 }
5757
5758 /**
5759 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5760 * @adap: the adapter
5761 * @mtus: where to store the MTU values
5762 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5763 *
5764 * Reads the HW path MTU table.
5765 */
t4_read_mtu_tbl(struct adapter * adap,u16 * mtus,u8 * mtu_log)5766 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5767 {
5768 u32 v;
5769 int i;
5770
5771 for (i = 0; i < NMTUS; ++i) {
5772 t4_write_reg(adap, TP_MTU_TABLE_A,
5773 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5774 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5775 mtus[i] = MTUVALUE_G(v);
5776 if (mtu_log)
5777 mtu_log[i] = MTUWIDTH_G(v);
5778 }
5779 }
5780
5781 /**
5782 * t4_read_cong_tbl - reads the congestion control table
5783 * @adap: the adapter
5784 * @incr: where to store the alpha values
5785 *
5786 * Reads the additive increments programmed into the HW congestion
5787 * control table.
5788 */
t4_read_cong_tbl(struct adapter * adap,u16 incr[NMTUS][NCCTRL_WIN])5789 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5790 {
5791 unsigned int mtu, w;
5792
5793 for (mtu = 0; mtu < NMTUS; ++mtu)
5794 for (w = 0; w < NCCTRL_WIN; ++w) {
5795 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5796 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5797 incr[mtu][w] = (u16)t4_read_reg(adap,
5798 TP_CCTRL_TABLE_A) & 0x1fff;
5799 }
5800 }
5801
5802 /**
5803 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5804 * @adap: the adapter
5805 * @addr: the indirect TP register address
5806 * @mask: specifies the field within the register to modify
5807 * @val: new value for the field
5808 *
5809 * Sets a field of an indirect TP register to the given value.
5810 */
t4_tp_wr_bits_indirect(struct adapter * adap,unsigned int addr,unsigned int mask,unsigned int val)5811 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5812 unsigned int mask, unsigned int val)
5813 {
5814 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5815 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5816 t4_write_reg(adap, TP_PIO_DATA_A, val);
5817 }
5818
5819 /**
5820 * init_cong_ctrl - initialize congestion control parameters
5821 * @a: the alpha values for congestion control
5822 * @b: the beta values for congestion control
5823 *
5824 * Initialize the congestion control parameters.
5825 */
init_cong_ctrl(unsigned short * a,unsigned short * b)5826 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5827 {
5828 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5829 a[9] = 2;
5830 a[10] = 3;
5831 a[11] = 4;
5832 a[12] = 5;
5833 a[13] = 6;
5834 a[14] = 7;
5835 a[15] = 8;
5836 a[16] = 9;
5837 a[17] = 10;
5838 a[18] = 14;
5839 a[19] = 17;
5840 a[20] = 21;
5841 a[21] = 25;
5842 a[22] = 30;
5843 a[23] = 35;
5844 a[24] = 45;
5845 a[25] = 60;
5846 a[26] = 80;
5847 a[27] = 100;
5848 a[28] = 200;
5849 a[29] = 300;
5850 a[30] = 400;
5851 a[31] = 500;
5852
5853 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5854 b[9] = b[10] = 1;
5855 b[11] = b[12] = 2;
5856 b[13] = b[14] = b[15] = b[16] = 3;
5857 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5858 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5859 b[28] = b[29] = 6;
5860 b[30] = b[31] = 7;
5861 }
5862
5863 /* The minimum additive increment value for the congestion control table */
5864 #define CC_MIN_INCR 2U
5865
5866 /**
5867 * t4_load_mtus - write the MTU and congestion control HW tables
5868 * @adap: the adapter
5869 * @mtus: the values for the MTU table
5870 * @alpha: the values for the congestion control alpha parameter
5871 * @beta: the values for the congestion control beta parameter
5872 *
5873 * Write the HW MTU table with the supplied MTUs and the high-speed
5874 * congestion control table with the supplied alpha, beta, and MTUs.
5875 * We write the two tables together because the additive increments
5876 * depend on the MTUs.
5877 */
t4_load_mtus(struct adapter * adap,const unsigned short * mtus,const unsigned short * alpha,const unsigned short * beta)5878 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5879 const unsigned short *alpha, const unsigned short *beta)
5880 {
5881 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5882 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5883 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5884 28672, 40960, 57344, 81920, 114688, 163840, 229376
5885 };
5886
5887 unsigned int i, w;
5888
5889 for (i = 0; i < NMTUS; ++i) {
5890 unsigned int mtu = mtus[i];
5891 unsigned int log2 = fls(mtu);
5892
5893 if (!(mtu & ((1 << log2) >> 2))) /* round */
5894 log2--;
5895 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5896 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5897
5898 for (w = 0; w < NCCTRL_WIN; ++w) {
5899 unsigned int inc;
5900
5901 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5902 CC_MIN_INCR);
5903
5904 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5905 (w << 16) | (beta[w] << 13) | inc);
5906 }
5907 }
5908 }
5909
5910 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5911 * clocks. The formula is
5912 *
5913 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5914 *
5915 * which is equivalent to
5916 *
5917 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5918 */
chan_rate(struct adapter * adap,unsigned int bytes256)5919 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5920 {
5921 u64 v = bytes256 * adap->params.vpd.cclk;
5922
5923 return v * 62 + v / 2;
5924 }
5925
5926 /**
5927 * t4_get_chan_txrate - get the current per channel Tx rates
5928 * @adap: the adapter
5929 * @nic_rate: rates for NIC traffic
5930 * @ofld_rate: rates for offloaded traffic
5931 *
5932 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5933 * for each channel.
5934 */
t4_get_chan_txrate(struct adapter * adap,u64 * nic_rate,u64 * ofld_rate)5935 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5936 {
5937 u32 v;
5938
5939 v = t4_read_reg(adap, TP_TX_TRATE_A);
5940 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5941 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5942 if (adap->params.arch.nchan == NCHAN) {
5943 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5944 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5945 }
5946
5947 v = t4_read_reg(adap, TP_TX_ORATE_A);
5948 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5949 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5950 if (adap->params.arch.nchan == NCHAN) {
5951 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5952 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5953 }
5954 }
5955
5956 /**
5957 * t4_set_trace_filter - configure one of the tracing filters
5958 * @adap: the adapter
5959 * @tp: the desired trace filter parameters
5960 * @idx: which filter to configure
5961 * @enable: whether to enable or disable the filter
5962 *
5963 * Configures one of the tracing filters available in HW. If @enable is
5964 * %0 @tp is not examined and may be %NULL. The user is responsible to
5965 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5966 */
t4_set_trace_filter(struct adapter * adap,const struct trace_params * tp,int idx,int enable)5967 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5968 int idx, int enable)
5969 {
5970 int i, ofst = idx * 4;
5971 u32 data_reg, mask_reg, cfg;
5972
5973 if (!enable) {
5974 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5975 return 0;
5976 }
5977
5978 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5979 if (cfg & TRCMULTIFILTER_F) {
5980 /* If multiple tracers are enabled, then maximum
5981 * capture size is 2.5KB (FIFO size of a single channel)
5982 * minus 2 flits for CPL_TRACE_PKT header.
5983 */
5984 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5985 return -EINVAL;
5986 } else {
5987 /* If multiple tracers are disabled, to avoid deadlocks
5988 * maximum packet capture size of 9600 bytes is recommended.
5989 * Also in this mode, only trace0 can be enabled and running.
5990 */
5991 if (tp->snap_len > 9600 || idx)
5992 return -EINVAL;
5993 }
5994
5995 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5996 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5997 tp->min_len > TFMINPKTSIZE_M)
5998 return -EINVAL;
5999
6000 /* stop the tracer we'll be changing */
6001 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
6002
6003 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
6004 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
6005 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
6006
6007 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6008 t4_write_reg(adap, data_reg, tp->data[i]);
6009 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
6010 }
6011 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
6012 TFCAPTUREMAX_V(tp->snap_len) |
6013 TFMINPKTSIZE_V(tp->min_len));
6014 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
6015 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
6016 (is_t4(adap->params.chip) ?
6017 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
6018 T5_TFPORT_V(tp->port) | T5_TFEN_F |
6019 T5_TFINVERTMATCH_V(tp->invert)));
6020
6021 return 0;
6022 }
6023
6024 /**
6025 * t4_get_trace_filter - query one of the tracing filters
6026 * @adap: the adapter
6027 * @tp: the current trace filter parameters
6028 * @idx: which trace filter to query
6029 * @enabled: non-zero if the filter is enabled
6030 *
6031 * Returns the current settings of one of the HW tracing filters.
6032 */
t4_get_trace_filter(struct adapter * adap,struct trace_params * tp,int idx,int * enabled)6033 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6034 int *enabled)
6035 {
6036 u32 ctla, ctlb;
6037 int i, ofst = idx * 4;
6038 u32 data_reg, mask_reg;
6039
6040 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
6041 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
6042
6043 if (is_t4(adap->params.chip)) {
6044 *enabled = !!(ctla & TFEN_F);
6045 tp->port = TFPORT_G(ctla);
6046 tp->invert = !!(ctla & TFINVERTMATCH_F);
6047 } else {
6048 *enabled = !!(ctla & T5_TFEN_F);
6049 tp->port = T5_TFPORT_G(ctla);
6050 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
6051 }
6052 tp->snap_len = TFCAPTUREMAX_G(ctlb);
6053 tp->min_len = TFMINPKTSIZE_G(ctlb);
6054 tp->skip_ofst = TFOFFSET_G(ctla);
6055 tp->skip_len = TFLENGTH_G(ctla);
6056
6057 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
6058 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
6059 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
6060
6061 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6062 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6063 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6064 }
6065 }
6066
6067 /**
6068 * t4_pmtx_get_stats - returns the HW stats from PMTX
6069 * @adap: the adapter
6070 * @cnt: where to store the count statistics
6071 * @cycles: where to store the cycle statistics
6072 *
6073 * Returns performance statistics from PMTX.
6074 */
t4_pmtx_get_stats(struct adapter * adap,u32 cnt[],u64 cycles[])6075 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6076 {
6077 int i;
6078 u32 data[2];
6079
6080 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6081 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
6082 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
6083 if (is_t4(adap->params.chip)) {
6084 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
6085 } else {
6086 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
6087 PM_TX_DBG_DATA_A, data, 2,
6088 PM_TX_DBG_STAT_MSB_A);
6089 cycles[i] = (((u64)data[0] << 32) | data[1]);
6090 }
6091 }
6092 }
6093
6094 /**
6095 * t4_pmrx_get_stats - returns the HW stats from PMRX
6096 * @adap: the adapter
6097 * @cnt: where to store the count statistics
6098 * @cycles: where to store the cycle statistics
6099 *
6100 * Returns performance statistics from PMRX.
6101 */
t4_pmrx_get_stats(struct adapter * adap,u32 cnt[],u64 cycles[])6102 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6103 {
6104 int i;
6105 u32 data[2];
6106
6107 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6108 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
6109 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6110 if (is_t4(adap->params.chip)) {
6111 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
6112 } else {
6113 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
6114 PM_RX_DBG_DATA_A, data, 2,
6115 PM_RX_DBG_STAT_MSB_A);
6116 cycles[i] = (((u64)data[0] << 32) | data[1]);
6117 }
6118 }
6119 }
6120
6121 /**
6122 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6123 * @adapter: the adapter
6124 * @pidx: the port index
6125 *
6126 * Computes and returns a bitmap indicating which MPS buffer groups are
6127 * associated with the given Port. Bit i is set if buffer group i is
6128 * used by the Port.
6129 */
compute_mps_bg_map(struct adapter * adapter,int pidx)6130 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
6131 int pidx)
6132 {
6133 unsigned int chip_version, nports;
6134
6135 chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6136 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6137
6138 switch (chip_version) {
6139 case CHELSIO_T4:
6140 case CHELSIO_T5:
6141 switch (nports) {
6142 case 1: return 0xf;
6143 case 2: return 3 << (2 * pidx);
6144 case 4: return 1 << pidx;
6145 }
6146 break;
6147
6148 case CHELSIO_T6:
6149 switch (nports) {
6150 case 2: return 1 << (2 * pidx);
6151 }
6152 break;
6153 }
6154
6155 dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6156 chip_version, nports);
6157
6158 return 0;
6159 }
6160
6161 /**
6162 * t4_get_mps_bg_map - return the buffer groups associated with a port
6163 * @adapter: the adapter
6164 * @pidx: the port index
6165 *
6166 * Returns a bitmap indicating which MPS buffer groups are associated
6167 * with the given Port. Bit i is set if buffer group i is used by the
6168 * Port.
6169 */
t4_get_mps_bg_map(struct adapter * adapter,int pidx)6170 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6171 {
6172 u8 *mps_bg_map;
6173 unsigned int nports;
6174
6175 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6176 if (pidx >= nports) {
6177 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6178 pidx, nports);
6179 return 0;
6180 }
6181
6182 /* If we've already retrieved/computed this, just return the result.
6183 */
6184 mps_bg_map = adapter->params.mps_bg_map;
6185 if (mps_bg_map[pidx])
6186 return mps_bg_map[pidx];
6187
6188 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6189 * If we're talking to such Firmware, let it tell us. If the new
6190 * API isn't supported, revert back to old hardcoded way. The value
6191 * obtained from Firmware is encoded in below format:
6192 *
6193 * val = (( MPSBGMAP[Port 3] << 24 ) |
6194 * ( MPSBGMAP[Port 2] << 16 ) |
6195 * ( MPSBGMAP[Port 1] << 8 ) |
6196 * ( MPSBGMAP[Port 0] << 0 ))
6197 */
6198 if (adapter->flags & CXGB4_FW_OK) {
6199 u32 param, val;
6200 int ret;
6201
6202 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6203 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6204 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6205 0, 1, ¶m, &val);
6206 if (!ret) {
6207 int p;
6208
6209 /* Store the BG Map for all of the Ports in order to
6210 * avoid more calls to the Firmware in the future.
6211 */
6212 for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6213 mps_bg_map[p] = val & 0xff;
6214
6215 return mps_bg_map[pidx];
6216 }
6217 }
6218
6219 /* Either we're not talking to the Firmware or we're dealing with
6220 * older Firmware which doesn't support the new API to get the MPS
6221 * Buffer Group Map. Fall back to computing it ourselves.
6222 */
6223 mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6224 return mps_bg_map[pidx];
6225 }
6226
6227 /**
6228 * t4_get_tp_e2c_map - return the E2C channel map associated with a port
6229 * @adapter: the adapter
6230 * @pidx: the port index
6231 */
t4_get_tp_e2c_map(struct adapter * adapter,int pidx)6232 static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
6233 {
6234 unsigned int nports;
6235 u32 param, val = 0;
6236 int ret;
6237
6238 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6239 if (pidx >= nports) {
6240 CH_WARN(adapter, "TP E2C Channel Port Index %d >= Nports %d\n",
6241 pidx, nports);
6242 return 0;
6243 }
6244
6245 /* FW version >= 1.16.44.0 can determine E2C channel map using
6246 * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6247 */
6248 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6249 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP));
6250 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6251 0, 1, ¶m, &val);
6252 if (!ret)
6253 return (val >> (8 * pidx)) & 0xff;
6254
6255 return 0;
6256 }
6257
6258 /**
6259 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6260 * @adap: the adapter
6261 * @pidx: the port index
6262 *
6263 * Returns a bitmap indicating which TP Ingress Channels are associated
6264 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6265 * the Port.
6266 */
t4_get_tp_ch_map(struct adapter * adap,int pidx)6267 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6268 {
6269 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6270 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6271
6272 if (pidx >= nports) {
6273 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6274 pidx, nports);
6275 return 0;
6276 }
6277
6278 switch (chip_version) {
6279 case CHELSIO_T4:
6280 case CHELSIO_T5:
6281 /* Note that this happens to be the same values as the MPS
6282 * Buffer Group Map for these Chips. But we replicate the code
6283 * here because they're really separate concepts.
6284 */
6285 switch (nports) {
6286 case 1: return 0xf;
6287 case 2: return 3 << (2 * pidx);
6288 case 4: return 1 << pidx;
6289 }
6290 break;
6291
6292 case CHELSIO_T6:
6293 switch (nports) {
6294 case 1:
6295 case 2: return 1 << pidx;
6296 }
6297 break;
6298 }
6299
6300 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6301 chip_version, nports);
6302 return 0;
6303 }
6304
6305 /**
6306 * t4_get_port_type_description - return Port Type string description
6307 * @port_type: firmware Port Type enumeration
6308 */
t4_get_port_type_description(enum fw_port_type port_type)6309 const char *t4_get_port_type_description(enum fw_port_type port_type)
6310 {
6311 static const char *const port_type_description[] = {
6312 "Fiber_XFI",
6313 "Fiber_XAUI",
6314 "BT_SGMII",
6315 "BT_XFI",
6316 "BT_XAUI",
6317 "KX4",
6318 "CX4",
6319 "KX",
6320 "KR",
6321 "SFP",
6322 "BP_AP",
6323 "BP4_AP",
6324 "QSFP_10G",
6325 "QSA",
6326 "QSFP",
6327 "BP40_BA",
6328 "KR4_100G",
6329 "CR4_QSFP",
6330 "CR_QSFP",
6331 "CR2_QSFP",
6332 "SFP28",
6333 "KR_SFP28",
6334 "KR_XLAUI"
6335 };
6336
6337 if (port_type < ARRAY_SIZE(port_type_description))
6338 return port_type_description[port_type];
6339 return "UNKNOWN";
6340 }
6341
6342 /**
6343 * t4_get_port_stats_offset - collect port stats relative to a previous
6344 * snapshot
6345 * @adap: The adapter
6346 * @idx: The port
6347 * @stats: Current stats to fill
6348 * @offset: Previous stats snapshot
6349 */
t4_get_port_stats_offset(struct adapter * adap,int idx,struct port_stats * stats,struct port_stats * offset)6350 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6351 struct port_stats *stats,
6352 struct port_stats *offset)
6353 {
6354 u64 *s, *o;
6355 int i;
6356
6357 t4_get_port_stats(adap, idx, stats);
6358 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6359 i < (sizeof(struct port_stats) / sizeof(u64));
6360 i++, s++, o++)
6361 *s -= *o;
6362 }
6363
6364 /**
6365 * t4_get_port_stats - collect port statistics
6366 * @adap: the adapter
6367 * @idx: the port index
6368 * @p: the stats structure to fill
6369 *
6370 * Collect statistics related to the given port from HW.
6371 */
t4_get_port_stats(struct adapter * adap,int idx,struct port_stats * p)6372 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6373 {
6374 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6375 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6376
6377 #define GET_STAT(name) \
6378 t4_read_reg64(adap, \
6379 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6380 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6381 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6382
6383 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6384 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6385 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6386 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6387 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6388 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6389 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6390 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6391 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6392 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6393 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6394 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6395 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6396 p->tx_drop = GET_STAT(TX_PORT_DROP);
6397 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6398 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6399 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6400 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6401 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6402 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6403 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6404 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6405 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6406
6407 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6408 if (stat_ctl & COUNTPAUSESTATTX_F)
6409 p->tx_frames_64 -= p->tx_pause;
6410 if (stat_ctl & COUNTPAUSEMCTX_F)
6411 p->tx_mcast_frames -= p->tx_pause;
6412 }
6413 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6414 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6415 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6416 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6417 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6418 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6419 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6420 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
6421 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6422 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6423 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6424 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6425 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6426 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6427 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6428 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6429 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6430 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6431 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6432 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6433 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6434 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6435 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6436 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6437 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6438 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6439 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6440
6441 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6442 if (stat_ctl & COUNTPAUSESTATRX_F)
6443 p->rx_frames_64 -= p->rx_pause;
6444 if (stat_ctl & COUNTPAUSEMCRX_F)
6445 p->rx_mcast_frames -= p->rx_pause;
6446 }
6447
6448 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6449 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6450 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6451 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6452 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6453 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6454 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6455 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6456
6457 #undef GET_STAT
6458 #undef GET_STAT_COM
6459 }
6460
6461 /**
6462 * t4_get_lb_stats - collect loopback port statistics
6463 * @adap: the adapter
6464 * @idx: the loopback port index
6465 * @p: the stats structure to fill
6466 *
6467 * Return HW statistics for the given loopback port.
6468 */
t4_get_lb_stats(struct adapter * adap,int idx,struct lb_port_stats * p)6469 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6470 {
6471 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6472
6473 #define GET_STAT(name) \
6474 t4_read_reg64(adap, \
6475 (is_t4(adap->params.chip) ? \
6476 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6477 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6478 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6479
6480 p->octets = GET_STAT(BYTES);
6481 p->frames = GET_STAT(FRAMES);
6482 p->bcast_frames = GET_STAT(BCAST);
6483 p->mcast_frames = GET_STAT(MCAST);
6484 p->ucast_frames = GET_STAT(UCAST);
6485 p->error_frames = GET_STAT(ERROR);
6486
6487 p->frames_64 = GET_STAT(64B);
6488 p->frames_65_127 = GET_STAT(65B_127B);
6489 p->frames_128_255 = GET_STAT(128B_255B);
6490 p->frames_256_511 = GET_STAT(256B_511B);
6491 p->frames_512_1023 = GET_STAT(512B_1023B);
6492 p->frames_1024_1518 = GET_STAT(1024B_1518B);
6493 p->frames_1519_max = GET_STAT(1519B_MAX);
6494 p->drop = GET_STAT(DROP_FRAMES);
6495
6496 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6497 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6498 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6499 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6500 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6501 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6502 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6503 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6504
6505 #undef GET_STAT
6506 #undef GET_STAT_COM
6507 }
6508
6509 /* t4_mk_filtdelwr - create a delete filter WR
6510 * @ftid: the filter ID
6511 * @wr: the filter work request to populate
6512 * @qid: ingress queue to receive the delete notification
6513 *
6514 * Creates a filter work request to delete the supplied filter. If @qid is
6515 * negative the delete notification is suppressed.
6516 */
t4_mk_filtdelwr(unsigned int ftid,struct fw_filter_wr * wr,int qid)6517 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6518 {
6519 memset(wr, 0, sizeof(*wr));
6520 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6521 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6522 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6523 FW_FILTER_WR_NOREPLY_V(qid < 0));
6524 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6525 if (qid >= 0)
6526 wr->rx_chan_rx_rpl_iq =
6527 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6528 }
6529
6530 #define INIT_CMD(var, cmd, rd_wr) do { \
6531 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6532 FW_CMD_REQUEST_F | \
6533 FW_CMD_##rd_wr##_F); \
6534 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6535 } while (0)
6536
t4_fwaddrspace_write(struct adapter * adap,unsigned int mbox,u32 addr,u32 val)6537 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6538 u32 addr, u32 val)
6539 {
6540 u32 ldst_addrspace;
6541 struct fw_ldst_cmd c;
6542
6543 memset(&c, 0, sizeof(c));
6544 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6545 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6546 FW_CMD_REQUEST_F |
6547 FW_CMD_WRITE_F |
6548 ldst_addrspace);
6549 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6550 c.u.addrval.addr = cpu_to_be32(addr);
6551 c.u.addrval.val = cpu_to_be32(val);
6552
6553 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6554 }
6555
6556 /**
6557 * t4_mdio_rd - read a PHY register through MDIO
6558 * @adap: the adapter
6559 * @mbox: mailbox to use for the FW command
6560 * @phy_addr: the PHY address
6561 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6562 * @reg: the register to read
6563 * @valp: where to store the value
6564 *
6565 * Issues a FW command through the given mailbox to read a PHY register.
6566 */
t4_mdio_rd(struct adapter * adap,unsigned int mbox,unsigned int phy_addr,unsigned int mmd,unsigned int reg,u16 * valp)6567 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6568 unsigned int mmd, unsigned int reg, u16 *valp)
6569 {
6570 int ret;
6571 u32 ldst_addrspace;
6572 struct fw_ldst_cmd c;
6573
6574 memset(&c, 0, sizeof(c));
6575 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6576 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6577 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6578 ldst_addrspace);
6579 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6580 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6581 FW_LDST_CMD_MMD_V(mmd));
6582 c.u.mdio.raddr = cpu_to_be16(reg);
6583
6584 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6585 if (ret == 0)
6586 *valp = be16_to_cpu(c.u.mdio.rval);
6587 return ret;
6588 }
6589
6590 /**
6591 * t4_mdio_wr - write a PHY register through MDIO
6592 * @adap: the adapter
6593 * @mbox: mailbox to use for the FW command
6594 * @phy_addr: the PHY address
6595 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6596 * @reg: the register to write
6597 * @val: value to write
6598 *
6599 * Issues a FW command through the given mailbox to write a PHY register.
6600 */
t4_mdio_wr(struct adapter * adap,unsigned int mbox,unsigned int phy_addr,unsigned int mmd,unsigned int reg,u16 val)6601 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6602 unsigned int mmd, unsigned int reg, u16 val)
6603 {
6604 u32 ldst_addrspace;
6605 struct fw_ldst_cmd c;
6606
6607 memset(&c, 0, sizeof(c));
6608 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6609 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6610 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6611 ldst_addrspace);
6612 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6613 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6614 FW_LDST_CMD_MMD_V(mmd));
6615 c.u.mdio.raddr = cpu_to_be16(reg);
6616 c.u.mdio.rval = cpu_to_be16(val);
6617
6618 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6619 }
6620
6621 /**
6622 * t4_sge_decode_idma_state - decode the idma state
6623 * @adapter: the adapter
6624 * @state: the state idma is stuck in
6625 */
t4_sge_decode_idma_state(struct adapter * adapter,int state)6626 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6627 {
6628 static const char * const t4_decode[] = {
6629 "IDMA_IDLE",
6630 "IDMA_PUSH_MORE_CPL_FIFO",
6631 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6632 "Not used",
6633 "IDMA_PHYSADDR_SEND_PCIEHDR",
6634 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6635 "IDMA_PHYSADDR_SEND_PAYLOAD",
6636 "IDMA_SEND_FIFO_TO_IMSG",
6637 "IDMA_FL_REQ_DATA_FL_PREP",
6638 "IDMA_FL_REQ_DATA_FL",
6639 "IDMA_FL_DROP",
6640 "IDMA_FL_H_REQ_HEADER_FL",
6641 "IDMA_FL_H_SEND_PCIEHDR",
6642 "IDMA_FL_H_PUSH_CPL_FIFO",
6643 "IDMA_FL_H_SEND_CPL",
6644 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6645 "IDMA_FL_H_SEND_IP_HDR",
6646 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6647 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6648 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6649 "IDMA_FL_D_SEND_PCIEHDR",
6650 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6651 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6652 "IDMA_FL_SEND_PCIEHDR",
6653 "IDMA_FL_PUSH_CPL_FIFO",
6654 "IDMA_FL_SEND_CPL",
6655 "IDMA_FL_SEND_PAYLOAD_FIRST",
6656 "IDMA_FL_SEND_PAYLOAD",
6657 "IDMA_FL_REQ_NEXT_DATA_FL",
6658 "IDMA_FL_SEND_NEXT_PCIEHDR",
6659 "IDMA_FL_SEND_PADDING",
6660 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6661 "IDMA_FL_SEND_FIFO_TO_IMSG",
6662 "IDMA_FL_REQ_DATAFL_DONE",
6663 "IDMA_FL_REQ_HEADERFL_DONE",
6664 };
6665 static const char * const t5_decode[] = {
6666 "IDMA_IDLE",
6667 "IDMA_ALMOST_IDLE",
6668 "IDMA_PUSH_MORE_CPL_FIFO",
6669 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6670 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6671 "IDMA_PHYSADDR_SEND_PCIEHDR",
6672 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6673 "IDMA_PHYSADDR_SEND_PAYLOAD",
6674 "IDMA_SEND_FIFO_TO_IMSG",
6675 "IDMA_FL_REQ_DATA_FL",
6676 "IDMA_FL_DROP",
6677 "IDMA_FL_DROP_SEND_INC",
6678 "IDMA_FL_H_REQ_HEADER_FL",
6679 "IDMA_FL_H_SEND_PCIEHDR",
6680 "IDMA_FL_H_PUSH_CPL_FIFO",
6681 "IDMA_FL_H_SEND_CPL",
6682 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6683 "IDMA_FL_H_SEND_IP_HDR",
6684 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6685 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6686 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6687 "IDMA_FL_D_SEND_PCIEHDR",
6688 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6689 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6690 "IDMA_FL_SEND_PCIEHDR",
6691 "IDMA_FL_PUSH_CPL_FIFO",
6692 "IDMA_FL_SEND_CPL",
6693 "IDMA_FL_SEND_PAYLOAD_FIRST",
6694 "IDMA_FL_SEND_PAYLOAD",
6695 "IDMA_FL_REQ_NEXT_DATA_FL",
6696 "IDMA_FL_SEND_NEXT_PCIEHDR",
6697 "IDMA_FL_SEND_PADDING",
6698 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6699 };
6700 static const char * const t6_decode[] = {
6701 "IDMA_IDLE",
6702 "IDMA_PUSH_MORE_CPL_FIFO",
6703 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6704 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6705 "IDMA_PHYSADDR_SEND_PCIEHDR",
6706 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6707 "IDMA_PHYSADDR_SEND_PAYLOAD",
6708 "IDMA_FL_REQ_DATA_FL",
6709 "IDMA_FL_DROP",
6710 "IDMA_FL_DROP_SEND_INC",
6711 "IDMA_FL_H_REQ_HEADER_FL",
6712 "IDMA_FL_H_SEND_PCIEHDR",
6713 "IDMA_FL_H_PUSH_CPL_FIFO",
6714 "IDMA_FL_H_SEND_CPL",
6715 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6716 "IDMA_FL_H_SEND_IP_HDR",
6717 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6718 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6719 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6720 "IDMA_FL_D_SEND_PCIEHDR",
6721 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6722 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6723 "IDMA_FL_SEND_PCIEHDR",
6724 "IDMA_FL_PUSH_CPL_FIFO",
6725 "IDMA_FL_SEND_CPL",
6726 "IDMA_FL_SEND_PAYLOAD_FIRST",
6727 "IDMA_FL_SEND_PAYLOAD",
6728 "IDMA_FL_REQ_NEXT_DATA_FL",
6729 "IDMA_FL_SEND_NEXT_PCIEHDR",
6730 "IDMA_FL_SEND_PADDING",
6731 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6732 };
6733 static const u32 sge_regs[] = {
6734 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6735 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6736 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6737 };
6738 const char **sge_idma_decode;
6739 int sge_idma_decode_nstates;
6740 int i;
6741 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6742
6743 /* Select the right set of decode strings to dump depending on the
6744 * adapter chip type.
6745 */
6746 switch (chip_version) {
6747 case CHELSIO_T4:
6748 sge_idma_decode = (const char **)t4_decode;
6749 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6750 break;
6751
6752 case CHELSIO_T5:
6753 sge_idma_decode = (const char **)t5_decode;
6754 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6755 break;
6756
6757 case CHELSIO_T6:
6758 sge_idma_decode = (const char **)t6_decode;
6759 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6760 break;
6761
6762 default:
6763 dev_err(adapter->pdev_dev,
6764 "Unsupported chip version %d\n", chip_version);
6765 return;
6766 }
6767
6768 if (is_t4(adapter->params.chip)) {
6769 sge_idma_decode = (const char **)t4_decode;
6770 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6771 } else {
6772 sge_idma_decode = (const char **)t5_decode;
6773 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6774 }
6775
6776 if (state < sge_idma_decode_nstates)
6777 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6778 else
6779 CH_WARN(adapter, "idma state %d unknown\n", state);
6780
6781 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6782 CH_WARN(adapter, "SGE register %#x value %#x\n",
6783 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6784 }
6785
6786 /**
6787 * t4_sge_ctxt_flush - flush the SGE context cache
6788 * @adap: the adapter
6789 * @mbox: mailbox to use for the FW command
6790 * @ctxt_type: Egress or Ingress
6791 *
6792 * Issues a FW command through the given mailbox to flush the
6793 * SGE context cache.
6794 */
t4_sge_ctxt_flush(struct adapter * adap,unsigned int mbox,int ctxt_type)6795 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6796 {
6797 int ret;
6798 u32 ldst_addrspace;
6799 struct fw_ldst_cmd c;
6800
6801 memset(&c, 0, sizeof(c));
6802 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6803 FW_LDST_ADDRSPC_SGE_EGRC :
6804 FW_LDST_ADDRSPC_SGE_INGC);
6805 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6806 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6807 ldst_addrspace);
6808 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6809 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6810
6811 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6812 return ret;
6813 }
6814
6815 /**
6816 * t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6817 * @adap: the adapter
6818 * @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6819 * @dbqtimers: SGE Doorbell Queue Timer table
6820 *
6821 * Reads the SGE Doorbell Queue Timer values into the provided table.
6822 * Returns 0 on success (Firmware and Hardware support this feature),
6823 * an error on failure.
6824 */
t4_read_sge_dbqtimers(struct adapter * adap,unsigned int ndbqtimers,u16 * dbqtimers)6825 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
6826 u16 *dbqtimers)
6827 {
6828 int ret, dbqtimerix;
6829
6830 ret = 0;
6831 dbqtimerix = 0;
6832 while (dbqtimerix < ndbqtimers) {
6833 int nparams, param;
6834 u32 params[7], vals[7];
6835
6836 nparams = ndbqtimers - dbqtimerix;
6837 if (nparams > ARRAY_SIZE(params))
6838 nparams = ARRAY_SIZE(params);
6839
6840 for (param = 0; param < nparams; param++)
6841 params[param] =
6842 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6843 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMER) |
6844 FW_PARAMS_PARAM_Y_V(dbqtimerix + param));
6845 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
6846 nparams, params, vals);
6847 if (ret)
6848 break;
6849
6850 for (param = 0; param < nparams; param++)
6851 dbqtimers[dbqtimerix++] = vals[param];
6852 }
6853 return ret;
6854 }
6855
6856 /**
6857 * t4_fw_hello - establish communication with FW
6858 * @adap: the adapter
6859 * @mbox: mailbox to use for the FW command
6860 * @evt_mbox: mailbox to receive async FW events
6861 * @master: specifies the caller's willingness to be the device master
6862 * @state: returns the current device state (if non-NULL)
6863 *
6864 * Issues a command to establish communication with FW. Returns either
6865 * an error (negative integer) or the mailbox of the Master PF.
6866 */
t4_fw_hello(struct adapter * adap,unsigned int mbox,unsigned int evt_mbox,enum dev_master master,enum dev_state * state)6867 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6868 enum dev_master master, enum dev_state *state)
6869 {
6870 int ret;
6871 struct fw_hello_cmd c;
6872 u32 v;
6873 unsigned int master_mbox;
6874 int retries = FW_CMD_HELLO_RETRIES;
6875
6876 retry:
6877 memset(&c, 0, sizeof(c));
6878 INIT_CMD(c, HELLO, WRITE);
6879 c.err_to_clearinit = cpu_to_be32(
6880 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6881 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6882 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6883 mbox : FW_HELLO_CMD_MBMASTER_M) |
6884 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6885 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6886 FW_HELLO_CMD_CLEARINIT_F);
6887
6888 /*
6889 * Issue the HELLO command to the firmware. If it's not successful
6890 * but indicates that we got a "busy" or "timeout" condition, retry
6891 * the HELLO until we exhaust our retry limit. If we do exceed our
6892 * retry limit, check to see if the firmware left us any error
6893 * information and report that if so.
6894 */
6895 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6896 if (ret < 0) {
6897 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6898 goto retry;
6899 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6900 t4_report_fw_error(adap);
6901 return ret;
6902 }
6903
6904 v = be32_to_cpu(c.err_to_clearinit);
6905 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6906 if (state) {
6907 if (v & FW_HELLO_CMD_ERR_F)
6908 *state = DEV_STATE_ERR;
6909 else if (v & FW_HELLO_CMD_INIT_F)
6910 *state = DEV_STATE_INIT;
6911 else
6912 *state = DEV_STATE_UNINIT;
6913 }
6914
6915 /*
6916 * If we're not the Master PF then we need to wait around for the
6917 * Master PF Driver to finish setting up the adapter.
6918 *
6919 * Note that we also do this wait if we're a non-Master-capable PF and
6920 * there is no current Master PF; a Master PF may show up momentarily
6921 * and we wouldn't want to fail pointlessly. (This can happen when an
6922 * OS loads lots of different drivers rapidly at the same time). In
6923 * this case, the Master PF returned by the firmware will be
6924 * PCIE_FW_MASTER_M so the test below will work ...
6925 */
6926 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6927 master_mbox != mbox) {
6928 int waiting = FW_CMD_HELLO_TIMEOUT;
6929
6930 /*
6931 * Wait for the firmware to either indicate an error or
6932 * initialized state. If we see either of these we bail out
6933 * and report the issue to the caller. If we exhaust the
6934 * "hello timeout" and we haven't exhausted our retries, try
6935 * again. Otherwise bail with a timeout error.
6936 */
6937 for (;;) {
6938 u32 pcie_fw;
6939
6940 msleep(50);
6941 waiting -= 50;
6942
6943 /*
6944 * If neither Error nor Initialized are indicated
6945 * by the firmware keep waiting till we exhaust our
6946 * timeout ... and then retry if we haven't exhausted
6947 * our retries ...
6948 */
6949 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6950 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6951 if (waiting <= 0) {
6952 if (retries-- > 0)
6953 goto retry;
6954
6955 return -ETIMEDOUT;
6956 }
6957 continue;
6958 }
6959
6960 /*
6961 * We either have an Error or Initialized condition
6962 * report errors preferentially.
6963 */
6964 if (state) {
6965 if (pcie_fw & PCIE_FW_ERR_F)
6966 *state = DEV_STATE_ERR;
6967 else if (pcie_fw & PCIE_FW_INIT_F)
6968 *state = DEV_STATE_INIT;
6969 }
6970
6971 /*
6972 * If we arrived before a Master PF was selected and
6973 * there's not a valid Master PF, grab its identity
6974 * for our caller.
6975 */
6976 if (master_mbox == PCIE_FW_MASTER_M &&
6977 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6978 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6979 break;
6980 }
6981 }
6982
6983 return master_mbox;
6984 }
6985
6986 /**
6987 * t4_fw_bye - end communication with FW
6988 * @adap: the adapter
6989 * @mbox: mailbox to use for the FW command
6990 *
6991 * Issues a command to terminate communication with FW.
6992 */
t4_fw_bye(struct adapter * adap,unsigned int mbox)6993 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6994 {
6995 struct fw_bye_cmd c;
6996
6997 memset(&c, 0, sizeof(c));
6998 INIT_CMD(c, BYE, WRITE);
6999 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7000 }
7001
7002 /**
7003 * t4_init_cmd - ask FW to initialize the device
7004 * @adap: the adapter
7005 * @mbox: mailbox to use for the FW command
7006 *
7007 * Issues a command to FW to partially initialize the device. This
7008 * performs initialization that generally doesn't depend on user input.
7009 */
t4_early_init(struct adapter * adap,unsigned int mbox)7010 int t4_early_init(struct adapter *adap, unsigned int mbox)
7011 {
7012 struct fw_initialize_cmd c;
7013
7014 memset(&c, 0, sizeof(c));
7015 INIT_CMD(c, INITIALIZE, WRITE);
7016 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7017 }
7018
7019 /**
7020 * t4_fw_reset - issue a reset to FW
7021 * @adap: the adapter
7022 * @mbox: mailbox to use for the FW command
7023 * @reset: specifies the type of reset to perform
7024 *
7025 * Issues a reset command of the specified type to FW.
7026 */
t4_fw_reset(struct adapter * adap,unsigned int mbox,int reset)7027 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7028 {
7029 struct fw_reset_cmd c;
7030
7031 memset(&c, 0, sizeof(c));
7032 INIT_CMD(c, RESET, WRITE);
7033 c.val = cpu_to_be32(reset);
7034 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7035 }
7036
7037 /**
7038 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7039 * @adap: the adapter
7040 * @mbox: mailbox to use for the FW RESET command (if desired)
7041 * @force: force uP into RESET even if FW RESET command fails
7042 *
7043 * Issues a RESET command to firmware (if desired) with a HALT indication
7044 * and then puts the microprocessor into RESET state. The RESET command
7045 * will only be issued if a legitimate mailbox is provided (mbox <=
7046 * PCIE_FW_MASTER_M).
7047 *
7048 * This is generally used in order for the host to safely manipulate the
7049 * adapter without fear of conflicting with whatever the firmware might
7050 * be doing. The only way out of this state is to RESTART the firmware
7051 * ...
7052 */
t4_fw_halt(struct adapter * adap,unsigned int mbox,int force)7053 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7054 {
7055 int ret = 0;
7056
7057 /*
7058 * If a legitimate mailbox is provided, issue a RESET command
7059 * with a HALT indication.
7060 */
7061 if (mbox <= PCIE_FW_MASTER_M) {
7062 struct fw_reset_cmd c;
7063
7064 memset(&c, 0, sizeof(c));
7065 INIT_CMD(c, RESET, WRITE);
7066 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
7067 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
7068 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7069 }
7070
7071 /*
7072 * Normally we won't complete the operation if the firmware RESET
7073 * command fails but if our caller insists we'll go ahead and put the
7074 * uP into RESET. This can be useful if the firmware is hung or even
7075 * missing ... We'll have to take the risk of putting the uP into
7076 * RESET without the cooperation of firmware in that case.
7077 *
7078 * We also force the firmware's HALT flag to be on in case we bypassed
7079 * the firmware RESET command above or we're dealing with old firmware
7080 * which doesn't have the HALT capability. This will serve as a flag
7081 * for the incoming firmware to know that it's coming out of a HALT
7082 * rather than a RESET ... if it's new enough to understand that ...
7083 */
7084 if (ret == 0 || force) {
7085 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
7086 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
7087 PCIE_FW_HALT_F);
7088 }
7089
7090 /*
7091 * And we always return the result of the firmware RESET command
7092 * even when we force the uP into RESET ...
7093 */
7094 return ret;
7095 }
7096
7097 /**
7098 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7099 * @adap: the adapter
7100 * @mbox: mailbox to use for the FW command
7101 * @reset: if we want to do a RESET to restart things
7102 *
7103 * Restart firmware previously halted by t4_fw_halt(). On successful
7104 * return the previous PF Master remains as the new PF Master and there
7105 * is no need to issue a new HELLO command, etc.
7106 *
7107 * We do this in two ways:
7108 *
7109 * 1. If we're dealing with newer firmware we'll simply want to take
7110 * the chip's microprocessor out of RESET. This will cause the
7111 * firmware to start up from its start vector. And then we'll loop
7112 * until the firmware indicates it's started again (PCIE_FW.HALT
7113 * reset to 0) or we timeout.
7114 *
7115 * 2. If we're dealing with older firmware then we'll need to RESET
7116 * the chip since older firmware won't recognize the PCIE_FW.HALT
7117 * flag and automatically RESET itself on startup.
7118 */
t4_fw_restart(struct adapter * adap,unsigned int mbox,int reset)7119 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
7120 {
7121 if (reset) {
7122 /*
7123 * Since we're directing the RESET instead of the firmware
7124 * doing it automatically, we need to clear the PCIE_FW.HALT
7125 * bit.
7126 */
7127 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
7128
7129 /*
7130 * If we've been given a valid mailbox, first try to get the
7131 * firmware to do the RESET. If that works, great and we can
7132 * return success. Otherwise, if we haven't been given a
7133 * valid mailbox or the RESET command failed, fall back to
7134 * hitting the chip with a hammer.
7135 */
7136 if (mbox <= PCIE_FW_MASTER_M) {
7137 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7138 msleep(100);
7139 if (t4_fw_reset(adap, mbox,
7140 PIORST_F | PIORSTMODE_F) == 0)
7141 return 0;
7142 }
7143
7144 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
7145 msleep(2000);
7146 } else {
7147 int ms;
7148
7149 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7150 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7151 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
7152 return 0;
7153 msleep(100);
7154 ms += 100;
7155 }
7156 return -ETIMEDOUT;
7157 }
7158 return 0;
7159 }
7160
7161 /**
7162 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7163 * @adap: the adapter
7164 * @mbox: mailbox to use for the FW RESET command (if desired)
7165 * @fw_data: the firmware image to write
7166 * @size: image size
7167 * @force: force upgrade even if firmware doesn't cooperate
7168 *
7169 * Perform all of the steps necessary for upgrading an adapter's
7170 * firmware image. Normally this requires the cooperation of the
7171 * existing firmware in order to halt all existing activities
7172 * but if an invalid mailbox token is passed in we skip that step
7173 * (though we'll still put the adapter microprocessor into RESET in
7174 * that case).
7175 *
7176 * On successful return the new firmware will have been loaded and
7177 * the adapter will have been fully RESET losing all previous setup
7178 * state. On unsuccessful return the adapter may be completely hosed ...
7179 * positive errno indicates that the adapter is ~probably~ intact, a
7180 * negative errno indicates that things are looking bad ...
7181 */
t4_fw_upgrade(struct adapter * adap,unsigned int mbox,const u8 * fw_data,unsigned int size,int force)7182 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7183 const u8 *fw_data, unsigned int size, int force)
7184 {
7185 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7186 int reset, ret;
7187
7188 if (!t4_fw_matches_chip(adap, fw_hdr))
7189 return -EINVAL;
7190
7191 /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7192 * set wont be sent when we are flashing FW.
7193 */
7194 adap->flags &= ~CXGB4_FW_OK;
7195
7196 ret = t4_fw_halt(adap, mbox, force);
7197 if (ret < 0 && !force)
7198 goto out;
7199
7200 ret = t4_load_fw(adap, fw_data, size);
7201 if (ret < 0)
7202 goto out;
7203
7204 /*
7205 * If there was a Firmware Configuration File stored in FLASH,
7206 * there's a good chance that it won't be compatible with the new
7207 * Firmware. In order to prevent difficult to diagnose adapter
7208 * initialization issues, we clear out the Firmware Configuration File
7209 * portion of the FLASH . The user will need to re-FLASH a new
7210 * Firmware Configuration File which is compatible with the new
7211 * Firmware if that's desired.
7212 */
7213 (void)t4_load_cfg(adap, NULL, 0);
7214
7215 /*
7216 * Older versions of the firmware don't understand the new
7217 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7218 * restart. So for newly loaded older firmware we'll have to do the
7219 * RESET for it so it starts up on a clean slate. We can tell if
7220 * the newly loaded firmware will handle this right by checking
7221 * its header flags to see if it advertises the capability.
7222 */
7223 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
7224 ret = t4_fw_restart(adap, mbox, reset);
7225
7226 /* Grab potentially new Firmware Device Log parameters so we can see
7227 * how healthy the new Firmware is. It's okay to contact the new
7228 * Firmware for these parameters even though, as far as it's
7229 * concerned, we've never said "HELLO" to it ...
7230 */
7231 (void)t4_init_devlog_params(adap);
7232 out:
7233 adap->flags |= CXGB4_FW_OK;
7234 return ret;
7235 }
7236
7237 /**
7238 * t4_fl_pkt_align - return the fl packet alignment
7239 * @adap: the adapter
7240 *
7241 * T4 has a single field to specify the packing and padding boundary.
7242 * T5 onwards has separate fields for this and hence the alignment for
7243 * next packet offset is maximum of these two.
7244 *
7245 */
t4_fl_pkt_align(struct adapter * adap)7246 int t4_fl_pkt_align(struct adapter *adap)
7247 {
7248 u32 sge_control, sge_control2;
7249 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7250
7251 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7252
7253 /* T4 uses a single control field to specify both the PCIe Padding and
7254 * Packing Boundary. T5 introduced the ability to specify these
7255 * separately. The actual Ingress Packet Data alignment boundary
7256 * within Packed Buffer Mode is the maximum of these two
7257 * specifications. (Note that it makes no real practical sense to
7258 * have the Padding Boundary be larger than the Packing Boundary but you
7259 * could set the chip up that way and, in fact, legacy T4 code would
7260 * end doing this because it would initialize the Padding Boundary and
7261 * leave the Packing Boundary initialized to 0 (16 bytes).)
7262 * Padding Boundary values in T6 starts from 8B,
7263 * where as it is 32B for T4 and T5.
7264 */
7265 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7266 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7267 else
7268 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7269
7270 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7271
7272 fl_align = ingpadboundary;
7273 if (!is_t4(adap->params.chip)) {
7274 /* T5 has a weird interpretation of one of the PCIe Packing
7275 * Boundary values. No idea why ...
7276 */
7277 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7278 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7279 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7280 ingpackboundary = 16;
7281 else
7282 ingpackboundary = 1 << (ingpackboundary +
7283 INGPACKBOUNDARY_SHIFT_X);
7284
7285 fl_align = max(ingpadboundary, ingpackboundary);
7286 }
7287 return fl_align;
7288 }
7289
7290 /**
7291 * t4_fixup_host_params - fix up host-dependent parameters
7292 * @adap: the adapter
7293 * @page_size: the host's Base Page Size
7294 * @cache_line_size: the host's Cache Line Size
7295 *
7296 * Various registers in T4 contain values which are dependent on the
7297 * host's Base Page and Cache Line Sizes. This function will fix all of
7298 * those registers with the appropriate values as passed in ...
7299 */
t4_fixup_host_params(struct adapter * adap,unsigned int page_size,unsigned int cache_line_size)7300 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7301 unsigned int cache_line_size)
7302 {
7303 unsigned int page_shift = fls(page_size) - 1;
7304 unsigned int sge_hps = page_shift - 10;
7305 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7306 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7307 unsigned int fl_align_log = fls(fl_align) - 1;
7308
7309 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7310 HOSTPAGESIZEPF0_V(sge_hps) |
7311 HOSTPAGESIZEPF1_V(sge_hps) |
7312 HOSTPAGESIZEPF2_V(sge_hps) |
7313 HOSTPAGESIZEPF3_V(sge_hps) |
7314 HOSTPAGESIZEPF4_V(sge_hps) |
7315 HOSTPAGESIZEPF5_V(sge_hps) |
7316 HOSTPAGESIZEPF6_V(sge_hps) |
7317 HOSTPAGESIZEPF7_V(sge_hps));
7318
7319 if (is_t4(adap->params.chip)) {
7320 t4_set_reg_field(adap, SGE_CONTROL_A,
7321 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7322 EGRSTATUSPAGESIZE_F,
7323 INGPADBOUNDARY_V(fl_align_log -
7324 INGPADBOUNDARY_SHIFT_X) |
7325 EGRSTATUSPAGESIZE_V(stat_len != 64));
7326 } else {
7327 unsigned int pack_align;
7328 unsigned int ingpad, ingpack;
7329
7330 /* T5 introduced the separation of the Free List Padding and
7331 * Packing Boundaries. Thus, we can select a smaller Padding
7332 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7333 * Bandwidth, and use a Packing Boundary which is large enough
7334 * to avoid false sharing between CPUs, etc.
7335 *
7336 * For the PCI Link, the smaller the Padding Boundary the
7337 * better. For the Memory Controller, a smaller Padding
7338 * Boundary is better until we cross under the Memory Line
7339 * Size (the minimum unit of transfer to/from Memory). If we
7340 * have a Padding Boundary which is smaller than the Memory
7341 * Line Size, that'll involve a Read-Modify-Write cycle on the
7342 * Memory Controller which is never good.
7343 */
7344
7345 /* We want the Packing Boundary to be based on the Cache Line
7346 * Size in order to help avoid False Sharing performance
7347 * issues between CPUs, etc. We also want the Packing
7348 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7349 * get best performance when the Packing Boundary is a
7350 * multiple of the Maximum Payload Size.
7351 */
7352 pack_align = fl_align;
7353 if (pci_is_pcie(adap->pdev)) {
7354 unsigned int mps, mps_log;
7355 u16 devctl;
7356
7357 /* The PCIe Device Control Maximum Payload Size field
7358 * [bits 7:5] encodes sizes as powers of 2 starting at
7359 * 128 bytes.
7360 */
7361 pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL,
7362 &devctl);
7363 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7364 mps = 1 << mps_log;
7365 if (mps > pack_align)
7366 pack_align = mps;
7367 }
7368
7369 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7370 * value for the Packing Boundary. This corresponds to 16
7371 * bytes instead of the expected 32 bytes. So if we want 32
7372 * bytes, the best we can really do is 64 bytes ...
7373 */
7374 if (pack_align <= 16) {
7375 ingpack = INGPACKBOUNDARY_16B_X;
7376 fl_align = 16;
7377 } else if (pack_align == 32) {
7378 ingpack = INGPACKBOUNDARY_64B_X;
7379 fl_align = 64;
7380 } else {
7381 unsigned int pack_align_log = fls(pack_align) - 1;
7382
7383 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7384 fl_align = pack_align;
7385 }
7386
7387 /* Use the smallest Ingress Padding which isn't smaller than
7388 * the Memory Controller Read/Write Size. We'll take that as
7389 * being 8 bytes since we don't know of any system with a
7390 * wider Memory Controller Bus Width.
7391 */
7392 if (is_t5(adap->params.chip))
7393 ingpad = INGPADBOUNDARY_32B_X;
7394 else
7395 ingpad = T6_INGPADBOUNDARY_8B_X;
7396
7397 t4_set_reg_field(adap, SGE_CONTROL_A,
7398 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7399 EGRSTATUSPAGESIZE_F,
7400 INGPADBOUNDARY_V(ingpad) |
7401 EGRSTATUSPAGESIZE_V(stat_len != 64));
7402 t4_set_reg_field(adap, SGE_CONTROL2_A,
7403 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7404 INGPACKBOUNDARY_V(ingpack));
7405 }
7406 /*
7407 * Adjust various SGE Free List Host Buffer Sizes.
7408 *
7409 * This is something of a crock since we're using fixed indices into
7410 * the array which are also known by the sge.c code and the T4
7411 * Firmware Configuration File. We need to come up with a much better
7412 * approach to managing this array. For now, the first four entries
7413 * are:
7414 *
7415 * 0: Host Page Size
7416 * 1: 64KB
7417 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7418 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7419 *
7420 * For the single-MTU buffers in unpacked mode we need to include
7421 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7422 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7423 * Padding boundary. All of these are accommodated in the Factory
7424 * Default Firmware Configuration File but we need to adjust it for
7425 * this host's cache line size.
7426 */
7427 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7428 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7429 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7430 & ~(fl_align-1));
7431 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7432 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7433 & ~(fl_align-1));
7434
7435 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7436
7437 return 0;
7438 }
7439
7440 /**
7441 * t4_fw_initialize - ask FW to initialize the device
7442 * @adap: the adapter
7443 * @mbox: mailbox to use for the FW command
7444 *
7445 * Issues a command to FW to partially initialize the device. This
7446 * performs initialization that generally doesn't depend on user input.
7447 */
t4_fw_initialize(struct adapter * adap,unsigned int mbox)7448 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7449 {
7450 struct fw_initialize_cmd c;
7451
7452 memset(&c, 0, sizeof(c));
7453 INIT_CMD(c, INITIALIZE, WRITE);
7454 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7455 }
7456
7457 /**
7458 * t4_query_params_rw - query FW or device parameters
7459 * @adap: the adapter
7460 * @mbox: mailbox to use for the FW command
7461 * @pf: the PF
7462 * @vf: the VF
7463 * @nparams: the number of parameters
7464 * @params: the parameter names
7465 * @val: the parameter values
7466 * @rw: Write and read flag
7467 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7468 *
7469 * Reads the value of FW or device parameters. Up to 7 parameters can be
7470 * queried at once.
7471 */
t4_query_params_rw(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,u32 * val,int rw,bool sleep_ok)7472 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7473 unsigned int vf, unsigned int nparams, const u32 *params,
7474 u32 *val, int rw, bool sleep_ok)
7475 {
7476 int i, ret;
7477 struct fw_params_cmd c;
7478 __be32 *p = &c.param[0].mnem;
7479
7480 if (nparams > 7)
7481 return -EINVAL;
7482
7483 memset(&c, 0, sizeof(c));
7484 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7485 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7486 FW_PARAMS_CMD_PFN_V(pf) |
7487 FW_PARAMS_CMD_VFN_V(vf));
7488 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7489
7490 for (i = 0; i < nparams; i++) {
7491 *p++ = cpu_to_be32(*params++);
7492 if (rw)
7493 *p = cpu_to_be32(*(val + i));
7494 p++;
7495 }
7496
7497 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7498 if (ret == 0)
7499 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7500 *val++ = be32_to_cpu(*p);
7501 return ret;
7502 }
7503
t4_query_params(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,u32 * val)7504 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7505 unsigned int vf, unsigned int nparams, const u32 *params,
7506 u32 *val)
7507 {
7508 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7509 true);
7510 }
7511
t4_query_params_ns(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,u32 * val)7512 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7513 unsigned int vf, unsigned int nparams, const u32 *params,
7514 u32 *val)
7515 {
7516 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7517 false);
7518 }
7519
7520 /**
7521 * t4_set_params_timeout - sets FW or device parameters
7522 * @adap: the adapter
7523 * @mbox: mailbox to use for the FW command
7524 * @pf: the PF
7525 * @vf: the VF
7526 * @nparams: the number of parameters
7527 * @params: the parameter names
7528 * @val: the parameter values
7529 * @timeout: the timeout time
7530 *
7531 * Sets the value of FW or device parameters. Up to 7 parameters can be
7532 * specified at once.
7533 */
t4_set_params_timeout(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,const u32 * val,int timeout)7534 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7535 unsigned int pf, unsigned int vf,
7536 unsigned int nparams, const u32 *params,
7537 const u32 *val, int timeout)
7538 {
7539 struct fw_params_cmd c;
7540 __be32 *p = &c.param[0].mnem;
7541
7542 if (nparams > 7)
7543 return -EINVAL;
7544
7545 memset(&c, 0, sizeof(c));
7546 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7547 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7548 FW_PARAMS_CMD_PFN_V(pf) |
7549 FW_PARAMS_CMD_VFN_V(vf));
7550 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7551
7552 while (nparams--) {
7553 *p++ = cpu_to_be32(*params++);
7554 *p++ = cpu_to_be32(*val++);
7555 }
7556
7557 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7558 }
7559
7560 /**
7561 * t4_set_params - sets FW or device parameters
7562 * @adap: the adapter
7563 * @mbox: mailbox to use for the FW command
7564 * @pf: the PF
7565 * @vf: the VF
7566 * @nparams: the number of parameters
7567 * @params: the parameter names
7568 * @val: the parameter values
7569 *
7570 * Sets the value of FW or device parameters. Up to 7 parameters can be
7571 * specified at once.
7572 */
t4_set_params(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,const u32 * val)7573 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7574 unsigned int vf, unsigned int nparams, const u32 *params,
7575 const u32 *val)
7576 {
7577 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7578 FW_CMD_MAX_TIMEOUT);
7579 }
7580
7581 /**
7582 * t4_cfg_pfvf - configure PF/VF resource limits
7583 * @adap: the adapter
7584 * @mbox: mailbox to use for the FW command
7585 * @pf: the PF being configured
7586 * @vf: the VF being configured
7587 * @txq: the max number of egress queues
7588 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7589 * @rxqi: the max number of interrupt-capable ingress queues
7590 * @rxq: the max number of interruptless ingress queues
7591 * @tc: the PCI traffic class
7592 * @vi: the max number of virtual interfaces
7593 * @cmask: the channel access rights mask for the PF/VF
7594 * @pmask: the port access rights mask for the PF/VF
7595 * @nexact: the maximum number of exact MPS filters
7596 * @rcaps: read capabilities
7597 * @wxcaps: write/execute capabilities
7598 *
7599 * Configures resource limits and capabilities for a physical or virtual
7600 * function.
7601 */
t4_cfg_pfvf(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int txq,unsigned int txq_eth_ctrl,unsigned int rxqi,unsigned int rxq,unsigned int tc,unsigned int vi,unsigned int cmask,unsigned int pmask,unsigned int nexact,unsigned int rcaps,unsigned int wxcaps)7602 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7603 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7604 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7605 unsigned int vi, unsigned int cmask, unsigned int pmask,
7606 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7607 {
7608 struct fw_pfvf_cmd c;
7609
7610 memset(&c, 0, sizeof(c));
7611 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7612 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7613 FW_PFVF_CMD_VFN_V(vf));
7614 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7615 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7616 FW_PFVF_CMD_NIQ_V(rxq));
7617 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7618 FW_PFVF_CMD_PMASK_V(pmask) |
7619 FW_PFVF_CMD_NEQ_V(txq));
7620 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7621 FW_PFVF_CMD_NVI_V(vi) |
7622 FW_PFVF_CMD_NEXACTF_V(nexact));
7623 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7624 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7625 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7626 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7627 }
7628
7629 /**
7630 * t4_alloc_vi - allocate a virtual interface
7631 * @adap: the adapter
7632 * @mbox: mailbox to use for the FW command
7633 * @port: physical port associated with the VI
7634 * @pf: the PF owning the VI
7635 * @vf: the VF owning the VI
7636 * @nmac: number of MAC addresses needed (1 to 5)
7637 * @mac: the MAC addresses of the VI
7638 * @rss_size: size of RSS table slice associated with this VI
7639 * @vivld: the destination to store the VI Valid value.
7640 * @vin: the destination to store the VIN value.
7641 *
7642 * Allocates a virtual interface for the given physical port. If @mac is
7643 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7644 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7645 * stored consecutively so the space needed is @nmac * 6 bytes.
7646 * Returns a negative error number or the non-negative VI id.
7647 */
t4_alloc_vi(struct adapter * adap,unsigned int mbox,unsigned int port,unsigned int pf,unsigned int vf,unsigned int nmac,u8 * mac,unsigned int * rss_size,u8 * vivld,u8 * vin)7648 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7649 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7650 unsigned int *rss_size, u8 *vivld, u8 *vin)
7651 {
7652 int ret;
7653 struct fw_vi_cmd c;
7654
7655 memset(&c, 0, sizeof(c));
7656 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7657 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7658 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7659 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7660 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7661 c.nmac = nmac - 1;
7662
7663 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7664 if (ret)
7665 return ret;
7666
7667 if (mac) {
7668 memcpy(mac, c.mac, sizeof(c.mac));
7669 switch (nmac) {
7670 case 5:
7671 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7672 fallthrough;
7673 case 4:
7674 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7675 fallthrough;
7676 case 3:
7677 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7678 fallthrough;
7679 case 2:
7680 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7681 }
7682 }
7683 if (rss_size)
7684 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7685
7686 if (vivld)
7687 *vivld = FW_VI_CMD_VFVLD_G(be32_to_cpu(c.alloc_to_len16));
7688
7689 if (vin)
7690 *vin = FW_VI_CMD_VIN_G(be32_to_cpu(c.alloc_to_len16));
7691
7692 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7693 }
7694
7695 /**
7696 * t4_free_vi - free a virtual interface
7697 * @adap: the adapter
7698 * @mbox: mailbox to use for the FW command
7699 * @pf: the PF owning the VI
7700 * @vf: the VF owning the VI
7701 * @viid: virtual interface identifiler
7702 *
7703 * Free a previously allocated virtual interface.
7704 */
t4_free_vi(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int viid)7705 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7706 unsigned int vf, unsigned int viid)
7707 {
7708 struct fw_vi_cmd c;
7709
7710 memset(&c, 0, sizeof(c));
7711 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7712 FW_CMD_REQUEST_F |
7713 FW_CMD_EXEC_F |
7714 FW_VI_CMD_PFN_V(pf) |
7715 FW_VI_CMD_VFN_V(vf));
7716 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7717 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7718
7719 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7720 }
7721
7722 /**
7723 * t4_set_rxmode - set Rx properties of a virtual interface
7724 * @adap: the adapter
7725 * @mbox: mailbox to use for the FW command
7726 * @viid: the VI id
7727 * @viid_mirror: the mirror VI id
7728 * @mtu: the new MTU or -1
7729 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7730 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7731 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7732 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7733 * @sleep_ok: if true we may sleep while awaiting command completion
7734 *
7735 * Sets Rx properties of a virtual interface.
7736 */
t4_set_rxmode(struct adapter * adap,unsigned int mbox,unsigned int viid,unsigned int viid_mirror,int mtu,int promisc,int all_multi,int bcast,int vlanex,bool sleep_ok)7737 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7738 unsigned int viid_mirror, int mtu, int promisc, int all_multi,
7739 int bcast, int vlanex, bool sleep_ok)
7740 {
7741 struct fw_vi_rxmode_cmd c, c_mirror;
7742 int ret;
7743
7744 /* convert to FW values */
7745 if (mtu < 0)
7746 mtu = FW_RXMODE_MTU_NO_CHG;
7747 if (promisc < 0)
7748 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7749 if (all_multi < 0)
7750 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7751 if (bcast < 0)
7752 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7753 if (vlanex < 0)
7754 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7755
7756 memset(&c, 0, sizeof(c));
7757 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7758 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7759 FW_VI_RXMODE_CMD_VIID_V(viid));
7760 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7761 c.mtu_to_vlanexen =
7762 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7763 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7764 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7765 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7766 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7767
7768 if (viid_mirror) {
7769 memcpy(&c_mirror, &c, sizeof(c_mirror));
7770 c_mirror.op_to_viid =
7771 cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7772 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7773 FW_VI_RXMODE_CMD_VIID_V(viid_mirror));
7774 }
7775
7776 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7777 if (ret)
7778 return ret;
7779
7780 if (viid_mirror)
7781 ret = t4_wr_mbox_meat(adap, mbox, &c_mirror, sizeof(c_mirror),
7782 NULL, sleep_ok);
7783
7784 return ret;
7785 }
7786
7787 /**
7788 * t4_free_encap_mac_filt - frees MPS entry at given index
7789 * @adap: the adapter
7790 * @viid: the VI id
7791 * @idx: index of MPS entry to be freed
7792 * @sleep_ok: call is allowed to sleep
7793 *
7794 * Frees the MPS entry at supplied index
7795 *
7796 * Returns a negative error number or zero on success
7797 */
t4_free_encap_mac_filt(struct adapter * adap,unsigned int viid,int idx,bool sleep_ok)7798 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7799 int idx, bool sleep_ok)
7800 {
7801 struct fw_vi_mac_exact *p;
7802 u8 addr[] = {0, 0, 0, 0, 0, 0};
7803 struct fw_vi_mac_cmd c;
7804 int ret = 0;
7805 u32 exact;
7806
7807 memset(&c, 0, sizeof(c));
7808 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7809 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7810 FW_CMD_EXEC_V(0) |
7811 FW_VI_MAC_CMD_VIID_V(viid));
7812 exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7813 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7814 exact |
7815 FW_CMD_LEN16_V(1));
7816 p = c.u.exact;
7817 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7818 FW_VI_MAC_CMD_IDX_V(idx));
7819 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7820 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7821 return ret;
7822 }
7823
7824 /**
7825 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7826 * @adap: the adapter
7827 * @viid: the VI id
7828 * @addr: the MAC address
7829 * @mask: the mask
7830 * @idx: index of the entry in mps tcam
7831 * @lookup_type: MAC address for inner (1) or outer (0) header
7832 * @port_id: the port index
7833 * @sleep_ok: call is allowed to sleep
7834 *
7835 * Removes the mac entry at the specified index using raw mac interface.
7836 *
7837 * Returns a negative error number on failure.
7838 */
t4_free_raw_mac_filt(struct adapter * adap,unsigned int viid,const u8 * addr,const u8 * mask,unsigned int idx,u8 lookup_type,u8 port_id,bool sleep_ok)7839 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7840 const u8 *addr, const u8 *mask, unsigned int idx,
7841 u8 lookup_type, u8 port_id, bool sleep_ok)
7842 {
7843 struct fw_vi_mac_cmd c;
7844 struct fw_vi_mac_raw *p = &c.u.raw;
7845 u32 val;
7846
7847 memset(&c, 0, sizeof(c));
7848 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7849 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7850 FW_CMD_EXEC_V(0) |
7851 FW_VI_MAC_CMD_VIID_V(viid));
7852 val = FW_CMD_LEN16_V(1) |
7853 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7854 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7855 FW_CMD_LEN16_V(val));
7856
7857 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7858 FW_VI_MAC_ID_BASED_FREE);
7859
7860 /* Lookup Type. Outer header: 0, Inner header: 1 */
7861 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7862 DATAPORTNUM_V(port_id));
7863 /* Lookup mask and port mask */
7864 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7865 DATAPORTNUM_V(DATAPORTNUM_M));
7866
7867 /* Copy the address and the mask */
7868 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7869 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7870
7871 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7872 }
7873
7874 /**
7875 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7876 * @adap: the adapter
7877 * @viid: the VI id
7878 * @addr: the MAC address
7879 * @mask: the mask
7880 * @vni: the VNI id for the tunnel protocol
7881 * @vni_mask: mask for the VNI id
7882 * @dip_hit: to enable DIP match for the MPS entry
7883 * @lookup_type: MAC address for inner (1) or outer (0) header
7884 * @sleep_ok: call is allowed to sleep
7885 *
7886 * Allocates an MPS entry with specified MAC address and VNI value.
7887 *
7888 * Returns a negative error number or the allocated index for this mac.
7889 */
t4_alloc_encap_mac_filt(struct adapter * adap,unsigned int viid,const u8 * addr,const u8 * mask,unsigned int vni,unsigned int vni_mask,u8 dip_hit,u8 lookup_type,bool sleep_ok)7890 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7891 const u8 *addr, const u8 *mask, unsigned int vni,
7892 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7893 bool sleep_ok)
7894 {
7895 struct fw_vi_mac_cmd c;
7896 struct fw_vi_mac_vni *p = c.u.exact_vni;
7897 int ret = 0;
7898 u32 val;
7899
7900 memset(&c, 0, sizeof(c));
7901 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7902 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7903 FW_VI_MAC_CMD_VIID_V(viid));
7904 val = FW_CMD_LEN16_V(1) |
7905 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7906 c.freemacs_to_len16 = cpu_to_be32(val);
7907 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7908 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7909 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7910 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7911
7912 p->lookup_type_to_vni =
7913 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7914 FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7915 FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7916 p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7917 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7918 if (ret == 0)
7919 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7920 return ret;
7921 }
7922
7923 /**
7924 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7925 * @adap: the adapter
7926 * @viid: the VI id
7927 * @addr: the MAC address
7928 * @mask: the mask
7929 * @idx: index at which to add this entry
7930 * @lookup_type: MAC address for inner (1) or outer (0) header
7931 * @port_id: the port index
7932 * @sleep_ok: call is allowed to sleep
7933 *
7934 * Adds the mac entry at the specified index using raw mac interface.
7935 *
7936 * Returns a negative error number or the allocated index for this mac.
7937 */
t4_alloc_raw_mac_filt(struct adapter * adap,unsigned int viid,const u8 * addr,const u8 * mask,unsigned int idx,u8 lookup_type,u8 port_id,bool sleep_ok)7938 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7939 const u8 *addr, const u8 *mask, unsigned int idx,
7940 u8 lookup_type, u8 port_id, bool sleep_ok)
7941 {
7942 int ret = 0;
7943 struct fw_vi_mac_cmd c;
7944 struct fw_vi_mac_raw *p = &c.u.raw;
7945 u32 val;
7946
7947 memset(&c, 0, sizeof(c));
7948 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7949 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7950 FW_VI_MAC_CMD_VIID_V(viid));
7951 val = FW_CMD_LEN16_V(1) |
7952 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7953 c.freemacs_to_len16 = cpu_to_be32(val);
7954
7955 /* Specify that this is an inner mac address */
7956 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7957
7958 /* Lookup Type. Outer header: 0, Inner header: 1 */
7959 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7960 DATAPORTNUM_V(port_id));
7961 /* Lookup mask and port mask */
7962 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7963 DATAPORTNUM_V(DATAPORTNUM_M));
7964
7965 /* Copy the address and the mask */
7966 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7967 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7968
7969 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7970 if (ret == 0) {
7971 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7972 if (ret != idx)
7973 ret = -ENOMEM;
7974 }
7975
7976 return ret;
7977 }
7978
7979 /**
7980 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7981 * @adap: the adapter
7982 * @mbox: mailbox to use for the FW command
7983 * @viid: the VI id
7984 * @free: if true any existing filters for this VI id are first removed
7985 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7986 * @addr: the MAC address(es)
7987 * @idx: where to store the index of each allocated filter
7988 * @hash: pointer to hash address filter bitmap
7989 * @sleep_ok: call is allowed to sleep
7990 *
7991 * Allocates an exact-match filter for each of the supplied addresses and
7992 * sets it to the corresponding address. If @idx is not %NULL it should
7993 * have at least @naddr entries, each of which will be set to the index of
7994 * the filter allocated for the corresponding MAC address. If a filter
7995 * could not be allocated for an address its index is set to 0xffff.
7996 * If @hash is not %NULL addresses that fail to allocate an exact filter
7997 * are hashed and update the hash filter bitmap pointed at by @hash.
7998 *
7999 * Returns a negative error number or the number of filters allocated.
8000 */
t4_alloc_mac_filt(struct adapter * adap,unsigned int mbox,unsigned int viid,bool free,unsigned int naddr,const u8 ** addr,u16 * idx,u64 * hash,bool sleep_ok)8001 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
8002 unsigned int viid, bool free, unsigned int naddr,
8003 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
8004 {
8005 int offset, ret = 0;
8006 struct fw_vi_mac_cmd c;
8007 unsigned int nfilters = 0;
8008 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
8009 unsigned int rem = naddr;
8010
8011 if (naddr > max_naddr)
8012 return -EINVAL;
8013
8014 for (offset = 0; offset < naddr ; /**/) {
8015 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
8016 rem : ARRAY_SIZE(c.u.exact));
8017 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8018 u.exact[fw_naddr]), 16);
8019 struct fw_vi_mac_exact *p;
8020 int i;
8021
8022 memset(&c, 0, sizeof(c));
8023 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8024 FW_CMD_REQUEST_F |
8025 FW_CMD_WRITE_F |
8026 FW_CMD_EXEC_V(free) |
8027 FW_VI_MAC_CMD_VIID_V(viid));
8028 c.freemacs_to_len16 =
8029 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
8030 FW_CMD_LEN16_V(len16));
8031
8032 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8033 p->valid_to_idx =
8034 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8035 FW_VI_MAC_CMD_IDX_V(
8036 FW_VI_MAC_ADD_MAC));
8037 memcpy(p->macaddr, addr[offset + i],
8038 sizeof(p->macaddr));
8039 }
8040
8041 /* It's okay if we run out of space in our MAC address arena.
8042 * Some of the addresses we submit may get stored so we need
8043 * to run through the reply to see what the results were ...
8044 */
8045 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8046 if (ret && ret != -FW_ENOMEM)
8047 break;
8048
8049 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8050 u16 index = FW_VI_MAC_CMD_IDX_G(
8051 be16_to_cpu(p->valid_to_idx));
8052
8053 if (idx)
8054 idx[offset + i] = (index >= max_naddr ?
8055 0xffff : index);
8056 if (index < max_naddr)
8057 nfilters++;
8058 else if (hash)
8059 *hash |= (1ULL <<
8060 hash_mac_addr(addr[offset + i]));
8061 }
8062
8063 free = false;
8064 offset += fw_naddr;
8065 rem -= fw_naddr;
8066 }
8067
8068 if (ret == 0 || ret == -FW_ENOMEM)
8069 ret = nfilters;
8070 return ret;
8071 }
8072
8073 /**
8074 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8075 * @adap: the adapter
8076 * @mbox: mailbox to use for the FW command
8077 * @viid: the VI id
8078 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8079 * @addr: the MAC address(es)
8080 * @sleep_ok: call is allowed to sleep
8081 *
8082 * Frees the exact-match filter for each of the supplied addresses
8083 *
8084 * Returns a negative error number or the number of filters freed.
8085 */
t4_free_mac_filt(struct adapter * adap,unsigned int mbox,unsigned int viid,unsigned int naddr,const u8 ** addr,bool sleep_ok)8086 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8087 unsigned int viid, unsigned int naddr,
8088 const u8 **addr, bool sleep_ok)
8089 {
8090 int offset, ret = 0;
8091 struct fw_vi_mac_cmd c;
8092 unsigned int nfilters = 0;
8093 unsigned int max_naddr = is_t4(adap->params.chip) ?
8094 NUM_MPS_CLS_SRAM_L_INSTANCES :
8095 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8096 unsigned int rem = naddr;
8097
8098 if (naddr > max_naddr)
8099 return -EINVAL;
8100
8101 for (offset = 0; offset < (int)naddr ; /**/) {
8102 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8103 ? rem
8104 : ARRAY_SIZE(c.u.exact));
8105 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8106 u.exact[fw_naddr]), 16);
8107 struct fw_vi_mac_exact *p;
8108 int i;
8109
8110 memset(&c, 0, sizeof(c));
8111 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8112 FW_CMD_REQUEST_F |
8113 FW_CMD_WRITE_F |
8114 FW_CMD_EXEC_V(0) |
8115 FW_VI_MAC_CMD_VIID_V(viid));
8116 c.freemacs_to_len16 =
8117 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
8118 FW_CMD_LEN16_V(len16));
8119
8120 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8121 p->valid_to_idx = cpu_to_be16(
8122 FW_VI_MAC_CMD_VALID_F |
8123 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
8124 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8125 }
8126
8127 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8128 if (ret)
8129 break;
8130
8131 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8132 u16 index = FW_VI_MAC_CMD_IDX_G(
8133 be16_to_cpu(p->valid_to_idx));
8134
8135 if (index < max_naddr)
8136 nfilters++;
8137 }
8138
8139 offset += fw_naddr;
8140 rem -= fw_naddr;
8141 }
8142
8143 if (ret == 0)
8144 ret = nfilters;
8145 return ret;
8146 }
8147
8148 /**
8149 * t4_change_mac - modifies the exact-match filter for a MAC address
8150 * @adap: the adapter
8151 * @mbox: mailbox to use for the FW command
8152 * @viid: the VI id
8153 * @idx: index of existing filter for old value of MAC address, or -1
8154 * @addr: the new MAC address value
8155 * @persist: whether a new MAC allocation should be persistent
8156 * @smt_idx: the destination to store the new SMT index.
8157 *
8158 * Modifies an exact-match filter and sets it to the new MAC address.
8159 * Note that in general it is not possible to modify the value of a given
8160 * filter so the generic way to modify an address filter is to free the one
8161 * being used by the old address value and allocate a new filter for the
8162 * new address value. @idx can be -1 if the address is a new addition.
8163 *
8164 * Returns a negative error number or the index of the filter with the new
8165 * MAC value.
8166 */
t4_change_mac(struct adapter * adap,unsigned int mbox,unsigned int viid,int idx,const u8 * addr,bool persist,u8 * smt_idx)8167 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8168 int idx, const u8 *addr, bool persist, u8 *smt_idx)
8169 {
8170 int ret, mode;
8171 struct fw_vi_mac_cmd c;
8172 struct fw_vi_mac_exact *p = c.u.exact;
8173 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
8174
8175 if (idx < 0) /* new allocation */
8176 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8177 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8178
8179 memset(&c, 0, sizeof(c));
8180 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8181 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8182 FW_VI_MAC_CMD_VIID_V(viid));
8183 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
8184 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8185 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
8186 FW_VI_MAC_CMD_IDX_V(idx));
8187 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8188
8189 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8190 if (ret == 0) {
8191 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
8192 if (ret >= max_mac_addr)
8193 ret = -ENOMEM;
8194 if (smt_idx) {
8195 if (adap->params.viid_smt_extn_support) {
8196 *smt_idx = FW_VI_MAC_CMD_SMTID_G
8197 (be32_to_cpu(c.op_to_viid));
8198 } else {
8199 /* In T4/T5, SMT contains 256 SMAC entries
8200 * organized in 128 rows of 2 entries each.
8201 * In T6, SMT contains 256 SMAC entries in
8202 * 256 rows.
8203 */
8204 if (CHELSIO_CHIP_VERSION(adap->params.chip) <=
8205 CHELSIO_T5)
8206 *smt_idx = (viid & FW_VIID_VIN_M) << 1;
8207 else
8208 *smt_idx = (viid & FW_VIID_VIN_M);
8209 }
8210 }
8211 }
8212 return ret;
8213 }
8214
8215 /**
8216 * t4_set_addr_hash - program the MAC inexact-match hash filter
8217 * @adap: the adapter
8218 * @mbox: mailbox to use for the FW command
8219 * @viid: the VI id
8220 * @ucast: whether the hash filter should also match unicast addresses
8221 * @vec: the value to be written to the hash filter
8222 * @sleep_ok: call is allowed to sleep
8223 *
8224 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8225 */
t4_set_addr_hash(struct adapter * adap,unsigned int mbox,unsigned int viid,bool ucast,u64 vec,bool sleep_ok)8226 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8227 bool ucast, u64 vec, bool sleep_ok)
8228 {
8229 struct fw_vi_mac_cmd c;
8230
8231 memset(&c, 0, sizeof(c));
8232 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8233 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8234 FW_VI_ENABLE_CMD_VIID_V(viid));
8235 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
8236 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
8237 FW_CMD_LEN16_V(1));
8238 c.u.hash.hashvec = cpu_to_be64(vec);
8239 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8240 }
8241
8242 /**
8243 * t4_enable_vi_params - enable/disable a virtual interface
8244 * @adap: the adapter
8245 * @mbox: mailbox to use for the FW command
8246 * @viid: the VI id
8247 * @rx_en: 1=enable Rx, 0=disable Rx
8248 * @tx_en: 1=enable Tx, 0=disable Tx
8249 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8250 *
8251 * Enables/disables a virtual interface. Note that setting DCB Enable
8252 * only makes sense when enabling a Virtual Interface ...
8253 */
t4_enable_vi_params(struct adapter * adap,unsigned int mbox,unsigned int viid,bool rx_en,bool tx_en,bool dcb_en)8254 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8255 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8256 {
8257 struct fw_vi_enable_cmd c;
8258
8259 memset(&c, 0, sizeof(c));
8260 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8261 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8262 FW_VI_ENABLE_CMD_VIID_V(viid));
8263 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
8264 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
8265 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
8266 FW_LEN16(c));
8267 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8268 }
8269
8270 /**
8271 * t4_enable_vi - enable/disable a virtual interface
8272 * @adap: the adapter
8273 * @mbox: mailbox to use for the FW command
8274 * @viid: the VI id
8275 * @rx_en: 1=enable Rx, 0=disable Rx
8276 * @tx_en: 1=enable Tx, 0=disable Tx
8277 *
8278 * Enables/disables a virtual interface.
8279 */
t4_enable_vi(struct adapter * adap,unsigned int mbox,unsigned int viid,bool rx_en,bool tx_en)8280 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8281 bool rx_en, bool tx_en)
8282 {
8283 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8284 }
8285
8286 /**
8287 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8288 * @adap: the adapter
8289 * @mbox: mailbox to use for the FW command
8290 * @pi: the Port Information structure
8291 * @rx_en: 1=enable Rx, 0=disable Rx
8292 * @tx_en: 1=enable Tx, 0=disable Tx
8293 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8294 *
8295 * Enables/disables a Port's Virtual Interface. Note that setting DCB
8296 * Enable only makes sense when enabling a Virtual Interface ...
8297 * If the Virtual Interface enable/disable operation is successful,
8298 * we notify the OS-specific code of a potential Link Status change
8299 * via the OS Contract API t4_os_link_changed().
8300 */
t4_enable_pi_params(struct adapter * adap,unsigned int mbox,struct port_info * pi,bool rx_en,bool tx_en,bool dcb_en)8301 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8302 struct port_info *pi,
8303 bool rx_en, bool tx_en, bool dcb_en)
8304 {
8305 int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8306 rx_en, tx_en, dcb_en);
8307 if (ret)
8308 return ret;
8309 t4_os_link_changed(adap, pi->port_id,
8310 rx_en && tx_en && pi->link_cfg.link_ok);
8311 return 0;
8312 }
8313
8314 /**
8315 * t4_identify_port - identify a VI's port by blinking its LED
8316 * @adap: the adapter
8317 * @mbox: mailbox to use for the FW command
8318 * @viid: the VI id
8319 * @nblinks: how many times to blink LED at 2.5 Hz
8320 *
8321 * Identifies a VI's port by blinking its LED.
8322 */
t4_identify_port(struct adapter * adap,unsigned int mbox,unsigned int viid,unsigned int nblinks)8323 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8324 unsigned int nblinks)
8325 {
8326 struct fw_vi_enable_cmd c;
8327
8328 memset(&c, 0, sizeof(c));
8329 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8330 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8331 FW_VI_ENABLE_CMD_VIID_V(viid));
8332 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8333 c.blinkdur = cpu_to_be16(nblinks);
8334 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8335 }
8336
8337 /**
8338 * t4_iq_stop - stop an ingress queue and its FLs
8339 * @adap: the adapter
8340 * @mbox: mailbox to use for the FW command
8341 * @pf: the PF owning the queues
8342 * @vf: the VF owning the queues
8343 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8344 * @iqid: ingress queue id
8345 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8346 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8347 *
8348 * Stops an ingress queue and its associated FLs, if any. This causes
8349 * any current or future data/messages destined for these queues to be
8350 * tossed.
8351 */
t4_iq_stop(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int iqtype,unsigned int iqid,unsigned int fl0id,unsigned int fl1id)8352 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8353 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8354 unsigned int fl0id, unsigned int fl1id)
8355 {
8356 struct fw_iq_cmd c;
8357
8358 memset(&c, 0, sizeof(c));
8359 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8360 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8361 FW_IQ_CMD_VFN_V(vf));
8362 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8363 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8364 c.iqid = cpu_to_be16(iqid);
8365 c.fl0id = cpu_to_be16(fl0id);
8366 c.fl1id = cpu_to_be16(fl1id);
8367 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8368 }
8369
8370 /**
8371 * t4_iq_free - free an ingress queue and its FLs
8372 * @adap: the adapter
8373 * @mbox: mailbox to use for the FW command
8374 * @pf: the PF owning the queues
8375 * @vf: the VF owning the queues
8376 * @iqtype: the ingress queue type
8377 * @iqid: ingress queue id
8378 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8379 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8380 *
8381 * Frees an ingress queue and its associated FLs, if any.
8382 */
t4_iq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int iqtype,unsigned int iqid,unsigned int fl0id,unsigned int fl1id)8383 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8384 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8385 unsigned int fl0id, unsigned int fl1id)
8386 {
8387 struct fw_iq_cmd c;
8388
8389 memset(&c, 0, sizeof(c));
8390 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8391 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8392 FW_IQ_CMD_VFN_V(vf));
8393 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8394 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8395 c.iqid = cpu_to_be16(iqid);
8396 c.fl0id = cpu_to_be16(fl0id);
8397 c.fl1id = cpu_to_be16(fl1id);
8398 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8399 }
8400
8401 /**
8402 * t4_eth_eq_free - free an Ethernet egress queue
8403 * @adap: the adapter
8404 * @mbox: mailbox to use for the FW command
8405 * @pf: the PF owning the queue
8406 * @vf: the VF owning the queue
8407 * @eqid: egress queue id
8408 *
8409 * Frees an Ethernet egress queue.
8410 */
t4_eth_eq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int eqid)8411 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8412 unsigned int vf, unsigned int eqid)
8413 {
8414 struct fw_eq_eth_cmd c;
8415
8416 memset(&c, 0, sizeof(c));
8417 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8418 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8419 FW_EQ_ETH_CMD_PFN_V(pf) |
8420 FW_EQ_ETH_CMD_VFN_V(vf));
8421 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8422 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8423 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8424 }
8425
8426 /**
8427 * t4_ctrl_eq_free - free a control egress queue
8428 * @adap: the adapter
8429 * @mbox: mailbox to use for the FW command
8430 * @pf: the PF owning the queue
8431 * @vf: the VF owning the queue
8432 * @eqid: egress queue id
8433 *
8434 * Frees a control egress queue.
8435 */
t4_ctrl_eq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int eqid)8436 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8437 unsigned int vf, unsigned int eqid)
8438 {
8439 struct fw_eq_ctrl_cmd c;
8440
8441 memset(&c, 0, sizeof(c));
8442 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8443 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8444 FW_EQ_CTRL_CMD_PFN_V(pf) |
8445 FW_EQ_CTRL_CMD_VFN_V(vf));
8446 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8447 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8448 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8449 }
8450
8451 /**
8452 * t4_ofld_eq_free - free an offload egress queue
8453 * @adap: the adapter
8454 * @mbox: mailbox to use for the FW command
8455 * @pf: the PF owning the queue
8456 * @vf: the VF owning the queue
8457 * @eqid: egress queue id
8458 *
8459 * Frees a control egress queue.
8460 */
t4_ofld_eq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int eqid)8461 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8462 unsigned int vf, unsigned int eqid)
8463 {
8464 struct fw_eq_ofld_cmd c;
8465
8466 memset(&c, 0, sizeof(c));
8467 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8468 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8469 FW_EQ_OFLD_CMD_PFN_V(pf) |
8470 FW_EQ_OFLD_CMD_VFN_V(vf));
8471 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8472 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8473 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8474 }
8475
8476 /**
8477 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8478 * @link_down_rc: Link Down Reason Code
8479 *
8480 * Returns a string representation of the Link Down Reason Code.
8481 */
t4_link_down_rc_str(unsigned char link_down_rc)8482 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8483 {
8484 static const char * const reason[] = {
8485 "Link Down",
8486 "Remote Fault",
8487 "Auto-negotiation Failure",
8488 "Reserved",
8489 "Insufficient Airflow",
8490 "Unable To Determine Reason",
8491 "No RX Signal Detected",
8492 "Reserved",
8493 };
8494
8495 if (link_down_rc >= ARRAY_SIZE(reason))
8496 return "Bad Reason Code";
8497
8498 return reason[link_down_rc];
8499 }
8500
8501 /* Return the highest speed set in the port capabilities, in Mb/s. */
fwcap_to_speed(fw_port_cap32_t caps)8502 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8503 {
8504 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8505 do { \
8506 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8507 return __speed; \
8508 } while (0)
8509
8510 TEST_SPEED_RETURN(400G, 400000);
8511 TEST_SPEED_RETURN(200G, 200000);
8512 TEST_SPEED_RETURN(100G, 100000);
8513 TEST_SPEED_RETURN(50G, 50000);
8514 TEST_SPEED_RETURN(40G, 40000);
8515 TEST_SPEED_RETURN(25G, 25000);
8516 TEST_SPEED_RETURN(10G, 10000);
8517 TEST_SPEED_RETURN(1G, 1000);
8518 TEST_SPEED_RETURN(100M, 100);
8519
8520 #undef TEST_SPEED_RETURN
8521
8522 return 0;
8523 }
8524
8525 /**
8526 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8527 * @acaps: advertised Port Capabilities
8528 *
8529 * Get the highest speed for the port from the advertised Port
8530 * Capabilities. It will be either the highest speed from the list of
8531 * speeds or whatever user has set using ethtool.
8532 */
fwcap_to_fwspeed(fw_port_cap32_t acaps)8533 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8534 {
8535 #define TEST_SPEED_RETURN(__caps_speed) \
8536 do { \
8537 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8538 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8539 } while (0)
8540
8541 TEST_SPEED_RETURN(400G);
8542 TEST_SPEED_RETURN(200G);
8543 TEST_SPEED_RETURN(100G);
8544 TEST_SPEED_RETURN(50G);
8545 TEST_SPEED_RETURN(40G);
8546 TEST_SPEED_RETURN(25G);
8547 TEST_SPEED_RETURN(10G);
8548 TEST_SPEED_RETURN(1G);
8549 TEST_SPEED_RETURN(100M);
8550
8551 #undef TEST_SPEED_RETURN
8552
8553 return 0;
8554 }
8555
8556 /**
8557 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8558 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8559 *
8560 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8561 * 32-bit Port Capabilities value.
8562 */
lstatus_to_fwcap(u32 lstatus)8563 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8564 {
8565 fw_port_cap32_t linkattr = 0;
8566
8567 /* Unfortunately the format of the Link Status in the old
8568 * 16-bit Port Information message isn't the same as the
8569 * 16-bit Port Capabilities bitfield used everywhere else ...
8570 */
8571 if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8572 linkattr |= FW_PORT_CAP32_FC_RX;
8573 if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8574 linkattr |= FW_PORT_CAP32_FC_TX;
8575 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8576 linkattr |= FW_PORT_CAP32_SPEED_100M;
8577 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8578 linkattr |= FW_PORT_CAP32_SPEED_1G;
8579 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8580 linkattr |= FW_PORT_CAP32_SPEED_10G;
8581 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8582 linkattr |= FW_PORT_CAP32_SPEED_25G;
8583 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8584 linkattr |= FW_PORT_CAP32_SPEED_40G;
8585 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8586 linkattr |= FW_PORT_CAP32_SPEED_100G;
8587
8588 return linkattr;
8589 }
8590
8591 /**
8592 * t4_handle_get_port_info - process a FW reply message
8593 * @pi: the port info
8594 * @rpl: start of the FW message
8595 *
8596 * Processes a GET_PORT_INFO FW reply message.
8597 */
t4_handle_get_port_info(struct port_info * pi,const __be64 * rpl)8598 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8599 {
8600 const struct fw_port_cmd *cmd = (const void *)rpl;
8601 fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8602 struct link_config *lc = &pi->link_cfg;
8603 struct adapter *adapter = pi->adapter;
8604 unsigned int speed, fc, fec, adv_fc;
8605 enum fw_port_module_type mod_type;
8606 int action, link_ok, linkdnrc;
8607 enum fw_port_type port_type;
8608
8609 /* Extract the various fields from the Port Information message.
8610 */
8611 action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8612 switch (action) {
8613 case FW_PORT_ACTION_GET_PORT_INFO: {
8614 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8615
8616 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8617 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8618 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8619 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8620 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8621 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8622 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8623 linkattr = lstatus_to_fwcap(lstatus);
8624 break;
8625 }
8626
8627 case FW_PORT_ACTION_GET_PORT_INFO32: {
8628 u32 lstatus32;
8629
8630 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8631 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8632 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8633 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8634 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8635 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8636 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8637 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8638 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8639 break;
8640 }
8641
8642 default:
8643 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8644 be32_to_cpu(cmd->action_to_len16));
8645 return;
8646 }
8647
8648 fec = fwcap_to_cc_fec(acaps);
8649 adv_fc = fwcap_to_cc_pause(acaps);
8650 fc = fwcap_to_cc_pause(linkattr);
8651 speed = fwcap_to_speed(linkattr);
8652
8653 /* Reset state for communicating new Transceiver Module status and
8654 * whether the OS-dependent layer wants us to redo the current
8655 * "sticky" L1 Configure Link Parameters.
8656 */
8657 lc->new_module = false;
8658 lc->redo_l1cfg = false;
8659
8660 if (mod_type != pi->mod_type) {
8661 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8662 * various fundamental Port Capabilities which used to be
8663 * immutable can now change radically. We can now have
8664 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8665 * all change based on what Transceiver Module is inserted.
8666 * So we need to record the Physical "Port" Capabilities on
8667 * every Transceiver Module change.
8668 */
8669 lc->pcaps = pcaps;
8670
8671 /* When a new Transceiver Module is inserted, the Firmware
8672 * will examine its i2c EPROM to determine its type and
8673 * general operating parameters including things like Forward
8674 * Error Control, etc. Various IEEE 802.3 standards dictate
8675 * how to interpret these i2c values to determine default
8676 * "sutomatic" settings. We record these for future use when
8677 * the user explicitly requests these standards-based values.
8678 */
8679 lc->def_acaps = acaps;
8680
8681 /* Some versions of the early T6 Firmware "cheated" when
8682 * handling different Transceiver Modules by changing the
8683 * underlaying Port Type reported to the Host Drivers. As
8684 * such we need to capture whatever Port Type the Firmware
8685 * sends us and record it in case it's different from what we
8686 * were told earlier. Unfortunately, since Firmware is
8687 * forever, we'll need to keep this code here forever, but in
8688 * later T6 Firmware it should just be an assignment of the
8689 * same value already recorded.
8690 */
8691 pi->port_type = port_type;
8692
8693 /* Record new Module Type information.
8694 */
8695 pi->mod_type = mod_type;
8696
8697 /* Let the OS-dependent layer know if we have a new
8698 * Transceiver Module inserted.
8699 */
8700 lc->new_module = t4_is_inserted_mod_type(mod_type);
8701
8702 t4_os_portmod_changed(adapter, pi->port_id);
8703 }
8704
8705 if (link_ok != lc->link_ok || speed != lc->speed ||
8706 fc != lc->fc || adv_fc != lc->advertised_fc ||
8707 fec != lc->fec) {
8708 /* something changed */
8709 if (!link_ok && lc->link_ok) {
8710 lc->link_down_rc = linkdnrc;
8711 dev_warn_ratelimited(adapter->pdev_dev,
8712 "Port %d link down, reason: %s\n",
8713 pi->tx_chan,
8714 t4_link_down_rc_str(linkdnrc));
8715 }
8716 lc->link_ok = link_ok;
8717 lc->speed = speed;
8718 lc->advertised_fc = adv_fc;
8719 lc->fc = fc;
8720 lc->fec = fec;
8721
8722 lc->lpacaps = lpacaps;
8723 lc->acaps = acaps & ADVERT_MASK;
8724
8725 /* If we're not physically capable of Auto-Negotiation, note
8726 * this as Auto-Negotiation disabled. Otherwise, we track
8727 * what Auto-Negotiation settings we have. Note parallel
8728 * structure in t4_link_l1cfg_core() and init_link_config().
8729 */
8730 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) {
8731 lc->autoneg = AUTONEG_DISABLE;
8732 } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
8733 lc->autoneg = AUTONEG_ENABLE;
8734 } else {
8735 /* When Autoneg is disabled, user needs to set
8736 * single speed.
8737 * Similar to cxgb4_ethtool.c: set_link_ksettings
8738 */
8739 lc->acaps = 0;
8740 lc->speed_caps = fwcap_to_fwspeed(acaps);
8741 lc->autoneg = AUTONEG_DISABLE;
8742 }
8743
8744 t4_os_link_changed(adapter, pi->port_id, link_ok);
8745 }
8746
8747 /* If we have a new Transceiver Module and the OS-dependent code has
8748 * told us that it wants us to redo whatever "sticky" L1 Configuration
8749 * Link Parameters are set, do that now.
8750 */
8751 if (lc->new_module && lc->redo_l1cfg) {
8752 struct link_config old_lc;
8753 int ret;
8754
8755 /* Save the current L1 Configuration and restore it if an
8756 * error occurs. We probably should fix the l1_cfg*()
8757 * routines not to change the link_config when an error
8758 * occurs ...
8759 */
8760 old_lc = *lc;
8761 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
8762 if (ret) {
8763 *lc = old_lc;
8764 dev_warn(adapter->pdev_dev,
8765 "Attempt to update new Transceiver Module settings failed\n");
8766 }
8767 }
8768 lc->new_module = false;
8769 lc->redo_l1cfg = false;
8770 }
8771
8772 /**
8773 * t4_update_port_info - retrieve and update port information if changed
8774 * @pi: the port_info
8775 *
8776 * We issue a Get Port Information Command to the Firmware and, if
8777 * successful, we check to see if anything is different from what we
8778 * last recorded and update things accordingly.
8779 */
t4_update_port_info(struct port_info * pi)8780 int t4_update_port_info(struct port_info *pi)
8781 {
8782 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8783 struct fw_port_cmd port_cmd;
8784 int ret;
8785
8786 memset(&port_cmd, 0, sizeof(port_cmd));
8787 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8788 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8789 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8790 port_cmd.action_to_len16 = cpu_to_be32(
8791 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8792 ? FW_PORT_ACTION_GET_PORT_INFO
8793 : FW_PORT_ACTION_GET_PORT_INFO32) |
8794 FW_LEN16(port_cmd));
8795 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8796 &port_cmd, sizeof(port_cmd), &port_cmd);
8797 if (ret)
8798 return ret;
8799
8800 t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8801 return 0;
8802 }
8803
8804 /**
8805 * t4_get_link_params - retrieve basic link parameters for given port
8806 * @pi: the port
8807 * @link_okp: value return pointer for link up/down
8808 * @speedp: value return pointer for speed (Mb/s)
8809 * @mtup: value return pointer for mtu
8810 *
8811 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8812 * and MTU for a specified port. A negative error is returned on
8813 * failure; 0 on success.
8814 */
t4_get_link_params(struct port_info * pi,unsigned int * link_okp,unsigned int * speedp,unsigned int * mtup)8815 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8816 unsigned int *speedp, unsigned int *mtup)
8817 {
8818 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8819 unsigned int action, link_ok, mtu;
8820 struct fw_port_cmd port_cmd;
8821 fw_port_cap32_t linkattr;
8822 int ret;
8823
8824 memset(&port_cmd, 0, sizeof(port_cmd));
8825 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8826 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8827 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8828 action = (fw_caps == FW_CAPS16
8829 ? FW_PORT_ACTION_GET_PORT_INFO
8830 : FW_PORT_ACTION_GET_PORT_INFO32);
8831 port_cmd.action_to_len16 = cpu_to_be32(
8832 FW_PORT_CMD_ACTION_V(action) |
8833 FW_LEN16(port_cmd));
8834 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8835 &port_cmd, sizeof(port_cmd), &port_cmd);
8836 if (ret)
8837 return ret;
8838
8839 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8840 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8841
8842 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8843 linkattr = lstatus_to_fwcap(lstatus);
8844 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8845 } else {
8846 u32 lstatus32 =
8847 be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8848
8849 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8850 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8851 mtu = FW_PORT_CMD_MTU32_G(
8852 be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8853 }
8854
8855 if (link_okp)
8856 *link_okp = link_ok;
8857 if (speedp)
8858 *speedp = fwcap_to_speed(linkattr);
8859 if (mtup)
8860 *mtup = mtu;
8861
8862 return 0;
8863 }
8864
8865 /**
8866 * t4_handle_fw_rpl - process a FW reply message
8867 * @adap: the adapter
8868 * @rpl: start of the FW message
8869 *
8870 * Processes a FW message, such as link state change messages.
8871 */
t4_handle_fw_rpl(struct adapter * adap,const __be64 * rpl)8872 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8873 {
8874 u8 opcode = *(const u8 *)rpl;
8875
8876 /* This might be a port command ... this simplifies the following
8877 * conditionals ... We can get away with pre-dereferencing
8878 * action_to_len16 because it's in the first 16 bytes and all messages
8879 * will be at least that long.
8880 */
8881 const struct fw_port_cmd *p = (const void *)rpl;
8882 unsigned int action =
8883 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8884
8885 if (opcode == FW_PORT_CMD &&
8886 (action == FW_PORT_ACTION_GET_PORT_INFO ||
8887 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8888 int i;
8889 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8890 struct port_info *pi = NULL;
8891
8892 for_each_port(adap, i) {
8893 pi = adap2pinfo(adap, i);
8894 if (pi->tx_chan == chan)
8895 break;
8896 }
8897
8898 t4_handle_get_port_info(pi, rpl);
8899 } else {
8900 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8901 opcode);
8902 return -EINVAL;
8903 }
8904 return 0;
8905 }
8906
get_pci_mode(struct adapter * adapter,struct pci_params * p)8907 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8908 {
8909 u16 val;
8910
8911 if (pci_is_pcie(adapter->pdev)) {
8912 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8913 p->speed = val & PCI_EXP_LNKSTA_CLS;
8914 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8915 }
8916 }
8917
8918 /**
8919 * init_link_config - initialize a link's SW state
8920 * @lc: pointer to structure holding the link state
8921 * @pcaps: link Port Capabilities
8922 * @acaps: link current Advertised Port Capabilities
8923 *
8924 * Initializes the SW state maintained for each link, including the link's
8925 * capabilities and default speed/flow-control/autonegotiation settings.
8926 */
init_link_config(struct link_config * lc,fw_port_cap32_t pcaps,fw_port_cap32_t acaps)8927 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8928 fw_port_cap32_t acaps)
8929 {
8930 lc->pcaps = pcaps;
8931 lc->def_acaps = acaps;
8932 lc->lpacaps = 0;
8933 lc->speed_caps = 0;
8934 lc->speed = 0;
8935 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8936
8937 /* For Forward Error Control, we default to whatever the Firmware
8938 * tells us the Link is currently advertising.
8939 */
8940 lc->requested_fec = FEC_AUTO;
8941 lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8942
8943 /* If the Port is capable of Auto-Negtotiation, initialize it as
8944 * "enabled" and copy over all of the Physical Port Capabilities
8945 * to the Advertised Port Capabilities. Otherwise mark it as
8946 * Auto-Negotiate disabled and select the highest supported speed
8947 * for the link. Note parallel structure in t4_link_l1cfg_core()
8948 * and t4_handle_get_port_info().
8949 */
8950 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8951 lc->acaps = lc->pcaps & ADVERT_MASK;
8952 lc->autoneg = AUTONEG_ENABLE;
8953 lc->requested_fc |= PAUSE_AUTONEG;
8954 } else {
8955 lc->acaps = 0;
8956 lc->autoneg = AUTONEG_DISABLE;
8957 lc->speed_caps = fwcap_to_fwspeed(acaps);
8958 }
8959 }
8960
8961 #define CIM_PF_NOACCESS 0xeeeeeeee
8962
t4_wait_dev_ready(void __iomem * regs)8963 int t4_wait_dev_ready(void __iomem *regs)
8964 {
8965 u32 whoami;
8966
8967 whoami = readl(regs + PL_WHOAMI_A);
8968 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8969 return 0;
8970
8971 msleep(500);
8972 whoami = readl(regs + PL_WHOAMI_A);
8973 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8974 }
8975
8976 struct flash_desc {
8977 u32 vendor_and_model_id;
8978 u32 size_mb;
8979 };
8980
t4_get_flash_params(struct adapter * adap)8981 static int t4_get_flash_params(struct adapter *adap)
8982 {
8983 /* Table for non-Numonix supported flash parts. Numonix parts are left
8984 * to the preexisting code. All flash parts have 64KB sectors.
8985 */
8986 static struct flash_desc supported_flash[] = {
8987 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8988 };
8989
8990 unsigned int part, manufacturer;
8991 unsigned int density, size = 0;
8992 u32 flashid = 0;
8993 int ret;
8994
8995 /* Issue a Read ID Command to the Flash part. We decode supported
8996 * Flash parts and their sizes from this. There's a newer Query
8997 * Command which can retrieve detailed geometry information but many
8998 * Flash parts don't support it.
8999 */
9000
9001 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
9002 if (!ret)
9003 ret = sf1_read(adap, 3, 0, 1, &flashid);
9004 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
9005 if (ret)
9006 return ret;
9007
9008 /* Check to see if it's one of our non-standard supported Flash parts.
9009 */
9010 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
9011 if (supported_flash[part].vendor_and_model_id == flashid) {
9012 adap->params.sf_size = supported_flash[part].size_mb;
9013 adap->params.sf_nsec =
9014 adap->params.sf_size / SF_SEC_SIZE;
9015 goto found;
9016 }
9017
9018 /* Decode Flash part size. The code below looks repetitive with
9019 * common encodings, but that's not guaranteed in the JEDEC
9020 * specification for the Read JEDEC ID command. The only thing that
9021 * we're guaranteed by the JEDEC specification is where the
9022 * Manufacturer ID is in the returned result. After that each
9023 * Manufacturer ~could~ encode things completely differently.
9024 * Note, all Flash parts must have 64KB sectors.
9025 */
9026 manufacturer = flashid & 0xff;
9027 switch (manufacturer) {
9028 case 0x20: { /* Micron/Numonix */
9029 /* This Density -> Size decoding table is taken from Micron
9030 * Data Sheets.
9031 */
9032 density = (flashid >> 16) & 0xff;
9033 switch (density) {
9034 case 0x14: /* 1MB */
9035 size = 1 << 20;
9036 break;
9037 case 0x15: /* 2MB */
9038 size = 1 << 21;
9039 break;
9040 case 0x16: /* 4MB */
9041 size = 1 << 22;
9042 break;
9043 case 0x17: /* 8MB */
9044 size = 1 << 23;
9045 break;
9046 case 0x18: /* 16MB */
9047 size = 1 << 24;
9048 break;
9049 case 0x19: /* 32MB */
9050 size = 1 << 25;
9051 break;
9052 case 0x20: /* 64MB */
9053 size = 1 << 26;
9054 break;
9055 case 0x21: /* 128MB */
9056 size = 1 << 27;
9057 break;
9058 case 0x22: /* 256MB */
9059 size = 1 << 28;
9060 break;
9061 }
9062 break;
9063 }
9064 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
9065 /* This Density -> Size decoding table is taken from ISSI
9066 * Data Sheets.
9067 */
9068 density = (flashid >> 16) & 0xff;
9069 switch (density) {
9070 case 0x16: /* 32 MB */
9071 size = 1 << 25;
9072 break;
9073 case 0x17: /* 64MB */
9074 size = 1 << 26;
9075 break;
9076 }
9077 break;
9078 }
9079 case 0xc2: { /* Macronix */
9080 /* This Density -> Size decoding table is taken from Macronix
9081 * Data Sheets.
9082 */
9083 density = (flashid >> 16) & 0xff;
9084 switch (density) {
9085 case 0x17: /* 8MB */
9086 size = 1 << 23;
9087 break;
9088 case 0x18: /* 16MB */
9089 size = 1 << 24;
9090 break;
9091 }
9092 break;
9093 }
9094 case 0xef: { /* Winbond */
9095 /* This Density -> Size decoding table is taken from Winbond
9096 * Data Sheets.
9097 */
9098 density = (flashid >> 16) & 0xff;
9099 switch (density) {
9100 case 0x17: /* 8MB */
9101 size = 1 << 23;
9102 break;
9103 case 0x18: /* 16MB */
9104 size = 1 << 24;
9105 break;
9106 }
9107 break;
9108 }
9109 }
9110
9111 /* If we didn't recognize the FLASH part, that's no real issue: the
9112 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9113 * use a FLASH part which is at least 4MB in size and has 64KB
9114 * sectors. The unrecognized FLASH part is likely to be much larger
9115 * than 4MB, but that's all we really need.
9116 */
9117 if (size == 0) {
9118 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9119 flashid);
9120 size = 1 << 22;
9121 }
9122
9123 /* Store decoded Flash size and fall through into vetting code. */
9124 adap->params.sf_size = size;
9125 adap->params.sf_nsec = size / SF_SEC_SIZE;
9126
9127 found:
9128 if (adap->params.sf_size < FLASH_MIN_SIZE)
9129 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9130 flashid, adap->params.sf_size, FLASH_MIN_SIZE);
9131 return 0;
9132 }
9133
9134 /**
9135 * t4_prep_adapter - prepare SW and HW for operation
9136 * @adapter: the adapter
9137 *
9138 * Initialize adapter SW state for the various HW modules, set initial
9139 * values for some adapter tunables, take PHYs out of reset, and
9140 * initialize the MDIO interface.
9141 */
t4_prep_adapter(struct adapter * adapter)9142 int t4_prep_adapter(struct adapter *adapter)
9143 {
9144 int ret, ver;
9145 uint16_t device_id;
9146 u32 pl_rev;
9147
9148 get_pci_mode(adapter, &adapter->params.pci);
9149 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
9150
9151 ret = t4_get_flash_params(adapter);
9152 if (ret < 0) {
9153 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
9154 return ret;
9155 }
9156
9157 /* Retrieve adapter's device ID
9158 */
9159 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
9160 ver = device_id >> 12;
9161 adapter->params.chip = 0;
9162 switch (ver) {
9163 case CHELSIO_T4:
9164 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
9165 adapter->params.arch.sge_fl_db = DBPRIO_F;
9166 adapter->params.arch.mps_tcam_size =
9167 NUM_MPS_CLS_SRAM_L_INSTANCES;
9168 adapter->params.arch.mps_rplc_size = 128;
9169 adapter->params.arch.nchan = NCHAN;
9170 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9171 adapter->params.arch.vfcount = 128;
9172 /* Congestion map is for 4 channels so that
9173 * MPS can have 4 priority per port.
9174 */
9175 adapter->params.arch.cng_ch_bits_log = 2;
9176 break;
9177 case CHELSIO_T5:
9178 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
9179 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
9180 adapter->params.arch.mps_tcam_size =
9181 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9182 adapter->params.arch.mps_rplc_size = 128;
9183 adapter->params.arch.nchan = NCHAN;
9184 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9185 adapter->params.arch.vfcount = 128;
9186 adapter->params.arch.cng_ch_bits_log = 2;
9187 break;
9188 case CHELSIO_T6:
9189 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
9190 adapter->params.arch.sge_fl_db = 0;
9191 adapter->params.arch.mps_tcam_size =
9192 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9193 adapter->params.arch.mps_rplc_size = 256;
9194 adapter->params.arch.nchan = 2;
9195 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
9196 adapter->params.arch.vfcount = 256;
9197 /* Congestion map will be for 2 channels so that
9198 * MPS can have 8 priority per port.
9199 */
9200 adapter->params.arch.cng_ch_bits_log = 3;
9201 break;
9202 default:
9203 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
9204 device_id);
9205 return -EINVAL;
9206 }
9207
9208 adapter->params.cim_la_size = CIMLA_SIZE;
9209 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9210
9211 /*
9212 * Default port for debugging in case we can't reach FW.
9213 */
9214 adapter->params.nports = 1;
9215 adapter->params.portvec = 1;
9216 adapter->params.vpd.cclk = 50000;
9217
9218 /* Set PCIe completion timeout to 4 seconds. */
9219 pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
9220 PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
9221 return 0;
9222 }
9223
9224 /**
9225 * t4_shutdown_adapter - shut down adapter, host & wire
9226 * @adapter: the adapter
9227 *
9228 * Perform an emergency shutdown of the adapter and stop it from
9229 * continuing any further communication on the ports or DMA to the
9230 * host. This is typically used when the adapter and/or firmware
9231 * have crashed and we want to prevent any further accidental
9232 * communication with the rest of the world. This will also force
9233 * the port Link Status to go down -- if register writes work --
9234 * which should help our peers figure out that we're down.
9235 */
t4_shutdown_adapter(struct adapter * adapter)9236 int t4_shutdown_adapter(struct adapter *adapter)
9237 {
9238 int port;
9239
9240 t4_intr_disable(adapter);
9241 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
9242 for_each_port(adapter, port) {
9243 u32 a_port_cfg = is_t4(adapter->params.chip) ?
9244 PORT_REG(port, XGMAC_PORT_CFG_A) :
9245 T5_PORT_REG(port, MAC_PORT_CFG_A);
9246
9247 t4_write_reg(adapter, a_port_cfg,
9248 t4_read_reg(adapter, a_port_cfg)
9249 & ~SIGNAL_DET_V(1));
9250 }
9251 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
9252
9253 return 0;
9254 }
9255
9256 /**
9257 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9258 * @adapter: the adapter
9259 * @qid: the Queue ID
9260 * @qtype: the Ingress or Egress type for @qid
9261 * @user: true if this request is for a user mode queue
9262 * @pbar2_qoffset: BAR2 Queue Offset
9263 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9264 *
9265 * Returns the BAR2 SGE Queue Registers information associated with the
9266 * indicated Absolute Queue ID. These are passed back in return value
9267 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9268 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9269 *
9270 * This may return an error which indicates that BAR2 SGE Queue
9271 * registers aren't available. If an error is not returned, then the
9272 * following values are returned:
9273 *
9274 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9275 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9276 *
9277 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9278 * require the "Inferred Queue ID" ability may be used. E.g. the
9279 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9280 * then these "Inferred Queue ID" register may not be used.
9281 */
t4_bar2_sge_qregs(struct adapter * adapter,unsigned int qid,enum t4_bar2_qtype qtype,int user,u64 * pbar2_qoffset,unsigned int * pbar2_qid)9282 int t4_bar2_sge_qregs(struct adapter *adapter,
9283 unsigned int qid,
9284 enum t4_bar2_qtype qtype,
9285 int user,
9286 u64 *pbar2_qoffset,
9287 unsigned int *pbar2_qid)
9288 {
9289 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9290 u64 bar2_page_offset, bar2_qoffset;
9291 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9292
9293 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9294 if (!user && is_t4(adapter->params.chip))
9295 return -EINVAL;
9296
9297 /* Get our SGE Page Size parameters.
9298 */
9299 page_shift = adapter->params.sge.hps + 10;
9300 page_size = 1 << page_shift;
9301
9302 /* Get the right Queues per Page parameters for our Queue.
9303 */
9304 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9305 ? adapter->params.sge.eq_qpp
9306 : adapter->params.sge.iq_qpp);
9307 qpp_mask = (1 << qpp_shift) - 1;
9308
9309 /* Calculate the basics of the BAR2 SGE Queue register area:
9310 * o The BAR2 page the Queue registers will be in.
9311 * o The BAR2 Queue ID.
9312 * o The BAR2 Queue ID Offset into the BAR2 page.
9313 */
9314 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9315 bar2_qid = qid & qpp_mask;
9316 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9317
9318 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9319 * hardware will infer the Absolute Queue ID simply from the writes to
9320 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9321 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9322 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9323 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9324 * from the BAR2 Page and BAR2 Queue ID.
9325 *
9326 * One important censequence of this is that some BAR2 SGE registers
9327 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9328 * there. But other registers synthesize the SGE Queue ID purely
9329 * from the writes to the registers -- the Write Combined Doorbell
9330 * Buffer is a good example. These BAR2 SGE Registers are only
9331 * available for those BAR2 SGE Register areas where the SGE Absolute
9332 * Queue ID can be inferred from simple writes.
9333 */
9334 bar2_qoffset = bar2_page_offset;
9335 bar2_qinferred = (bar2_qid_offset < page_size);
9336 if (bar2_qinferred) {
9337 bar2_qoffset += bar2_qid_offset;
9338 bar2_qid = 0;
9339 }
9340
9341 *pbar2_qoffset = bar2_qoffset;
9342 *pbar2_qid = bar2_qid;
9343 return 0;
9344 }
9345
9346 /**
9347 * t4_init_devlog_params - initialize adapter->params.devlog
9348 * @adap: the adapter
9349 *
9350 * Initialize various fields of the adapter's Firmware Device Log
9351 * Parameters structure.
9352 */
t4_init_devlog_params(struct adapter * adap)9353 int t4_init_devlog_params(struct adapter *adap)
9354 {
9355 struct devlog_params *dparams = &adap->params.devlog;
9356 u32 pf_dparams;
9357 unsigned int devlog_meminfo;
9358 struct fw_devlog_cmd devlog_cmd;
9359 int ret;
9360
9361 /* If we're dealing with newer firmware, the Device Log Parameters
9362 * are stored in a designated register which allows us to access the
9363 * Device Log even if we can't talk to the firmware.
9364 */
9365 pf_dparams =
9366 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9367 if (pf_dparams) {
9368 unsigned int nentries, nentries128;
9369
9370 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9371 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9372
9373 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9374 nentries = (nentries128 + 1) * 128;
9375 dparams->size = nentries * sizeof(struct fw_devlog_e);
9376
9377 return 0;
9378 }
9379
9380 /* Otherwise, ask the firmware for it's Device Log Parameters.
9381 */
9382 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9383 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9384 FW_CMD_REQUEST_F | FW_CMD_READ_F);
9385 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9386 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9387 &devlog_cmd);
9388 if (ret)
9389 return ret;
9390
9391 devlog_meminfo =
9392 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9393 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9394 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9395 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9396
9397 return 0;
9398 }
9399
9400 /**
9401 * t4_init_sge_params - initialize adap->params.sge
9402 * @adapter: the adapter
9403 *
9404 * Initialize various fields of the adapter's SGE Parameters structure.
9405 */
t4_init_sge_params(struct adapter * adapter)9406 int t4_init_sge_params(struct adapter *adapter)
9407 {
9408 struct sge_params *sge_params = &adapter->params.sge;
9409 u32 hps, qpp;
9410 unsigned int s_hps, s_qpp;
9411
9412 /* Extract the SGE Page Size for our PF.
9413 */
9414 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9415 s_hps = (HOSTPAGESIZEPF0_S +
9416 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9417 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9418
9419 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9420 */
9421 s_qpp = (QUEUESPERPAGEPF0_S +
9422 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9423 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9424 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9425 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9426 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9427
9428 return 0;
9429 }
9430
9431 /**
9432 * t4_init_tp_params - initialize adap->params.tp
9433 * @adap: the adapter
9434 * @sleep_ok: if true we may sleep while awaiting command completion
9435 *
9436 * Initialize various fields of the adapter's TP Parameters structure.
9437 */
t4_init_tp_params(struct adapter * adap,bool sleep_ok)9438 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9439 {
9440 u32 param, val, v;
9441 int chan, ret;
9442
9443
9444 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9445 adap->params.tp.tre = TIMERRESOLUTION_G(v);
9446 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9447
9448 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9449 for (chan = 0; chan < NCHAN; chan++)
9450 adap->params.tp.tx_modq[chan] = chan;
9451
9452 /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9453 * Configuration.
9454 */
9455 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
9456 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FILTER) |
9457 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_FILTER_MODE_MASK));
9458
9459 /* Read current value */
9460 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
9461 ¶m, &val);
9462 if (ret == 0) {
9463 dev_info(adap->pdev_dev,
9464 "Current filter mode/mask 0x%x:0x%x\n",
9465 FW_PARAMS_PARAM_FILTER_MODE_G(val),
9466 FW_PARAMS_PARAM_FILTER_MASK_G(val));
9467 adap->params.tp.vlan_pri_map =
9468 FW_PARAMS_PARAM_FILTER_MODE_G(val);
9469 adap->params.tp.filter_mask =
9470 FW_PARAMS_PARAM_FILTER_MASK_G(val);
9471 } else {
9472 dev_info(adap->pdev_dev,
9473 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
9474
9475 /* Incase of older-fw (which doesn't expose the api
9476 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9477 * the fw api) combination, fall-back to older method of reading
9478 * the filter mode from indirect-register
9479 */
9480 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9481 TP_VLAN_PRI_MAP_A, sleep_ok);
9482
9483 /* With the older-fw and newer-driver combination we might run
9484 * into an issue when user wants to use hash filter region but
9485 * the filter_mask is zero, in this case filter_mask validation
9486 * is tough. To avoid that we set the filter_mask same as filter
9487 * mode, which will behave exactly as the older way of ignoring
9488 * the filter mask validation.
9489 */
9490 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
9491 }
9492
9493 t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9494 TP_INGRESS_CONFIG_A, sleep_ok);
9495
9496 /* For T6, cache the adapter's compressed error vector
9497 * and passing outer header info for encapsulated packets.
9498 */
9499 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9500 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9501 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9502 }
9503
9504 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9505 * shift positions of several elements of the Compressed Filter Tuple
9506 * for this adapter which we need frequently ...
9507 */
9508 adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9509 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9510 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9511 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9512 adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9513 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9514 PROTOCOL_F);
9515 adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9516 ETHERTYPE_F);
9517 adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9518 MACMATCH_F);
9519 adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9520 MPSHITTYPE_F);
9521 adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9522 FRAGMENTATION_F);
9523
9524 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9525 * represents the presence of an Outer VLAN instead of a VNIC ID.
9526 */
9527 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9528 adap->params.tp.vnic_shift = -1;
9529
9530 v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9531 adap->params.tp.hash_filter_mask = v;
9532 v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9533 adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9534 return 0;
9535 }
9536
9537 /**
9538 * t4_filter_field_shift - calculate filter field shift
9539 * @adap: the adapter
9540 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9541 *
9542 * Return the shift position of a filter field within the Compressed
9543 * Filter Tuple. The filter field is specified via its selection bit
9544 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9545 */
t4_filter_field_shift(const struct adapter * adap,int filter_sel)9546 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9547 {
9548 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9549 unsigned int sel;
9550 int field_shift;
9551
9552 if ((filter_mode & filter_sel) == 0)
9553 return -1;
9554
9555 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9556 switch (filter_mode & sel) {
9557 case FCOE_F:
9558 field_shift += FT_FCOE_W;
9559 break;
9560 case PORT_F:
9561 field_shift += FT_PORT_W;
9562 break;
9563 case VNIC_ID_F:
9564 field_shift += FT_VNIC_ID_W;
9565 break;
9566 case VLAN_F:
9567 field_shift += FT_VLAN_W;
9568 break;
9569 case TOS_F:
9570 field_shift += FT_TOS_W;
9571 break;
9572 case PROTOCOL_F:
9573 field_shift += FT_PROTOCOL_W;
9574 break;
9575 case ETHERTYPE_F:
9576 field_shift += FT_ETHERTYPE_W;
9577 break;
9578 case MACMATCH_F:
9579 field_shift += FT_MACMATCH_W;
9580 break;
9581 case MPSHITTYPE_F:
9582 field_shift += FT_MPSHITTYPE_W;
9583 break;
9584 case FRAGMENTATION_F:
9585 field_shift += FT_FRAGMENTATION_W;
9586 break;
9587 }
9588 }
9589 return field_shift;
9590 }
9591
t4_init_rss_mode(struct adapter * adap,int mbox)9592 int t4_init_rss_mode(struct adapter *adap, int mbox)
9593 {
9594 int i, ret;
9595 struct fw_rss_vi_config_cmd rvc;
9596
9597 memset(&rvc, 0, sizeof(rvc));
9598
9599 for_each_port(adap, i) {
9600 struct port_info *p = adap2pinfo(adap, i);
9601
9602 rvc.op_to_viid =
9603 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9604 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9605 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9606 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9607 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9608 if (ret)
9609 return ret;
9610 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9611 }
9612 return 0;
9613 }
9614
9615 /**
9616 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9617 * @pi: the port_info
9618 * @mbox: mailbox to use for the FW command
9619 * @port: physical port associated with the VI
9620 * @pf: the PF owning the VI
9621 * @vf: the VF owning the VI
9622 * @mac: the MAC address of the VI
9623 *
9624 * Allocates a virtual interface for the given physical port. If @mac is
9625 * not %NULL it contains the MAC address of the VI as assigned by FW.
9626 * @mac should be large enough to hold an Ethernet address.
9627 * Returns < 0 on error.
9628 */
t4_init_portinfo(struct port_info * pi,int mbox,int port,int pf,int vf,u8 mac[])9629 int t4_init_portinfo(struct port_info *pi, int mbox,
9630 int port, int pf, int vf, u8 mac[])
9631 {
9632 struct adapter *adapter = pi->adapter;
9633 unsigned int fw_caps = adapter->params.fw_caps_support;
9634 struct fw_port_cmd cmd;
9635 unsigned int rss_size;
9636 enum fw_port_type port_type;
9637 int mdio_addr;
9638 fw_port_cap32_t pcaps, acaps;
9639 u8 vivld = 0, vin = 0;
9640 int ret;
9641
9642 /* If we haven't yet determined whether we're talking to Firmware
9643 * which knows the new 32-bit Port Capabilities, it's time to find
9644 * out now. This will also tell new Firmware to send us Port Status
9645 * Updates using the new 32-bit Port Capabilities version of the
9646 * Port Information message.
9647 */
9648 if (fw_caps == FW_CAPS_UNKNOWN) {
9649 u32 param, val;
9650
9651 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9652 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9653 val = 1;
9654 ret = t4_set_params(adapter, mbox, pf, vf, 1, ¶m, &val);
9655 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9656 adapter->params.fw_caps_support = fw_caps;
9657 }
9658
9659 memset(&cmd, 0, sizeof(cmd));
9660 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9661 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9662 FW_PORT_CMD_PORTID_V(port));
9663 cmd.action_to_len16 = cpu_to_be32(
9664 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9665 ? FW_PORT_ACTION_GET_PORT_INFO
9666 : FW_PORT_ACTION_GET_PORT_INFO32) |
9667 FW_LEN16(cmd));
9668 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9669 if (ret)
9670 return ret;
9671
9672 /* Extract the various fields from the Port Information message.
9673 */
9674 if (fw_caps == FW_CAPS16) {
9675 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9676
9677 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9678 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9679 ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9680 : -1);
9681 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9682 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9683 } else {
9684 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9685
9686 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9687 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9688 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9689 : -1);
9690 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9691 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9692 }
9693
9694 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size,
9695 &vivld, &vin);
9696 if (ret < 0)
9697 return ret;
9698
9699 pi->viid = ret;
9700 pi->tx_chan = port;
9701 pi->lport = port;
9702 pi->rss_size = rss_size;
9703 pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
9704
9705 /* If fw supports returning the VIN as part of FW_VI_CMD,
9706 * save the returned values.
9707 */
9708 if (adapter->params.viid_smt_extn_support) {
9709 pi->vivld = vivld;
9710 pi->vin = vin;
9711 } else {
9712 /* Retrieve the values from VIID */
9713 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
9714 pi->vin = FW_VIID_VIN_G(pi->viid);
9715 }
9716
9717 pi->port_type = port_type;
9718 pi->mdio_addr = mdio_addr;
9719 pi->mod_type = FW_PORT_MOD_TYPE_NA;
9720
9721 init_link_config(&pi->link_cfg, pcaps, acaps);
9722 return 0;
9723 }
9724
t4_port_init(struct adapter * adap,int mbox,int pf,int vf)9725 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9726 {
9727 u8 addr[6];
9728 int ret, i, j = 0;
9729
9730 for_each_port(adap, i) {
9731 struct port_info *pi = adap2pinfo(adap, i);
9732
9733 while ((adap->params.portvec & (1 << j)) == 0)
9734 j++;
9735
9736 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9737 if (ret)
9738 return ret;
9739
9740 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9741 j++;
9742 }
9743 return 0;
9744 }
9745
t4_init_port_mirror(struct port_info * pi,u8 mbox,u8 port,u8 pf,u8 vf,u16 * mirror_viid)9746 int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
9747 u16 *mirror_viid)
9748 {
9749 int ret;
9750
9751 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, NULL, NULL,
9752 NULL, NULL);
9753 if (ret < 0)
9754 return ret;
9755
9756 if (mirror_viid)
9757 *mirror_viid = ret;
9758
9759 return 0;
9760 }
9761
9762 /**
9763 * t4_read_cimq_cfg - read CIM queue configuration
9764 * @adap: the adapter
9765 * @base: holds the queue base addresses in bytes
9766 * @size: holds the queue sizes in bytes
9767 * @thres: holds the queue full thresholds in bytes
9768 *
9769 * Returns the current configuration of the CIM queues, starting with
9770 * the IBQs, then the OBQs.
9771 */
t4_read_cimq_cfg(struct adapter * adap,u16 * base,u16 * size,u16 * thres)9772 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9773 {
9774 unsigned int i, v;
9775 int cim_num_obq = is_t4(adap->params.chip) ?
9776 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9777
9778 for (i = 0; i < CIM_NUM_IBQ; i++) {
9779 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9780 QUENUMSELECT_V(i));
9781 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9782 /* value is in 256-byte units */
9783 *base++ = CIMQBASE_G(v) * 256;
9784 *size++ = CIMQSIZE_G(v) * 256;
9785 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9786 }
9787 for (i = 0; i < cim_num_obq; i++) {
9788 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9789 QUENUMSELECT_V(i));
9790 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9791 /* value is in 256-byte units */
9792 *base++ = CIMQBASE_G(v) * 256;
9793 *size++ = CIMQSIZE_G(v) * 256;
9794 }
9795 }
9796
9797 /**
9798 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9799 * @adap: the adapter
9800 * @qid: the queue index
9801 * @data: where to store the queue contents
9802 * @n: capacity of @data in 32-bit words
9803 *
9804 * Reads the contents of the selected CIM queue starting at address 0 up
9805 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9806 * error and the number of 32-bit words actually read on success.
9807 */
t4_read_cim_ibq(struct adapter * adap,unsigned int qid,u32 * data,size_t n)9808 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9809 {
9810 int i, err, attempts;
9811 unsigned int addr;
9812 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9813
9814 if (qid > 5 || (n & 3))
9815 return -EINVAL;
9816
9817 addr = qid * nwords;
9818 if (n > nwords)
9819 n = nwords;
9820
9821 /* It might take 3-10ms before the IBQ debug read access is allowed.
9822 * Wait for 1 Sec with a delay of 1 usec.
9823 */
9824 attempts = 1000000;
9825
9826 for (i = 0; i < n; i++, addr++) {
9827 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9828 IBQDBGEN_F);
9829 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9830 attempts, 1);
9831 if (err)
9832 return err;
9833 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9834 }
9835 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9836 return i;
9837 }
9838
9839 /**
9840 * t4_read_cim_obq - read the contents of a CIM outbound queue
9841 * @adap: the adapter
9842 * @qid: the queue index
9843 * @data: where to store the queue contents
9844 * @n: capacity of @data in 32-bit words
9845 *
9846 * Reads the contents of the selected CIM queue starting at address 0 up
9847 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9848 * error and the number of 32-bit words actually read on success.
9849 */
t4_read_cim_obq(struct adapter * adap,unsigned int qid,u32 * data,size_t n)9850 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9851 {
9852 int i, err;
9853 unsigned int addr, v, nwords;
9854 int cim_num_obq = is_t4(adap->params.chip) ?
9855 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9856
9857 if ((qid > (cim_num_obq - 1)) || (n & 3))
9858 return -EINVAL;
9859
9860 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9861 QUENUMSELECT_V(qid));
9862 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9863
9864 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
9865 nwords = CIMQSIZE_G(v) * 64; /* same */
9866 if (n > nwords)
9867 n = nwords;
9868
9869 for (i = 0; i < n; i++, addr++) {
9870 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9871 OBQDBGEN_F);
9872 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9873 2, 1);
9874 if (err)
9875 return err;
9876 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9877 }
9878 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9879 return i;
9880 }
9881
9882 /**
9883 * t4_cim_read - read a block from CIM internal address space
9884 * @adap: the adapter
9885 * @addr: the start address within the CIM address space
9886 * @n: number of words to read
9887 * @valp: where to store the result
9888 *
9889 * Reads a block of 4-byte words from the CIM intenal address space.
9890 */
t4_cim_read(struct adapter * adap,unsigned int addr,unsigned int n,unsigned int * valp)9891 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9892 unsigned int *valp)
9893 {
9894 int ret = 0;
9895
9896 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9897 return -EBUSY;
9898
9899 for ( ; !ret && n--; addr += 4) {
9900 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9901 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9902 0, 5, 2);
9903 if (!ret)
9904 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9905 }
9906 return ret;
9907 }
9908
9909 /**
9910 * t4_cim_write - write a block into CIM internal address space
9911 * @adap: the adapter
9912 * @addr: the start address within the CIM address space
9913 * @n: number of words to write
9914 * @valp: set of values to write
9915 *
9916 * Writes a block of 4-byte words into the CIM intenal address space.
9917 */
t4_cim_write(struct adapter * adap,unsigned int addr,unsigned int n,const unsigned int * valp)9918 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9919 const unsigned int *valp)
9920 {
9921 int ret = 0;
9922
9923 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9924 return -EBUSY;
9925
9926 for ( ; !ret && n--; addr += 4) {
9927 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9928 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9929 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9930 0, 5, 2);
9931 }
9932 return ret;
9933 }
9934
t4_cim_write1(struct adapter * adap,unsigned int addr,unsigned int val)9935 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9936 unsigned int val)
9937 {
9938 return t4_cim_write(adap, addr, 1, &val);
9939 }
9940
9941 /**
9942 * t4_cim_read_la - read CIM LA capture buffer
9943 * @adap: the adapter
9944 * @la_buf: where to store the LA data
9945 * @wrptr: the HW write pointer within the capture buffer
9946 *
9947 * Reads the contents of the CIM LA buffer with the most recent entry at
9948 * the end of the returned data and with the entry at @wrptr first.
9949 * We try to leave the LA in the running state we find it in.
9950 */
t4_cim_read_la(struct adapter * adap,u32 * la_buf,unsigned int * wrptr)9951 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9952 {
9953 int i, ret;
9954 unsigned int cfg, val, idx;
9955
9956 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9957 if (ret)
9958 return ret;
9959
9960 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
9961 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9962 if (ret)
9963 return ret;
9964 }
9965
9966 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9967 if (ret)
9968 goto restart;
9969
9970 idx = UPDBGLAWRPTR_G(val);
9971 if (wrptr)
9972 *wrptr = idx;
9973
9974 for (i = 0; i < adap->params.cim_la_size; i++) {
9975 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9976 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9977 if (ret)
9978 break;
9979 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9980 if (ret)
9981 break;
9982 if (val & UPDBGLARDEN_F) {
9983 ret = -ETIMEDOUT;
9984 break;
9985 }
9986 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9987 if (ret)
9988 break;
9989
9990 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9991 * identify the 32-bit portion of the full 312-bit data
9992 */
9993 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9994 idx = (idx & 0xff0) + 0x10;
9995 else
9996 idx++;
9997 /* address can't exceed 0xfff */
9998 idx &= UPDBGLARDPTR_M;
9999 }
10000 restart:
10001 if (cfg & UPDBGLAEN_F) {
10002 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
10003 cfg & ~UPDBGLARDEN_F);
10004 if (!ret)
10005 ret = r;
10006 }
10007 return ret;
10008 }
10009
10010 /**
10011 * t4_tp_read_la - read TP LA capture buffer
10012 * @adap: the adapter
10013 * @la_buf: where to store the LA data
10014 * @wrptr: the HW write pointer within the capture buffer
10015 *
10016 * Reads the contents of the TP LA buffer with the most recent entry at
10017 * the end of the returned data and with the entry at @wrptr first.
10018 * We leave the LA in the running state we find it in.
10019 */
t4_tp_read_la(struct adapter * adap,u64 * la_buf,unsigned int * wrptr)10020 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
10021 {
10022 bool last_incomplete;
10023 unsigned int i, cfg, val, idx;
10024
10025 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
10026 if (cfg & DBGLAENABLE_F) /* freeze LA */
10027 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10028 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
10029
10030 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
10031 idx = DBGLAWPTR_G(val);
10032 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
10033 if (last_incomplete)
10034 idx = (idx + 1) & DBGLARPTR_M;
10035 if (wrptr)
10036 *wrptr = idx;
10037
10038 val &= 0xffff;
10039 val &= ~DBGLARPTR_V(DBGLARPTR_M);
10040 val |= adap->params.tp.la_mask;
10041
10042 for (i = 0; i < TPLA_SIZE; i++) {
10043 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
10044 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
10045 idx = (idx + 1) & DBGLARPTR_M;
10046 }
10047
10048 /* Wipe out last entry if it isn't valid */
10049 if (last_incomplete)
10050 la_buf[TPLA_SIZE - 1] = ~0ULL;
10051
10052 if (cfg & DBGLAENABLE_F) /* restore running state */
10053 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10054 cfg | adap->params.tp.la_mask);
10055 }
10056
10057 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10058 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
10059 * state for more than the Warning Threshold then we'll issue a warning about
10060 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
10061 * appears to be hung every Warning Repeat second till the situation clears.
10062 * If the situation clears, we'll note that as well.
10063 */
10064 #define SGE_IDMA_WARN_THRESH 1
10065 #define SGE_IDMA_WARN_REPEAT 300
10066
10067 /**
10068 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10069 * @adapter: the adapter
10070 * @idma: the adapter IDMA Monitor state
10071 *
10072 * Initialize the state of an SGE Ingress DMA Monitor.
10073 */
t4_idma_monitor_init(struct adapter * adapter,struct sge_idma_monitor_state * idma)10074 void t4_idma_monitor_init(struct adapter *adapter,
10075 struct sge_idma_monitor_state *idma)
10076 {
10077 /* Initialize the state variables for detecting an SGE Ingress DMA
10078 * hang. The SGE has internal counters which count up on each clock
10079 * tick whenever the SGE finds its Ingress DMA State Engines in the
10080 * same state they were on the previous clock tick. The clock used is
10081 * the Core Clock so we have a limit on the maximum "time" they can
10082 * record; typically a very small number of seconds. For instance,
10083 * with a 600MHz Core Clock, we can only count up to a bit more than
10084 * 7s. So we'll synthesize a larger counter in order to not run the
10085 * risk of having the "timers" overflow and give us the flexibility to
10086 * maintain a Hung SGE State Machine of our own which operates across
10087 * a longer time frame.
10088 */
10089 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10090 idma->idma_stalled[0] = 0;
10091 idma->idma_stalled[1] = 0;
10092 }
10093
10094 /**
10095 * t4_idma_monitor - monitor SGE Ingress DMA state
10096 * @adapter: the adapter
10097 * @idma: the adapter IDMA Monitor state
10098 * @hz: number of ticks/second
10099 * @ticks: number of ticks since the last IDMA Monitor call
10100 */
t4_idma_monitor(struct adapter * adapter,struct sge_idma_monitor_state * idma,int hz,int ticks)10101 void t4_idma_monitor(struct adapter *adapter,
10102 struct sge_idma_monitor_state *idma,
10103 int hz, int ticks)
10104 {
10105 int i, idma_same_state_cnt[2];
10106
10107 /* Read the SGE Debug Ingress DMA Same State Count registers. These
10108 * are counters inside the SGE which count up on each clock when the
10109 * SGE finds its Ingress DMA State Engines in the same states they
10110 * were in the previous clock. The counters will peg out at
10111 * 0xffffffff without wrapping around so once they pass the 1s
10112 * threshold they'll stay above that till the IDMA state changes.
10113 */
10114 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
10115 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
10116 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10117
10118 for (i = 0; i < 2; i++) {
10119 u32 debug0, debug11;
10120
10121 /* If the Ingress DMA Same State Counter ("timer") is less
10122 * than 1s, then we can reset our synthesized Stall Timer and
10123 * continue. If we have previously emitted warnings about a
10124 * potential stalled Ingress Queue, issue a note indicating
10125 * that the Ingress Queue has resumed forward progress.
10126 */
10127 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10128 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
10129 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
10130 "resumed after %d seconds\n",
10131 i, idma->idma_qid[i],
10132 idma->idma_stalled[i] / hz);
10133 idma->idma_stalled[i] = 0;
10134 continue;
10135 }
10136
10137 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10138 * domain. The first time we get here it'll be because we
10139 * passed the 1s Threshold; each additional time it'll be
10140 * because the RX Timer Callback is being fired on its regular
10141 * schedule.
10142 *
10143 * If the stall is below our Potential Hung Ingress Queue
10144 * Warning Threshold, continue.
10145 */
10146 if (idma->idma_stalled[i] == 0) {
10147 idma->idma_stalled[i] = hz;
10148 idma->idma_warn[i] = 0;
10149 } else {
10150 idma->idma_stalled[i] += ticks;
10151 idma->idma_warn[i] -= ticks;
10152 }
10153
10154 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
10155 continue;
10156
10157 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10158 */
10159 if (idma->idma_warn[i] > 0)
10160 continue;
10161 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
10162
10163 /* Read and save the SGE IDMA State and Queue ID information.
10164 * We do this every time in case it changes across time ...
10165 * can't be too careful ...
10166 */
10167 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
10168 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10169 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10170
10171 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
10172 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10173 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10174
10175 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
10176 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10177 i, idma->idma_qid[i], idma->idma_state[i],
10178 idma->idma_stalled[i] / hz,
10179 debug0, debug11);
10180 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10181 }
10182 }
10183
10184 /**
10185 * t4_load_cfg - download config file
10186 * @adap: the adapter
10187 * @cfg_data: the cfg text file to write
10188 * @size: text file size
10189 *
10190 * Write the supplied config text file to the card's serial flash.
10191 */
t4_load_cfg(struct adapter * adap,const u8 * cfg_data,unsigned int size)10192 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10193 {
10194 int ret, i, n, cfg_addr;
10195 unsigned int addr;
10196 unsigned int flash_cfg_start_sec;
10197 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10198
10199 cfg_addr = t4_flash_cfg_addr(adap);
10200 if (cfg_addr < 0)
10201 return cfg_addr;
10202
10203 addr = cfg_addr;
10204 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10205
10206 if (size > FLASH_CFG_MAX_SIZE) {
10207 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
10208 FLASH_CFG_MAX_SIZE);
10209 return -EFBIG;
10210 }
10211
10212 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
10213 sf_sec_size);
10214 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10215 flash_cfg_start_sec + i - 1);
10216 /* If size == 0 then we're simply erasing the FLASH sectors associated
10217 * with the on-adapter Firmware Configuration File.
10218 */
10219 if (ret || size == 0)
10220 goto out;
10221
10222 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10223 for (i = 0; i < size; i += SF_PAGE_SIZE) {
10224 if ((size - i) < SF_PAGE_SIZE)
10225 n = size - i;
10226 else
10227 n = SF_PAGE_SIZE;
10228 ret = t4_write_flash(adap, addr, n, cfg_data, true);
10229 if (ret)
10230 goto out;
10231
10232 addr += SF_PAGE_SIZE;
10233 cfg_data += SF_PAGE_SIZE;
10234 }
10235
10236 out:
10237 if (ret)
10238 dev_err(adap->pdev_dev, "config file %s failed %d\n",
10239 (size == 0 ? "clear" : "download"), ret);
10240 return ret;
10241 }
10242
10243 /**
10244 * t4_set_vf_mac - Set MAC address for the specified VF
10245 * @adapter: The adapter
10246 * @vf: one of the VFs instantiated by the specified PF
10247 * @naddr: the number of MAC addresses
10248 * @addr: the MAC address(es) to be set to the specified VF
10249 */
t4_set_vf_mac_acl(struct adapter * adapter,unsigned int vf,unsigned int naddr,u8 * addr)10250 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
10251 unsigned int naddr, u8 *addr)
10252 {
10253 struct fw_acl_mac_cmd cmd;
10254
10255 memset(&cmd, 0, sizeof(cmd));
10256 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
10257 FW_CMD_REQUEST_F |
10258 FW_CMD_WRITE_F |
10259 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
10260 FW_ACL_MAC_CMD_VFN_V(vf));
10261
10262 /* Note: Do not enable the ACL */
10263 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10264 cmd.nmac = naddr;
10265
10266 switch (adapter->pf) {
10267 case 3:
10268 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10269 break;
10270 case 2:
10271 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10272 break;
10273 case 1:
10274 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10275 break;
10276 case 0:
10277 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10278 break;
10279 }
10280
10281 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10282 }
10283
10284 /**
10285 * t4_read_pace_tbl - read the pace table
10286 * @adap: the adapter
10287 * @pace_vals: holds the returned values
10288 *
10289 * Returns the values of TP's pace table in microseconds.
10290 */
t4_read_pace_tbl(struct adapter * adap,unsigned int pace_vals[NTX_SCHED])10291 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10292 {
10293 unsigned int i, v;
10294
10295 for (i = 0; i < NTX_SCHED; i++) {
10296 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
10297 v = t4_read_reg(adap, TP_PACE_TABLE_A);
10298 pace_vals[i] = dack_ticks_to_usec(adap, v);
10299 }
10300 }
10301
10302 /**
10303 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10304 * @adap: the adapter
10305 * @sched: the scheduler index
10306 * @kbps: the byte rate in Kbps
10307 * @ipg: the interpacket delay in tenths of nanoseconds
10308 * @sleep_ok: if true we may sleep while awaiting command completion
10309 *
10310 * Return the current configuration of a HW Tx scheduler.
10311 */
t4_get_tx_sched(struct adapter * adap,unsigned int sched,unsigned int * kbps,unsigned int * ipg,bool sleep_ok)10312 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
10313 unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
10314 {
10315 unsigned int v, addr, bpt, cpt;
10316
10317 if (kbps) {
10318 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
10319 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10320 if (sched & 1)
10321 v >>= 16;
10322 bpt = (v >> 8) & 0xff;
10323 cpt = v & 0xff;
10324 if (!cpt) {
10325 *kbps = 0; /* scheduler disabled */
10326 } else {
10327 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10328 *kbps = (v * bpt) / 125;
10329 }
10330 }
10331 if (ipg) {
10332 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
10333 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10334 if (sched & 1)
10335 v >>= 16;
10336 v &= 0xffff;
10337 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10338 }
10339 }
10340
10341 /* t4_sge_ctxt_rd - read an SGE context through FW
10342 * @adap: the adapter
10343 * @mbox: mailbox to use for the FW command
10344 * @cid: the context id
10345 * @ctype: the context type
10346 * @data: where to store the context data
10347 *
10348 * Issues a FW command through the given mailbox to read an SGE context.
10349 */
t4_sge_ctxt_rd(struct adapter * adap,unsigned int mbox,unsigned int cid,enum ctxt_type ctype,u32 * data)10350 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10351 enum ctxt_type ctype, u32 *data)
10352 {
10353 struct fw_ldst_cmd c;
10354 int ret;
10355
10356 if (ctype == CTXT_FLM)
10357 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10358 else
10359 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10360
10361 memset(&c, 0, sizeof(c));
10362 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10363 FW_CMD_REQUEST_F | FW_CMD_READ_F |
10364 FW_LDST_CMD_ADDRSPACE_V(ret));
10365 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10366 c.u.idctxt.physid = cpu_to_be32(cid);
10367
10368 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10369 if (ret == 0) {
10370 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10371 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10372 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10373 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10374 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10375 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10376 }
10377 return ret;
10378 }
10379
10380 /**
10381 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10382 * @adap: the adapter
10383 * @cid: the context id
10384 * @ctype: the context type
10385 * @data: where to store the context data
10386 *
10387 * Reads an SGE context directly, bypassing FW. This is only for
10388 * debugging when FW is unavailable.
10389 */
t4_sge_ctxt_rd_bd(struct adapter * adap,unsigned int cid,enum ctxt_type ctype,u32 * data)10390 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10391 enum ctxt_type ctype, u32 *data)
10392 {
10393 int i, ret;
10394
10395 t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10396 ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10397 if (!ret)
10398 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
10399 *data++ = t4_read_reg(adap, i);
10400 return ret;
10401 }
10402
t4_sched_params(struct adapter * adapter,u8 type,u8 level,u8 mode,u8 rateunit,u8 ratemode,u8 channel,u8 class,u32 minrate,u32 maxrate,u16 weight,u16 pktsize,u16 burstsize)10403 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
10404 u8 rateunit, u8 ratemode, u8 channel, u8 class,
10405 u32 minrate, u32 maxrate, u16 weight, u16 pktsize,
10406 u16 burstsize)
10407 {
10408 struct fw_sched_cmd cmd;
10409
10410 memset(&cmd, 0, sizeof(cmd));
10411 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
10412 FW_CMD_REQUEST_F |
10413 FW_CMD_WRITE_F);
10414 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10415
10416 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10417 cmd.u.params.type = type;
10418 cmd.u.params.level = level;
10419 cmd.u.params.mode = mode;
10420 cmd.u.params.ch = channel;
10421 cmd.u.params.cl = class;
10422 cmd.u.params.unit = rateunit;
10423 cmd.u.params.rate = ratemode;
10424 cmd.u.params.min = cpu_to_be32(minrate);
10425 cmd.u.params.max = cpu_to_be32(maxrate);
10426 cmd.u.params.weight = cpu_to_be16(weight);
10427 cmd.u.params.pktsize = cpu_to_be16(pktsize);
10428 cmd.u.params.burstsize = cpu_to_be16(burstsize);
10429
10430 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
10431 NULL, 1);
10432 }
10433
10434 /**
10435 * t4_i2c_rd - read I2C data from adapter
10436 * @adap: the adapter
10437 * @mbox: mailbox to use for the FW command
10438 * @port: Port number if per-port device; <0 if not
10439 * @devid: per-port device ID or absolute device ID
10440 * @offset: byte offset into device I2C space
10441 * @len: byte length of I2C space data
10442 * @buf: buffer in which to return I2C data
10443 *
10444 * Reads the I2C data from the indicated device and location.
10445 */
t4_i2c_rd(struct adapter * adap,unsigned int mbox,int port,unsigned int devid,unsigned int offset,unsigned int len,u8 * buf)10446 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10447 unsigned int devid, unsigned int offset,
10448 unsigned int len, u8 *buf)
10449 {
10450 struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10451 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10452 int ret = 0;
10453
10454 if (len > I2C_PAGE_SIZE)
10455 return -EINVAL;
10456
10457 /* Dont allow reads that spans multiple pages */
10458 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10459 return -EINVAL;
10460
10461 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10462 ldst_cmd.op_to_addrspace =
10463 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10464 FW_CMD_REQUEST_F |
10465 FW_CMD_READ_F |
10466 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10467 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10468 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10469 ldst_cmd.u.i2c.did = devid;
10470
10471 while (len > 0) {
10472 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10473
10474 ldst_cmd.u.i2c.boffset = offset;
10475 ldst_cmd.u.i2c.blen = i2c_len;
10476
10477 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10478 &ldst_rpl);
10479 if (ret)
10480 break;
10481
10482 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10483 offset += i2c_len;
10484 buf += i2c_len;
10485 len -= i2c_len;
10486 }
10487
10488 return ret;
10489 }
10490
10491 /**
10492 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10493 * @adap: the adapter
10494 * @mbox: mailbox to use for the FW command
10495 * @vf: one of the VFs instantiated by the specified PF
10496 * @vlan: The vlanid to be set
10497 */
t4_set_vlan_acl(struct adapter * adap,unsigned int mbox,unsigned int vf,u16 vlan)10498 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10499 u16 vlan)
10500 {
10501 struct fw_acl_vlan_cmd vlan_cmd;
10502 unsigned int enable;
10503
10504 enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10505 memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10506 vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10507 FW_CMD_REQUEST_F |
10508 FW_CMD_WRITE_F |
10509 FW_CMD_EXEC_F |
10510 FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10511 FW_ACL_VLAN_CMD_VFN_V(vf));
10512 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10513 /* Drop all packets that donot match vlan id */
10514 vlan_cmd.dropnovlan_fm = (enable
10515 ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F |
10516 FW_ACL_VLAN_CMD_FM_F) : 0);
10517 if (enable != 0) {
10518 vlan_cmd.nvlan = 1;
10519 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10520 }
10521
10522 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
10523 }
10524
10525 /**
10526 * modify_device_id - Modifies the device ID of the Boot BIOS image
10527 * @device_id: the device ID to write.
10528 * @boot_data: the boot image to modify.
10529 *
10530 * Write the supplied device ID to the boot BIOS image.
10531 */
modify_device_id(int device_id,u8 * boot_data)10532 static void modify_device_id(int device_id, u8 *boot_data)
10533 {
10534 struct cxgb4_pcir_data *pcir_header;
10535 struct legacy_pci_rom_hdr *header;
10536 u8 *cur_header = boot_data;
10537 u16 pcir_offset;
10538
10539 /* Loop through all chained images and change the device ID's */
10540 do {
10541 header = (struct legacy_pci_rom_hdr *)cur_header;
10542 pcir_offset = le16_to_cpu(header->pcir_offset);
10543 pcir_header = (struct cxgb4_pcir_data *)(cur_header +
10544 pcir_offset);
10545
10546 /**
10547 * Only modify the Device ID if code type is Legacy or HP.
10548 * 0x00: Okay to modify
10549 * 0x01: FCODE. Do not modify
10550 * 0x03: Okay to modify
10551 * 0x04-0xFF: Do not modify
10552 */
10553 if (pcir_header->code_type == CXGB4_HDR_CODE1) {
10554 u8 csum = 0;
10555 int i;
10556
10557 /**
10558 * Modify Device ID to match current adatper
10559 */
10560 pcir_header->device_id = cpu_to_le16(device_id);
10561
10562 /**
10563 * Set checksum temporarily to 0.
10564 * We will recalculate it later.
10565 */
10566 header->cksum = 0x0;
10567
10568 /**
10569 * Calculate and update checksum
10570 */
10571 for (i = 0; i < (header->size512 * 512); i++)
10572 csum += cur_header[i];
10573
10574 /**
10575 * Invert summed value to create the checksum
10576 * Writing new checksum value directly to the boot data
10577 */
10578 cur_header[7] = -csum;
10579
10580 } else if (pcir_header->code_type == CXGB4_HDR_CODE2) {
10581 /**
10582 * Modify Device ID to match current adatper
10583 */
10584 pcir_header->device_id = cpu_to_le16(device_id);
10585 }
10586
10587 /**
10588 * Move header pointer up to the next image in the ROM.
10589 */
10590 cur_header += header->size512 * 512;
10591 } while (!(pcir_header->indicator & CXGB4_HDR_INDI));
10592 }
10593
10594 /**
10595 * t4_load_boot - download boot flash
10596 * @adap: the adapter
10597 * @boot_data: the boot image to write
10598 * @boot_addr: offset in flash to write boot_data
10599 * @size: image size
10600 *
10601 * Write the supplied boot image to the card's serial flash.
10602 * The boot image has the following sections: a 28-byte header and the
10603 * boot image.
10604 */
t4_load_boot(struct adapter * adap,u8 * boot_data,unsigned int boot_addr,unsigned int size)10605 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10606 unsigned int boot_addr, unsigned int size)
10607 {
10608 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10609 unsigned int boot_sector = (boot_addr * 1024);
10610 struct cxgb4_pci_exp_rom_header *header;
10611 struct cxgb4_pcir_data *pcir_header;
10612 int pcir_offset;
10613 unsigned int i;
10614 u16 device_id;
10615 int ret, addr;
10616
10617 /**
10618 * Make sure the boot image does not encroach on the firmware region
10619 */
10620 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10621 dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n");
10622 return -EFBIG;
10623 }
10624
10625 /* Get boot header */
10626 header = (struct cxgb4_pci_exp_rom_header *)boot_data;
10627 pcir_offset = le16_to_cpu(header->pcir_offset);
10628 /* PCIR Data Structure */
10629 pcir_header = (struct cxgb4_pcir_data *)&boot_data[pcir_offset];
10630
10631 /**
10632 * Perform some primitive sanity testing to avoid accidentally
10633 * writing garbage over the boot sectors. We ought to check for
10634 * more but it's not worth it for now ...
10635 */
10636 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10637 dev_err(adap->pdev_dev, "boot image too small/large\n");
10638 return -EFBIG;
10639 }
10640
10641 if (le16_to_cpu(header->signature) != BOOT_SIGNATURE) {
10642 dev_err(adap->pdev_dev, "Boot image missing signature\n");
10643 return -EINVAL;
10644 }
10645
10646 /* Check PCI header signature */
10647 if (le32_to_cpu(pcir_header->signature) != PCIR_SIGNATURE) {
10648 dev_err(adap->pdev_dev, "PCI header missing signature\n");
10649 return -EINVAL;
10650 }
10651
10652 /* Check Vendor ID matches Chelsio ID*/
10653 if (le16_to_cpu(pcir_header->vendor_id) != PCI_VENDOR_ID_CHELSIO) {
10654 dev_err(adap->pdev_dev, "Vendor ID missing signature\n");
10655 return -EINVAL;
10656 }
10657
10658 /**
10659 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10660 * and Boot configuration data sections. These 3 boot sections span
10661 * sectors 0 to 7 in flash and live right before the FW image location.
10662 */
10663 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, sf_sec_size);
10664 ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10665 (boot_sector >> 16) + i - 1);
10666
10667 /**
10668 * If size == 0 then we're simply erasing the FLASH sectors associated
10669 * with the on-adapter option ROM file
10670 */
10671 if (ret || size == 0)
10672 goto out;
10673 /* Retrieve adapter's device ID */
10674 pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &device_id);
10675 /* Want to deal with PF 0 so I strip off PF 4 indicator */
10676 device_id = device_id & 0xf0ff;
10677
10678 /* Check PCIE Device ID */
10679 if (le16_to_cpu(pcir_header->device_id) != device_id) {
10680 /**
10681 * Change the device ID in the Boot BIOS image to match
10682 * the Device ID of the current adapter.
10683 */
10684 modify_device_id(device_id, boot_data);
10685 }
10686
10687 /**
10688 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10689 * we finish copying the rest of the boot image. This will ensure
10690 * that the BIOS boot header will only be written if the boot image
10691 * was written in full.
10692 */
10693 addr = boot_sector;
10694 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10695 addr += SF_PAGE_SIZE;
10696 boot_data += SF_PAGE_SIZE;
10697 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data,
10698 false);
10699 if (ret)
10700 goto out;
10701 }
10702
10703 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10704 (const u8 *)header, false);
10705
10706 out:
10707 if (ret)
10708 dev_err(adap->pdev_dev, "boot image load failed, error %d\n",
10709 ret);
10710 return ret;
10711 }
10712
10713 /**
10714 * t4_flash_bootcfg_addr - return the address of the flash
10715 * optionrom configuration
10716 * @adapter: the adapter
10717 *
10718 * Return the address within the flash where the OptionROM Configuration
10719 * is stored, or an error if the device FLASH is too small to contain
10720 * a OptionROM Configuration.
10721 */
t4_flash_bootcfg_addr(struct adapter * adapter)10722 static int t4_flash_bootcfg_addr(struct adapter *adapter)
10723 {
10724 /**
10725 * If the device FLASH isn't large enough to hold a Firmware
10726 * Configuration File, return an error.
10727 */
10728 if (adapter->params.sf_size <
10729 FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10730 return -ENOSPC;
10731
10732 return FLASH_BOOTCFG_START;
10733 }
10734
t4_load_bootcfg(struct adapter * adap,const u8 * cfg_data,unsigned int size)10735 int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10736 {
10737 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10738 struct cxgb4_bootcfg_data *header;
10739 unsigned int flash_cfg_start_sec;
10740 unsigned int addr, npad;
10741 int ret, i, n, cfg_addr;
10742
10743 cfg_addr = t4_flash_bootcfg_addr(adap);
10744 if (cfg_addr < 0)
10745 return cfg_addr;
10746
10747 addr = cfg_addr;
10748 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10749
10750 if (size > FLASH_BOOTCFG_MAX_SIZE) {
10751 dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n",
10752 FLASH_BOOTCFG_MAX_SIZE);
10753 return -EFBIG;
10754 }
10755
10756 header = (struct cxgb4_bootcfg_data *)cfg_data;
10757 if (le16_to_cpu(header->signature) != BOOT_CFG_SIG) {
10758 dev_err(adap->pdev_dev, "Wrong bootcfg signature\n");
10759 ret = -EINVAL;
10760 goto out;
10761 }
10762
10763 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,
10764 sf_sec_size);
10765 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10766 flash_cfg_start_sec + i - 1);
10767
10768 /**
10769 * If size == 0 then we're simply erasing the FLASH sectors associated
10770 * with the on-adapter OptionROM Configuration File.
10771 */
10772 if (ret || size == 0)
10773 goto out;
10774
10775 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10776 for (i = 0; i < size; i += SF_PAGE_SIZE) {
10777 n = min_t(u32, size - i, SF_PAGE_SIZE);
10778
10779 ret = t4_write_flash(adap, addr, n, cfg_data, false);
10780 if (ret)
10781 goto out;
10782
10783 addr += SF_PAGE_SIZE;
10784 cfg_data += SF_PAGE_SIZE;
10785 }
10786
10787 npad = ((size + 4 - 1) & ~3) - size;
10788 for (i = 0; i < npad; i++) {
10789 u8 data = 0;
10790
10791 ret = t4_write_flash(adap, cfg_addr + size + i, 1, &data,
10792 false);
10793 if (ret)
10794 goto out;
10795 }
10796
10797 out:
10798 if (ret)
10799 dev_err(adap->pdev_dev, "boot config data %s failed %d\n",
10800 (size == 0 ? "clear" : "download"), ret);
10801 return ret;
10802 }
10803