1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "adreno_pm4.xml.h"
31 #include "adreno_common.xml.h"
32
33 #include "vk_format.h"
34 #include "vk_util.h"
35
36 #include "tu_cs.h"
37
38 #include "tu_tracepoints.h"
39
40 void
tu6_emit_event_write(struct tu_cmd_buffer * cmd,struct tu_cs * cs,enum vgt_event_type event)41 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
42 struct tu_cs *cs,
43 enum vgt_event_type event)
44 {
45 bool need_seqno = false;
46 switch (event) {
47 case CACHE_FLUSH_TS:
48 case WT_DONE_TS:
49 case RB_DONE_TS:
50 case PC_CCU_FLUSH_DEPTH_TS:
51 case PC_CCU_FLUSH_COLOR_TS:
52 case PC_CCU_RESOLVE_TS:
53 need_seqno = true;
54 break;
55 default:
56 break;
57 }
58
59 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
60 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
61 if (need_seqno) {
62 tu_cs_emit_qw(cs, global_iova(cmd, seqno_dummy));
63 tu_cs_emit(cs, 0);
64 }
65 }
66
67 static void
tu6_emit_flushes(struct tu_cmd_buffer * cmd_buffer,struct tu_cs * cs,enum tu_cmd_flush_bits flushes)68 tu6_emit_flushes(struct tu_cmd_buffer *cmd_buffer,
69 struct tu_cs *cs,
70 enum tu_cmd_flush_bits flushes)
71 {
72 if (unlikely(cmd_buffer->device->physical_device->instance->debug_flags & TU_DEBUG_FLUSHALL))
73 flushes |= TU_CMD_FLAG_ALL_FLUSH | TU_CMD_FLAG_ALL_INVALIDATE;
74
75 if (unlikely(cmd_buffer->device->physical_device->instance->debug_flags & TU_DEBUG_SYNCDRAW))
76 flushes |= TU_CMD_FLAG_WAIT_MEM_WRITES |
77 TU_CMD_FLAG_WAIT_FOR_IDLE |
78 TU_CMD_FLAG_WAIT_FOR_ME;
79
80 /* Experiments show that invalidating CCU while it still has data in it
81 * doesn't work, so make sure to always flush before invalidating in case
82 * any data remains that hasn't yet been made available through a barrier.
83 * However it does seem to work for UCHE.
84 */
85 if (flushes & (TU_CMD_FLAG_CCU_FLUSH_COLOR |
86 TU_CMD_FLAG_CCU_INVALIDATE_COLOR))
87 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_COLOR_TS);
88 if (flushes & (TU_CMD_FLAG_CCU_FLUSH_DEPTH |
89 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH))
90 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_DEPTH_TS);
91 if (flushes & TU_CMD_FLAG_CCU_INVALIDATE_COLOR)
92 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_COLOR);
93 if (flushes & TU_CMD_FLAG_CCU_INVALIDATE_DEPTH)
94 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_DEPTH);
95 if (flushes & TU_CMD_FLAG_CACHE_FLUSH)
96 tu6_emit_event_write(cmd_buffer, cs, CACHE_FLUSH_TS);
97 if (flushes & TU_CMD_FLAG_CACHE_INVALIDATE)
98 tu6_emit_event_write(cmd_buffer, cs, CACHE_INVALIDATE);
99 if (flushes & TU_CMD_FLAG_WAIT_MEM_WRITES)
100 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
101 if ((flushes & TU_CMD_FLAG_WAIT_FOR_IDLE) ||
102 (cmd_buffer->device->physical_device->info->a6xx.has_ccu_flush_bug &&
103 (flushes & (TU_CMD_FLAG_CCU_FLUSH_COLOR | TU_CMD_FLAG_CCU_FLUSH_DEPTH))))
104 tu_cs_emit_wfi(cs);
105 if (flushes & TU_CMD_FLAG_WAIT_FOR_ME)
106 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
107 }
108
109 /* "Normal" cache flushes, that don't require any special handling */
110
111 static void
tu_emit_cache_flush(struct tu_cmd_buffer * cmd_buffer,struct tu_cs * cs)112 tu_emit_cache_flush(struct tu_cmd_buffer *cmd_buffer,
113 struct tu_cs *cs)
114 {
115 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.cache.flush_bits);
116 cmd_buffer->state.cache.flush_bits = 0;
117 }
118
119 /* Renderpass cache flushes */
120
121 void
tu_emit_cache_flush_renderpass(struct tu_cmd_buffer * cmd_buffer,struct tu_cs * cs)122 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer *cmd_buffer,
123 struct tu_cs *cs)
124 {
125 if (!cmd_buffer->state.renderpass_cache.flush_bits &&
126 likely(!cmd_buffer->device->physical_device->instance->debug_flags))
127 return;
128 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.renderpass_cache.flush_bits);
129 cmd_buffer->state.renderpass_cache.flush_bits = 0;
130 }
131
132 /* Cache flushes for things that use the color/depth read/write path (i.e.
133 * blits and draws). This deals with changing CCU state as well as the usual
134 * cache flushing.
135 */
136
137 void
tu_emit_cache_flush_ccu(struct tu_cmd_buffer * cmd_buffer,struct tu_cs * cs,enum tu_cmd_ccu_state ccu_state)138 tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer,
139 struct tu_cs *cs,
140 enum tu_cmd_ccu_state ccu_state)
141 {
142 enum tu_cmd_flush_bits flushes = cmd_buffer->state.cache.flush_bits;
143
144 assert(ccu_state != TU_CMD_CCU_UNKNOWN);
145
146 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
147 * the CCU may also contain data that we haven't flushed out yet, so we
148 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
149 * emit a WFI as it isn't pipelined.
150 */
151 if (ccu_state != cmd_buffer->state.ccu_state) {
152 if (cmd_buffer->state.ccu_state != TU_CMD_CCU_GMEM) {
153 flushes |=
154 TU_CMD_FLAG_CCU_FLUSH_COLOR |
155 TU_CMD_FLAG_CCU_FLUSH_DEPTH;
156 cmd_buffer->state.cache.pending_flush_bits &= ~(
157 TU_CMD_FLAG_CCU_FLUSH_COLOR |
158 TU_CMD_FLAG_CCU_FLUSH_DEPTH);
159 }
160 flushes |=
161 TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
162 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
163 TU_CMD_FLAG_WAIT_FOR_IDLE;
164 cmd_buffer->state.cache.pending_flush_bits &= ~(
165 TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
166 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
167 TU_CMD_FLAG_WAIT_FOR_IDLE);
168 }
169
170 tu6_emit_flushes(cmd_buffer, cs, flushes);
171 cmd_buffer->state.cache.flush_bits = 0;
172
173 if (ccu_state != cmd_buffer->state.ccu_state) {
174 struct tu_physical_device *phys_dev = cmd_buffer->device->physical_device;
175 tu_cs_emit_regs(cs,
176 A6XX_RB_CCU_CNTL(.color_offset =
177 ccu_state == TU_CMD_CCU_GMEM ?
178 phys_dev->ccu_offset_gmem :
179 phys_dev->ccu_offset_bypass,
180 .gmem = ccu_state == TU_CMD_CCU_GMEM));
181 cmd_buffer->state.ccu_state = ccu_state;
182 }
183 }
184
185 static void
tu6_emit_zs(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs)186 tu6_emit_zs(struct tu_cmd_buffer *cmd,
187 const struct tu_subpass *subpass,
188 struct tu_cs *cs)
189 {
190 const uint32_t a = subpass->depth_stencil_attachment.attachment;
191 if (a == VK_ATTACHMENT_UNUSED) {
192 tu_cs_emit_regs(cs,
193 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE),
194 A6XX_RB_DEPTH_BUFFER_PITCH(0),
195 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
196 A6XX_RB_DEPTH_BUFFER_BASE(0),
197 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
198
199 tu_cs_emit_regs(cs,
200 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
201
202 tu_cs_emit_regs(cs,
203 A6XX_GRAS_LRZ_BUFFER_BASE(0),
204 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
205 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
206
207 tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
208
209 return;
210 }
211
212 const struct tu_image_view *iview = cmd->state.attachments[a];
213 const struct tu_render_pass_attachment *attachment =
214 &cmd->state.pass->attachments[a];
215 enum a6xx_depth_format fmt = tu6_pipe2depth(attachment->format);
216
217 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
218 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt).value);
219 tu_cs_image_ref(cs, iview, 0);
220 tu_cs_emit(cs, attachment->gmem_offset);
221
222 tu_cs_emit_regs(cs,
223 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
224
225 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE, 3);
226 tu_cs_image_flag_ref(cs, iview, 0);
227
228 tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_BUFFER_BASE(.bo = iview->image->bo,
229 .bo_offset = iview->image->bo_offset + iview->image->lrz_offset),
230 A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = iview->image->lrz_pitch),
231 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE());
232
233 if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
234 attachment->format == VK_FORMAT_S8_UINT) {
235
236 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 6);
237 tu_cs_emit(cs, A6XX_RB_STENCIL_INFO(.separate_stencil = true).value);
238 if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
239 tu_cs_image_stencil_ref(cs, iview, 0);
240 tu_cs_emit(cs, attachment->gmem_offset_stencil);
241 } else {
242 tu_cs_image_ref(cs, iview, 0);
243 tu_cs_emit(cs, attachment->gmem_offset);
244 }
245 } else {
246 tu_cs_emit_regs(cs,
247 A6XX_RB_STENCIL_INFO(0));
248 }
249 }
250
251 static void
tu6_emit_mrt(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs)252 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
253 const struct tu_subpass *subpass,
254 struct tu_cs *cs)
255 {
256 const struct tu_framebuffer *fb = cmd->state.framebuffer;
257
258 for (uint32_t i = 0; i < subpass->color_count; ++i) {
259 uint32_t a = subpass->color_attachments[i].attachment;
260 if (a == VK_ATTACHMENT_UNUSED)
261 continue;
262
263 const struct tu_image_view *iview = cmd->state.attachments[a];
264
265 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
266 tu_cs_emit(cs, iview->RB_MRT_BUF_INFO);
267 tu_cs_image_ref(cs, iview, 0);
268 tu_cs_emit(cs, cmd->state.pass->attachments[a].gmem_offset);
269
270 tu_cs_emit_regs(cs,
271 A6XX_SP_FS_MRT_REG(i, .dword = iview->SP_FS_MRT_REG));
272
273 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(i), 3);
274 tu_cs_image_flag_ref(cs, iview, 0);
275 }
276
277 tu_cs_emit_regs(cs,
278 A6XX_RB_SRGB_CNTL(.dword = subpass->srgb_cntl));
279 tu_cs_emit_regs(cs,
280 A6XX_SP_SRGB_CNTL(.dword = subpass->srgb_cntl));
281
282 unsigned layers = MAX2(fb->layers, util_logbase2(subpass->multiview_mask) + 1);
283 tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(layers - 1));
284
285 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SC_CNTL,
286 A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(2));
287
288 /* If there is a feedback loop, then the shader can read the previous value
289 * of a pixel being written out. It can also write some components and then
290 * read different components without a barrier in between. This is a
291 * problem in sysmem mode with UBWC, because the main buffer and flags
292 * buffer can get out-of-sync if only one is flushed. We fix this by
293 * setting the SINGLE_PRIM_MODE field to the same value that the blob does
294 * for advanced_blend in sysmem mode if a feedback loop is detected.
295 */
296 if (subpass->feedback) {
297 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
298 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SC_CNTL,
299 A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(2) |
300 A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(
301 FLUSH_PER_OVERLAP_AND_OVERWRITE));
302 tu_cond_exec_end(cs);
303 }
304 }
305
306 void
tu6_emit_msaa(struct tu_cs * cs,VkSampleCountFlagBits vk_samples,enum a5xx_line_mode line_mode)307 tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples,
308 enum a5xx_line_mode line_mode)
309 {
310 const enum a3xx_msaa_samples samples = tu_msaa_samples(vk_samples);
311 bool msaa_disable = (samples == MSAA_ONE) || (line_mode == BRESENHAM);
312
313 tu_cs_emit_regs(cs,
314 A6XX_SP_TP_RAS_MSAA_CNTL(samples),
315 A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
316 .msaa_disable = msaa_disable));
317
318 tu_cs_emit_regs(cs,
319 A6XX_GRAS_RAS_MSAA_CNTL(samples),
320 A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
321 .msaa_disable = msaa_disable));
322
323 tu_cs_emit_regs(cs,
324 A6XX_RB_RAS_MSAA_CNTL(samples),
325 A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
326 .msaa_disable = msaa_disable));
327
328 tu_cs_emit_regs(cs,
329 A6XX_RB_MSAA_CNTL(samples));
330 }
331
332 static void
tu6_emit_bin_size(struct tu_cs * cs,uint32_t bin_w,uint32_t bin_h,uint32_t flags)333 tu6_emit_bin_size(struct tu_cs *cs,
334 uint32_t bin_w, uint32_t bin_h, uint32_t flags)
335 {
336 tu_cs_emit_regs(cs,
337 A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
338 .binh = bin_h,
339 .dword = flags));
340
341 tu_cs_emit_regs(cs,
342 A6XX_RB_BIN_CONTROL(.binw = bin_w,
343 .binh = bin_h,
344 .dword = flags));
345
346 /* no flag for RB_BIN_CONTROL2... */
347 tu_cs_emit_regs(cs,
348 A6XX_RB_BIN_CONTROL2(.binw = bin_w,
349 .binh = bin_h));
350 }
351
352 static void
tu6_emit_render_cntl(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs,bool binning)353 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
354 const struct tu_subpass *subpass,
355 struct tu_cs *cs,
356 bool binning)
357 {
358 /* doesn't RB_RENDER_CNTL set differently for binning pass: */
359 bool no_track = !cmd->device->physical_device->info->a6xx.has_cp_reg_write;
360 uint32_t cntl = 0;
361 cntl |= A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(2);
362 if (binning) {
363 if (no_track)
364 return;
365 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
366 } else {
367 uint32_t mrts_ubwc_enable = 0;
368 for (uint32_t i = 0; i < subpass->color_count; ++i) {
369 uint32_t a = subpass->color_attachments[i].attachment;
370 if (a == VK_ATTACHMENT_UNUSED)
371 continue;
372
373 const struct tu_image_view *iview = cmd->state.attachments[a];
374 if (iview->ubwc_enabled)
375 mrts_ubwc_enable |= 1 << i;
376 }
377
378 cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
379
380 const uint32_t a = subpass->depth_stencil_attachment.attachment;
381 if (a != VK_ATTACHMENT_UNUSED) {
382 const struct tu_image_view *iview = cmd->state.attachments[a];
383 if (iview->ubwc_enabled)
384 cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
385 }
386
387 if (no_track) {
388 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CNTL, 1);
389 tu_cs_emit(cs, cntl);
390 return;
391 }
392
393 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
394 * in order to set it correctly for the different subpasses. However,
395 * that means the packets we're emitting also happen during binning. So
396 * we need to guard the write on !BINNING at CP execution time.
397 */
398 tu_cs_reserve(cs, 3 + 4);
399 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
400 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
401 CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
402 tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4));
403 }
404
405 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
406 tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
407 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
408 tu_cs_emit(cs, cntl);
409 }
410
411 static void
tu6_emit_blit_scissor(struct tu_cmd_buffer * cmd,struct tu_cs * cs,bool align)412 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
413 {
414 struct tu_physical_device *phys_dev = cmd->device->physical_device;
415 const VkRect2D *render_area = &cmd->state.render_area;
416
417 /* Avoid assertion fails with an empty render area at (0, 0) where the
418 * subtraction below wraps around. Empty render areas should be forced to
419 * the sysmem path by use_sysmem_rendering(). It's not even clear whether
420 * an empty scissor here works, and the blob seems to force sysmem too as
421 * it sets something wrong (non-empty) for the scissor.
422 */
423 if (render_area->extent.width == 0 ||
424 render_area->extent.height == 0)
425 return;
426
427 uint32_t x1 = render_area->offset.x;
428 uint32_t y1 = render_area->offset.y;
429 uint32_t x2 = x1 + render_area->extent.width - 1;
430 uint32_t y2 = y1 + render_area->extent.height - 1;
431
432 if (align) {
433 x1 = x1 & ~(phys_dev->info->gmem_align_w - 1);
434 y1 = y1 & ~(phys_dev->info->gmem_align_h - 1);
435 x2 = ALIGN_POT(x2 + 1, phys_dev->info->gmem_align_w) - 1;
436 y2 = ALIGN_POT(y2 + 1, phys_dev->info->gmem_align_h) - 1;
437 }
438
439 tu_cs_emit_regs(cs,
440 A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
441 A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
442 }
443
444 void
tu6_emit_window_scissor(struct tu_cs * cs,uint32_t x1,uint32_t y1,uint32_t x2,uint32_t y2)445 tu6_emit_window_scissor(struct tu_cs *cs,
446 uint32_t x1,
447 uint32_t y1,
448 uint32_t x2,
449 uint32_t y2)
450 {
451 tu_cs_emit_regs(cs,
452 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
453 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
454
455 tu_cs_emit_regs(cs,
456 A6XX_GRAS_2D_RESOLVE_CNTL_1(.x = x1, .y = y1),
457 A6XX_GRAS_2D_RESOLVE_CNTL_2(.x = x2, .y = y2));
458 }
459
460 void
tu6_emit_window_offset(struct tu_cs * cs,uint32_t x1,uint32_t y1)461 tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1)
462 {
463 tu_cs_emit_regs(cs,
464 A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
465
466 tu_cs_emit_regs(cs,
467 A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
468
469 tu_cs_emit_regs(cs,
470 A6XX_SP_WINDOW_OFFSET(.x = x1, .y = y1));
471
472 tu_cs_emit_regs(cs,
473 A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
474 }
475
476 void
tu6_apply_depth_bounds_workaround(struct tu_device * device,uint32_t * rb_depth_cntl)477 tu6_apply_depth_bounds_workaround(struct tu_device *device,
478 uint32_t *rb_depth_cntl)
479 {
480 return;
481 if (!device->physical_device->info->a6xx.depth_bounds_require_depth_test_quirk)
482 return;
483
484 /* On some GPUs it is necessary to enable z test for depth bounds test when
485 * UBWC is enabled. Otherwise, the GPU would hang. FUNC_ALWAYS is required to
486 * pass z test. Relevant tests:
487 * dEQP-VK.pipeline.extended_dynamic_state.two_draws_dynamic.depth_bounds_test_disable
488 * dEQP-VK.dynamic_state.ds_state.depth_bounds_1
489 */
490 *rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE |
491 A6XX_RB_DEPTH_CNTL_ZFUNC(FUNC_ALWAYS);
492 }
493
494 static void
tu_cs_emit_draw_state(struct tu_cs * cs,uint32_t id,struct tu_draw_state state)495 tu_cs_emit_draw_state(struct tu_cs *cs, uint32_t id, struct tu_draw_state state)
496 {
497 uint32_t enable_mask;
498 switch (id) {
499 case TU_DRAW_STATE_PROGRAM:
500 case TU_DRAW_STATE_VI:
501 case TU_DRAW_STATE_FS_CONST:
502 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
503 * when resources would actually be used in the binning shader.
504 * Presumably the overhead of prefetching the resources isn't
505 * worth it.
506 */
507 case TU_DRAW_STATE_DESC_SETS_LOAD:
508 enable_mask = CP_SET_DRAW_STATE__0_GMEM |
509 CP_SET_DRAW_STATE__0_SYSMEM;
510 break;
511 case TU_DRAW_STATE_PROGRAM_BINNING:
512 case TU_DRAW_STATE_VI_BINNING:
513 enable_mask = CP_SET_DRAW_STATE__0_BINNING;
514 break;
515 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM:
516 enable_mask = CP_SET_DRAW_STATE__0_GMEM;
517 break;
518 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM:
519 enable_mask = CP_SET_DRAW_STATE__0_SYSMEM;
520 break;
521 default:
522 enable_mask = CP_SET_DRAW_STATE__0_GMEM |
523 CP_SET_DRAW_STATE__0_SYSMEM |
524 CP_SET_DRAW_STATE__0_BINNING;
525 break;
526 }
527
528 STATIC_ASSERT(TU_DRAW_STATE_COUNT <= 32);
529
530 /* We need to reload the descriptors every time the descriptor sets
531 * change. However, the commands we send only depend on the pipeline
532 * because the whole point is to cache descriptors which are used by the
533 * pipeline. There's a problem here, in that the firmware has an
534 * "optimization" which skips executing groups that are set to the same
535 * value as the last draw. This means that if the descriptor sets change
536 * but not the pipeline, we'd try to re-execute the same buffer which
537 * the firmware would ignore and we wouldn't pre-load the new
538 * descriptors. Set the DIRTY bit to avoid this optimization
539 */
540 if (id == TU_DRAW_STATE_DESC_SETS_LOAD)
541 enable_mask |= CP_SET_DRAW_STATE__0_DIRTY;
542
543 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(state.size) |
544 enable_mask |
545 CP_SET_DRAW_STATE__0_GROUP_ID(id) |
546 COND(!state.size, CP_SET_DRAW_STATE__0_DISABLE));
547 tu_cs_emit_qw(cs, state.iova);
548 }
549
550 static bool
use_hw_binning(struct tu_cmd_buffer * cmd)551 use_hw_binning(struct tu_cmd_buffer *cmd)
552 {
553 const struct tu_framebuffer *fb = cmd->state.framebuffer;
554
555 /* XFB commands are emitted for BINNING || SYSMEM, which makes it incompatible
556 * with non-hw binning GMEM rendering. this is required because some of the
557 * XFB commands need to only be executed once
558 */
559 if (cmd->state.xfb_used)
560 return true;
561
562 if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
563 return false;
564
565 if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN))
566 return true;
567
568 return (fb->tile_count.width * fb->tile_count.height) > 2;
569 }
570
571 static bool
use_sysmem_rendering(struct tu_cmd_buffer * cmd)572 use_sysmem_rendering(struct tu_cmd_buffer *cmd)
573 {
574 if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_SYSMEM))
575 return true;
576
577 /* can't fit attachments into gmem */
578 if (!cmd->state.pass->gmem_pixels)
579 return true;
580
581 if (cmd->state.framebuffer->layers > 1)
582 return true;
583
584 /* Use sysmem for empty render areas */
585 if (cmd->state.render_area.extent.width == 0 ||
586 cmd->state.render_area.extent.height == 0)
587 return true;
588
589 if (cmd->state.has_tess)
590 return true;
591
592 if (cmd->state.disable_gmem)
593 return true;
594
595 return false;
596 }
597
598 static void
tu6_emit_tile_select(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t tx,uint32_t ty,uint32_t pipe,uint32_t slot)599 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
600 struct tu_cs *cs,
601 uint32_t tx, uint32_t ty, uint32_t pipe, uint32_t slot)
602 {
603 const struct tu_framebuffer *fb = cmd->state.framebuffer;
604
605 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
606 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
607
608 const uint32_t x1 = fb->tile0.width * tx;
609 const uint32_t y1 = fb->tile0.height * ty;
610 const uint32_t x2 = MIN2(x1 + fb->tile0.width - 1, MAX_VIEWPORT_SIZE - 1);
611 const uint32_t y2 = MIN2(y1 + fb->tile0.height - 1, MAX_VIEWPORT_SIZE - 1);
612 tu6_emit_window_scissor(cs, x1, y1, x2, y2);
613 tu6_emit_window_offset(cs, x1, y1);
614
615 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
616
617 if (use_hw_binning(cmd)) {
618 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
619
620 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
621 tu_cs_emit(cs, 0x0);
622
623 tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5_OFFSET, 4);
624 tu_cs_emit(cs, fb->pipe_sizes[pipe] |
625 CP_SET_BIN_DATA5_0_VSC_N(slot));
626 tu_cs_emit(cs, pipe * cmd->vsc_draw_strm_pitch);
627 tu_cs_emit(cs, pipe * 4);
628 tu_cs_emit(cs, pipe * cmd->vsc_prim_strm_pitch);
629
630 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
631 tu_cs_emit(cs, 0x0);
632
633 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
634 tu_cs_emit(cs, 0x0);
635 } else {
636 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
637 tu_cs_emit(cs, 0x1);
638
639 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
640 tu_cs_emit(cs, 0x0);
641 }
642 }
643
644 static void
tu6_emit_sysmem_resolve(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t layer_mask,uint32_t a,uint32_t gmem_a)645 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
646 struct tu_cs *cs,
647 uint32_t layer_mask,
648 uint32_t a,
649 uint32_t gmem_a)
650 {
651 const struct tu_framebuffer *fb = cmd->state.framebuffer;
652 const struct tu_image_view *dst = cmd->state.attachments[a];
653 const struct tu_image_view *src = cmd->state.attachments[gmem_a];
654
655 tu_resolve_sysmem(cmd, cs, src, dst, layer_mask, fb->layers, &cmd->state.render_area);
656 }
657
658 static void
tu6_emit_sysmem_resolves(struct tu_cmd_buffer * cmd,struct tu_cs * cs,const struct tu_subpass * subpass)659 tu6_emit_sysmem_resolves(struct tu_cmd_buffer *cmd,
660 struct tu_cs *cs,
661 const struct tu_subpass *subpass)
662 {
663 if (subpass->resolve_attachments) {
664 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
665 * Commands":
666 *
667 * End-of-subpass multisample resolves are treated as color
668 * attachment writes for the purposes of synchronization.
669 * This applies to resolve operations for both color and
670 * depth/stencil attachments. That is, they are considered to
671 * execute in the VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
672 * pipeline stage and their writes are synchronized with
673 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
674 * rendering within a subpass and any resolve operations at the end
675 * of the subpass occurs automatically, without need for explicit
676 * dependencies or pipeline barriers. However, if the resolve
677 * attachment is also used in a different subpass, an explicit
678 * dependency is needed.
679 *
680 * We use the CP_BLIT path for sysmem resolves, which is really a
681 * transfer command, so we have to manually flush similar to the gmem
682 * resolve case. However, a flush afterwards isn't needed because of the
683 * last sentence and the fact that we're in sysmem mode.
684 */
685 tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS);
686 if (subpass->resolve_depth_stencil)
687 tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS);
688
689 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE);
690
691 /* Wait for the flushes to land before using the 2D engine */
692 tu_cs_emit_wfi(cs);
693
694 for (unsigned i = 0; i < subpass->resolve_count; i++) {
695 uint32_t a = subpass->resolve_attachments[i].attachment;
696 if (a == VK_ATTACHMENT_UNUSED)
697 continue;
698
699 uint32_t gmem_a = tu_subpass_get_attachment_to_resolve(subpass, i);
700
701 tu6_emit_sysmem_resolve(cmd, cs, subpass->multiview_mask, a, gmem_a);
702 }
703 }
704 }
705
706 static void
tu6_emit_tile_store(struct tu_cmd_buffer * cmd,struct tu_cs * cs)707 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
708 {
709 const struct tu_render_pass *pass = cmd->state.pass;
710 const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
711
712 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
713 tu_cs_emit(cs, 0x0);
714
715 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
716 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
717
718 tu6_emit_blit_scissor(cmd, cs, true);
719
720 for (uint32_t a = 0; a < pass->attachment_count; ++a) {
721 if (pass->attachments[a].gmem_offset >= 0)
722 tu_store_gmem_attachment(cmd, cs, a, a);
723 }
724
725 if (subpass->resolve_attachments) {
726 for (unsigned i = 0; i < subpass->resolve_count; i++) {
727 uint32_t a = subpass->resolve_attachments[i].attachment;
728 if (a != VK_ATTACHMENT_UNUSED) {
729 uint32_t gmem_a = tu_subpass_get_attachment_to_resolve(subpass, i);
730 tu_store_gmem_attachment(cmd, cs, a, gmem_a);
731 }
732 }
733 }
734 }
735
736 void
tu_disable_draw_states(struct tu_cmd_buffer * cmd,struct tu_cs * cs)737 tu_disable_draw_states(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
738 {
739 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
740 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
741 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
742 CP_SET_DRAW_STATE__0_GROUP_ID(0));
743 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
744 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
745
746 cmd->state.dirty |= TU_CMD_DIRTY_DRAW_STATE;
747 }
748
749 static void
tu6_init_hw(struct tu_cmd_buffer * cmd,struct tu_cs * cs)750 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
751 {
752 struct tu_device *dev = cmd->device;
753 const struct tu_physical_device *phys_dev = dev->physical_device;
754
755 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE);
756
757 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
758 .vs_state = true,
759 .hs_state = true,
760 .ds_state = true,
761 .gs_state = true,
762 .fs_state = true,
763 .cs_state = true,
764 .gfx_ibo = true,
765 .cs_ibo = true,
766 .gfx_shared_const = true,
767 .cs_shared_const = true,
768 .gfx_bindless = 0x1f,
769 .cs_bindless = 0x1f));
770
771 tu_cs_emit_wfi(cs);
772
773 cmd->state.cache.pending_flush_bits &=
774 ~(TU_CMD_FLAG_WAIT_FOR_IDLE | TU_CMD_FLAG_CACHE_INVALIDATE);
775
776 tu_cs_emit_regs(cs,
777 A6XX_RB_CCU_CNTL(.color_offset = phys_dev->ccu_offset_bypass));
778 cmd->state.ccu_state = TU_CMD_CCU_SYSMEM;
779 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
780 tu_cs_emit_write_reg(cs, REG_A6XX_SP_FLOAT_CNTL, 0);
781 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
782 tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
783 tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
784 tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_DBG_ECO_CNTL,
785 phys_dev->info->a6xx.magic.TPL1_DBG_ECO_CNTL);
786 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
787 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
788
789 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
790 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_DBG_ECO_CNTL, 0x880);
791 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
792 tu_cs_emit_write_reg(cs, REG_A6XX_SP_CHICKEN_BITS, 0x00000410);
793 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
794 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
795 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_SHARED_CONSTS, 0);
796 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
797 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
798 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
799 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
800 tu_cs_emit_write_reg(cs, REG_A6XX_SP_MODE_CONTROL,
801 A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
802
803 /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
804 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
805 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
806 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
807
808 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
809
810 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
811 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
812 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
813 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
814 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
815 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
816 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
817 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
818
819 tu_cs_emit_regs(cs, A6XX_VPC_POINT_COORD_INVERT(false));
820 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
821
822 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
823
824 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
825
826 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 0);
827 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
828 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
829 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
830 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
831 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
832 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_MODE_CNTL,
833 0x000000a0 |
834 A6XX_SP_TP_MODE_CNTL_ISAMMODE(ISAMMODE_GL));
835 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
836
837 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
838
839 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
840
841 tu_cs_emit_regs(cs, A6XX_RB_ALPHA_CONTROL()); /* always disable alpha test */
842 tu_cs_emit_regs(cs, A6XX_RB_DITHER_CNTL()); /* always disable dithering */
843
844 tu_disable_draw_states(cmd, cs);
845
846 tu_cs_emit_regs(cs,
847 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo = &dev->global_bo,
848 .bo_offset = gb_offset(bcolor_builtin)));
849 tu_cs_emit_regs(cs,
850 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo = &dev->global_bo,
851 .bo_offset = gb_offset(bcolor_builtin)));
852
853 /* VSC buffers:
854 * use vsc pitches from the largest values used so far with this device
855 * if there hasn't been overflow, there will already be a scratch bo
856 * allocated for these sizes
857 *
858 * if overflow is detected, the stream size is increased by 2x
859 */
860 mtx_lock(&dev->mutex);
861
862 struct tu6_global *global = dev->global_bo.map;
863
864 uint32_t vsc_draw_overflow = global->vsc_draw_overflow;
865 uint32_t vsc_prim_overflow = global->vsc_prim_overflow;
866
867 if (vsc_draw_overflow >= dev->vsc_draw_strm_pitch)
868 dev->vsc_draw_strm_pitch = (dev->vsc_draw_strm_pitch - VSC_PAD) * 2 + VSC_PAD;
869
870 if (vsc_prim_overflow >= dev->vsc_prim_strm_pitch)
871 dev->vsc_prim_strm_pitch = (dev->vsc_prim_strm_pitch - VSC_PAD) * 2 + VSC_PAD;
872
873 cmd->vsc_prim_strm_pitch = dev->vsc_prim_strm_pitch;
874 cmd->vsc_draw_strm_pitch = dev->vsc_draw_strm_pitch;
875
876 mtx_unlock(&dev->mutex);
877
878 struct tu_bo *vsc_bo;
879 uint32_t size0 = cmd->vsc_prim_strm_pitch * MAX_VSC_PIPES +
880 cmd->vsc_draw_strm_pitch * MAX_VSC_PIPES;
881
882 tu_get_scratch_bo(dev, size0 + MAX_VSC_PIPES * 4, &vsc_bo);
883
884 tu_cs_emit_regs(cs,
885 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo = vsc_bo, .bo_offset = size0));
886 tu_cs_emit_regs(cs,
887 A6XX_VSC_PRIM_STRM_ADDRESS(.bo = vsc_bo));
888 tu_cs_emit_regs(cs,
889 A6XX_VSC_DRAW_STRM_ADDRESS(.bo = vsc_bo,
890 .bo_offset = cmd->vsc_prim_strm_pitch * MAX_VSC_PIPES));
891
892 tu_cs_sanity_check(cs);
893 }
894
895 static void
update_vsc_pipe(struct tu_cmd_buffer * cmd,struct tu_cs * cs)896 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
897 {
898 const struct tu_framebuffer *fb = cmd->state.framebuffer;
899
900 tu_cs_emit_regs(cs,
901 A6XX_VSC_BIN_SIZE(.width = fb->tile0.width,
902 .height = fb->tile0.height));
903
904 tu_cs_emit_regs(cs,
905 A6XX_VSC_BIN_COUNT(.nx = fb->tile_count.width,
906 .ny = fb->tile_count.height));
907
908 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
909 tu_cs_emit_array(cs, fb->pipe_config, 32);
910
911 tu_cs_emit_regs(cs,
912 A6XX_VSC_PRIM_STRM_PITCH(cmd->vsc_prim_strm_pitch),
913 A6XX_VSC_PRIM_STRM_LIMIT(cmd->vsc_prim_strm_pitch - VSC_PAD));
914
915 tu_cs_emit_regs(cs,
916 A6XX_VSC_DRAW_STRM_PITCH(cmd->vsc_draw_strm_pitch),
917 A6XX_VSC_DRAW_STRM_LIMIT(cmd->vsc_draw_strm_pitch - VSC_PAD));
918 }
919
920 static void
emit_vsc_overflow_test(struct tu_cmd_buffer * cmd,struct tu_cs * cs)921 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
922 {
923 const struct tu_framebuffer *fb = cmd->state.framebuffer;
924 const uint32_t used_pipe_count =
925 fb->pipe_count.width * fb->pipe_count.height;
926
927 for (int i = 0; i < used_pipe_count; i++) {
928 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
929 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
930 CP_COND_WRITE5_0_WRITE_MEMORY);
931 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
932 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
933 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_draw_strm_pitch - VSC_PAD));
934 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
935 tu_cs_emit_qw(cs, global_iova(cmd, vsc_draw_overflow));
936 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_draw_strm_pitch));
937
938 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
939 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
940 CP_COND_WRITE5_0_WRITE_MEMORY);
941 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
942 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
943 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_prim_strm_pitch - VSC_PAD));
944 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
945 tu_cs_emit_qw(cs, global_iova(cmd, vsc_prim_overflow));
946 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_prim_strm_pitch));
947 }
948
949 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
950 }
951
952 static void
tu6_emit_binning_pass(struct tu_cmd_buffer * cmd,struct tu_cs * cs)953 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
954 {
955 struct tu_physical_device *phys_dev = cmd->device->physical_device;
956 const struct tu_framebuffer *fb = cmd->state.framebuffer;
957
958 tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
959
960 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
961 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
962
963 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
964 tu_cs_emit(cs, 0x1);
965
966 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
967 tu_cs_emit(cs, 0x1);
968
969 tu_cs_emit_wfi(cs);
970
971 tu_cs_emit_regs(cs,
972 A6XX_VFD_MODE_CNTL(.render_mode = BINNING_PASS));
973
974 update_vsc_pipe(cmd, cs);
975
976 tu_cs_emit_regs(cs,
977 A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
978
979 tu_cs_emit_regs(cs,
980 A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
981
982 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
983 tu_cs_emit(cs, UNK_2C);
984
985 tu_cs_emit_regs(cs,
986 A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
987
988 tu_cs_emit_regs(cs,
989 A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
990
991 trace_start_binning_ib(&cmd->trace, cs);
992
993 /* emit IB to binning drawcmds: */
994 tu_cs_emit_call(cs, &cmd->draw_cs);
995
996 trace_end_binning_ib(&cmd->trace, cs);
997
998 /* switching from binning pass to GMEM pass will cause a switch from
999 * PROGRAM_BINNING to PROGRAM, which invalidates const state (XS_CONST states)
1000 * so make sure these states are re-emitted
1001 * (eventually these states shouldn't exist at all with shader prologue)
1002 * only VS and GS are invalidated, as FS isn't emitted in binning pass,
1003 * and we don't use HW binning when tesselation is used
1004 */
1005 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1006 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1007 CP_SET_DRAW_STATE__0_DISABLE |
1008 CP_SET_DRAW_STATE__0_GROUP_ID(TU_DRAW_STATE_SHADER_GEOM_CONST));
1009 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1010 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1011
1012 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1013 tu_cs_emit(cs, UNK_2D);
1014
1015 /* This flush is probably required because the VSC, which produces the
1016 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1017 * visibility stream (without caching) to do draw skipping. The
1018 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1019 * submitted are finished before reading the VSC regs (in
1020 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1021 * part of draws).
1022 */
1023 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS);
1024
1025 tu_cs_emit_wfi(cs);
1026
1027 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1028
1029 emit_vsc_overflow_test(cmd, cs);
1030
1031 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1032 tu_cs_emit(cs, 0x0);
1033
1034 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1035 tu_cs_emit(cs, 0x0);
1036 }
1037
1038 static struct tu_draw_state
tu_emit_input_attachments(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,bool gmem)1039 tu_emit_input_attachments(struct tu_cmd_buffer *cmd,
1040 const struct tu_subpass *subpass,
1041 bool gmem)
1042 {
1043 /* note: we can probably emit input attachments just once for the whole
1044 * renderpass, this would avoid emitting both sysmem/gmem versions
1045 *
1046 * emit two texture descriptors for each input, as a workaround for
1047 * d24s8/d32s8, which can be sampled as both float (depth) and integer (stencil)
1048 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1049 * in the pair
1050 * TODO: a smarter workaround
1051 */
1052
1053 if (!subpass->input_count)
1054 return (struct tu_draw_state) {};
1055
1056 struct tu_cs_memory texture;
1057 VkResult result = tu_cs_alloc(&cmd->sub_cs, subpass->input_count * 2,
1058 A6XX_TEX_CONST_DWORDS, &texture);
1059 if (result != VK_SUCCESS) {
1060 cmd->record_result = result;
1061 return (struct tu_draw_state) {};
1062 }
1063
1064 for (unsigned i = 0; i < subpass->input_count * 2; i++) {
1065 uint32_t a = subpass->input_attachments[i / 2].attachment;
1066 if (a == VK_ATTACHMENT_UNUSED)
1067 continue;
1068
1069 const struct tu_image_view *iview = cmd->state.attachments[a];
1070 const struct tu_render_pass_attachment *att =
1071 &cmd->state.pass->attachments[a];
1072 uint32_t *dst = &texture.map[A6XX_TEX_CONST_DWORDS * i];
1073 uint32_t gmem_offset = att->gmem_offset;
1074 uint32_t cpp = att->cpp;
1075
1076 memcpy(dst, iview->descriptor, A6XX_TEX_CONST_DWORDS * 4);
1077
1078 if (i % 2 == 1 && att->format == VK_FORMAT_D24_UNORM_S8_UINT) {
1079 /* note this works because spec says fb and input attachments
1080 * must use identity swizzle
1081 */
1082 dst[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK |
1083 A6XX_TEX_CONST_0_SWIZ_X__MASK | A6XX_TEX_CONST_0_SWIZ_Y__MASK |
1084 A6XX_TEX_CONST_0_SWIZ_Z__MASK | A6XX_TEX_CONST_0_SWIZ_W__MASK);
1085 if (!cmd->device->physical_device->info->a6xx.has_z24uint_s8uint) {
1086 dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_8_8_8_8_UINT) |
1087 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_W) |
1088 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO) |
1089 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO) |
1090 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE);
1091 } else {
1092 dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_Z24_UINT_S8_UINT) |
1093 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y) |
1094 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO) |
1095 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO) |
1096 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE);
1097 }
1098 }
1099
1100 if (i % 2 == 1 && att->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
1101 dst[0] &= ~A6XX_TEX_CONST_0_FMT__MASK;
1102 dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_8_UINT);
1103 dst[2] &= ~(A6XX_TEX_CONST_2_PITCHALIGN__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
1104 dst[2] |= A6XX_TEX_CONST_2_PITCH(iview->stencil_PITCH << 6);
1105 dst[3] = 0;
1106 dst[4] = iview->stencil_base_addr;
1107 dst[5] = (dst[5] & 0xffff) | iview->stencil_base_addr >> 32;
1108
1109 cpp = att->samples;
1110 gmem_offset = att->gmem_offset_stencil;
1111 }
1112
1113 if (!gmem || !subpass->input_attachments[i / 2].patch_input_gmem)
1114 continue;
1115
1116 /* patched for gmem */
1117 dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
1118 dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
1119 dst[2] =
1120 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
1121 A6XX_TEX_CONST_2_PITCH(cmd->state.framebuffer->tile0.width * cpp);
1122 dst[3] = 0;
1123 dst[4] = cmd->device->physical_device->gmem_base + gmem_offset;
1124 dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
1125 for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
1126 dst[i] = 0;
1127 }
1128
1129 struct tu_cs cs;
1130 struct tu_draw_state ds = tu_cs_draw_state(&cmd->sub_cs, &cs, 9);
1131
1132 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 3);
1133 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1134 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1135 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1136 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX) |
1137 CP_LOAD_STATE6_0_NUM_UNIT(subpass->input_count * 2));
1138 tu_cs_emit_qw(&cs, texture.iova);
1139
1140 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
1141
1142 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_COUNT(subpass->input_count * 2));
1143
1144 assert(cs.cur == cs.end); /* validate draw state size */
1145
1146 return ds;
1147 }
1148
1149 static void
tu_set_input_attachments(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass)1150 tu_set_input_attachments(struct tu_cmd_buffer *cmd, const struct tu_subpass *subpass)
1151 {
1152 struct tu_cs *cs = &cmd->draw_cs;
1153
1154 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 6);
1155 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM,
1156 tu_emit_input_attachments(cmd, subpass, true));
1157 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM,
1158 tu_emit_input_attachments(cmd, subpass, false));
1159 }
1160
1161 static void
tu_emit_renderpass_begin(struct tu_cmd_buffer * cmd,const VkRenderPassBeginInfo * info)1162 tu_emit_renderpass_begin(struct tu_cmd_buffer *cmd,
1163 const VkRenderPassBeginInfo *info)
1164 {
1165 struct tu_cs *cs = &cmd->draw_cs;
1166
1167 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
1168
1169 tu6_emit_blit_scissor(cmd, cs, true);
1170
1171 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1172 tu_load_gmem_attachment(cmd, cs, i, false);
1173
1174 tu6_emit_blit_scissor(cmd, cs, false);
1175
1176 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1177 tu_clear_gmem_attachment(cmd, cs, i, info);
1178
1179 tu_cond_exec_end(cs);
1180
1181 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
1182
1183 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1184 tu_clear_sysmem_attachment(cmd, cs, i, info);
1185
1186 tu_cond_exec_end(cs);
1187 }
1188
1189 static void
tu6_sysmem_render_begin(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1190 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1191 {
1192 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1193
1194 assert(fb->width > 0 && fb->height > 0);
1195 tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
1196 tu6_emit_window_offset(cs, 0, 0);
1197
1198 tu6_emit_bin_size(cs, 0, 0,
1199 A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(BUFFERS_IN_SYSMEM));
1200
1201 tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
1202
1203 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1204 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1205
1206 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1207 tu_cs_emit(cs, 0x0);
1208
1209 tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_SYSMEM);
1210
1211 /* enable stream-out, with sysmem there is only one pass: */
1212 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
1213
1214 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1215 tu_cs_emit(cs, 0x1);
1216
1217 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1218 tu_cs_emit(cs, 0x0);
1219
1220 tu_cs_sanity_check(cs);
1221 }
1222
1223 static void
tu6_sysmem_render_end(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1224 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1225 {
1226 /* Do any resolves of the last subpass. These are handled in the
1227 * tile_store_cs in the gmem path.
1228 */
1229 tu6_emit_sysmem_resolves(cmd, cs, cmd->state.subpass);
1230
1231 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1232
1233 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1234 tu_cs_emit(cs, 0x0);
1235
1236 tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
1237
1238 tu_cs_sanity_check(cs);
1239 }
1240
1241 static void
tu6_tile_render_begin(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1242 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1243 {
1244 struct tu_physical_device *phys_dev = cmd->device->physical_device;
1245
1246 tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
1247
1248 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1249 tu_cs_emit(cs, 0x0);
1250
1251 tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_GMEM);
1252
1253 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1254 if (use_hw_binning(cmd)) {
1255 /* enable stream-out during binning pass: */
1256 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
1257
1258 tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height,
1259 A6XX_RB_BIN_CONTROL_RENDER_MODE(BINNING_PASS) |
1260 A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(0x6));
1261
1262 tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
1263
1264 tu6_emit_binning_pass(cmd, cs);
1265
1266 /* and disable stream-out for draw pass: */
1267 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
1268
1269 tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height,
1270 A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS |
1271 A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(0x6));
1272
1273 tu_cs_emit_regs(cs,
1274 A6XX_VFD_MODE_CNTL(0));
1275
1276 tu_cs_emit_regs(cs,
1277 A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
1278
1279 tu_cs_emit_regs(cs,
1280 A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
1281
1282 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1283 tu_cs_emit(cs, 0x1);
1284 } else {
1285 /* no binning pass, so enable stream-out for draw pass:: */
1286 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
1287
1288 tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height,
1289 A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(0x6));
1290 }
1291
1292 tu_cs_sanity_check(cs);
1293 }
1294
1295 static void
tu6_render_tile(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1296 tu6_render_tile(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1297 {
1298 tu_cs_emit_call(cs, &cmd->draw_cs);
1299
1300 if (use_hw_binning(cmd)) {
1301 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1302 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1303 }
1304
1305 tu_cs_emit_call(cs, &cmd->tile_store_cs);
1306
1307 if (!u_trace_iterator_equal(cmd->trace_renderpass_start, cmd->trace_renderpass_end)) {
1308 tu_cs_emit_wfi(cs);
1309 tu_cs_emit_pkt7(&cmd->cs, CP_WAIT_FOR_ME, 0);
1310 u_trace_clone_append(cmd->trace_renderpass_start,
1311 cmd->trace_renderpass_end,
1312 &cmd->trace,
1313 cs, tu_copy_timestamp_buffer);
1314 }
1315
1316 tu_cs_sanity_check(cs);
1317 }
1318
1319 static void
tu6_tile_render_end(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1320 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1321 {
1322 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1323
1324 tu_cs_emit_regs(cs,
1325 A6XX_GRAS_LRZ_CNTL(0));
1326
1327 tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
1328
1329 tu6_emit_event_write(cmd, cs, PC_CCU_RESOLVE_TS);
1330
1331 tu_cs_sanity_check(cs);
1332 }
1333
1334 static void
tu_cmd_render_tiles(struct tu_cmd_buffer * cmd)1335 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1336 {
1337 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1338
1339 tu6_tile_render_begin(cmd, &cmd->cs);
1340
1341 uint32_t pipe = 0;
1342 for (uint32_t py = 0; py < fb->pipe_count.height; py++) {
1343 for (uint32_t px = 0; px < fb->pipe_count.width; px++, pipe++) {
1344 uint32_t tx1 = px * fb->pipe0.width;
1345 uint32_t ty1 = py * fb->pipe0.height;
1346 uint32_t tx2 = MIN2(tx1 + fb->pipe0.width, fb->tile_count.width);
1347 uint32_t ty2 = MIN2(ty1 + fb->pipe0.height, fb->tile_count.height);
1348 uint32_t slot = 0;
1349 for (uint32_t ty = ty1; ty < ty2; ty++) {
1350 for (uint32_t tx = tx1; tx < tx2; tx++, slot++) {
1351 tu6_emit_tile_select(cmd, &cmd->cs, tx, ty, pipe, slot);
1352
1353 trace_start_draw_ib_gmem(&cmd->trace, &cmd->cs);
1354 tu6_render_tile(cmd, &cmd->cs);
1355 trace_end_draw_ib_gmem(&cmd->trace, &cmd->cs);
1356 }
1357 }
1358 }
1359 }
1360
1361 tu6_tile_render_end(cmd, &cmd->cs);
1362
1363 trace_end_render_pass(&cmd->trace, &cmd->cs, fb);
1364
1365 if (!u_trace_iterator_equal(cmd->trace_renderpass_start, cmd->trace_renderpass_end))
1366 u_trace_disable_event_range(cmd->trace_renderpass_start,
1367 cmd->trace_renderpass_end);
1368 }
1369
1370 static void
tu_cmd_render_sysmem(struct tu_cmd_buffer * cmd)1371 tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd)
1372 {
1373 tu6_sysmem_render_begin(cmd, &cmd->cs);
1374
1375 trace_start_draw_ib_sysmem(&cmd->trace, &cmd->cs);
1376
1377 tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
1378
1379 trace_end_draw_ib_sysmem(&cmd->trace, &cmd->cs);
1380
1381 tu6_sysmem_render_end(cmd, &cmd->cs);
1382
1383 trace_end_render_pass(&cmd->trace, &cmd->cs, cmd->state.framebuffer);
1384 }
1385
1386 static VkResult
tu_create_cmd_buffer(struct tu_device * device,struct tu_cmd_pool * pool,VkCommandBufferLevel level,VkCommandBuffer * pCommandBuffer)1387 tu_create_cmd_buffer(struct tu_device *device,
1388 struct tu_cmd_pool *pool,
1389 VkCommandBufferLevel level,
1390 VkCommandBuffer *pCommandBuffer)
1391 {
1392 struct tu_cmd_buffer *cmd_buffer;
1393
1394 cmd_buffer = vk_zalloc2(&device->vk.alloc, NULL, sizeof(*cmd_buffer), 8,
1395 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1396
1397 if (cmd_buffer == NULL)
1398 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
1399
1400 VkResult result = vk_command_buffer_init(&cmd_buffer->vk, &device->vk);
1401 if (result != VK_SUCCESS) {
1402 vk_free2(&device->vk.alloc, NULL, cmd_buffer);
1403 return result;
1404 }
1405
1406 cmd_buffer->device = device;
1407 cmd_buffer->pool = pool;
1408 cmd_buffer->level = level;
1409
1410 if (pool) {
1411 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1412 cmd_buffer->queue_family_index = pool->queue_family_index;
1413
1414 } else {
1415 /* Init the pool_link so we can safely call list_del when we destroy
1416 * the command buffer
1417 */
1418 list_inithead(&cmd_buffer->pool_link);
1419 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1420 }
1421
1422 u_trace_init(&cmd_buffer->trace, &device->trace_context);
1423
1424 tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096);
1425 tu_cs_init(&cmd_buffer->draw_cs, device, TU_CS_MODE_GROW, 4096);
1426 tu_cs_init(&cmd_buffer->tile_store_cs, device, TU_CS_MODE_GROW, 2048);
1427 tu_cs_init(&cmd_buffer->draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096);
1428 tu_cs_init(&cmd_buffer->sub_cs, device, TU_CS_MODE_SUB_STREAM, 2048);
1429
1430 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1431
1432 return VK_SUCCESS;
1433 }
1434
1435 static void
tu_cmd_buffer_destroy(struct tu_cmd_buffer * cmd_buffer)1436 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1437 {
1438 list_del(&cmd_buffer->pool_link);
1439
1440 tu_cs_finish(&cmd_buffer->cs);
1441 tu_cs_finish(&cmd_buffer->draw_cs);
1442 tu_cs_finish(&cmd_buffer->tile_store_cs);
1443 tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
1444 tu_cs_finish(&cmd_buffer->sub_cs);
1445
1446 u_trace_fini(&cmd_buffer->trace);
1447
1448 vk_command_buffer_finish(&cmd_buffer->vk);
1449 vk_free2(&cmd_buffer->device->vk.alloc, &cmd_buffer->pool->alloc,
1450 cmd_buffer);
1451 }
1452
1453 static VkResult
tu_reset_cmd_buffer(struct tu_cmd_buffer * cmd_buffer)1454 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1455 {
1456 vk_command_buffer_reset(&cmd_buffer->vk);
1457
1458 cmd_buffer->record_result = VK_SUCCESS;
1459
1460 tu_cs_reset(&cmd_buffer->cs);
1461 tu_cs_reset(&cmd_buffer->draw_cs);
1462 tu_cs_reset(&cmd_buffer->tile_store_cs);
1463 tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
1464 tu_cs_reset(&cmd_buffer->sub_cs);
1465
1466 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
1467 memset(&cmd_buffer->descriptors[i].sets, 0, sizeof(cmd_buffer->descriptors[i].sets));
1468 memset(&cmd_buffer->descriptors[i].push_set, 0, sizeof(cmd_buffer->descriptors[i].push_set));
1469 cmd_buffer->descriptors[i].push_set.base.type = VK_OBJECT_TYPE_DESCRIPTOR_SET;
1470 }
1471
1472 u_trace_fini(&cmd_buffer->trace);
1473 u_trace_init(&cmd_buffer->trace, &cmd_buffer->device->trace_context);
1474
1475 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1476
1477 return cmd_buffer->record_result;
1478 }
1479
1480 VKAPI_ATTR VkResult VKAPI_CALL
tu_AllocateCommandBuffers(VkDevice _device,const VkCommandBufferAllocateInfo * pAllocateInfo,VkCommandBuffer * pCommandBuffers)1481 tu_AllocateCommandBuffers(VkDevice _device,
1482 const VkCommandBufferAllocateInfo *pAllocateInfo,
1483 VkCommandBuffer *pCommandBuffers)
1484 {
1485 TU_FROM_HANDLE(tu_device, device, _device);
1486 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1487
1488 VkResult result = VK_SUCCESS;
1489 uint32_t i;
1490
1491 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1492
1493 if (!list_is_empty(&pool->free_cmd_buffers)) {
1494 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1495 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1496
1497 list_del(&cmd_buffer->pool_link);
1498 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1499
1500 result = tu_reset_cmd_buffer(cmd_buffer);
1501 cmd_buffer->level = pAllocateInfo->level;
1502 vk_command_buffer_finish(&cmd_buffer->vk);
1503 VkResult init_result =
1504 vk_command_buffer_init(&cmd_buffer->vk, &device->vk);
1505 if (init_result != VK_SUCCESS)
1506 result = init_result;
1507
1508 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1509 } else {
1510 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1511 &pCommandBuffers[i]);
1512 }
1513 if (result != VK_SUCCESS)
1514 break;
1515 }
1516
1517 if (result != VK_SUCCESS) {
1518 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1519 pCommandBuffers);
1520
1521 /* From the Vulkan 1.0.66 spec:
1522 *
1523 * "vkAllocateCommandBuffers can be used to create multiple
1524 * command buffers. If the creation of any of those command
1525 * buffers fails, the implementation must destroy all
1526 * successfully created command buffer objects from this
1527 * command, set all entries of the pCommandBuffers array to
1528 * NULL and return the error."
1529 */
1530 memset(pCommandBuffers, 0,
1531 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1532 }
1533
1534 return result;
1535 }
1536
1537 VKAPI_ATTR void VKAPI_CALL
tu_FreeCommandBuffers(VkDevice device,VkCommandPool commandPool,uint32_t commandBufferCount,const VkCommandBuffer * pCommandBuffers)1538 tu_FreeCommandBuffers(VkDevice device,
1539 VkCommandPool commandPool,
1540 uint32_t commandBufferCount,
1541 const VkCommandBuffer *pCommandBuffers)
1542 {
1543 for (uint32_t i = 0; i < commandBufferCount; i++) {
1544 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1545
1546 if (cmd_buffer) {
1547 if (cmd_buffer->pool) {
1548 list_del(&cmd_buffer->pool_link);
1549 list_addtail(&cmd_buffer->pool_link,
1550 &cmd_buffer->pool->free_cmd_buffers);
1551 } else
1552 tu_cmd_buffer_destroy(cmd_buffer);
1553 }
1554 }
1555 }
1556
1557 VKAPI_ATTR VkResult VKAPI_CALL
tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,VkCommandBufferResetFlags flags)1558 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1559 VkCommandBufferResetFlags flags)
1560 {
1561 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1562 return tu_reset_cmd_buffer(cmd_buffer);
1563 }
1564
1565 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1566 * invalidations.
1567 */
1568 static void
tu_cache_init(struct tu_cache_state * cache)1569 tu_cache_init(struct tu_cache_state *cache)
1570 {
1571 cache->flush_bits = 0;
1572 cache->pending_flush_bits = TU_CMD_FLAG_ALL_INVALIDATE;
1573 }
1574
1575 VKAPI_ATTR VkResult VKAPI_CALL
tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,const VkCommandBufferBeginInfo * pBeginInfo)1576 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1577 const VkCommandBufferBeginInfo *pBeginInfo)
1578 {
1579 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1580 VkResult result = VK_SUCCESS;
1581
1582 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1583 /* If the command buffer has already been resetted with
1584 * vkResetCommandBuffer, no need to do it again.
1585 */
1586 result = tu_reset_cmd_buffer(cmd_buffer);
1587 if (result != VK_SUCCESS)
1588 return result;
1589 }
1590
1591 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1592 cmd_buffer->state.index_size = 0xff; /* dirty restart index */
1593 cmd_buffer->state.line_mode = RECTANGULAR;
1594
1595 tu_cache_init(&cmd_buffer->state.cache);
1596 tu_cache_init(&cmd_buffer->state.renderpass_cache);
1597 cmd_buffer->usage_flags = pBeginInfo->flags;
1598
1599 tu_cs_begin(&cmd_buffer->cs);
1600 tu_cs_begin(&cmd_buffer->draw_cs);
1601 tu_cs_begin(&cmd_buffer->tile_store_cs);
1602 tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
1603
1604 /* setup initial configuration into command buffer */
1605 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1606 switch (cmd_buffer->queue_family_index) {
1607 case TU_QUEUE_GENERAL:
1608 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1609 break;
1610 default:
1611 break;
1612 }
1613 } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
1614 assert(pBeginInfo->pInheritanceInfo);
1615
1616 vk_foreach_struct(ext, pBeginInfo->pInheritanceInfo) {
1617 switch (ext->sType) {
1618 case VK_STRUCTURE_TYPE_COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT: {
1619 const VkCommandBufferInheritanceConditionalRenderingInfoEXT *cond_rend = (void *) ext;
1620 cmd_buffer->state.predication_active = cond_rend->conditionalRenderingEnable;
1621 break;
1622 default:
1623 break;
1624 }
1625 }
1626 }
1627
1628 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1629 cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1630 cmd_buffer->state.subpass =
1631 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1632 } else {
1633 /* When executing in the middle of another command buffer, the CCU
1634 * state is unknown.
1635 */
1636 cmd_buffer->state.ccu_state = TU_CMD_CCU_UNKNOWN;
1637 }
1638 }
1639
1640 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1641
1642 return VK_SUCCESS;
1643 }
1644
1645 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,uint32_t firstBinding,uint32_t bindingCount,const VkBuffer * pBuffers,const VkDeviceSize * pOffsets)1646 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1647 uint32_t firstBinding,
1648 uint32_t bindingCount,
1649 const VkBuffer *pBuffers,
1650 const VkDeviceSize *pOffsets)
1651 {
1652 tu_CmdBindVertexBuffers2EXT(commandBuffer, firstBinding, bindingCount,
1653 pBuffers, pOffsets, NULL, NULL);
1654 }
1655
1656 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindVertexBuffers2EXT(VkCommandBuffer commandBuffer,uint32_t firstBinding,uint32_t bindingCount,const VkBuffer * pBuffers,const VkDeviceSize * pOffsets,const VkDeviceSize * pSizes,const VkDeviceSize * pStrides)1657 tu_CmdBindVertexBuffers2EXT(VkCommandBuffer commandBuffer,
1658 uint32_t firstBinding,
1659 uint32_t bindingCount,
1660 const VkBuffer* pBuffers,
1661 const VkDeviceSize* pOffsets,
1662 const VkDeviceSize* pSizes,
1663 const VkDeviceSize* pStrides)
1664 {
1665 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1666 struct tu_cs cs;
1667 /* TODO: track a "max_vb" value for the cmdbuf to save a bit of memory */
1668 cmd->state.vertex_buffers.iova = tu_cs_draw_state(&cmd->sub_cs, &cs, 4 * MAX_VBS).iova;
1669
1670 for (uint32_t i = 0; i < bindingCount; i++) {
1671 if (pBuffers[i] == VK_NULL_HANDLE) {
1672 cmd->state.vb[firstBinding + i].base = 0;
1673 cmd->state.vb[firstBinding + i].size = 0;
1674 } else {
1675 struct tu_buffer *buf = tu_buffer_from_handle(pBuffers[i]);
1676 cmd->state.vb[firstBinding + i].base = tu_buffer_iova(buf) + pOffsets[i];
1677 cmd->state.vb[firstBinding + i].size = pSizes ? pSizes[i] : (buf->size - pOffsets[i]);
1678 }
1679
1680 if (pStrides)
1681 cmd->state.vb[firstBinding + i].stride = pStrides[i];
1682 }
1683
1684 for (uint32_t i = 0; i < MAX_VBS; i++) {
1685 tu_cs_emit_regs(&cs,
1686 A6XX_VFD_FETCH_BASE(i, .qword = cmd->state.vb[i].base),
1687 A6XX_VFD_FETCH_SIZE(i, cmd->state.vb[i].size));
1688 }
1689
1690 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1691
1692 if (pStrides) {
1693 cmd->state.dynamic_state[TU_DYNAMIC_STATE_VB_STRIDE].iova =
1694 tu_cs_draw_state(&cmd->sub_cs, &cs, 2 * MAX_VBS).iova;
1695
1696 for (uint32_t i = 0; i < MAX_VBS; i++)
1697 tu_cs_emit_regs(&cs, A6XX_VFD_FETCH_STRIDE(i, cmd->state.vb[i].stride));
1698
1699 cmd->state.dirty |= TU_CMD_DIRTY_VB_STRIDE;
1700 }
1701 }
1702
1703 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,VkBuffer buffer,VkDeviceSize offset,VkIndexType indexType)1704 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1705 VkBuffer buffer,
1706 VkDeviceSize offset,
1707 VkIndexType indexType)
1708 {
1709 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1710 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1711
1712
1713
1714 uint32_t index_size, index_shift, restart_index;
1715
1716 switch (indexType) {
1717 case VK_INDEX_TYPE_UINT16:
1718 index_size = INDEX4_SIZE_16_BIT;
1719 index_shift = 1;
1720 restart_index = 0xffff;
1721 break;
1722 case VK_INDEX_TYPE_UINT32:
1723 index_size = INDEX4_SIZE_32_BIT;
1724 index_shift = 2;
1725 restart_index = 0xffffffff;
1726 break;
1727 case VK_INDEX_TYPE_UINT8_EXT:
1728 index_size = INDEX4_SIZE_8_BIT;
1729 index_shift = 0;
1730 restart_index = 0xff;
1731 break;
1732 default:
1733 unreachable("invalid VkIndexType");
1734 }
1735
1736 /* initialize/update the restart index */
1737 if (cmd->state.index_size != index_size)
1738 tu_cs_emit_regs(&cmd->draw_cs, A6XX_PC_RESTART_INDEX(restart_index));
1739
1740 assert(buf->size >= offset);
1741
1742 cmd->state.index_va = buf->bo->iova + buf->bo_offset + offset;
1743 cmd->state.max_index_count = (buf->size - offset) >> index_shift;
1744 cmd->state.index_size = index_size;
1745 }
1746
1747 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,VkPipelineBindPoint pipelineBindPoint,VkPipelineLayout _layout,uint32_t firstSet,uint32_t descriptorSetCount,const VkDescriptorSet * pDescriptorSets,uint32_t dynamicOffsetCount,const uint32_t * pDynamicOffsets)1748 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1749 VkPipelineBindPoint pipelineBindPoint,
1750 VkPipelineLayout _layout,
1751 uint32_t firstSet,
1752 uint32_t descriptorSetCount,
1753 const VkDescriptorSet *pDescriptorSets,
1754 uint32_t dynamicOffsetCount,
1755 const uint32_t *pDynamicOffsets)
1756 {
1757 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1758 TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1759 unsigned dyn_idx = 0;
1760
1761 struct tu_descriptor_state *descriptors_state =
1762 tu_get_descriptors_state(cmd, pipelineBindPoint);
1763
1764 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1765 unsigned idx = i + firstSet;
1766 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1767
1768 descriptors_state->sets[idx] = set;
1769
1770 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1771 /* update the contents of the dynamic descriptor set */
1772 unsigned src_idx = j;
1773 unsigned dst_idx = j + layout->set[idx].dynamic_offset_start;
1774 assert(dyn_idx < dynamicOffsetCount);
1775
1776 uint32_t *dst =
1777 &descriptors_state->dynamic_descriptors[dst_idx * A6XX_TEX_CONST_DWORDS];
1778 uint32_t *src =
1779 &set->dynamic_descriptors[src_idx * A6XX_TEX_CONST_DWORDS];
1780 uint32_t offset = pDynamicOffsets[dyn_idx];
1781
1782 /* Patch the storage/uniform descriptors right away. */
1783 if (layout->set[idx].layout->dynamic_ubo & (1 << j)) {
1784 /* Note: we can assume here that the addition won't roll over and
1785 * change the SIZE field.
1786 */
1787 uint64_t va = src[0] | ((uint64_t)src[1] << 32);
1788 va += offset;
1789 dst[0] = va;
1790 dst[1] = va >> 32;
1791 } else {
1792 memcpy(dst, src, A6XX_TEX_CONST_DWORDS * 4);
1793 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1794 uint64_t va = dst[4] | ((uint64_t)dst[5] << 32);
1795 va += offset;
1796 dst[4] = va;
1797 dst[5] = va >> 32;
1798 }
1799 }
1800 }
1801 assert(dyn_idx == dynamicOffsetCount);
1802
1803 uint32_t sp_bindless_base_reg, hlsq_bindless_base_reg, hlsq_invalidate_value;
1804 uint64_t addr[MAX_SETS + 1] = {};
1805 struct tu_cs *cs, state_cs;
1806
1807 for (uint32_t i = 0; i < MAX_SETS; i++) {
1808 struct tu_descriptor_set *set = descriptors_state->sets[i];
1809 if (set)
1810 addr[i] = set->va | 3;
1811 }
1812
1813 if (layout->dynamic_offset_count) {
1814 /* allocate and fill out dynamic descriptor set */
1815 struct tu_cs_memory dynamic_desc_set;
1816 VkResult result = tu_cs_alloc(&cmd->sub_cs, layout->dynamic_offset_count,
1817 A6XX_TEX_CONST_DWORDS, &dynamic_desc_set);
1818 if (result != VK_SUCCESS) {
1819 cmd->record_result = result;
1820 return;
1821 }
1822
1823 memcpy(dynamic_desc_set.map, descriptors_state->dynamic_descriptors,
1824 layout->dynamic_offset_count * A6XX_TEX_CONST_DWORDS * 4);
1825 addr[MAX_SETS] = dynamic_desc_set.iova | 3;
1826 }
1827
1828 if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS) {
1829 sp_bindless_base_reg = REG_A6XX_SP_BINDLESS_BASE(0);
1830 hlsq_bindless_base_reg = REG_A6XX_HLSQ_BINDLESS_BASE(0);
1831 hlsq_invalidate_value = A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(0x1f);
1832
1833 cmd->state.desc_sets = tu_cs_draw_state(&cmd->sub_cs, &state_cs, 24);
1834 cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS_LOAD | TU_CMD_DIRTY_SHADER_CONSTS;
1835 cs = &state_cs;
1836 } else {
1837 assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE);
1838
1839 sp_bindless_base_reg = REG_A6XX_SP_CS_BINDLESS_BASE(0);
1840 hlsq_bindless_base_reg = REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
1841 hlsq_invalidate_value = A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(0x1f);
1842
1843 cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD;
1844 cs = &cmd->cs;
1845 }
1846
1847 tu_cs_emit_pkt4(cs, sp_bindless_base_reg, 10);
1848 tu_cs_emit_array(cs, (const uint32_t*) addr, 10);
1849 tu_cs_emit_pkt4(cs, hlsq_bindless_base_reg, 10);
1850 tu_cs_emit_array(cs, (const uint32_t*) addr, 10);
1851 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(.dword = hlsq_invalidate_value));
1852
1853 if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS) {
1854 assert(cs->cur == cs->end); /* validate draw state size */
1855 /* note: this also avoids emitting draw states before renderpass clears,
1856 * which may use the 3D clear path (for MSAA cases)
1857 */
1858 if (!(cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
1859 tu_cs_emit_pkt7(&cmd->draw_cs, CP_SET_DRAW_STATE, 3);
1860 tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
1861 }
1862 }
1863 }
1864
1865 VKAPI_ATTR void VKAPI_CALL
tu_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer,VkPipelineBindPoint pipelineBindPoint,VkPipelineLayout _layout,uint32_t _set,uint32_t descriptorWriteCount,const VkWriteDescriptorSet * pDescriptorWrites)1866 tu_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer,
1867 VkPipelineBindPoint pipelineBindPoint,
1868 VkPipelineLayout _layout,
1869 uint32_t _set,
1870 uint32_t descriptorWriteCount,
1871 const VkWriteDescriptorSet *pDescriptorWrites)
1872 {
1873 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1874 TU_FROM_HANDLE(tu_pipeline_layout, pipe_layout, _layout);
1875 struct tu_descriptor_set_layout *layout = pipe_layout->set[_set].layout;
1876 struct tu_descriptor_set *set =
1877 &tu_get_descriptors_state(cmd, pipelineBindPoint)->push_set;
1878
1879 struct tu_cs_memory set_mem;
1880 VkResult result = tu_cs_alloc(&cmd->sub_cs,
1881 DIV_ROUND_UP(layout->size, A6XX_TEX_CONST_DWORDS * 4),
1882 A6XX_TEX_CONST_DWORDS, &set_mem);
1883 if (result != VK_SUCCESS) {
1884 cmd->record_result = result;
1885 return;
1886 }
1887
1888 /* preserve previous content if the layout is the same: */
1889 if (set->layout == layout)
1890 memcpy(set_mem.map, set->mapped_ptr, layout->size);
1891
1892 set->layout = layout;
1893 set->mapped_ptr = set_mem.map;
1894 set->va = set_mem.iova;
1895
1896 tu_update_descriptor_sets(cmd->device, tu_descriptor_set_to_handle(set),
1897 descriptorWriteCount, pDescriptorWrites, 0, NULL);
1898
1899 tu_CmdBindDescriptorSets(commandBuffer, pipelineBindPoint, _layout, _set,
1900 1, (VkDescriptorSet[]) { tu_descriptor_set_to_handle(set) },
1901 0, NULL);
1902 }
1903
1904 VKAPI_ATTR void VKAPI_CALL
tu_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer,VkDescriptorUpdateTemplate descriptorUpdateTemplate,VkPipelineLayout _layout,uint32_t _set,const void * pData)1905 tu_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer,
1906 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1907 VkPipelineLayout _layout,
1908 uint32_t _set,
1909 const void* pData)
1910 {
1911 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1912 TU_FROM_HANDLE(tu_pipeline_layout, pipe_layout, _layout);
1913 TU_FROM_HANDLE(tu_descriptor_update_template, templ, descriptorUpdateTemplate);
1914 struct tu_descriptor_set_layout *layout = pipe_layout->set[_set].layout;
1915 struct tu_descriptor_set *set =
1916 &tu_get_descriptors_state(cmd, templ->bind_point)->push_set;
1917
1918 struct tu_cs_memory set_mem;
1919 VkResult result = tu_cs_alloc(&cmd->sub_cs,
1920 DIV_ROUND_UP(layout->size, A6XX_TEX_CONST_DWORDS * 4),
1921 A6XX_TEX_CONST_DWORDS, &set_mem);
1922 if (result != VK_SUCCESS) {
1923 cmd->record_result = result;
1924 return;
1925 }
1926
1927 /* preserve previous content if the layout is the same: */
1928 if (set->layout == layout)
1929 memcpy(set_mem.map, set->mapped_ptr, layout->size);
1930
1931 set->layout = layout;
1932 set->mapped_ptr = set_mem.map;
1933 set->va = set_mem.iova;
1934
1935 tu_update_descriptor_set_with_template(cmd->device, set, descriptorUpdateTemplate, pData);
1936
1937 tu_CmdBindDescriptorSets(commandBuffer, templ->bind_point, _layout, _set,
1938 1, (VkDescriptorSet[]) { tu_descriptor_set_to_handle(set) },
1939 0, NULL);
1940 }
1941
1942 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,uint32_t firstBinding,uint32_t bindingCount,const VkBuffer * pBuffers,const VkDeviceSize * pOffsets,const VkDeviceSize * pSizes)1943 tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
1944 uint32_t firstBinding,
1945 uint32_t bindingCount,
1946 const VkBuffer *pBuffers,
1947 const VkDeviceSize *pOffsets,
1948 const VkDeviceSize *pSizes)
1949 {
1950 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1951 struct tu_cs *cs = &cmd->draw_cs;
1952
1953 /* using COND_REG_EXEC for xfb commands matches the blob behavior
1954 * presumably there isn't any benefit using a draw state when the
1955 * condition is (SYSMEM | BINNING)
1956 */
1957 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
1958 CP_COND_REG_EXEC_0_SYSMEM |
1959 CP_COND_REG_EXEC_0_BINNING);
1960
1961 for (uint32_t i = 0; i < bindingCount; i++) {
1962 TU_FROM_HANDLE(tu_buffer, buf, pBuffers[i]);
1963 uint64_t iova = buf->bo->iova + pOffsets[i];
1964 uint32_t size = buf->bo->size - pOffsets[i];
1965 uint32_t idx = i + firstBinding;
1966
1967 if (pSizes && pSizes[i] != VK_WHOLE_SIZE)
1968 size = pSizes[i];
1969
1970 /* BUFFER_BASE is 32-byte aligned, add remaining offset to BUFFER_OFFSET */
1971 uint32_t offset = iova & 0x1f;
1972 iova &= ~(uint64_t) 0x1f;
1973
1974 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE(idx), 3);
1975 tu_cs_emit_qw(cs, iova);
1976 tu_cs_emit(cs, size + offset);
1977
1978 cmd->state.streamout_offset[idx] = offset;
1979 }
1980
1981 tu_cond_exec_end(cs);
1982 }
1983
1984 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,uint32_t firstCounterBuffer,uint32_t counterBufferCount,const VkBuffer * pCounterBuffers,const VkDeviceSize * pCounterBufferOffsets)1985 tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
1986 uint32_t firstCounterBuffer,
1987 uint32_t counterBufferCount,
1988 const VkBuffer *pCounterBuffers,
1989 const VkDeviceSize *pCounterBufferOffsets)
1990 {
1991 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1992 struct tu_cs *cs = &cmd->draw_cs;
1993
1994 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
1995 CP_COND_REG_EXEC_0_SYSMEM |
1996 CP_COND_REG_EXEC_0_BINNING);
1997
1998 /* TODO: only update offset for active buffers */
1999 for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++)
2000 tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, cmd->state.streamout_offset[i]));
2001
2002 for (uint32_t i = 0; i < (pCounterBuffers ? counterBufferCount : 0); i++) {
2003 uint32_t idx = firstCounterBuffer + i;
2004 uint32_t offset = cmd->state.streamout_offset[idx];
2005 uint64_t counter_buffer_offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0u;
2006
2007 if (!pCounterBuffers[i])
2008 continue;
2009
2010 TU_FROM_HANDLE(tu_buffer, buf, pCounterBuffers[i]);
2011
2012 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
2013 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) |
2014 CP_MEM_TO_REG_0_UNK31 |
2015 CP_MEM_TO_REG_0_CNT(1));
2016 tu_cs_emit_qw(cs, buf->bo->iova + counter_buffer_offset);
2017
2018 if (offset) {
2019 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
2020 tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) |
2021 CP_REG_RMW_0_SRC1_ADD);
2022 tu_cs_emit(cs, 0xffffffff);
2023 tu_cs_emit(cs, offset);
2024 }
2025 }
2026
2027 tu_cond_exec_end(cs);
2028 }
2029
2030 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,uint32_t firstCounterBuffer,uint32_t counterBufferCount,const VkBuffer * pCounterBuffers,const VkDeviceSize * pCounterBufferOffsets)2031 tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
2032 uint32_t firstCounterBuffer,
2033 uint32_t counterBufferCount,
2034 const VkBuffer *pCounterBuffers,
2035 const VkDeviceSize *pCounterBufferOffsets)
2036 {
2037 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2038 struct tu_cs *cs = &cmd->draw_cs;
2039
2040 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
2041 CP_COND_REG_EXEC_0_SYSMEM |
2042 CP_COND_REG_EXEC_0_BINNING);
2043
2044 /* TODO: only flush buffers that need to be flushed */
2045 for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2046 /* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
2047 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE(i), 2);
2048 tu_cs_emit_qw(cs, global_iova(cmd, flush_base[i]));
2049 tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i);
2050 }
2051
2052 for (uint32_t i = 0; i < (pCounterBuffers ? counterBufferCount : 0); i++) {
2053 uint32_t idx = firstCounterBuffer + i;
2054 uint32_t offset = cmd->state.streamout_offset[idx];
2055 uint64_t counter_buffer_offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0u;
2056
2057 if (!pCounterBuffers[i])
2058 continue;
2059
2060 TU_FROM_HANDLE(tu_buffer, buf, pCounterBuffers[i]);
2061
2062 /* VPC_SO_FLUSH_BASE has dwords counter, but counter should be in bytes */
2063 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
2064 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
2065 CP_MEM_TO_REG_0_SHIFT_BY_2 |
2066 0x40000 | /* ??? */
2067 CP_MEM_TO_REG_0_UNK31 |
2068 CP_MEM_TO_REG_0_CNT(1));
2069 tu_cs_emit_qw(cs, global_iova(cmd, flush_base[idx]));
2070
2071 if (offset) {
2072 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
2073 tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
2074 CP_REG_RMW_0_SRC1_ADD);
2075 tu_cs_emit(cs, 0xffffffff);
2076 tu_cs_emit(cs, -offset);
2077 }
2078
2079 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
2080 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
2081 CP_REG_TO_MEM_0_CNT(1));
2082 tu_cs_emit_qw(cs, buf->bo->iova + counter_buffer_offset);
2083 }
2084
2085 tu_cond_exec_end(cs);
2086
2087 cmd->state.xfb_used = true;
2088 }
2089
2090 VKAPI_ATTR void VKAPI_CALL
tu_CmdPushConstants(VkCommandBuffer commandBuffer,VkPipelineLayout layout,VkShaderStageFlags stageFlags,uint32_t offset,uint32_t size,const void * pValues)2091 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
2092 VkPipelineLayout layout,
2093 VkShaderStageFlags stageFlags,
2094 uint32_t offset,
2095 uint32_t size,
2096 const void *pValues)
2097 {
2098 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2099 memcpy((void*) cmd->push_constants + offset, pValues, size);
2100 cmd->state.dirty |= TU_CMD_DIRTY_SHADER_CONSTS;
2101 }
2102
2103 /* Flush everything which has been made available but we haven't actually
2104 * flushed yet.
2105 */
2106 static void
tu_flush_all_pending(struct tu_cache_state * cache)2107 tu_flush_all_pending(struct tu_cache_state *cache)
2108 {
2109 cache->flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_FLUSH;
2110 cache->pending_flush_bits &= ~TU_CMD_FLAG_ALL_FLUSH;
2111 }
2112
2113 VKAPI_ATTR VkResult VKAPI_CALL
tu_EndCommandBuffer(VkCommandBuffer commandBuffer)2114 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
2115 {
2116 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2117
2118 /* We currently flush CCU at the end of the command buffer, like
2119 * what the blob does. There's implicit synchronization around every
2120 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
2121 * know yet if this command buffer will be the last in the submit so we
2122 * have to defensively flush everything else.
2123 *
2124 * TODO: We could definitely do better than this, since these flushes
2125 * aren't required by Vulkan, but we'd need kernel support to do that.
2126 * Ideally, we'd like the kernel to flush everything afterwards, so that we
2127 * wouldn't have to do any flushes here, and when submitting multiple
2128 * command buffers there wouldn't be any unnecessary flushes in between.
2129 */
2130 if (cmd_buffer->state.pass) {
2131 tu_flush_all_pending(&cmd_buffer->state.renderpass_cache);
2132 tu_emit_cache_flush_renderpass(cmd_buffer, &cmd_buffer->draw_cs);
2133 } else {
2134 tu_flush_all_pending(&cmd_buffer->state.cache);
2135 cmd_buffer->state.cache.flush_bits |=
2136 TU_CMD_FLAG_CCU_FLUSH_COLOR |
2137 TU_CMD_FLAG_CCU_FLUSH_DEPTH;
2138 tu_emit_cache_flush(cmd_buffer, &cmd_buffer->cs);
2139 }
2140
2141 tu_cs_end(&cmd_buffer->cs);
2142 tu_cs_end(&cmd_buffer->draw_cs);
2143 tu_cs_end(&cmd_buffer->tile_store_cs);
2144 tu_cs_end(&cmd_buffer->draw_epilogue_cs);
2145
2146 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
2147
2148 return cmd_buffer->record_result;
2149 }
2150
2151 static struct tu_cs
tu_cmd_dynamic_state(struct tu_cmd_buffer * cmd,uint32_t id,uint32_t size)2152 tu_cmd_dynamic_state(struct tu_cmd_buffer *cmd, uint32_t id, uint32_t size)
2153 {
2154 struct tu_cs cs;
2155
2156 assert(id < ARRAY_SIZE(cmd->state.dynamic_state));
2157 cmd->state.dynamic_state[id] = tu_cs_draw_state(&cmd->sub_cs, &cs, size);
2158
2159 /* note: this also avoids emitting draw states before renderpass clears,
2160 * which may use the 3D clear path (for MSAA cases)
2161 */
2162 if (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)
2163 return cs;
2164
2165 tu_cs_emit_pkt7(&cmd->draw_cs, CP_SET_DRAW_STATE, 3);
2166 tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DYNAMIC + id, cmd->state.dynamic_state[id]);
2167
2168 return cs;
2169 }
2170
2171 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindPipeline(VkCommandBuffer commandBuffer,VkPipelineBindPoint pipelineBindPoint,VkPipeline _pipeline)2172 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2173 VkPipelineBindPoint pipelineBindPoint,
2174 VkPipeline _pipeline)
2175 {
2176 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2177 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2178
2179 if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE) {
2180 cmd->state.compute_pipeline = pipeline;
2181 tu_cs_emit_state_ib(&cmd->cs, pipeline->program.state);
2182 return;
2183 }
2184
2185 assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS);
2186
2187 cmd->state.pipeline = pipeline;
2188 cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS_LOAD | TU_CMD_DIRTY_SHADER_CONSTS |
2189 TU_CMD_DIRTY_LRZ | TU_CMD_DIRTY_VS_PARAMS;
2190
2191 /* note: this also avoids emitting draw states before renderpass clears,
2192 * which may use the 3D clear path (for MSAA cases)
2193 */
2194 if (!(cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
2195 struct tu_cs *cs = &cmd->draw_cs;
2196 uint32_t mask = ~pipeline->dynamic_state_mask & BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT);
2197
2198 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (7 + util_bitcount(mask)));
2199 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, pipeline->program.config_state);
2200 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state);
2201 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_BINNING, pipeline->program.binning_state);
2202 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state);
2203 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI_BINNING, pipeline->vi.binning_state);
2204 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_RAST, pipeline->rast_state);
2205 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_BLEND, pipeline->blend_state);
2206
2207 u_foreach_bit(i, mask)
2208 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i, pipeline->dynamic_state[i]);
2209 }
2210
2211 if (cmd->state.line_mode != pipeline->line_mode) {
2212 cmd->state.line_mode = pipeline->line_mode;
2213
2214 /* We have to disable MSAA when bresenham lines are used, this is
2215 * a hardware limitation and spec allows it:
2216 *
2217 * When Bresenham lines are being rasterized, sample locations may
2218 * all be treated as being at the pixel center (this may affect
2219 * attribute and depth interpolation).
2220 */
2221 if (cmd->state.subpass && cmd->state.subpass->samples) {
2222 tu6_emit_msaa(&cmd->draw_cs, cmd->state.subpass->samples, cmd->state.line_mode);
2223 }
2224 }
2225
2226 /* the vertex_buffers draw state always contains all the currently
2227 * bound vertex buffers. update its size to only emit the vbs which
2228 * are actually used by the pipeline
2229 * note there is a HW optimization which makes it so the draw state
2230 * is not re-executed completely when only the size changes
2231 */
2232 if (cmd->state.vertex_buffers.size != pipeline->num_vbs * 4) {
2233 cmd->state.vertex_buffers.size = pipeline->num_vbs * 4;
2234 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
2235 }
2236
2237 if ((pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_VB_STRIDE)) &&
2238 cmd->state.dynamic_state[TU_DYNAMIC_STATE_VB_STRIDE].size != pipeline->num_vbs * 2) {
2239 cmd->state.dynamic_state[TU_DYNAMIC_STATE_VB_STRIDE].size = pipeline->num_vbs * 2;
2240 cmd->state.dirty |= TU_CMD_DIRTY_VB_STRIDE;
2241 }
2242
2243 #define UPDATE_REG(X, Y) { \
2244 /* note: would be better to have pipeline bits already masked */ \
2245 uint32_t pipeline_bits = pipeline->X & pipeline->X##_mask; \
2246 if ((cmd->state.X & pipeline->X##_mask) != pipeline_bits) { \
2247 cmd->state.X &= ~pipeline->X##_mask; \
2248 cmd->state.X |= pipeline_bits; \
2249 cmd->state.dirty |= TU_CMD_DIRTY_##Y; \
2250 } \
2251 if (!(pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_##Y))) \
2252 cmd->state.dirty &= ~TU_CMD_DIRTY_##Y; \
2253 }
2254
2255 /* these registers can have bits set from both pipeline and dynamic state
2256 * this updates the bits set by the pipeline
2257 * if the pipeline doesn't use a dynamic state for the register, then
2258 * the relevant dirty bit is cleared to avoid overriding the non-dynamic
2259 * state with a dynamic state the next draw.
2260 */
2261 UPDATE_REG(gras_su_cntl, GRAS_SU_CNTL);
2262 UPDATE_REG(rb_depth_cntl, RB_DEPTH_CNTL);
2263 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL);
2264 UPDATE_REG(pc_raster_cntl, RASTERIZER_DISCARD);
2265 UPDATE_REG(vpc_unknown_9107, RASTERIZER_DISCARD);
2266 #undef UPDATE_REG
2267
2268 if (pipeline->rb_depth_cntl_disable)
2269 cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
2270 }
2271
2272 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetViewport(VkCommandBuffer commandBuffer,uint32_t firstViewport,uint32_t viewportCount,const VkViewport * pViewports)2273 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2274 uint32_t firstViewport,
2275 uint32_t viewportCount,
2276 const VkViewport *pViewports)
2277 {
2278 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2279 struct tu_cs cs;
2280
2281 memcpy(&cmd->state.viewport[firstViewport], pViewports, viewportCount * sizeof(*pViewports));
2282 cmd->state.max_viewport = MAX2(cmd->state.max_viewport, firstViewport + viewportCount);
2283
2284 cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_VIEWPORT, 8 + 10 * cmd->state.max_viewport);
2285 tu6_emit_viewport(&cs, cmd->state.viewport, cmd->state.max_viewport);
2286 }
2287
2288 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetScissor(VkCommandBuffer commandBuffer,uint32_t firstScissor,uint32_t scissorCount,const VkRect2D * pScissors)2289 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2290 uint32_t firstScissor,
2291 uint32_t scissorCount,
2292 const VkRect2D *pScissors)
2293 {
2294 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2295 struct tu_cs cs;
2296
2297 memcpy(&cmd->state.scissor[firstScissor], pScissors, scissorCount * sizeof(*pScissors));
2298 cmd->state.max_scissor = MAX2(cmd->state.max_scissor, firstScissor + scissorCount);
2299
2300 cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_SCISSOR, 1 + 2 * cmd->state.max_scissor);
2301 tu6_emit_scissor(&cs, cmd->state.scissor, cmd->state.max_scissor);
2302 }
2303
2304 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetLineWidth(VkCommandBuffer commandBuffer,float lineWidth)2305 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2306 {
2307 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2308
2309 cmd->state.gras_su_cntl &= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2310 cmd->state.gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth / 2.0f);
2311
2312 cmd->state.dirty |= TU_CMD_DIRTY_GRAS_SU_CNTL;
2313 }
2314
2315 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,float depthBiasConstantFactor,float depthBiasClamp,float depthBiasSlopeFactor)2316 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2317 float depthBiasConstantFactor,
2318 float depthBiasClamp,
2319 float depthBiasSlopeFactor)
2320 {
2321 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2322 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BIAS, 4);
2323
2324 tu6_emit_depth_bias(&cs, depthBiasConstantFactor, depthBiasClamp, depthBiasSlopeFactor);
2325 }
2326
2327 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,const float blendConstants[4])2328 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2329 const float blendConstants[4])
2330 {
2331 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2332 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5);
2333
2334 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2335 tu_cs_emit_array(&cs, (const uint32_t *) blendConstants, 4);
2336 }
2337
2338 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,float minDepthBounds,float maxDepthBounds)2339 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2340 float minDepthBounds,
2341 float maxDepthBounds)
2342 {
2343 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2344 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3);
2345
2346 tu_cs_emit_regs(&cs,
2347 A6XX_RB_Z_BOUNDS_MIN(minDepthBounds),
2348 A6XX_RB_Z_BOUNDS_MAX(maxDepthBounds));
2349 }
2350
2351 void
update_stencil_mask(uint32_t * value,VkStencilFaceFlags face,uint32_t mask)2352 update_stencil_mask(uint32_t *value, VkStencilFaceFlags face, uint32_t mask)
2353 {
2354 if (face & VK_STENCIL_FACE_FRONT_BIT)
2355 *value = (*value & 0xff00) | (mask & 0xff);
2356 if (face & VK_STENCIL_FACE_BACK_BIT)
2357 *value = (*value & 0xff) | (mask & 0xff) << 8;
2358 }
2359
2360 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,VkStencilFaceFlags faceMask,uint32_t compareMask)2361 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2362 VkStencilFaceFlags faceMask,
2363 uint32_t compareMask)
2364 {
2365 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2366 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2);
2367
2368 update_stencil_mask(&cmd->state.dynamic_stencil_mask, faceMask, compareMask);
2369
2370 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.dword = cmd->state.dynamic_stencil_mask));
2371 }
2372
2373 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,VkStencilFaceFlags faceMask,uint32_t writeMask)2374 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2375 VkStencilFaceFlags faceMask,
2376 uint32_t writeMask)
2377 {
2378 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2379 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2);
2380
2381 update_stencil_mask(&cmd->state.dynamic_stencil_wrmask, faceMask, writeMask);
2382
2383 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.dword = cmd->state.dynamic_stencil_wrmask));
2384
2385 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
2386 }
2387
2388 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,VkStencilFaceFlags faceMask,uint32_t reference)2389 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2390 VkStencilFaceFlags faceMask,
2391 uint32_t reference)
2392 {
2393 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2394 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2);
2395
2396 update_stencil_mask(&cmd->state.dynamic_stencil_ref, faceMask, reference);
2397
2398 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.dword = cmd->state.dynamic_stencil_ref));
2399 }
2400
2401 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer,const VkSampleLocationsInfoEXT * pSampleLocationsInfo)2402 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer,
2403 const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
2404 {
2405 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2406 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS, 9);
2407
2408 assert(pSampleLocationsInfo);
2409
2410 tu6_emit_sample_locations(&cs, pSampleLocationsInfo);
2411 }
2412
2413 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetCullModeEXT(VkCommandBuffer commandBuffer,VkCullModeFlags cullMode)2414 tu_CmdSetCullModeEXT(VkCommandBuffer commandBuffer, VkCullModeFlags cullMode)
2415 {
2416 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2417
2418 cmd->state.gras_su_cntl &=
2419 ~(A6XX_GRAS_SU_CNTL_CULL_FRONT | A6XX_GRAS_SU_CNTL_CULL_BACK);
2420
2421 if (cullMode & VK_CULL_MODE_FRONT_BIT)
2422 cmd->state.gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
2423 if (cullMode & VK_CULL_MODE_BACK_BIT)
2424 cmd->state.gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
2425
2426 cmd->state.dirty |= TU_CMD_DIRTY_GRAS_SU_CNTL;
2427 }
2428
2429 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetFrontFaceEXT(VkCommandBuffer commandBuffer,VkFrontFace frontFace)2430 tu_CmdSetFrontFaceEXT(VkCommandBuffer commandBuffer, VkFrontFace frontFace)
2431 {
2432 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2433
2434 cmd->state.gras_su_cntl &= ~A6XX_GRAS_SU_CNTL_FRONT_CW;
2435
2436 if (frontFace == VK_FRONT_FACE_CLOCKWISE)
2437 cmd->state.gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
2438
2439 cmd->state.dirty |= TU_CMD_DIRTY_GRAS_SU_CNTL;
2440 }
2441
2442 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetPrimitiveTopologyEXT(VkCommandBuffer commandBuffer,VkPrimitiveTopology primitiveTopology)2443 tu_CmdSetPrimitiveTopologyEXT(VkCommandBuffer commandBuffer,
2444 VkPrimitiveTopology primitiveTopology)
2445 {
2446 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2447
2448 cmd->state.primtype = tu6_primtype(primitiveTopology);
2449 }
2450
2451 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetViewportWithCountEXT(VkCommandBuffer commandBuffer,uint32_t viewportCount,const VkViewport * pViewports)2452 tu_CmdSetViewportWithCountEXT(VkCommandBuffer commandBuffer,
2453 uint32_t viewportCount,
2454 const VkViewport* pViewports)
2455 {
2456 tu_CmdSetViewport(commandBuffer, 0, viewportCount, pViewports);
2457 }
2458
2459 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetScissorWithCountEXT(VkCommandBuffer commandBuffer,uint32_t scissorCount,const VkRect2D * pScissors)2460 tu_CmdSetScissorWithCountEXT(VkCommandBuffer commandBuffer,
2461 uint32_t scissorCount,
2462 const VkRect2D* pScissors)
2463 {
2464 tu_CmdSetScissor(commandBuffer, 0, scissorCount, pScissors);
2465 }
2466
2467 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetDepthTestEnableEXT(VkCommandBuffer commandBuffer,VkBool32 depthTestEnable)2468 tu_CmdSetDepthTestEnableEXT(VkCommandBuffer commandBuffer,
2469 VkBool32 depthTestEnable)
2470 {
2471 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2472
2473 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
2474
2475 if (depthTestEnable)
2476 cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
2477
2478 cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
2479 }
2480
2481 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetDepthWriteEnableEXT(VkCommandBuffer commandBuffer,VkBool32 depthWriteEnable)2482 tu_CmdSetDepthWriteEnableEXT(VkCommandBuffer commandBuffer,
2483 VkBool32 depthWriteEnable)
2484 {
2485 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2486
2487 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
2488
2489 if (depthWriteEnable)
2490 cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
2491
2492 cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
2493 }
2494
2495 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetDepthCompareOpEXT(VkCommandBuffer commandBuffer,VkCompareOp depthCompareOp)2496 tu_CmdSetDepthCompareOpEXT(VkCommandBuffer commandBuffer,
2497 VkCompareOp depthCompareOp)
2498 {
2499 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2500
2501 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
2502
2503 cmd->state.rb_depth_cntl |=
2504 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(depthCompareOp));
2505
2506 cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
2507 }
2508
2509 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetDepthBoundsTestEnableEXT(VkCommandBuffer commandBuffer,VkBool32 depthBoundsTestEnable)2510 tu_CmdSetDepthBoundsTestEnableEXT(VkCommandBuffer commandBuffer,
2511 VkBool32 depthBoundsTestEnable)
2512 {
2513 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2514
2515 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE;
2516
2517 if (depthBoundsTestEnable)
2518 cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE;
2519
2520 cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
2521 }
2522
2523 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetStencilTestEnableEXT(VkCommandBuffer commandBuffer,VkBool32 stencilTestEnable)2524 tu_CmdSetStencilTestEnableEXT(VkCommandBuffer commandBuffer,
2525 VkBool32 stencilTestEnable)
2526 {
2527 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2528
2529 cmd->state.rb_stencil_cntl &= ~(
2530 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
2531 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
2532 A6XX_RB_STENCIL_CONTROL_STENCIL_READ);
2533
2534 if (stencilTestEnable) {
2535 cmd->state.rb_stencil_cntl |=
2536 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
2537 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
2538 A6XX_RB_STENCIL_CONTROL_STENCIL_READ;
2539 }
2540
2541 cmd->state.dirty |= TU_CMD_DIRTY_RB_STENCIL_CNTL;
2542 }
2543
2544 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetStencilOpEXT(VkCommandBuffer commandBuffer,VkStencilFaceFlags faceMask,VkStencilOp failOp,VkStencilOp passOp,VkStencilOp depthFailOp,VkCompareOp compareOp)2545 tu_CmdSetStencilOpEXT(VkCommandBuffer commandBuffer,
2546 VkStencilFaceFlags faceMask,
2547 VkStencilOp failOp,
2548 VkStencilOp passOp,
2549 VkStencilOp depthFailOp,
2550 VkCompareOp compareOp)
2551 {
2552 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2553
2554 if (faceMask & VK_STENCIL_FACE_FRONT_BIT) {
2555 cmd->state.rb_stencil_cntl &= ~(
2556 A6XX_RB_STENCIL_CONTROL_FUNC__MASK |
2557 A6XX_RB_STENCIL_CONTROL_FAIL__MASK |
2558 A6XX_RB_STENCIL_CONTROL_ZPASS__MASK |
2559 A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK);
2560
2561 cmd->state.rb_stencil_cntl |=
2562 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(compareOp)) |
2563 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(failOp)) |
2564 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(passOp)) |
2565 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(depthFailOp));
2566 }
2567
2568 if (faceMask & VK_STENCIL_FACE_BACK_BIT) {
2569 cmd->state.rb_stencil_cntl &= ~(
2570 A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK |
2571 A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK |
2572 A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK |
2573 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK);
2574
2575 cmd->state.rb_stencil_cntl |=
2576 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(compareOp)) |
2577 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(failOp)) |
2578 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(passOp)) |
2579 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(depthFailOp));
2580 }
2581
2582 cmd->state.dirty |= TU_CMD_DIRTY_RB_STENCIL_CNTL;
2583 }
2584
2585 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetDepthBiasEnableEXT(VkCommandBuffer commandBuffer,VkBool32 depthBiasEnable)2586 tu_CmdSetDepthBiasEnableEXT(VkCommandBuffer commandBuffer,
2587 VkBool32 depthBiasEnable)
2588 {
2589 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2590
2591 cmd->state.gras_su_cntl &= ~A6XX_GRAS_SU_CNTL_POLY_OFFSET;
2592 if (depthBiasEnable)
2593 cmd->state.gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
2594
2595 cmd->state.dirty |= TU_CMD_DIRTY_GRAS_SU_CNTL;
2596 }
2597
2598 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetPrimitiveRestartEnableEXT(VkCommandBuffer commandBuffer,VkBool32 primitiveRestartEnable)2599 tu_CmdSetPrimitiveRestartEnableEXT(VkCommandBuffer commandBuffer,
2600 VkBool32 primitiveRestartEnable)
2601 {
2602 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2603
2604 cmd->state.primitive_restart_enable = primitiveRestartEnable;
2605 }
2606
2607 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetRasterizerDiscardEnableEXT(VkCommandBuffer commandBuffer,VkBool32 rasterizerDiscardEnable)2608 tu_CmdSetRasterizerDiscardEnableEXT(VkCommandBuffer commandBuffer,
2609 VkBool32 rasterizerDiscardEnable)
2610 {
2611 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2612
2613 cmd->state.pc_raster_cntl &= ~A6XX_PC_RASTER_CNTL_DISCARD;
2614 cmd->state.vpc_unknown_9107 &= ~A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD;
2615 if (rasterizerDiscardEnable) {
2616 cmd->state.pc_raster_cntl |= A6XX_PC_RASTER_CNTL_DISCARD;
2617 cmd->state.vpc_unknown_9107 |= A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD;
2618 }
2619
2620 cmd->state.dirty |= TU_CMD_DIRTY_RASTERIZER_DISCARD;
2621 }
2622
2623 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetLogicOpEXT(VkCommandBuffer commandBuffer,VkLogicOp logicOp)2624 tu_CmdSetLogicOpEXT(VkCommandBuffer commandBuffer,
2625 VkLogicOp logicOp)
2626 {
2627 tu_stub();
2628 }
2629
2630 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetPatchControlPointsEXT(VkCommandBuffer commandBuffer,uint32_t patchControlPoints)2631 tu_CmdSetPatchControlPointsEXT(VkCommandBuffer commandBuffer,
2632 uint32_t patchControlPoints)
2633 {
2634 tu_stub();
2635 }
2636
2637 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetLineStippleEXT(VkCommandBuffer commandBuffer,uint32_t lineStippleFactor,uint16_t lineStipplePattern)2638 tu_CmdSetLineStippleEXT(VkCommandBuffer commandBuffer,
2639 uint32_t lineStippleFactor,
2640 uint16_t lineStipplePattern)
2641 {
2642 tu_stub();
2643 }
2644
2645 static void
tu_flush_for_access(struct tu_cache_state * cache,enum tu_cmd_access_mask src_mask,enum tu_cmd_access_mask dst_mask)2646 tu_flush_for_access(struct tu_cache_state *cache,
2647 enum tu_cmd_access_mask src_mask,
2648 enum tu_cmd_access_mask dst_mask)
2649 {
2650 enum tu_cmd_flush_bits flush_bits = 0;
2651
2652 if (src_mask & TU_ACCESS_SYSMEM_WRITE) {
2653 cache->pending_flush_bits |= TU_CMD_FLAG_ALL_INVALIDATE;
2654 }
2655
2656 if (src_mask & TU_ACCESS_CP_WRITE) {
2657 /* Flush the CP write queue.
2658 */
2659 cache->pending_flush_bits |=
2660 TU_CMD_FLAG_WAIT_MEM_WRITES |
2661 TU_CMD_FLAG_ALL_INVALIDATE;
2662 }
2663
2664 #define SRC_FLUSH(domain, flush, invalidate) \
2665 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2666 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
2667 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2668 }
2669
2670 SRC_FLUSH(UCHE, CACHE_FLUSH, CACHE_INVALIDATE)
2671 SRC_FLUSH(CCU_COLOR, CCU_FLUSH_COLOR, CCU_INVALIDATE_COLOR)
2672 SRC_FLUSH(CCU_DEPTH, CCU_FLUSH_DEPTH, CCU_INVALIDATE_DEPTH)
2673
2674 #undef SRC_FLUSH
2675
2676 #define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
2677 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
2678 flush_bits |= TU_CMD_FLAG_##flush; \
2679 cache->pending_flush_bits |= \
2680 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2681 }
2682
2683 SRC_INCOHERENT_FLUSH(CCU_COLOR, CCU_FLUSH_COLOR, CCU_INVALIDATE_COLOR)
2684 SRC_INCOHERENT_FLUSH(CCU_DEPTH, CCU_FLUSH_DEPTH, CCU_INVALIDATE_DEPTH)
2685
2686 #undef SRC_INCOHERENT_FLUSH
2687
2688 /* Treat host & sysmem write accesses the same, since the kernel implicitly
2689 * drains the queue before signalling completion to the host.
2690 */
2691 if (dst_mask & (TU_ACCESS_SYSMEM_READ | TU_ACCESS_SYSMEM_WRITE)) {
2692 flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_FLUSH;
2693 }
2694
2695 #define DST_FLUSH(domain, flush, invalidate) \
2696 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2697 TU_ACCESS_##domain##_WRITE)) { \
2698 flush_bits |= cache->pending_flush_bits & \
2699 (TU_CMD_FLAG_##invalidate | \
2700 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2701 }
2702
2703 DST_FLUSH(UCHE, CACHE_FLUSH, CACHE_INVALIDATE)
2704 DST_FLUSH(CCU_COLOR, CCU_FLUSH_COLOR, CCU_INVALIDATE_COLOR)
2705 DST_FLUSH(CCU_DEPTH, CCU_FLUSH_DEPTH, CCU_INVALIDATE_DEPTH)
2706
2707 #undef DST_FLUSH
2708
2709 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
2710 if (dst_mask & (TU_ACCESS_##domain##_INCOHERENT_READ | \
2711 TU_ACCESS_##domain##_INCOHERENT_WRITE)) { \
2712 flush_bits |= TU_CMD_FLAG_##invalidate | \
2713 (cache->pending_flush_bits & \
2714 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2715 }
2716
2717 DST_INCOHERENT_FLUSH(CCU_COLOR, CCU_FLUSH_COLOR, CCU_INVALIDATE_COLOR)
2718 DST_INCOHERENT_FLUSH(CCU_DEPTH, CCU_FLUSH_DEPTH, CCU_INVALIDATE_DEPTH)
2719
2720 #undef DST_INCOHERENT_FLUSH
2721
2722 cache->flush_bits |= flush_bits;
2723 cache->pending_flush_bits &= ~flush_bits;
2724 }
2725
2726 static void
tu_flush_for_stage(struct tu_cache_state * cache,enum tu_stage src_stage,enum tu_stage dst_stage)2727 tu_flush_for_stage(struct tu_cache_state *cache,
2728 enum tu_stage src_stage, enum tu_stage dst_stage)
2729 {
2730 /* As far as we know, flushes take place in the last stage so if there are
2731 * any pending flushes then we have to move down the source stage, because
2732 * the data only becomes available when the flush finishes. In particular
2733 * this can matter when the CP writes something and we need to invalidate
2734 * UCHE to read it.
2735 */
2736 if (cache->flush_bits & (TU_CMD_FLAG_ALL_FLUSH | TU_CMD_FLAG_ALL_INVALIDATE))
2737 src_stage = TU_STAGE_PS;
2738
2739 /* Note: if the destination stage is the CP, then the CP also has to wait
2740 * for any WFI's to finish. This is already done for draw calls, including
2741 * before indirect param reads, for the most part, so we just need to WFI.
2742 *
2743 * Transform feedback counters are read via CP_MEM_TO_REG, which implicitly
2744 * does CP_WAIT_FOR_ME, but we still need a WFI if the GPU writes it.
2745 *
2746 * Currently we read the draw predicate using CP_MEM_TO_MEM, which
2747 * also implicitly does CP_WAIT_FOR_ME. However CP_DRAW_PRED_SET does *not*
2748 * implicitly do CP_WAIT_FOR_ME, it seems to only wait for counters to
2749 * complete since it's written for DX11 where you can only predicate on the
2750 * result of a query object. So if we implement 64-bit comparisons in the
2751 * future, or if CP_DRAW_PRED_SET grows the capability to do 32-bit
2752 * comparisons, then this will have to be dealt with.
2753 */
2754 if (src_stage > dst_stage)
2755 cache->flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
2756 }
2757
2758 static enum tu_cmd_access_mask
vk2tu_access(VkAccessFlags flags,bool gmem)2759 vk2tu_access(VkAccessFlags flags, bool gmem)
2760 {
2761 enum tu_cmd_access_mask mask = 0;
2762
2763 if (flags &
2764 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT | /* Read performed by CP */
2765 VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT | /* Read performed by CP */
2766 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT | /* Read performed by CP */
2767 VK_ACCESS_MEMORY_READ_BIT)) {
2768 mask |= TU_ACCESS_SYSMEM_READ;
2769 }
2770
2771 if (flags &
2772 (VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT |
2773 VK_ACCESS_MEMORY_WRITE_BIT)) {
2774 mask |= TU_ACCESS_CP_WRITE;
2775 }
2776
2777 if (flags &
2778 (VK_ACCESS_HOST_READ_BIT |
2779 VK_ACCESS_MEMORY_WRITE_BIT)) {
2780 mask |= TU_ACCESS_SYSMEM_READ;
2781 }
2782
2783 if (flags &
2784 (VK_ACCESS_HOST_WRITE_BIT |
2785 VK_ACCESS_MEMORY_WRITE_BIT)) {
2786 mask |= TU_ACCESS_SYSMEM_WRITE;
2787 }
2788
2789 if (flags &
2790 (VK_ACCESS_INDEX_READ_BIT | /* Read performed by PC, I think */
2791 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT | /* Read performed by VFD */
2792 VK_ACCESS_UNIFORM_READ_BIT | /* Read performed by SP */
2793 /* TODO: Is there a no-cache bit for textures so that we can ignore
2794 * these?
2795 */
2796 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT | /* Read performed by TP */
2797 VK_ACCESS_SHADER_READ_BIT | /* Read perfomed by SP/TP */
2798 VK_ACCESS_MEMORY_READ_BIT)) {
2799 mask |= TU_ACCESS_UCHE_READ;
2800 }
2801
2802 if (flags &
2803 (VK_ACCESS_SHADER_WRITE_BIT | /* Write performed by SP */
2804 VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT | /* Write performed by VPC */
2805 VK_ACCESS_MEMORY_WRITE_BIT)) {
2806 mask |= TU_ACCESS_UCHE_WRITE;
2807 }
2808
2809 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
2810 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
2811 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
2812 * can ignore CCU and pretend that color attachments and transfers use
2813 * sysmem directly.
2814 */
2815
2816 if (flags &
2817 (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT |
2818 VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT |
2819 VK_ACCESS_MEMORY_READ_BIT)) {
2820 if (gmem)
2821 mask |= TU_ACCESS_SYSMEM_READ;
2822 else
2823 mask |= TU_ACCESS_CCU_COLOR_INCOHERENT_READ;
2824 }
2825
2826 if (flags &
2827 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT |
2828 VK_ACCESS_MEMORY_READ_BIT)) {
2829 if (gmem)
2830 mask |= TU_ACCESS_SYSMEM_READ;
2831 else
2832 mask |= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ;
2833 }
2834
2835 if (flags &
2836 (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT |
2837 VK_ACCESS_MEMORY_WRITE_BIT)) {
2838 if (gmem) {
2839 mask |= TU_ACCESS_SYSMEM_WRITE;
2840 } else {
2841 mask |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
2842 }
2843 }
2844
2845 if (flags &
2846 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT |
2847 VK_ACCESS_MEMORY_WRITE_BIT)) {
2848 if (gmem) {
2849 mask |= TU_ACCESS_SYSMEM_WRITE;
2850 } else {
2851 mask |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE;
2852 }
2853 }
2854
2855 if (flags &
2856 (VK_ACCESS_TRANSFER_WRITE_BIT |
2857 VK_ACCESS_MEMORY_WRITE_BIT)) {
2858 if (gmem) {
2859 mask |= TU_ACCESS_SYSMEM_WRITE;
2860 } else {
2861 mask |= TU_ACCESS_CCU_COLOR_WRITE;
2862 }
2863 }
2864
2865 if (flags &
2866 (VK_ACCESS_TRANSFER_READ_BIT | /* Access performed by TP */
2867 VK_ACCESS_MEMORY_READ_BIT)) {
2868 mask |= TU_ACCESS_UCHE_READ;
2869 }
2870
2871 return mask;
2872 }
2873
2874 static enum tu_stage
vk2tu_single_stage(VkPipelineStageFlags vk_stage,bool dst)2875 vk2tu_single_stage(VkPipelineStageFlags vk_stage, bool dst)
2876 {
2877 switch (vk_stage) {
2878 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
2879 case VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT:
2880 case VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT:
2881 return TU_STAGE_CP;
2882 case VK_PIPELINE_STAGE_VERTEX_INPUT_BIT:
2883 return TU_STAGE_FE;
2884 case VK_PIPELINE_STAGE_VERTEX_SHADER_BIT:
2885 case VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT:
2886 case VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT:
2887 case VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT:
2888 return TU_STAGE_SP_VS;
2889 case VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT:
2890 case VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT:
2891 return TU_STAGE_SP_PS;
2892 case VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT: /* Yes, really */
2893 /* See comment in TU_STAGE_GRAS about early fragment tests */
2894 case VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT:
2895 case VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT:
2896 case VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT:
2897 case VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT:
2898 return TU_STAGE_PS;
2899
2900 case VK_PIPELINE_STAGE_TRANSFER_BIT:
2901 /* Blits read in SP_PS and write in PS, in both 2d and 3d cases */
2902 return dst ? TU_STAGE_SP_PS : TU_STAGE_PS;
2903
2904 case VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT:
2905 case VK_PIPELINE_STAGE_ALL_COMMANDS_BIT:
2906 /* Be conservative */
2907 return dst ? TU_STAGE_CP : TU_STAGE_PS;
2908
2909 case VK_PIPELINE_STAGE_HOST_BIT:
2910 return dst ? TU_STAGE_PS : TU_STAGE_CP;
2911 }
2912
2913 unreachable("unknown pipeline stage");
2914 }
2915
2916 static enum tu_stage
vk2tu_src_stage(VkPipelineStageFlags vk_stages)2917 vk2tu_src_stage(VkPipelineStageFlags vk_stages)
2918 {
2919 enum tu_stage stage = TU_STAGE_CP;
2920 u_foreach_bit (bit, vk_stages) {
2921 enum tu_stage new_stage = vk2tu_single_stage(1ull << bit, false);
2922 stage = MAX2(stage, new_stage);
2923 }
2924
2925 return stage;
2926 }
2927
2928 static enum tu_stage
vk2tu_dst_stage(VkPipelineStageFlags vk_stages)2929 vk2tu_dst_stage(VkPipelineStageFlags vk_stages)
2930 {
2931 enum tu_stage stage = TU_STAGE_PS;
2932 u_foreach_bit (bit, vk_stages) {
2933 enum tu_stage new_stage = vk2tu_single_stage(1ull << bit, true);
2934 stage = MIN2(stage, new_stage);
2935 }
2936
2937 return stage;
2938 }
2939
2940 VKAPI_ATTR void VKAPI_CALL
tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,uint32_t commandBufferCount,const VkCommandBuffer * pCmdBuffers)2941 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2942 uint32_t commandBufferCount,
2943 const VkCommandBuffer *pCmdBuffers)
2944 {
2945 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2946 VkResult result;
2947
2948 assert(commandBufferCount > 0);
2949
2950 /* Emit any pending flushes. */
2951 if (cmd->state.pass) {
2952 tu_flush_all_pending(&cmd->state.renderpass_cache);
2953 tu_emit_cache_flush_renderpass(cmd, &cmd->draw_cs);
2954 } else {
2955 tu_flush_all_pending(&cmd->state.cache);
2956 tu_emit_cache_flush(cmd, &cmd->cs);
2957 }
2958
2959 for (uint32_t i = 0; i < commandBufferCount; i++) {
2960 TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2961
2962 if (secondary->usage_flags &
2963 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2964 assert(tu_cs_is_empty(&secondary->cs));
2965
2966 result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2967 if (result != VK_SUCCESS) {
2968 cmd->record_result = result;
2969 break;
2970 }
2971
2972 result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
2973 &secondary->draw_epilogue_cs);
2974 if (result != VK_SUCCESS) {
2975 cmd->record_result = result;
2976 break;
2977 }
2978
2979 if (secondary->state.has_tess)
2980 cmd->state.has_tess = true;
2981 if (secondary->state.has_subpass_predication)
2982 cmd->state.has_subpass_predication = true;
2983 if (secondary->state.disable_gmem)
2984 cmd->state.disable_gmem = true;
2985 } else {
2986 assert(tu_cs_is_empty(&secondary->draw_cs));
2987 assert(tu_cs_is_empty(&secondary->draw_epilogue_cs));
2988
2989 tu_cs_add_entries(&cmd->cs, &secondary->cs);
2990 }
2991
2992 cmd->state.index_size = secondary->state.index_size; /* for restart index update */
2993 }
2994 cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2995
2996 if (cmd->state.pass) {
2997 /* After a secondary command buffer is executed, LRZ is not valid
2998 * until it is cleared again.
2999 */
3000 cmd->state.lrz.valid = false;
3001 }
3002
3003 /* After executing secondary command buffers, there may have been arbitrary
3004 * flushes executed, so when we encounter a pipeline barrier with a
3005 * srcMask, we have to assume that we need to invalidate. Therefore we need
3006 * to re-initialize the cache with all pending invalidate bits set.
3007 */
3008 if (cmd->state.pass) {
3009 tu_cache_init(&cmd->state.renderpass_cache);
3010 } else {
3011 tu_cache_init(&cmd->state.cache);
3012 }
3013 }
3014
3015 VKAPI_ATTR VkResult VKAPI_CALL
tu_CreateCommandPool(VkDevice _device,const VkCommandPoolCreateInfo * pCreateInfo,const VkAllocationCallbacks * pAllocator,VkCommandPool * pCmdPool)3016 tu_CreateCommandPool(VkDevice _device,
3017 const VkCommandPoolCreateInfo *pCreateInfo,
3018 const VkAllocationCallbacks *pAllocator,
3019 VkCommandPool *pCmdPool)
3020 {
3021 TU_FROM_HANDLE(tu_device, device, _device);
3022 struct tu_cmd_pool *pool;
3023
3024 pool = vk_object_alloc(&device->vk, pAllocator, sizeof(*pool),
3025 VK_OBJECT_TYPE_COMMAND_POOL);
3026 if (pool == NULL)
3027 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
3028
3029 if (pAllocator)
3030 pool->alloc = *pAllocator;
3031 else
3032 pool->alloc = device->vk.alloc;
3033
3034 list_inithead(&pool->cmd_buffers);
3035 list_inithead(&pool->free_cmd_buffers);
3036
3037 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3038
3039 *pCmdPool = tu_cmd_pool_to_handle(pool);
3040
3041 return VK_SUCCESS;
3042 }
3043
3044 VKAPI_ATTR void VKAPI_CALL
tu_DestroyCommandPool(VkDevice _device,VkCommandPool commandPool,const VkAllocationCallbacks * pAllocator)3045 tu_DestroyCommandPool(VkDevice _device,
3046 VkCommandPool commandPool,
3047 const VkAllocationCallbacks *pAllocator)
3048 {
3049 TU_FROM_HANDLE(tu_device, device, _device);
3050 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
3051
3052 if (!pool)
3053 return;
3054
3055 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
3056 &pool->cmd_buffers, pool_link)
3057 {
3058 tu_cmd_buffer_destroy(cmd_buffer);
3059 }
3060
3061 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
3062 &pool->free_cmd_buffers, pool_link)
3063 {
3064 tu_cmd_buffer_destroy(cmd_buffer);
3065 }
3066
3067 vk_object_free(&device->vk, pAllocator, pool);
3068 }
3069
3070 VKAPI_ATTR VkResult VKAPI_CALL
tu_ResetCommandPool(VkDevice device,VkCommandPool commandPool,VkCommandPoolResetFlags flags)3071 tu_ResetCommandPool(VkDevice device,
3072 VkCommandPool commandPool,
3073 VkCommandPoolResetFlags flags)
3074 {
3075 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
3076 VkResult result;
3077
3078 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
3079 pool_link)
3080 {
3081 result = tu_reset_cmd_buffer(cmd_buffer);
3082 if (result != VK_SUCCESS)
3083 return result;
3084 }
3085
3086 return VK_SUCCESS;
3087 }
3088
3089 VKAPI_ATTR void VKAPI_CALL
tu_TrimCommandPool(VkDevice device,VkCommandPool commandPool,VkCommandPoolTrimFlags flags)3090 tu_TrimCommandPool(VkDevice device,
3091 VkCommandPool commandPool,
3092 VkCommandPoolTrimFlags flags)
3093 {
3094 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
3095
3096 if (!pool)
3097 return;
3098
3099 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
3100 &pool->free_cmd_buffers, pool_link)
3101 {
3102 tu_cmd_buffer_destroy(cmd_buffer);
3103 }
3104 }
3105
3106 static void
tu_subpass_barrier(struct tu_cmd_buffer * cmd_buffer,const struct tu_subpass_barrier * barrier,bool external)3107 tu_subpass_barrier(struct tu_cmd_buffer *cmd_buffer,
3108 const struct tu_subpass_barrier *barrier,
3109 bool external)
3110 {
3111 /* Note: we don't know until the end of the subpass whether we'll use
3112 * sysmem, so assume sysmem here to be safe.
3113 */
3114 struct tu_cache_state *cache =
3115 external ? &cmd_buffer->state.cache : &cmd_buffer->state.renderpass_cache;
3116 enum tu_cmd_access_mask src_flags =
3117 vk2tu_access(barrier->src_access_mask, false);
3118 enum tu_cmd_access_mask dst_flags =
3119 vk2tu_access(barrier->dst_access_mask, false);
3120
3121 if (barrier->incoherent_ccu_color)
3122 src_flags |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
3123 if (barrier->incoherent_ccu_depth)
3124 src_flags |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE;
3125
3126 tu_flush_for_access(cache, src_flags, dst_flags);
3127
3128 enum tu_stage src_stage = vk2tu_src_stage(barrier->src_stage_mask);
3129 enum tu_stage dst_stage = vk2tu_dst_stage(barrier->dst_stage_mask);
3130 tu_flush_for_stage(cache, src_stage, dst_stage);
3131 }
3132
3133 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,const VkRenderPassBeginInfo * pRenderPassBegin,const VkSubpassBeginInfo * pSubpassBeginInfo)3134 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
3135 const VkRenderPassBeginInfo *pRenderPassBegin,
3136 const VkSubpassBeginInfo *pSubpassBeginInfo)
3137 {
3138 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3139 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
3140 TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
3141
3142 const struct VkRenderPassAttachmentBeginInfo *pAttachmentInfo =
3143 vk_find_struct_const(pRenderPassBegin->pNext,
3144 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
3145
3146 cmd->state.pass = pass;
3147 cmd->state.subpass = pass->subpasses;
3148 cmd->state.framebuffer = fb;
3149 cmd->state.render_area = pRenderPassBegin->renderArea;
3150
3151 cmd->state.attachments =
3152 vk_alloc(&cmd->pool->alloc, pass->attachment_count *
3153 sizeof(cmd->state.attachments[0]), 8,
3154 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3155
3156 if (!cmd->state.attachments) {
3157 cmd->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
3158 return;
3159 }
3160
3161 for (unsigned i = 0; i < pass->attachment_count; i++) {
3162 cmd->state.attachments[i] = pAttachmentInfo ?
3163 tu_image_view_from_handle(pAttachmentInfo->pAttachments[i]) :
3164 cmd->state.framebuffer->attachments[i].attachment;
3165 }
3166
3167 trace_start_render_pass(&cmd->trace, &cmd->cs);
3168
3169 /* Note: because this is external, any flushes will happen before draw_cs
3170 * gets called. However deferred flushes could have to happen later as part
3171 * of the subpass.
3172 */
3173 tu_subpass_barrier(cmd, &pass->subpasses[0].start_barrier, true);
3174 cmd->state.renderpass_cache.pending_flush_bits =
3175 cmd->state.cache.pending_flush_bits;
3176 cmd->state.renderpass_cache.flush_bits = 0;
3177
3178 if (pass->subpasses[0].feedback_invalidate)
3179 cmd->state.renderpass_cache.flush_bits |= TU_CMD_FLAG_CACHE_INVALIDATE;
3180
3181 /* Track LRZ valid state */
3182 uint32_t a = cmd->state.subpass->depth_stencil_attachment.attachment;
3183 if (a != VK_ATTACHMENT_UNUSED) {
3184 const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
3185 struct tu_image *image = cmd->state.attachments[a]->image;
3186 /* if image has lrz and it isn't a stencil-only clear: */
3187 if (image->lrz_height &&
3188 (att->clear_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_DEPTH_BIT))) {
3189 cmd->state.lrz.image = image;
3190 cmd->state.lrz.valid = true;
3191 cmd->state.lrz.prev_direction = TU_LRZ_UNKNOWN;
3192
3193 tu6_clear_lrz(cmd, &cmd->cs, image, &pRenderPassBegin->pClearValues[a]);
3194
3195 /* Clearing writes via CCU color in the PS stage, and LRZ is read via
3196 * UCHE in the earlier GRAS stage.
3197 */
3198 cmd->state.cache.flush_bits |=
3199 TU_CMD_FLAG_CCU_FLUSH_COLOR | TU_CMD_FLAG_CACHE_INVALIDATE |
3200 TU_CMD_FLAG_WAIT_FOR_IDLE;
3201 } else {
3202 cmd->state.lrz.valid = false;
3203 }
3204 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
3205 }
3206
3207 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
3208
3209 tu_emit_renderpass_begin(cmd, pRenderPassBegin);
3210
3211 tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
3212 tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
3213 if (cmd->state.subpass->samples)
3214 tu6_emit_msaa(&cmd->draw_cs, cmd->state.subpass->samples, cmd->state.line_mode);
3215 tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
3216
3217 tu_set_input_attachments(cmd, cmd->state.subpass);
3218 }
3219
3220 VKAPI_ATTR void VKAPI_CALL
tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,const VkSubpassBeginInfo * pSubpassBeginInfo,const VkSubpassEndInfo * pSubpassEndInfo)3221 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
3222 const VkSubpassBeginInfo *pSubpassBeginInfo,
3223 const VkSubpassEndInfo *pSubpassEndInfo)
3224 {
3225 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3226 const struct tu_render_pass *pass = cmd->state.pass;
3227 struct tu_cs *cs = &cmd->draw_cs;
3228
3229 const struct tu_subpass *subpass = cmd->state.subpass++;
3230
3231 /* Track LRZ valid state
3232 *
3233 * TODO: Improve this tracking for keeping the state of the past depth/stencil images,
3234 * so if they become active again, we reuse its old state.
3235 */
3236 cmd->state.lrz.valid = false;
3237 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
3238
3239 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
3240
3241 if (subpass->resolve_attachments) {
3242 tu6_emit_blit_scissor(cmd, cs, true);
3243
3244 for (unsigned i = 0; i < subpass->resolve_count; i++) {
3245 uint32_t a = subpass->resolve_attachments[i].attachment;
3246 if (a == VK_ATTACHMENT_UNUSED)
3247 continue;
3248
3249 uint32_t gmem_a = tu_subpass_get_attachment_to_resolve(subpass, i);
3250
3251 tu_store_gmem_attachment(cmd, cs, a, gmem_a);
3252
3253 if (pass->attachments[a].gmem_offset < 0)
3254 continue;
3255
3256 /* TODO:
3257 * check if the resolved attachment is needed by later subpasses,
3258 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
3259 */
3260 tu_finishme("missing GMEM->GMEM resolve path\n");
3261 tu_load_gmem_attachment(cmd, cs, a, true);
3262 }
3263 }
3264
3265 tu_cond_exec_end(cs);
3266
3267 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
3268
3269 tu6_emit_sysmem_resolves(cmd, cs, subpass);
3270
3271 tu_cond_exec_end(cs);
3272
3273 /* Handle dependencies for the next subpass */
3274 tu_subpass_barrier(cmd, &cmd->state.subpass->start_barrier, false);
3275
3276 if (cmd->state.subpass->feedback_invalidate)
3277 cmd->state.renderpass_cache.flush_bits |= TU_CMD_FLAG_CACHE_INVALIDATE;
3278
3279 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
3280 tu6_emit_zs(cmd, cmd->state.subpass, cs);
3281 tu6_emit_mrt(cmd, cmd->state.subpass, cs);
3282 if (cmd->state.subpass->samples)
3283 tu6_emit_msaa(cs, cmd->state.subpass->samples, cmd->state.line_mode);
3284 tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false);
3285
3286 tu_set_input_attachments(cmd, cmd->state.subpass);
3287 }
3288
3289 static uint32_t
tu6_user_consts_size(const struct tu_pipeline * pipeline,struct tu_descriptor_state * descriptors_state,gl_shader_stage type)3290 tu6_user_consts_size(const struct tu_pipeline *pipeline,
3291 struct tu_descriptor_state *descriptors_state,
3292 gl_shader_stage type)
3293 {
3294 const struct tu_program_descriptor_linkage *link =
3295 &pipeline->program.link[type];
3296 const struct ir3_ubo_analysis_state *state = &link->const_state.ubo_state;
3297 uint32_t dwords = 0;
3298
3299 if (link->push_consts.count > 0) {
3300 unsigned num_units = link->push_consts.count;
3301 dwords += 4 + num_units * 4;
3302 }
3303
3304 for (uint32_t i = 0; i < state->num_enabled; i++) {
3305 uint32_t size = state->range[i].end - state->range[i].start;
3306
3307 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
3308
3309 if (size == 0)
3310 continue;
3311
3312 if (!state->range[i].ubo.bindless)
3313 continue;
3314
3315 uint32_t *base = state->range[i].ubo.bindless_base == MAX_SETS ?
3316 descriptors_state->dynamic_descriptors :
3317 descriptors_state->sets[state->range[i].ubo.bindless_base]->mapped_ptr;
3318 unsigned block = state->range[i].ubo.block;
3319 uint32_t *desc = base + block * A6XX_TEX_CONST_DWORDS;
3320 uint32_t desc_size = (desc[1] >> A6XX_UBO_1_SIZE__SHIFT) * 16;
3321 desc_size = desc_size > state->range[i].start ?
3322 desc_size - state->range[i].start : 0;
3323
3324 if (desc_size < size) {
3325 uint32_t zero_size = size - desc_size;
3326 dwords += 4 + zero_size / 4;
3327 size = desc_size;
3328 }
3329
3330 if (size > 0) {
3331 dwords += 4;
3332 }
3333 }
3334
3335 return dwords;
3336 }
3337
3338 static void
tu6_emit_user_consts(struct tu_cs * cs,const struct tu_pipeline * pipeline,struct tu_descriptor_state * descriptors_state,gl_shader_stage type,uint32_t * push_constants)3339 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
3340 struct tu_descriptor_state *descriptors_state,
3341 gl_shader_stage type,
3342 uint32_t *push_constants)
3343 {
3344 const struct tu_program_descriptor_linkage *link =
3345 &pipeline->program.link[type];
3346 const struct ir3_const_state *const_state = &link->const_state;
3347 const struct ir3_ubo_analysis_state *state = &const_state->ubo_state;
3348
3349 if (link->push_consts.count > 0) {
3350 unsigned num_units = link->push_consts.count;
3351 unsigned offset = link->push_consts.lo;
3352 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_units * 4);
3353 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3354 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3355 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3356 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3357 CP_LOAD_STATE6_0_NUM_UNIT(num_units));
3358 tu_cs_emit(cs, 0);
3359 tu_cs_emit(cs, 0);
3360 for (unsigned i = 0; i < num_units * 4; i++)
3361 tu_cs_emit(cs, push_constants[i + offset * 4]);
3362 }
3363
3364 for (uint32_t i = 0; i < state->num_enabled; i++) {
3365 uint32_t size = state->range[i].end - state->range[i].start;
3366 uint32_t offset = state->range[i].start;
3367
3368 /* and even if the start of the const buffer is before
3369 * first_immediate, the end may not be:
3370 */
3371 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
3372
3373 if (size == 0)
3374 continue;
3375
3376 /* things should be aligned to vec4: */
3377 debug_assert((state->range[i].offset % 16) == 0);
3378 debug_assert((size % 16) == 0);
3379 debug_assert((offset % 16) == 0);
3380
3381 /* Dig out the descriptor from the descriptor state and read the VA from
3382 * it. All our UBOs are bindless with the exception of the NIR
3383 * constant_data, which is uploaded once in the pipeline.
3384 */
3385 if (!state->range[i].ubo.bindless) {
3386 assert(state->range[i].ubo.block == const_state->constant_data_ubo);
3387 continue;
3388 }
3389
3390 uint32_t *base = state->range[i].ubo.bindless_base == MAX_SETS ?
3391 descriptors_state->dynamic_descriptors :
3392 descriptors_state->sets[state->range[i].ubo.bindless_base]->mapped_ptr;
3393 unsigned block = state->range[i].ubo.block;
3394 uint32_t *desc = base + block * A6XX_TEX_CONST_DWORDS;
3395 uint64_t va = desc[0] | ((uint64_t)(desc[1] & A6XX_UBO_1_BASE_HI__MASK) << 32);
3396 uint32_t desc_size = (desc[1] >> A6XX_UBO_1_SIZE__SHIFT) * 16;
3397 desc_size = desc_size > state->range[i].start ?
3398 desc_size - state->range[i].start : 0;
3399
3400 /* Handle null UBO descriptors and out-of-range UBO reads by filling the
3401 * rest with 0, simulating what reading with ldc would do. This behavior
3402 * is required by VK_EXT_robustness2.
3403 */
3404 if (desc_size < size) {
3405 uint32_t zero_size = size - desc_size;
3406 uint32_t zero_offset = state->range[i].offset + desc_size;
3407 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + zero_size / 4);
3408 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(zero_offset / 16) |
3409 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3410 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3411 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3412 CP_LOAD_STATE6_0_NUM_UNIT(zero_size / 16));
3413 tu_cs_emit_qw(cs, 0);
3414 for (unsigned i = 0; i < zero_size / 4; i++) {
3415 tu_cs_emit(cs, 0);
3416 }
3417 size = desc_size;
3418 }
3419
3420 if (size > 0) {
3421 assert(va);
3422 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
3423 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
3424 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3425 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3426 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3427 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
3428 tu_cs_emit_qw(cs, va + offset);
3429 }
3430 }
3431 }
3432
3433 static struct tu_draw_state
tu6_emit_consts(struct tu_cmd_buffer * cmd,const struct tu_pipeline * pipeline,struct tu_descriptor_state * descriptors_state,gl_shader_stage type)3434 tu6_emit_consts(struct tu_cmd_buffer *cmd,
3435 const struct tu_pipeline *pipeline,
3436 struct tu_descriptor_state *descriptors_state,
3437 gl_shader_stage type)
3438 {
3439 uint32_t dwords = tu6_user_consts_size(pipeline, descriptors_state, type);
3440 if (dwords == 0)
3441 return (struct tu_draw_state) {};
3442
3443 struct tu_cs cs;
3444 tu_cs_begin_sub_stream(&cmd->sub_cs, dwords, &cs);
3445
3446 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
3447
3448 return tu_cs_end_draw_state(&cmd->sub_cs, &cs);
3449 }
3450
3451 static struct tu_draw_state
tu6_emit_consts_geom(struct tu_cmd_buffer * cmd,const struct tu_pipeline * pipeline,struct tu_descriptor_state * descriptors_state)3452 tu6_emit_consts_geom(struct tu_cmd_buffer *cmd,
3453 const struct tu_pipeline *pipeline,
3454 struct tu_descriptor_state *descriptors_state)
3455 {
3456 uint32_t dwords = 0;
3457
3458 for (uint32_t type = MESA_SHADER_VERTEX; type < MESA_SHADER_FRAGMENT; type++)
3459 dwords += tu6_user_consts_size(pipeline, descriptors_state, type);
3460
3461 if (dwords == 0)
3462 return (struct tu_draw_state) {};
3463
3464 struct tu_cs cs;
3465 tu_cs_begin_sub_stream(&cmd->sub_cs, dwords, &cs);
3466
3467 for (uint32_t type = MESA_SHADER_VERTEX; type < MESA_SHADER_FRAGMENT; type++)
3468 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
3469
3470 return tu_cs_end_draw_state(&cmd->sub_cs, &cs);
3471 }
3472
3473 static uint64_t
get_tess_param_bo_size(const struct tu_pipeline * pipeline,uint32_t draw_count)3474 get_tess_param_bo_size(const struct tu_pipeline *pipeline,
3475 uint32_t draw_count)
3476 {
3477 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
3478 * Still not sure what to do here, so just allocate a reasonably large
3479 * BO and hope for the best for now. */
3480 if (!draw_count)
3481 draw_count = 2048;
3482
3483 /* the tess param BO is pipeline->tess.param_stride bytes per patch,
3484 * which includes both the per-vertex outputs and per-patch outputs
3485 * build_primitive_map in ir3 calculates this stride
3486 */
3487 uint32_t verts_per_patch = pipeline->ia.primtype - DI_PT_PATCHES0;
3488 uint32_t num_patches = draw_count / verts_per_patch;
3489 return num_patches * pipeline->tess.param_stride;
3490 }
3491
3492 static uint64_t
get_tess_factor_bo_size(const struct tu_pipeline * pipeline,uint32_t draw_count)3493 get_tess_factor_bo_size(const struct tu_pipeline *pipeline,
3494 uint32_t draw_count)
3495 {
3496 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
3497 * Still not sure what to do here, so just allocate a reasonably large
3498 * BO and hope for the best for now. */
3499 if (!draw_count)
3500 draw_count = 2048;
3501
3502 /* Each distinct patch gets its own tess factor output. */
3503 uint32_t verts_per_patch = pipeline->ia.primtype - DI_PT_PATCHES0;
3504 uint32_t num_patches = draw_count / verts_per_patch;
3505 uint32_t factor_stride;
3506 switch (pipeline->tess.patch_type) {
3507 case IR3_TESS_ISOLINES:
3508 factor_stride = 12;
3509 break;
3510 case IR3_TESS_TRIANGLES:
3511 factor_stride = 20;
3512 break;
3513 case IR3_TESS_QUADS:
3514 factor_stride = 28;
3515 break;
3516 default:
3517 unreachable("bad tessmode");
3518 }
3519 return factor_stride * num_patches;
3520 }
3521
3522 static VkResult
tu6_emit_tess_consts(struct tu_cmd_buffer * cmd,uint32_t draw_count,const struct tu_pipeline * pipeline,struct tu_draw_state * state,uint64_t * factor_iova)3523 tu6_emit_tess_consts(struct tu_cmd_buffer *cmd,
3524 uint32_t draw_count,
3525 const struct tu_pipeline *pipeline,
3526 struct tu_draw_state *state,
3527 uint64_t *factor_iova)
3528 {
3529 struct tu_cs cs;
3530 VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 16, &cs);
3531 if (result != VK_SUCCESS)
3532 return result;
3533
3534 const struct tu_program_descriptor_linkage *hs_link =
3535 &pipeline->program.link[MESA_SHADER_TESS_CTRL];
3536 bool hs_uses_bo = pipeline->tess.hs_bo_regid < hs_link->constlen;
3537
3538 const struct tu_program_descriptor_linkage *ds_link =
3539 &pipeline->program.link[MESA_SHADER_TESS_EVAL];
3540 bool ds_uses_bo = pipeline->tess.ds_bo_regid < ds_link->constlen;
3541
3542 uint64_t tess_factor_size = get_tess_factor_bo_size(pipeline, draw_count);
3543 uint64_t tess_param_size = get_tess_param_bo_size(pipeline, draw_count);
3544 uint64_t tess_bo_size = tess_factor_size + tess_param_size;
3545 if ((hs_uses_bo || ds_uses_bo) && tess_bo_size > 0) {
3546 struct tu_bo *tess_bo;
3547 result = tu_get_scratch_bo(cmd->device, tess_bo_size, &tess_bo);
3548 if (result != VK_SUCCESS)
3549 return result;
3550
3551 uint64_t tess_factor_iova = tess_bo->iova;
3552 uint64_t tess_param_iova = tess_factor_iova + tess_factor_size;
3553
3554 if (hs_uses_bo) {
3555 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
3556 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(pipeline->tess.hs_bo_regid) |
3557 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3558 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3559 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_HS_SHADER) |
3560 CP_LOAD_STATE6_0_NUM_UNIT(1));
3561 tu_cs_emit(&cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
3562 tu_cs_emit(&cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
3563 tu_cs_emit_qw(&cs, tess_param_iova);
3564 tu_cs_emit_qw(&cs, tess_factor_iova);
3565 }
3566
3567 if (ds_uses_bo) {
3568 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
3569 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(pipeline->tess.ds_bo_regid) |
3570 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3571 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3572 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_DS_SHADER) |
3573 CP_LOAD_STATE6_0_NUM_UNIT(1));
3574 tu_cs_emit(&cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
3575 tu_cs_emit(&cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
3576 tu_cs_emit_qw(&cs, tess_param_iova);
3577 tu_cs_emit_qw(&cs, tess_factor_iova);
3578 }
3579
3580 *factor_iova = tess_factor_iova;
3581 }
3582 *state = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
3583 return VK_SUCCESS;
3584 }
3585
3586 static enum tu_lrz_direction
tu6_lrz_depth_mode(struct A6XX_GRAS_LRZ_CNTL * gras_lrz_cntl,VkCompareOp depthCompareOp,bool * invalidate_lrz)3587 tu6_lrz_depth_mode(struct A6XX_GRAS_LRZ_CNTL *gras_lrz_cntl,
3588 VkCompareOp depthCompareOp,
3589 bool *invalidate_lrz)
3590 {
3591 enum tu_lrz_direction lrz_direction = TU_LRZ_UNKNOWN;
3592
3593 /* LRZ does not support some depth modes. */
3594 switch (depthCompareOp) {
3595 case VK_COMPARE_OP_ALWAYS:
3596 case VK_COMPARE_OP_NOT_EQUAL:
3597 *invalidate_lrz = true;
3598 gras_lrz_cntl->lrz_write = false;
3599 break;
3600 case VK_COMPARE_OP_EQUAL:
3601 case VK_COMPARE_OP_NEVER:
3602 gras_lrz_cntl->lrz_write = false;
3603 break;
3604 case VK_COMPARE_OP_GREATER:
3605 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3606 lrz_direction = TU_LRZ_GREATER;
3607 gras_lrz_cntl->greater = true;
3608 break;
3609 case VK_COMPARE_OP_LESS:
3610 case VK_COMPARE_OP_LESS_OR_EQUAL:
3611 lrz_direction = TU_LRZ_LESS;
3612 break;
3613 default:
3614 unreachable("bad VK_COMPARE_OP value or uninitialized");
3615 break;
3616 };
3617
3618 return lrz_direction;
3619 }
3620
3621 /* update lrz state based on stencil-test func:
3622 *
3623 * Conceptually the order of the pipeline is:
3624 *
3625 *
3626 * FS -> Alpha-Test -> Stencil-Test -> Depth-Test
3627 * | |
3628 * if wrmask != 0 if wrmask != 0
3629 * | |
3630 * v v
3631 * Stencil-Write Depth-Write
3632 *
3633 * Because Stencil-Test can have side effects (Stencil-Write) prior
3634 * to depth test, in this case we potentially need to disable early
3635 * lrz-test. See:
3636 *
3637 * https://www.khronos.org/opengl/wiki/Per-Sample_Processing
3638 */
3639 static void
tu6_lrz_stencil_op(struct A6XX_GRAS_LRZ_CNTL * gras_lrz_cntl,VkCompareOp func,bool stencil_write,bool * invalidate_lrz)3640 tu6_lrz_stencil_op(struct A6XX_GRAS_LRZ_CNTL *gras_lrz_cntl,
3641 VkCompareOp func,
3642 bool stencil_write,
3643 bool *invalidate_lrz)
3644 {
3645 switch (func) {
3646 case VK_COMPARE_OP_ALWAYS:
3647 /* nothing to do for LRZ, but for stencil test when stencil-
3648 * write is enabled, we need to disable lrz-test, since
3649 * conceptually stencil test and write happens before depth-test.
3650 */
3651 if (stencil_write) {
3652 gras_lrz_cntl->enable = false;
3653 gras_lrz_cntl->z_test_enable = false;
3654 *invalidate_lrz = true;
3655 }
3656 break;
3657 case VK_COMPARE_OP_NEVER:
3658 /* fragment never passes, disable lrz_write for this draw. */
3659 gras_lrz_cntl->lrz_write = false;
3660 break;
3661 default:
3662 /* whether the fragment passes or not depends on result
3663 * of stencil test, which we cannot know when doing binning
3664 * pass.
3665 */
3666 gras_lrz_cntl->lrz_write = false;
3667 /* similarly to the VK_COMPARE_OP_ALWAYS case, if there are side-
3668 * effects from stencil test we need to disable lrz-test.
3669 */
3670 if (stencil_write) {
3671 gras_lrz_cntl->enable = false;
3672 gras_lrz_cntl->z_test_enable = false;
3673 *invalidate_lrz = true;
3674 }
3675 break;
3676 }
3677 }
3678
3679 static struct A6XX_GRAS_LRZ_CNTL
tu6_calculate_lrz_state(struct tu_cmd_buffer * cmd,const uint32_t a)3680 tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd,
3681 const uint32_t a)
3682 {
3683 struct tu_pipeline *pipeline = cmd->state.pipeline;
3684 struct A6XX_GRAS_LRZ_CNTL gras_lrz_cntl = { 0 };
3685 bool invalidate_lrz = pipeline->lrz.force_disable_mask & TU_LRZ_FORCE_DISABLE_LRZ;
3686 bool force_disable_write = pipeline->lrz.force_disable_mask & TU_LRZ_FORCE_DISABLE_WRITE;
3687 enum tu_lrz_direction lrz_direction = TU_LRZ_UNKNOWN;
3688
3689 gras_lrz_cntl.enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
3690 gras_lrz_cntl.lrz_write = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
3691 gras_lrz_cntl.z_test_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE;
3692 gras_lrz_cntl.z_bounds_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE;
3693
3694 VkCompareOp depth_compare_op = (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK) >> A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT;
3695 lrz_direction = tu6_lrz_depth_mode(&gras_lrz_cntl, depth_compare_op, &invalidate_lrz);
3696
3697 /* LRZ doesn't transition properly between GREATER* and LESS* depth compare ops */
3698 if (cmd->state.lrz.prev_direction != TU_LRZ_UNKNOWN &&
3699 lrz_direction != TU_LRZ_UNKNOWN &&
3700 cmd->state.lrz.prev_direction != lrz_direction) {
3701 invalidate_lrz = true;
3702 }
3703
3704 cmd->state.lrz.prev_direction = lrz_direction;
3705
3706 /* Invalidate LRZ and disable write if stencil test is enabled */
3707 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE;
3708 if (stencil_test_enable) {
3709 bool stencil_front_writemask =
3710 (pipeline->dynamic_state_mask & BIT(VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) ?
3711 (cmd->state.dynamic_stencil_wrmask & 0xff) :
3712 (pipeline->stencil_wrmask & 0xff);
3713
3714 bool stencil_back_writemask =
3715 (pipeline->dynamic_state_mask & BIT(VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) ?
3716 ((cmd->state.dynamic_stencil_wrmask & 0xff00) >> 8) :
3717 (pipeline->stencil_wrmask & 0xff00) >> 8;
3718
3719 VkCompareOp stencil_front_compare_op =
3720 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FUNC__MASK) >> A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT;
3721
3722 VkCompareOp stencil_back_compare_op =
3723 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT;
3724
3725 tu6_lrz_stencil_op(&gras_lrz_cntl, stencil_front_compare_op,
3726 stencil_front_writemask, &invalidate_lrz);
3727
3728 tu6_lrz_stencil_op(&gras_lrz_cntl, stencil_back_compare_op,
3729 stencil_back_writemask, &invalidate_lrz);
3730 }
3731
3732 if (force_disable_write)
3733 gras_lrz_cntl.lrz_write = false;
3734
3735 if (invalidate_lrz) {
3736 cmd->state.lrz.valid = false;
3737 }
3738
3739 /* In case no depth attachment or invalid, we clear the gras_lrz_cntl register */
3740 if (a == VK_ATTACHMENT_UNUSED || !cmd->state.lrz.valid)
3741 memset(&gras_lrz_cntl, 0, sizeof(gras_lrz_cntl));
3742
3743 return gras_lrz_cntl;
3744 }
3745
3746 static struct tu_draw_state
tu6_build_lrz(struct tu_cmd_buffer * cmd)3747 tu6_build_lrz(struct tu_cmd_buffer *cmd)
3748 {
3749 const uint32_t a = cmd->state.subpass->depth_stencil_attachment.attachment;
3750 struct tu_cs lrz_cs;
3751 struct tu_draw_state ds = tu_cs_draw_state(&cmd->sub_cs, &lrz_cs, 4);
3752
3753 struct A6XX_GRAS_LRZ_CNTL gras_lrz_cntl = tu6_calculate_lrz_state(cmd, a);
3754
3755 tu_cs_emit_regs(&lrz_cs, A6XX_GRAS_LRZ_CNTL(
3756 .enable = gras_lrz_cntl.enable,
3757 .greater = gras_lrz_cntl.greater,
3758 .lrz_write = gras_lrz_cntl.lrz_write,
3759 .z_test_enable = gras_lrz_cntl.z_test_enable,
3760 .z_bounds_enable = gras_lrz_cntl.z_bounds_enable));
3761 tu_cs_emit_regs(&lrz_cs, A6XX_RB_LRZ_CNTL(.enable = gras_lrz_cntl.enable));
3762
3763 return ds;
3764 }
3765
3766 static bool
tu6_writes_depth(struct tu_cmd_buffer * cmd,bool depth_test_enable)3767 tu6_writes_depth(struct tu_cmd_buffer *cmd, bool depth_test_enable)
3768 {
3769 bool depth_write_enable =
3770 cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
3771
3772 VkCompareOp depth_compare_op =
3773 (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK) >> A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT;
3774
3775 bool depth_compare_op_writes = depth_compare_op != VK_COMPARE_OP_NEVER;
3776
3777 return depth_test_enable && depth_write_enable && depth_compare_op_writes;
3778 }
3779
3780 static bool
tu6_writes_stencil(struct tu_cmd_buffer * cmd)3781 tu6_writes_stencil(struct tu_cmd_buffer *cmd)
3782 {
3783 bool stencil_test_enable =
3784 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE;
3785
3786 bool stencil_front_writemask =
3787 (cmd->state.pipeline->dynamic_state_mask & BIT(VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) ?
3788 (cmd->state.dynamic_stencil_wrmask & 0xff) :
3789 (cmd->state.pipeline->stencil_wrmask & 0xff);
3790
3791 bool stencil_back_writemask =
3792 (cmd->state.pipeline->dynamic_state_mask & BIT(VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) ?
3793 ((cmd->state.dynamic_stencil_wrmask & 0xff00) >> 8) :
3794 (cmd->state.pipeline->stencil_wrmask & 0xff00) >> 8;
3795
3796 VkStencilOp front_fail_op =
3797 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT;
3798 VkStencilOp front_pass_op =
3799 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK) >> A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT;
3800 VkStencilOp front_depth_fail_op =
3801 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT;
3802 VkStencilOp back_fail_op =
3803 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT;
3804 VkStencilOp back_pass_op =
3805 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT;
3806 VkStencilOp back_depth_fail_op =
3807 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT;
3808
3809 bool stencil_front_op_writes =
3810 front_pass_op != VK_STENCIL_OP_KEEP &&
3811 front_fail_op != VK_STENCIL_OP_KEEP &&
3812 front_depth_fail_op != VK_STENCIL_OP_KEEP;
3813
3814 bool stencil_back_op_writes =
3815 back_pass_op != VK_STENCIL_OP_KEEP &&
3816 back_fail_op != VK_STENCIL_OP_KEEP &&
3817 back_depth_fail_op != VK_STENCIL_OP_KEEP;
3818
3819 return stencil_test_enable &&
3820 ((stencil_front_writemask && stencil_front_op_writes) ||
3821 (stencil_back_writemask && stencil_back_op_writes));
3822 }
3823
3824 static struct tu_draw_state
tu6_build_depth_plane_z_mode(struct tu_cmd_buffer * cmd)3825 tu6_build_depth_plane_z_mode(struct tu_cmd_buffer *cmd)
3826 {
3827 struct tu_cs cs;
3828 struct tu_draw_state ds = tu_cs_draw_state(&cmd->sub_cs, &cs, 4);
3829
3830 enum a6xx_ztest_mode zmode = A6XX_EARLY_Z;
3831 bool depth_test_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
3832 bool depth_write = tu6_writes_depth(cmd, depth_test_enable);
3833 bool stencil_write = tu6_writes_stencil(cmd);
3834
3835 if (cmd->state.pipeline->lrz.fs_has_kill &&
3836 (depth_write || stencil_write)) {
3837 zmode = cmd->state.lrz.valid ? A6XX_EARLY_LRZ_LATE_Z : A6XX_LATE_Z;
3838 }
3839
3840 if (cmd->state.pipeline->lrz.force_late_z || !depth_test_enable)
3841 zmode = A6XX_LATE_Z;
3842
3843 /* User defined early tests take precedence above all else */
3844 if (cmd->state.pipeline->lrz.early_fragment_tests)
3845 zmode = A6XX_EARLY_Z;
3846
3847 tu_cs_emit_pkt4(&cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
3848 tu_cs_emit(&cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
3849
3850 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
3851 tu_cs_emit(&cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
3852 return ds;
3853 }
3854
3855 static VkResult
tu6_draw_common(struct tu_cmd_buffer * cmd,struct tu_cs * cs,bool indexed,uint32_t draw_count)3856 tu6_draw_common(struct tu_cmd_buffer *cmd,
3857 struct tu_cs *cs,
3858 bool indexed,
3859 /* note: draw_count is 0 for indirect */
3860 uint32_t draw_count)
3861 {
3862 const struct tu_pipeline *pipeline = cmd->state.pipeline;
3863 VkResult result;
3864
3865 tu_emit_cache_flush_renderpass(cmd, cs);
3866
3867 bool primitive_restart_enabled = pipeline->ia.primitive_restart;
3868 if (pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE))
3869 primitive_restart_enabled = cmd->state.primitive_restart_enable;
3870
3871 tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0(
3872 .primitive_restart =
3873 primitive_restart_enabled && indexed,
3874 .provoking_vtx_last = pipeline->provoking_vertex_last,
3875 .tess_upper_left_domain_origin =
3876 pipeline->tess.upper_left_domain_origin));
3877
3878 bool has_tess =
3879 pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
3880
3881 /* Early exit if there is nothing to emit, saves CPU cycles */
3882 if (!(cmd->state.dirty & ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD) &&
3883 !has_tess)
3884 return VK_SUCCESS;
3885
3886 bool dirty_lrz = cmd->state.dirty & (TU_CMD_DIRTY_LRZ | TU_CMD_DIRTY_RB_DEPTH_CNTL | TU_CMD_DIRTY_RB_STENCIL_CNTL);
3887
3888 struct tu_descriptor_state *descriptors_state =
3889 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3890
3891 if (dirty_lrz) {
3892 cmd->state.lrz.state = tu6_build_lrz(cmd);
3893 cmd->state.depth_plane_state = tu6_build_depth_plane_z_mode(cmd);
3894 }
3895
3896 if (cmd->state.dirty & TU_CMD_DIRTY_RASTERIZER_DISCARD) {
3897 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RASTERIZER_DISCARD, 4);
3898 tu_cs_emit_regs(&cs, A6XX_PC_RASTER_CNTL(.dword = cmd->state.pc_raster_cntl));
3899 tu_cs_emit_regs(&cs, A6XX_VPC_UNKNOWN_9107(.dword = cmd->state.vpc_unknown_9107));
3900 }
3901
3902 if (cmd->state.dirty & TU_CMD_DIRTY_GRAS_SU_CNTL) {
3903 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_GRAS_SU_CNTL, 2);
3904 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = cmd->state.gras_su_cntl));
3905 }
3906
3907 if (cmd->state.dirty & TU_CMD_DIRTY_RB_DEPTH_CNTL) {
3908 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_DEPTH_CNTL, 2);
3909 uint32_t rb_depth_cntl = cmd->state.rb_depth_cntl;
3910
3911 if ((rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE) ||
3912 (rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE))
3913 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE;
3914
3915 if ((rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE) &&
3916 !(rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE))
3917 tu6_apply_depth_bounds_workaround(cmd->device, &rb_depth_cntl);
3918
3919 if (pipeline->rb_depth_cntl_disable)
3920 rb_depth_cntl = 0;
3921
3922 tu_cs_emit_regs(&cs, A6XX_RB_DEPTH_CNTL(.dword = rb_depth_cntl));
3923 }
3924
3925 if (cmd->state.dirty & TU_CMD_DIRTY_RB_STENCIL_CNTL) {
3926 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_STENCIL_CNTL, 2);
3927 tu_cs_emit_regs(&cs, A6XX_RB_STENCIL_CONTROL(.dword = cmd->state.rb_stencil_cntl));
3928 }
3929
3930 if (cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS) {
3931 cmd->state.shader_const[0] =
3932 tu6_emit_consts_geom(cmd, pipeline, descriptors_state);
3933 cmd->state.shader_const[1] =
3934 tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT);
3935 }
3936
3937 struct tu_draw_state tess_consts = {};
3938 if (has_tess) {
3939 uint64_t tess_factor_iova = 0;
3940
3941 cmd->state.has_tess = true;
3942 result = tu6_emit_tess_consts(cmd, draw_count, pipeline, &tess_consts, &tess_factor_iova);
3943 if (result != VK_SUCCESS)
3944 return result;
3945
3946 /* this sequence matches what the blob does before every tess draw
3947 * PC_TESSFACTOR_ADDR_LO is a non-context register and needs a wfi
3948 * before writing to it
3949 */
3950 tu_cs_emit_wfi(cs);
3951
3952 tu_cs_emit_regs(cs, A6XX_PC_TESSFACTOR_ADDR(.qword = tess_factor_iova));
3953
3954 tu_cs_emit_pkt7(cs, CP_SET_SUBDRAW_SIZE, 1);
3955 tu_cs_emit(cs, draw_count);
3956 }
3957
3958 /* for the first draw in a renderpass, re-emit all the draw states
3959 *
3960 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
3961 * used, then draw states must be re-emitted. note however this only happens
3962 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
3963 *
3964 * the two input attachment states are excluded because secondary command
3965 * buffer doesn't have a state ib to restore it, and not re-emitting them
3966 * is OK since CmdClearAttachments won't disable/overwrite them
3967 */
3968 if (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE) {
3969 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (TU_DRAW_STATE_COUNT - 2));
3970
3971 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, pipeline->program.config_state);
3972 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state);
3973 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_BINNING, pipeline->program.binning_state);
3974 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_TESS, tess_consts);
3975 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state);
3976 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI_BINNING, pipeline->vi.binning_state);
3977 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_RAST, pipeline->rast_state);
3978 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_BLEND, pipeline->blend_state);
3979 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_SHADER_GEOM_CONST, cmd->state.shader_const[0]);
3980 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS_CONST, cmd->state.shader_const[1]);
3981 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
3982 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, pipeline->load_state);
3983 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
3984 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
3985 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ, cmd->state.lrz.state);
3986 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DEPTH_PLANE, cmd->state.depth_plane_state);
3987
3988 for (uint32_t i = 0; i < ARRAY_SIZE(cmd->state.dynamic_state); i++) {
3989 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i,
3990 ((pipeline->dynamic_state_mask & BIT(i)) ?
3991 cmd->state.dynamic_state[i] :
3992 pipeline->dynamic_state[i]));
3993 }
3994 } else {
3995 /* emit draw states that were just updated
3996 * note we eventually don't want to have to emit anything here
3997 */
3998 bool emit_binding_stride = false;
3999 uint32_t draw_state_count =
4000 has_tess +
4001 ((cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS) ? 2 : 0) +
4002 ((cmd->state.dirty & TU_CMD_DIRTY_DESC_SETS_LOAD) ? 1 : 0) +
4003 ((cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) ? 1 : 0) +
4004 ((cmd->state.dirty & TU_CMD_DIRTY_VS_PARAMS) ? 1 : 0) +
4005 (dirty_lrz ? 2 : 0);
4006
4007 if ((cmd->state.dirty & TU_CMD_DIRTY_VB_STRIDE) &&
4008 (pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_VB_STRIDE))) {
4009 emit_binding_stride = true;
4010 draw_state_count += 1;
4011 }
4012
4013 if (draw_state_count > 0)
4014 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_count);
4015
4016 /* We may need to re-emit tess consts if the current draw call is
4017 * sufficiently larger than the last draw call. */
4018 if (has_tess)
4019 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_TESS, tess_consts);
4020 if (cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS) {
4021 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_SHADER_GEOM_CONST, cmd->state.shader_const[0]);
4022 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS_CONST, cmd->state.shader_const[1]);
4023 }
4024 if (cmd->state.dirty & TU_CMD_DIRTY_DESC_SETS_LOAD)
4025 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, pipeline->load_state);
4026 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS)
4027 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
4028 if (emit_binding_stride) {
4029 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_VB_STRIDE,
4030 cmd->state.dynamic_state[TU_DYNAMIC_STATE_VB_STRIDE]);
4031 }
4032 if (cmd->state.dirty & TU_CMD_DIRTY_VS_PARAMS)
4033 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
4034
4035 if (dirty_lrz) {
4036 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ, cmd->state.lrz.state);
4037 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DEPTH_PLANE, cmd->state.depth_plane_state);
4038 }
4039 }
4040
4041 tu_cs_sanity_check(cs);
4042
4043 /* There are too many graphics dirty bits to list here, so just list the
4044 * bits to preserve instead. The only things not emitted here are
4045 * compute-related state.
4046 */
4047 cmd->state.dirty &= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD;
4048 return VK_SUCCESS;
4049 }
4050
4051 static uint32_t
tu_draw_initiator(struct tu_cmd_buffer * cmd,enum pc_di_src_sel src_sel)4052 tu_draw_initiator(struct tu_cmd_buffer *cmd, enum pc_di_src_sel src_sel)
4053 {
4054 const struct tu_pipeline *pipeline = cmd->state.pipeline;
4055 enum pc_di_primtype primtype = pipeline->ia.primtype;
4056
4057 if (pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY)) {
4058 if (primtype < DI_PT_PATCHES0) {
4059 /* If tesselation used, only VK_PRIMITIVE_TOPOLOGY_PATCH_LIST can be
4060 * set via vkCmdSetPrimitiveTopologyEXT, but primtype is already
4061 * calculated at the pipeline creation based on control points
4062 * for each patch.
4063 *
4064 * Just use the primtype as is for the case.
4065 */
4066 primtype = cmd->state.primtype;
4067 }
4068 }
4069
4070 uint32_t initiator =
4071 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
4072 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel) |
4073 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(cmd->state.index_size) |
4074 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY);
4075
4076 if (pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT)
4077 initiator |= CP_DRAW_INDX_OFFSET_0_GS_ENABLE;
4078
4079 switch (pipeline->tess.patch_type) {
4080 case IR3_TESS_TRIANGLES:
4081 initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES) |
4082 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
4083 break;
4084 case IR3_TESS_ISOLINES:
4085 initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES) |
4086 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
4087 break;
4088 case IR3_TESS_NONE:
4089 initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS);
4090 break;
4091 case IR3_TESS_QUADS:
4092 initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS) |
4093 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
4094 break;
4095 }
4096 return initiator;
4097 }
4098
4099
4100 static uint32_t
vs_params_offset(struct tu_cmd_buffer * cmd)4101 vs_params_offset(struct tu_cmd_buffer *cmd)
4102 {
4103 const struct tu_program_descriptor_linkage *link =
4104 &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
4105 const struct ir3_const_state *const_state = &link->const_state;
4106
4107 if (const_state->offsets.driver_param >= link->constlen)
4108 return 0;
4109
4110 /* this layout is required by CP_DRAW_INDIRECT_MULTI */
4111 STATIC_ASSERT(IR3_DP_DRAWID == 0);
4112 STATIC_ASSERT(IR3_DP_VTXID_BASE == 1);
4113 STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
4114
4115 /* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
4116 assert(const_state->offsets.driver_param != 0);
4117
4118 return const_state->offsets.driver_param;
4119 }
4120
4121 static void
tu6_emit_empty_vs_params(struct tu_cmd_buffer * cmd)4122 tu6_emit_empty_vs_params(struct tu_cmd_buffer *cmd)
4123 {
4124 if (cmd->state.vs_params.iova) {
4125 cmd->state.vs_params = (struct tu_draw_state) {};
4126 cmd->state.dirty |= TU_CMD_DIRTY_VS_PARAMS;
4127 }
4128 }
4129
4130 static void
tu6_emit_vs_params(struct tu_cmd_buffer * cmd,uint32_t vertex_offset,uint32_t first_instance)4131 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
4132 uint32_t vertex_offset,
4133 uint32_t first_instance)
4134 {
4135 /* Beside re-emitting params when they are changed, we should re-emit
4136 * them after constants are invalidated via HLSQ_INVALIDATE_CMD.
4137 */
4138 if (!(cmd->state.dirty & (TU_CMD_DIRTY_DRAW_STATE | TU_CMD_DIRTY_VS_PARAMS)) &&
4139 vertex_offset == cmd->state.last_vs_params.vertex_offset &&
4140 first_instance == cmd->state.last_vs_params.first_instance) {
4141 return;
4142 }
4143
4144 uint32_t offset = vs_params_offset(cmd);
4145
4146 struct tu_cs cs;
4147 VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 3 + (offset ? 8 : 0), &cs);
4148 if (result != VK_SUCCESS) {
4149 cmd->record_result = result;
4150 return;
4151 }
4152
4153 tu_cs_emit_regs(&cs,
4154 A6XX_VFD_INDEX_OFFSET(vertex_offset),
4155 A6XX_VFD_INSTANCE_START_OFFSET(first_instance));
4156
4157 if (offset) {
4158 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
4159 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
4160 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
4161 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
4162 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
4163 CP_LOAD_STATE6_0_NUM_UNIT(1));
4164 tu_cs_emit(&cs, 0);
4165 tu_cs_emit(&cs, 0);
4166
4167 tu_cs_emit(&cs, 0);
4168 tu_cs_emit(&cs, vertex_offset);
4169 tu_cs_emit(&cs, first_instance);
4170 tu_cs_emit(&cs, 0);
4171 }
4172
4173 cmd->state.last_vs_params.vertex_offset = vertex_offset;
4174 cmd->state.last_vs_params.first_instance = first_instance;
4175
4176 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
4177 cmd->state.vs_params = (struct tu_draw_state) {entry.bo->iova + entry.offset, entry.size / 4};
4178
4179 cmd->state.dirty |= TU_CMD_DIRTY_VS_PARAMS;
4180 }
4181
4182 VKAPI_ATTR void VKAPI_CALL
tu_CmdDraw(VkCommandBuffer commandBuffer,uint32_t vertexCount,uint32_t instanceCount,uint32_t firstVertex,uint32_t firstInstance)4183 tu_CmdDraw(VkCommandBuffer commandBuffer,
4184 uint32_t vertexCount,
4185 uint32_t instanceCount,
4186 uint32_t firstVertex,
4187 uint32_t firstInstance)
4188 {
4189 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4190 struct tu_cs *cs = &cmd->draw_cs;
4191
4192 tu6_emit_vs_params(cmd, firstVertex, firstInstance);
4193
4194 tu6_draw_common(cmd, cs, false, vertexCount);
4195
4196 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
4197 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
4198 tu_cs_emit(cs, instanceCount);
4199 tu_cs_emit(cs, vertexCount);
4200 }
4201
4202 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,uint32_t indexCount,uint32_t instanceCount,uint32_t firstIndex,int32_t vertexOffset,uint32_t firstInstance)4203 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
4204 uint32_t indexCount,
4205 uint32_t instanceCount,
4206 uint32_t firstIndex,
4207 int32_t vertexOffset,
4208 uint32_t firstInstance)
4209 {
4210 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4211 struct tu_cs *cs = &cmd->draw_cs;
4212
4213 tu6_emit_vs_params(cmd, vertexOffset, firstInstance);
4214
4215 tu6_draw_common(cmd, cs, true, indexCount);
4216
4217 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
4218 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
4219 tu_cs_emit(cs, instanceCount);
4220 tu_cs_emit(cs, indexCount);
4221 tu_cs_emit(cs, firstIndex);
4222 tu_cs_emit_qw(cs, cmd->state.index_va);
4223 tu_cs_emit(cs, cmd->state.max_index_count);
4224 }
4225
4226 /* Various firmware bugs/inconsistencies mean that some indirect draw opcodes
4227 * do not wait for WFI's to complete before executing. Add a WAIT_FOR_ME if
4228 * pending for these opcodes. This may result in a few extra WAIT_FOR_ME's
4229 * with these opcodes, but the alternative would add unnecessary WAIT_FOR_ME's
4230 * before draw opcodes that don't need it.
4231 */
4232 static void
draw_wfm(struct tu_cmd_buffer * cmd)4233 draw_wfm(struct tu_cmd_buffer *cmd)
4234 {
4235 cmd->state.renderpass_cache.flush_bits |=
4236 cmd->state.renderpass_cache.pending_flush_bits & TU_CMD_FLAG_WAIT_FOR_ME;
4237 cmd->state.renderpass_cache.pending_flush_bits &= ~TU_CMD_FLAG_WAIT_FOR_ME;
4238 }
4239
4240 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,uint32_t drawCount,uint32_t stride)4241 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
4242 VkBuffer _buffer,
4243 VkDeviceSize offset,
4244 uint32_t drawCount,
4245 uint32_t stride)
4246 {
4247 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4248 TU_FROM_HANDLE(tu_buffer, buf, _buffer);
4249 struct tu_cs *cs = &cmd->draw_cs;
4250
4251 tu6_emit_empty_vs_params(cmd);
4252
4253 if (cmd->device->physical_device->info->a6xx.indirect_draw_wfm_quirk)
4254 draw_wfm(cmd);
4255
4256 tu6_draw_common(cmd, cs, false, 0);
4257
4258 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 6);
4259 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
4260 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL) |
4261 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
4262 tu_cs_emit(cs, drawCount);
4263 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
4264 tu_cs_emit(cs, stride);
4265 }
4266
4267 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,uint32_t drawCount,uint32_t stride)4268 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
4269 VkBuffer _buffer,
4270 VkDeviceSize offset,
4271 uint32_t drawCount,
4272 uint32_t stride)
4273 {
4274 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4275 TU_FROM_HANDLE(tu_buffer, buf, _buffer);
4276 struct tu_cs *cs = &cmd->draw_cs;
4277
4278 tu6_emit_empty_vs_params(cmd);
4279
4280 if (cmd->device->physical_device->info->a6xx.indirect_draw_wfm_quirk)
4281 draw_wfm(cmd);
4282
4283 tu6_draw_common(cmd, cs, true, 0);
4284
4285 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 9);
4286 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
4287 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED) |
4288 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
4289 tu_cs_emit(cs, drawCount);
4290 tu_cs_emit_qw(cs, cmd->state.index_va);
4291 tu_cs_emit(cs, cmd->state.max_index_count);
4292 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
4293 tu_cs_emit(cs, stride);
4294 }
4295
4296 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,VkBuffer countBuffer,VkDeviceSize countBufferOffset,uint32_t drawCount,uint32_t stride)4297 tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer,
4298 VkBuffer _buffer,
4299 VkDeviceSize offset,
4300 VkBuffer countBuffer,
4301 VkDeviceSize countBufferOffset,
4302 uint32_t drawCount,
4303 uint32_t stride)
4304 {
4305 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4306 TU_FROM_HANDLE(tu_buffer, buf, _buffer);
4307 TU_FROM_HANDLE(tu_buffer, count_buf, countBuffer);
4308 struct tu_cs *cs = &cmd->draw_cs;
4309
4310 tu6_emit_empty_vs_params(cmd);
4311
4312 /* It turns out that the firmware we have for a650 only partially fixed the
4313 * problem with CP_DRAW_INDIRECT_MULTI not waiting for WFI's to complete
4314 * before reading indirect parameters. It waits for WFI's before reading
4315 * the draw parameters, but after reading the indirect count :(.
4316 */
4317 draw_wfm(cmd);
4318
4319 tu6_draw_common(cmd, cs, false, 0);
4320
4321 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 8);
4322 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
4323 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT) |
4324 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
4325 tu_cs_emit(cs, drawCount);
4326 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
4327 tu_cs_emit_qw(cs, count_buf->bo->iova + count_buf->bo_offset + countBufferOffset);
4328 tu_cs_emit(cs, stride);
4329 }
4330
4331 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,VkBuffer countBuffer,VkDeviceSize countBufferOffset,uint32_t drawCount,uint32_t stride)4332 tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer,
4333 VkBuffer _buffer,
4334 VkDeviceSize offset,
4335 VkBuffer countBuffer,
4336 VkDeviceSize countBufferOffset,
4337 uint32_t drawCount,
4338 uint32_t stride)
4339 {
4340 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4341 TU_FROM_HANDLE(tu_buffer, buf, _buffer);
4342 TU_FROM_HANDLE(tu_buffer, count_buf, countBuffer);
4343 struct tu_cs *cs = &cmd->draw_cs;
4344
4345 tu6_emit_empty_vs_params(cmd);
4346
4347 draw_wfm(cmd);
4348
4349 tu6_draw_common(cmd, cs, true, 0);
4350
4351 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 11);
4352 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
4353 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT_INDEXED) |
4354 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
4355 tu_cs_emit(cs, drawCount);
4356 tu_cs_emit_qw(cs, cmd->state.index_va);
4357 tu_cs_emit(cs, cmd->state.max_index_count);
4358 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
4359 tu_cs_emit_qw(cs, count_buf->bo->iova + count_buf->bo_offset + countBufferOffset);
4360 tu_cs_emit(cs, stride);
4361 }
4362
4363 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,uint32_t instanceCount,uint32_t firstInstance,VkBuffer _counterBuffer,VkDeviceSize counterBufferOffset,uint32_t counterOffset,uint32_t vertexStride)4364 tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,
4365 uint32_t instanceCount,
4366 uint32_t firstInstance,
4367 VkBuffer _counterBuffer,
4368 VkDeviceSize counterBufferOffset,
4369 uint32_t counterOffset,
4370 uint32_t vertexStride)
4371 {
4372 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4373 TU_FROM_HANDLE(tu_buffer, buf, _counterBuffer);
4374 struct tu_cs *cs = &cmd->draw_cs;
4375
4376 /* All known firmware versions do not wait for WFI's with CP_DRAW_AUTO.
4377 * Plus, for the common case where the counter buffer is written by
4378 * vkCmdEndTransformFeedback, we need to wait for the CP_WAIT_MEM_WRITES to
4379 * complete which means we need a WAIT_FOR_ME anyway.
4380 */
4381 draw_wfm(cmd);
4382
4383 tu6_emit_vs_params(cmd, 0, firstInstance);
4384
4385 tu6_draw_common(cmd, cs, false, 0);
4386
4387 tu_cs_emit_pkt7(cs, CP_DRAW_AUTO, 6);
4388 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_XFB));
4389 tu_cs_emit(cs, instanceCount);
4390 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + counterBufferOffset);
4391 tu_cs_emit(cs, counterOffset);
4392 tu_cs_emit(cs, vertexStride);
4393 }
4394
4395 struct tu_dispatch_info
4396 {
4397 /**
4398 * Determine the layout of the grid (in block units) to be used.
4399 */
4400 uint32_t blocks[3];
4401
4402 /**
4403 * A starting offset for the grid. If unaligned is set, the offset
4404 * must still be aligned.
4405 */
4406 uint32_t offsets[3];
4407 /**
4408 * Whether it's an unaligned compute dispatch.
4409 */
4410 bool unaligned;
4411
4412 /**
4413 * Indirect compute parameters resource.
4414 */
4415 struct tu_buffer *indirect;
4416 uint64_t indirect_offset;
4417 };
4418
4419 static void
tu_emit_compute_driver_params(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_pipeline * pipeline,const struct tu_dispatch_info * info)4420 tu_emit_compute_driver_params(struct tu_cmd_buffer *cmd,
4421 struct tu_cs *cs, struct tu_pipeline *pipeline,
4422 const struct tu_dispatch_info *info)
4423 {
4424 gl_shader_stage type = MESA_SHADER_COMPUTE;
4425 const struct tu_program_descriptor_linkage *link =
4426 &pipeline->program.link[type];
4427 const struct ir3_const_state *const_state = &link->const_state;
4428 uint32_t offset = const_state->offsets.driver_param;
4429 unsigned subgroup_size = pipeline->compute.subgroup_size;
4430 unsigned subgroup_shift = util_logbase2(subgroup_size);
4431
4432 if (link->constlen <= offset)
4433 return;
4434
4435 uint32_t num_consts = MIN2(const_state->num_driver_params,
4436 (link->constlen - offset) * 4);
4437
4438 if (!info->indirect) {
4439 uint32_t driver_params[12] = {
4440 [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
4441 [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
4442 [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
4443 [IR3_DP_BASE_GROUP_X] = info->offsets[0],
4444 [IR3_DP_BASE_GROUP_Y] = info->offsets[1],
4445 [IR3_DP_BASE_GROUP_Z] = info->offsets[2],
4446 [IR3_DP_SUBGROUP_SIZE] = subgroup_size,
4447 [IR3_DP_SUBGROUP_ID_SHIFT] = subgroup_shift,
4448 };
4449
4450 assert(num_consts <= ARRAY_SIZE(driver_params));
4451
4452 /* push constants */
4453 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
4454 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
4455 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
4456 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
4457 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
4458 CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
4459 tu_cs_emit(cs, 0);
4460 tu_cs_emit(cs, 0);
4461 uint32_t i;
4462 for (i = 0; i < num_consts; i++)
4463 tu_cs_emit(cs, driver_params[i]);
4464 } else if (!(info->indirect_offset & 0xf)) {
4465 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
4466 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
4467 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
4468 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
4469 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
4470 CP_LOAD_STATE6_0_NUM_UNIT(1));
4471 tu_cs_emit_qw(cs, tu_buffer_iova(info->indirect) + info->indirect_offset);
4472 } else {
4473 /* Vulkan guarantees only 4 byte alignment for indirect_offset.
4474 * However, CP_LOAD_STATE.EXT_SRC_ADDR needs 16 byte alignment.
4475 */
4476
4477 uint64_t indirect_iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
4478
4479 for (uint32_t i = 0; i < 3; i++) {
4480 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
4481 tu_cs_emit(cs, 0);
4482 tu_cs_emit_qw(cs, global_iova(cmd, cs_indirect_xyz[i]));
4483 tu_cs_emit_qw(cs, indirect_iova + i * 4);
4484 }
4485
4486 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
4487 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE);
4488
4489 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
4490 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
4491 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
4492 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
4493 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
4494 CP_LOAD_STATE6_0_NUM_UNIT(1));
4495 tu_cs_emit_qw(cs, global_iova(cmd, cs_indirect_xyz[0]));
4496 }
4497
4498 /* Fill out IR3_DP_SUBGROUP_SIZE and IR3_DP_SUBGROUP_ID_SHIFT for indirect
4499 * dispatch.
4500 */
4501 if (info->indirect && num_consts > IR3_DP_BASE_GROUP_X) {
4502 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 7);
4503 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset + (IR3_DP_BASE_GROUP_X / 4)) |
4504 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
4505 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
4506 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
4507 CP_LOAD_STATE6_0_NUM_UNIT((num_consts - IR3_DP_BASE_GROUP_X) / 4));
4508 tu_cs_emit_qw(cs, 0);
4509 tu_cs_emit(cs, 0); /* BASE_GROUP_X */
4510 tu_cs_emit(cs, 0); /* BASE_GROUP_Y */
4511 tu_cs_emit(cs, 0); /* BASE_GROUP_Z */
4512 tu_cs_emit(cs, subgroup_size);
4513 if (num_consts > IR3_DP_LOCAL_GROUP_SIZE_X) {
4514 assert(num_consts == align(IR3_DP_SUBGROUP_ID_SHIFT, 4));
4515 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_X */
4516 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_Y */
4517 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_Z */
4518 tu_cs_emit(cs, subgroup_shift);
4519 }
4520 }
4521 }
4522
4523 static void
tu_dispatch(struct tu_cmd_buffer * cmd,const struct tu_dispatch_info * info)4524 tu_dispatch(struct tu_cmd_buffer *cmd,
4525 const struct tu_dispatch_info *info)
4526 {
4527 if (!info->indirect &&
4528 (info->blocks[0] == 0 || info->blocks[1] == 0 || info->blocks[2] == 0))
4529 return;
4530
4531 struct tu_cs *cs = &cmd->cs;
4532 struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
4533 struct tu_descriptor_state *descriptors_state =
4534 &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
4535
4536 /* TODO: We could probably flush less if we add a compute_flush_bits
4537 * bitfield.
4538 */
4539 tu_emit_cache_flush(cmd, cs);
4540
4541 /* note: no reason to have this in a separate IB */
4542 tu_cs_emit_state_ib(cs,
4543 tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE));
4544
4545 tu_emit_compute_driver_params(cmd, cs, pipeline, info);
4546
4547 if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD)
4548 tu_cs_emit_state_ib(cs, pipeline->load_state);
4549
4550 cmd->state.dirty &= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD;
4551
4552 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
4553 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
4554
4555 const uint32_t *local_size = pipeline->compute.local_size;
4556 const uint32_t *num_groups = info->blocks;
4557 tu_cs_emit_regs(cs,
4558 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim = 3,
4559 .localsizex = local_size[0] - 1,
4560 .localsizey = local_size[1] - 1,
4561 .localsizez = local_size[2] - 1),
4562 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x = local_size[0] * num_groups[0]),
4563 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x = 0),
4564 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y = local_size[1] * num_groups[1]),
4565 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y = 0),
4566 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z = local_size[2] * num_groups[2]),
4567 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z = 0));
4568
4569 tu_cs_emit_regs(cs,
4570 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
4571 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
4572 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
4573
4574 trace_start_compute(&cmd->trace, cs);
4575
4576 if (info->indirect) {
4577 uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
4578
4579 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
4580 tu_cs_emit(cs, 0x00000000);
4581 tu_cs_emit_qw(cs, iova);
4582 tu_cs_emit(cs,
4583 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
4584 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
4585 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
4586 } else {
4587 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
4588 tu_cs_emit(cs, 0x00000000);
4589 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
4590 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
4591 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
4592 }
4593
4594 trace_end_compute(&cmd->trace, cs,
4595 info->indirect != NULL,
4596 local_size[0], local_size[1], local_size[2],
4597 info->blocks[0], info->blocks[1], info->blocks[2]);
4598
4599 tu_cs_emit_wfi(cs);
4600 }
4601
4602 VKAPI_ATTR void VKAPI_CALL
tu_CmdDispatchBase(VkCommandBuffer commandBuffer,uint32_t base_x,uint32_t base_y,uint32_t base_z,uint32_t x,uint32_t y,uint32_t z)4603 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
4604 uint32_t base_x,
4605 uint32_t base_y,
4606 uint32_t base_z,
4607 uint32_t x,
4608 uint32_t y,
4609 uint32_t z)
4610 {
4611 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4612 struct tu_dispatch_info info = {};
4613
4614 info.blocks[0] = x;
4615 info.blocks[1] = y;
4616 info.blocks[2] = z;
4617
4618 info.offsets[0] = base_x;
4619 info.offsets[1] = base_y;
4620 info.offsets[2] = base_z;
4621 tu_dispatch(cmd_buffer, &info);
4622 }
4623
4624 VKAPI_ATTR void VKAPI_CALL
tu_CmdDispatch(VkCommandBuffer commandBuffer,uint32_t x,uint32_t y,uint32_t z)4625 tu_CmdDispatch(VkCommandBuffer commandBuffer,
4626 uint32_t x,
4627 uint32_t y,
4628 uint32_t z)
4629 {
4630 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4631 }
4632
4633 VKAPI_ATTR void VKAPI_CALL
tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset)4634 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
4635 VkBuffer _buffer,
4636 VkDeviceSize offset)
4637 {
4638 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4639 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
4640 struct tu_dispatch_info info = {};
4641
4642 info.indirect = buffer;
4643 info.indirect_offset = offset;
4644
4645 tu_dispatch(cmd_buffer, &info);
4646 }
4647
4648 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,const VkSubpassEndInfoKHR * pSubpassEndInfo)4649 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
4650 const VkSubpassEndInfoKHR *pSubpassEndInfo)
4651 {
4652 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4653
4654 tu6_emit_tile_store(cmd_buffer, &cmd_buffer->tile_store_cs);
4655
4656 tu_cs_end(&cmd_buffer->draw_cs);
4657 tu_cs_end(&cmd_buffer->tile_store_cs);
4658 tu_cs_end(&cmd_buffer->draw_epilogue_cs);
4659
4660 cmd_buffer->trace_renderpass_end = u_trace_end_iterator(&cmd_buffer->trace);
4661
4662 if (use_sysmem_rendering(cmd_buffer))
4663 tu_cmd_render_sysmem(cmd_buffer);
4664 else
4665 tu_cmd_render_tiles(cmd_buffer);
4666
4667 /* Outside of renderpasses we assume all draw states are disabled. We do
4668 * this outside the draw CS for the normal case where 3d gmem stores aren't
4669 * used.
4670 */
4671 tu_disable_draw_states(cmd_buffer, &cmd_buffer->cs);
4672
4673 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
4674 rendered */
4675 tu_cs_discard_entries(&cmd_buffer->draw_cs);
4676 tu_cs_begin(&cmd_buffer->draw_cs);
4677 tu_cs_discard_entries(&cmd_buffer->tile_store_cs);
4678 tu_cs_begin(&cmd_buffer->tile_store_cs);
4679 tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
4680 tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
4681
4682 cmd_buffer->state.cache.pending_flush_bits |=
4683 cmd_buffer->state.renderpass_cache.pending_flush_bits;
4684 tu_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier, true);
4685
4686 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4687
4688 cmd_buffer->state.pass = NULL;
4689 cmd_buffer->state.subpass = NULL;
4690 cmd_buffer->state.framebuffer = NULL;
4691 cmd_buffer->state.attachments = NULL;
4692 cmd_buffer->state.has_tess = false;
4693 cmd_buffer->state.has_subpass_predication = false;
4694 cmd_buffer->state.disable_gmem = false;
4695
4696 /* LRZ is not valid next time we use it */
4697 cmd_buffer->state.lrz.valid = false;
4698 cmd_buffer->state.dirty |= TU_CMD_DIRTY_LRZ;
4699 }
4700
4701 struct tu_barrier_info
4702 {
4703 uint32_t eventCount;
4704 const VkEvent *pEvents;
4705 VkPipelineStageFlags srcStageMask;
4706 VkPipelineStageFlags dstStageMask;
4707 };
4708
4709 static void
tu_barrier(struct tu_cmd_buffer * cmd,uint32_t memoryBarrierCount,const VkMemoryBarrier * pMemoryBarriers,uint32_t bufferMemoryBarrierCount,const VkBufferMemoryBarrier * pBufferMemoryBarriers,uint32_t imageMemoryBarrierCount,const VkImageMemoryBarrier * pImageMemoryBarriers,const struct tu_barrier_info * info)4710 tu_barrier(struct tu_cmd_buffer *cmd,
4711 uint32_t memoryBarrierCount,
4712 const VkMemoryBarrier *pMemoryBarriers,
4713 uint32_t bufferMemoryBarrierCount,
4714 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4715 uint32_t imageMemoryBarrierCount,
4716 const VkImageMemoryBarrier *pImageMemoryBarriers,
4717 const struct tu_barrier_info *info)
4718 {
4719 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
4720 VkAccessFlags srcAccessMask = 0;
4721 VkAccessFlags dstAccessMask = 0;
4722
4723 if (cmd->state.pass) {
4724 const VkPipelineStageFlags framebuffer_space_stages =
4725 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
4726 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
4727 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
4728 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
4729
4730 /* We cannot have non-by-region "fb-space to fb-space" barriers.
4731 *
4732 * From the Vulkan 1.2.185 spec, section 7.6.1 "Subpass Self-dependency":
4733 *
4734 * If the source and destination stage masks both include
4735 * framebuffer-space stages, then dependencyFlags must include
4736 * VK_DEPENDENCY_BY_REGION_BIT.
4737 * [...]
4738 * Each of the synchronization scopes and access scopes of a
4739 * vkCmdPipelineBarrier2KHR or vkCmdPipelineBarrier command inside
4740 * a render pass instance must be a subset of the scopes of one of
4741 * the self-dependencies for the current subpass.
4742 *
4743 * If the self-dependency has VK_DEPENDENCY_BY_REGION_BIT or
4744 * VK_DEPENDENCY_VIEW_LOCAL_BIT set, then so must the pipeline barrier.
4745 *
4746 * By-region barriers are ok for gmem. All other barriers would involve
4747 * vtx stages which are NOT ok for gmem rendering.
4748 * See dep_invalid_for_gmem().
4749 */
4750 if ((info->srcStageMask & ~framebuffer_space_stages) ||
4751 (info->dstStageMask & ~framebuffer_space_stages)) {
4752 cmd->state.disable_gmem = true;
4753 }
4754 }
4755
4756 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4757 srcAccessMask |= pMemoryBarriers[i].srcAccessMask;
4758 dstAccessMask |= pMemoryBarriers[i].dstAccessMask;
4759 }
4760
4761 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4762 srcAccessMask |= pBufferMemoryBarriers[i].srcAccessMask;
4763 dstAccessMask |= pBufferMemoryBarriers[i].dstAccessMask;
4764 }
4765
4766 enum tu_cmd_access_mask src_flags = 0;
4767 enum tu_cmd_access_mask dst_flags = 0;
4768
4769 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4770 VkImageLayout old_layout = pImageMemoryBarriers[i].oldLayout;
4771 if (old_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4772 /* The underlying memory for this image may have been used earlier
4773 * within the same queue submission for a different image, which
4774 * means that there may be old, stale cache entries which are in the
4775 * "wrong" location, which could cause problems later after writing
4776 * to the image. We don't want these entries being flushed later and
4777 * overwriting the actual image, so we need to flush the CCU.
4778 */
4779 src_flags |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
4780 }
4781 srcAccessMask |= pImageMemoryBarriers[i].srcAccessMask;
4782 dstAccessMask |= pImageMemoryBarriers[i].dstAccessMask;
4783 }
4784
4785 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
4786 * so we have to use the sysmem flushes.
4787 */
4788 bool gmem = cmd->state.ccu_state == TU_CMD_CCU_GMEM &&
4789 !cmd->state.pass;
4790 src_flags |= vk2tu_access(srcAccessMask, gmem);
4791 dst_flags |= vk2tu_access(dstAccessMask, gmem);
4792
4793 struct tu_cache_state *cache =
4794 cmd->state.pass ? &cmd->state.renderpass_cache : &cmd->state.cache;
4795 tu_flush_for_access(cache, src_flags, dst_flags);
4796
4797 enum tu_stage src_stage = vk2tu_src_stage(info->srcStageMask);
4798 enum tu_stage dst_stage = vk2tu_dst_stage(info->dstStageMask);
4799 tu_flush_for_stage(cache, src_stage, dst_stage);
4800
4801 for (uint32_t i = 0; i < info->eventCount; i++) {
4802 TU_FROM_HANDLE(tu_event, event, info->pEvents[i]);
4803
4804 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
4805 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
4806 CP_WAIT_REG_MEM_0_POLL_MEMORY);
4807 tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
4808 tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
4809 tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
4810 tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
4811 }
4812 }
4813
4814 VKAPI_ATTR void VKAPI_CALL
tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,VkPipelineStageFlags srcStageMask,VkPipelineStageFlags dstStageMask,VkDependencyFlags dependencyFlags,uint32_t memoryBarrierCount,const VkMemoryBarrier * pMemoryBarriers,uint32_t bufferMemoryBarrierCount,const VkBufferMemoryBarrier * pBufferMemoryBarriers,uint32_t imageMemoryBarrierCount,const VkImageMemoryBarrier * pImageMemoryBarriers)4815 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
4816 VkPipelineStageFlags srcStageMask,
4817 VkPipelineStageFlags dstStageMask,
4818 VkDependencyFlags dependencyFlags,
4819 uint32_t memoryBarrierCount,
4820 const VkMemoryBarrier *pMemoryBarriers,
4821 uint32_t bufferMemoryBarrierCount,
4822 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4823 uint32_t imageMemoryBarrierCount,
4824 const VkImageMemoryBarrier *pImageMemoryBarriers)
4825 {
4826 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4827 struct tu_barrier_info info;
4828
4829 info.eventCount = 0;
4830 info.pEvents = NULL;
4831 info.srcStageMask = srcStageMask;
4832 info.dstStageMask = dstStageMask;
4833
4834 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4835 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4836 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4837 }
4838
4839 static void
write_event(struct tu_cmd_buffer * cmd,struct tu_event * event,VkPipelineStageFlags stageMask,unsigned value)4840 write_event(struct tu_cmd_buffer *cmd, struct tu_event *event,
4841 VkPipelineStageFlags stageMask, unsigned value)
4842 {
4843 struct tu_cs *cs = &cmd->cs;
4844
4845 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
4846 assert(!cmd->state.pass);
4847
4848 tu_emit_cache_flush(cmd, cs);
4849
4850 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
4851 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
4852 */
4853 VkPipelineStageFlags top_of_pipe_flags =
4854 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
4855 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT;
4856
4857 if (!(stageMask & ~top_of_pipe_flags)) {
4858 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
4859 tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
4860 tu_cs_emit(cs, value);
4861 } else {
4862 /* Use a RB_DONE_TS event to wait for everything to complete. */
4863 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 4);
4864 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS));
4865 tu_cs_emit_qw(cs, event->bo.iova);
4866 tu_cs_emit(cs, value);
4867 }
4868 }
4869
4870 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetEvent(VkCommandBuffer commandBuffer,VkEvent _event,VkPipelineStageFlags stageMask)4871 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
4872 VkEvent _event,
4873 VkPipelineStageFlags stageMask)
4874 {
4875 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4876 TU_FROM_HANDLE(tu_event, event, _event);
4877
4878 write_event(cmd, event, stageMask, 1);
4879 }
4880
4881 VKAPI_ATTR void VKAPI_CALL
tu_CmdResetEvent(VkCommandBuffer commandBuffer,VkEvent _event,VkPipelineStageFlags stageMask)4882 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
4883 VkEvent _event,
4884 VkPipelineStageFlags stageMask)
4885 {
4886 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4887 TU_FROM_HANDLE(tu_event, event, _event);
4888
4889 write_event(cmd, event, stageMask, 0);
4890 }
4891
4892 VKAPI_ATTR void VKAPI_CALL
tu_CmdWaitEvents(VkCommandBuffer commandBuffer,uint32_t eventCount,const VkEvent * pEvents,VkPipelineStageFlags srcStageMask,VkPipelineStageFlags dstStageMask,uint32_t memoryBarrierCount,const VkMemoryBarrier * pMemoryBarriers,uint32_t bufferMemoryBarrierCount,const VkBufferMemoryBarrier * pBufferMemoryBarriers,uint32_t imageMemoryBarrierCount,const VkImageMemoryBarrier * pImageMemoryBarriers)4893 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
4894 uint32_t eventCount,
4895 const VkEvent *pEvents,
4896 VkPipelineStageFlags srcStageMask,
4897 VkPipelineStageFlags dstStageMask,
4898 uint32_t memoryBarrierCount,
4899 const VkMemoryBarrier *pMemoryBarriers,
4900 uint32_t bufferMemoryBarrierCount,
4901 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4902 uint32_t imageMemoryBarrierCount,
4903 const VkImageMemoryBarrier *pImageMemoryBarriers)
4904 {
4905 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4906 struct tu_barrier_info info;
4907
4908 info.eventCount = eventCount;
4909 info.pEvents = pEvents;
4910 info.srcStageMask = srcStageMask;
4911 info.dstStageMask = dstStageMask;
4912
4913 tu_barrier(cmd, memoryBarrierCount, pMemoryBarriers,
4914 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4915 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4916 }
4917
4918 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer,uint32_t deviceMask)4919 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
4920 {
4921 /* No-op */
4922 }
4923
4924
4925 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer,const VkConditionalRenderingBeginInfoEXT * pConditionalRenderingBegin)4926 tu_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer,
4927 const VkConditionalRenderingBeginInfoEXT *pConditionalRenderingBegin)
4928 {
4929 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4930
4931 cmd->state.predication_active = true;
4932 if (cmd->state.pass)
4933 cmd->state.has_subpass_predication = true;
4934
4935 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
4936
4937 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_GLOBAL, 1);
4938 tu_cs_emit(cs, 1);
4939
4940 /* Wait for any writes to the predicate to land */
4941 if (cmd->state.pass)
4942 tu_emit_cache_flush_renderpass(cmd, cs);
4943 else
4944 tu_emit_cache_flush(cmd, cs);
4945
4946 TU_FROM_HANDLE(tu_buffer, buf, pConditionalRenderingBegin->buffer);
4947 uint64_t iova = tu_buffer_iova(buf) + pConditionalRenderingBegin->offset;
4948
4949 /* qcom doesn't support 32-bit reference values, only 64-bit, but Vulkan
4950 * mandates 32-bit comparisons. Our workaround is to copy the the reference
4951 * value to the low 32-bits of a location where the high 32 bits are known
4952 * to be 0 and then compare that.
4953 */
4954 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
4955 tu_cs_emit(cs, 0);
4956 tu_cs_emit_qw(cs, global_iova(cmd, predicate));
4957 tu_cs_emit_qw(cs, iova);
4958
4959 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
4960 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
4961
4962 bool inv = pConditionalRenderingBegin->flags & VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT;
4963 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_SET, 3);
4964 tu_cs_emit(cs, CP_DRAW_PRED_SET_0_SRC(PRED_SRC_MEM) |
4965 CP_DRAW_PRED_SET_0_TEST(inv ? EQ_0_PASS : NE_0_PASS));
4966 tu_cs_emit_qw(cs, global_iova(cmd, predicate));
4967 }
4968
4969 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer)4970 tu_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer)
4971 {
4972 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4973
4974 cmd->state.predication_active = false;
4975
4976 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
4977
4978 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_GLOBAL, 1);
4979 tu_cs_emit(cs, 0);
4980 }
4981
4982