| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_opcodes.c | 532 unsigned int writemask, in rc_compute_sources_for_writemask()
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| D | radeon_rename_regs.c | 72 unsigned writemask; in rc_rename_regs() local
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| D | radeon_pair_regalloc.c | 289 unsigned int writemask, in find_class()
332 unsigned int writemask = rc_variable_writemask_sum(variable); in variable_get_class() local
474 static int get_reg_id(unsigned int index, unsigned int writemask) in get_reg_id()
560 unsigned int chan, writemask = 0; in do_advanced_regalloc() local
628 unsigned int writemask = reg_get_writemask(reg); in do_advanced_regalloc() local
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| D | radeon_variable.c | 321 unsigned int writemask; in get_variable_pair_helper() local
393 unsigned int writemask = 0; in rc_variable_writemask_sum() local
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| D | radeon_compiler.c | 172 …c_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask) in rc_move_output()
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| D | radeon_dataflow_deadcode.c | 256 unsigned int writemask = ptr->U.I.DstReg.WriteMask; in rc_dataflow_deadcode() local
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_instruction_export.cpp | 104 int align, int align_offset, int writemask): in WriteScratchInstruction()
115 … int align, int align_offset, int writemask, int array_size): in WriteScratchInstruction()
150 static char *writemask_to_swizzle(int writemask, char *buf) in writemask_to_swizzle()
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| D | sfn_shader_fragment.cpp | 875 … const Interpolator& ip, EAluOp op, int writemask) in load_interpolated_two_comp()
912 unsigned writemask = nir_intrinsic_write_mask(instr); in emit_export_pixel() local
983 unsigned writemask = nir_intrinsic_write_mask(instr); in emit_export_pixel() local
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| D | sfn_shader_base.cpp | 747 int writemask = nir_intrinsic_write_mask(instr); in emit_store_scratch() local
1031 …or::emit_load_literal(const nir_load_const_instr * literal, const nir_src& src, unsigned writemask) in emit_load_literal()
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| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_lower_fragcolor.c | 81 nir_component_mask_t writemask = nir_intrinsic_write_mask(instr); in lower_fragcolor_instr() local
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| D | nir_opt_large_constants.c | 106 unsigned writemask, in handle_constant_store()
221 unsigned writemask = 0; in nir_opt_large_constants() local
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_scan.c | 1032 unsigned writemask = 0; in get_inst_tessfactor_writemask() local
1056 unsigned writemask = 0; in get_block_tessfactor_writemask() local
1104 unsigned writemask; in get_if_block_tessfactor_writemask() local
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| D | tgsi_text.c | 443 uint *writemask ) in parse_opt_writemask()
812 uint writemask; in parse_dst_operand() local
1289 uint writemask; in parse_declaration() local
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| /third_party/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi_private.cpp | 275 st_dst_reg::st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type, int index) in st_dst_reg()
289 st_dst_reg::st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type) in st_dst_reg()
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| D | st_glsl_to_tgsi_private.h | 109 unsigned writemask:4; /**< Bitfield of WRITEMASK_[XYZW] */ variable
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| /third_party/mesa3d/src/compiler/glsl/ |
| D | ir_builder.h | 32 enum writemask { enum
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| D | ir_builder.cpp | 49 assign(deref lhs, operand rhs, operand condition, int writemask) in assign()
68 assign(deref lhs, operand rhs, int writemask) in assign()
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| /third_party/mesa3d/src/gallium/frontends/d3d10umd/ |
| D | ShaderTGSI.c | 221 uint writemask; member
401 swizzle_reg(struct ureg_src src, uint writemask, in swizzle_reg()
427 unsigned writemask = in dcl_base_output() local
456 unsigned writemask = in dcl_base_input() local
709 unsigned writemask) in translate_operand()
821 unsigned writemask = in translate_dst_operand() local
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4.cpp | 106 unsigned writemask) in dst_reg()
117 unsigned writemask) in dst_reg()
410 unsigned writemask = 0; in opt_vector_float() local
2403 scalarize_predicate(brw_predicate predicate, unsigned writemask) in scalarize_predicate()
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| D | brw_nir_lower_mem_access_bit_sizes.c | 173 nir_component_mask_t writemask = nir_intrinsic_write_mask(intrin); in lower_mem_store_bit_size() local
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| D | brw_vec4_tcs.cpp | 220 unsigned writemask, in emit_urb_write()
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| D | brw_ir_vec4.h | 205 writemask(dst_reg reg, unsigned mask) in writemask() function
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| /third_party/mesa3d/src/gallium/drivers/i915/ |
| D | i915_state_emit.c | 125 uint32_t writemask = imm & S5_WRITEDISABLE_MASK; in emit_immediate_s5() local
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_nir_lower_esgs_io_to_mem.c | 84 unsigned writemask, bool swizzled, bool slc) in emit_split_buffer_store()
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| /third_party/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_nir.c | 1299 int writemask = instr->const_index[0]; in visit_store_var() local
1358 int writemask = instr->const_index[0]; in visit_store_ssbo() local
1594 int writemask = instr->const_index[1]; in visit_shared_store() local
1659 int writemask = instr->const_index[0]; in visit_store_global() local
1723 int writemask = instr->const_index[2]; in visit_store_scratch() local
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