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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/crypto/
Dallwinner,sun8i-ss.yaml55 reg = <0x01c15000 0x1000>;
Dallwinner,sun8i-ce.yaml82 reg = <0x01c15000 0x1000>;
Dallwinner,sun4i-a10-crypto.yaml79 reg = <0x01c15000 0x1000>;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
84 reg = <0x01c00000 0x1000>;
91 reg = <0x00018000 0x1c000>;
94 ranges = <0 0x00018000 0x1c000>;
96 ve_sram: sram-section@0 {
99 reg = <0x000000 0x1c000>;
106 reg = <0x01c0e000 0x1000>;
117 reg = <0x01c15000 0x1000>;
[all …]
Dsun50i-a64.dtsi46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&ths 0>;
221 polling-delay-passive = <0>;
222 polling-delay = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsun8i-h3.dtsi72 #size-cells = <0>;
74 cpu0: cpu@0 {
77 reg = <0>;
155 reg = <0x01400000 0x20000>;
168 reg = <0x01c00000 0x1000>;
175 reg = <0x01d00000 0x80000>;
178 ranges = <0 0x01d00000 0x80000>;
180 ve_sram: sram-section@0 {
183 reg = <0x000000 0x80000>;
190 reg = <0x01c0e000 0x1000>;
[all …]
Dsun8i-a33.dtsi127 cpu@0 {
208 reg = <0x01c0e000 0x1000>;
219 reg = <0x01c15000 0x1000>;
228 #sound-dai-cells = <0>;
230 reg = <0x01c22c00 0x200>;
241 #sound-dai-cells = <0>;
243 reg = <0x01c22e00 0x400>;
252 reg = <0x01c25000 0x100>;
253 #thermal-sensor-cells = <0>;
254 #io-channel-cells = <0>;
[all …]
Dsun8i-v3s.dtsi70 #size-cells = <0>;
72 cpu@0 {
75 reg = <0>;
100 #clock-cells = <0>;
108 #clock-cells = <0>;
124 reg = <0x01000000 0x10000>;
136 reg = <0x01100000 0x100000>;
137 clocks = <&display_clocks 0>,
141 resets = <&display_clocks 0>;
145 #size-cells = <0>;
[all …]
Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
Dsun8i-r40.dtsi63 #clock-cells = <0>;
71 #clock-cells = <0>;
81 #size-cells = <0>;
83 cpu0: cpu@0 {
86 reg = <0>;
117 polling-delay-passive = <0>;
118 polling-delay = <0>;
119 thermal-sensors = <&ths 0>;
124 polling-delay-passive = <0>;
125 polling-delay = <0>;
[all …]
Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
200 size = <0x6000000>;
201 alloc-ranges = <0x40000000 0x10000000>;
215 reg = <0x01c00000 0x30>;
220 sram_a: sram@0 {
222 reg = <0x00000000 0xc000>;
[all …]
Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
Dsun6i-a31.dtsi100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
216 #clock-cells = <0>;
224 #clock-cells = <0>;
241 #clock-cells = <0>;
248 #clock-cells = <0>;
255 #clock-cells = <0>;
257 reg = <0x01c200d0 0x4>;
277 reg = <0x01c02000 0x1000>;
[all …]
Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
183 size = <0x6000000>;
184 alloc-ranges = <0x40000000 0x10000000>;
210 #clock-cells = <0>;
217 #clock-cells = <0>;
233 #clock-cells = <0>;
240 #clock-cells = <0>;
247 #clock-cells = <0>;
[all …]